| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.02 | 95.49 | 93.82 | 95.32 | 94.57 | 97.35 | 99.55 |
| T2767 | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1805330816 | Aug 06 09:00:38 PM PDT 24 | Aug 06 09:07:17 PM PDT 24 | 9278124176 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/92.xbar_random.2539000078 | Aug 06 09:04:28 PM PDT 24 | Aug 06 09:05:02 PM PDT 24 | 846541881 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.3296182400 | Aug 06 08:51:27 PM PDT 24 | Aug 06 08:53:17 PM PDT 24 | 9755945293 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.449498651 | Aug 06 08:46:52 PM PDT 24 | Aug 06 08:48:27 PM PDT 24 | 1102690107 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.4191113450 | Aug 06 09:04:25 PM PDT 24 | Aug 06 09:06:50 PM PDT 24 | 8579018951 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2251907473 | Aug 06 08:50:36 PM PDT 24 | Aug 06 08:52:24 PM PDT 24 | 2692675741 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3879329784 | Aug 06 08:46:22 PM PDT 24 | Aug 06 08:50:40 PM PDT 24 | 3478500656 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2130688469 | Aug 06 08:53:51 PM PDT 24 | Aug 06 08:58:03 PM PDT 24 | 14761793896 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2486803509 | Aug 06 08:50:32 PM PDT 24 | Aug 06 08:56:29 PM PDT 24 | 9670241651 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.184491192 | Aug 06 09:00:09 PM PDT 24 | Aug 06 09:00:15 PM PDT 24 | 42354473 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/89.xbar_error_random.3334714314 | Aug 06 09:04:03 PM PDT 24 | Aug 06 09:04:11 PM PDT 24 | 65312237 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.240379915 | Aug 06 09:00:44 PM PDT 24 | Aug 06 09:01:01 PM PDT 24 | 322187621 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.191122662 | Aug 06 08:56:52 PM PDT 24 | Aug 06 08:58:31 PM PDT 24 | 5726835601 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/39.xbar_error_random.550115390 | Aug 06 08:56:08 PM PDT 24 | Aug 06 08:56:24 PM PDT 24 | 373245717 ps | ||
| T746 | /workspace/coverage/cover_reg_top/14.chip_tl_errors.1484498847 | Aug 06 08:50:00 PM PDT 24 | Aug 06 08:52:57 PM PDT 24 | 3205926028 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2145923802 | Aug 06 09:02:51 PM PDT 24 | Aug 06 09:03:09 PM PDT 24 | 179751288 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1957849691 | Aug 06 09:05:08 PM PDT 24 | Aug 06 09:09:00 PM PDT 24 | 2860168467 ps | ||
| T452 | /workspace/coverage/cover_reg_top/9.chip_csr_rw.1104616019 | Aug 06 08:48:03 PM PDT 24 | Aug 06 08:58:05 PM PDT 24 | 5822142315 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1409637917 | Aug 06 09:02:05 PM PDT 24 | Aug 06 09:05:30 PM PDT 24 | 6308644289 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2013391136 | Aug 06 08:44:13 PM PDT 24 | Aug 06 08:44:42 PM PDT 24 | 554242408 ps | ||
| T144 | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.940018540 | Aug 06 08:45:06 PM PDT 24 | Aug 06 08:52:44 PM PDT 24 | 7718385232 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3825126915 | Aug 06 08:52:07 PM PDT 24 | Aug 06 08:52:14 PM PDT 24 | 46625645 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1158966578 | Aug 06 08:54:44 PM PDT 24 | Aug 06 08:56:26 PM PDT 24 | 5651729728 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3010475789 | Aug 06 08:48:52 PM PDT 24 | Aug 06 08:50:29 PM PDT 24 | 5648567630 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1556651761 | Aug 06 08:59:31 PM PDT 24 | Aug 06 09:01:29 PM PDT 24 | 2945104413 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2063367692 | Aug 06 09:00:27 PM PDT 24 | Aug 06 09:00:41 PM PDT 24 | 134552543 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1798152451 | Aug 06 08:58:11 PM PDT 24 | Aug 06 08:58:17 PM PDT 24 | 39172209 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1521611098 | Aug 06 08:58:03 PM PDT 24 | Aug 06 08:59:58 PM PDT 24 | 6721630480 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1088285180 | Aug 06 09:03:01 PM PDT 24 | Aug 06 09:34:42 PM PDT 24 | 104571202044 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3433840790 | Aug 06 08:55:32 PM PDT 24 | Aug 06 09:06:18 PM PDT 24 | 34740452742 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4045471752 | Aug 06 08:41:32 PM PDT 24 | Aug 06 08:42:07 PM PDT 24 | 67132730 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4005128481 | Aug 06 08:43:43 PM PDT 24 | Aug 06 09:11:02 PM PDT 24 | 89342580568 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3889877874 | Aug 06 08:58:39 PM PDT 24 | Aug 06 09:06:16 PM PDT 24 | 7903112118 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3442514465 | Aug 06 09:00:29 PM PDT 24 | Aug 06 09:01:02 PM PDT 24 | 683019662 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3192701509 | Aug 06 08:43:12 PM PDT 24 | Aug 06 08:44:47 PM PDT 24 | 9054141876 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/94.xbar_smoke.4287916181 | Aug 06 09:04:41 PM PDT 24 | Aug 06 09:04:51 PM PDT 24 | 207853411 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3853341015 | Aug 06 09:04:13 PM PDT 24 | Aug 06 09:08:11 PM PDT 24 | 23122973006 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.980585704 | Aug 06 08:52:45 PM PDT 24 | Aug 06 08:52:51 PM PDT 24 | 26973973 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.66334671 | Aug 06 08:47:22 PM PDT 24 | Aug 06 08:48:24 PM PDT 24 | 1239107406 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.4149652070 | Aug 06 09:00:25 PM PDT 24 | Aug 06 09:24:01 PM PDT 24 | 81834198590 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/43.xbar_stress_all.639900881 | Aug 06 08:56:54 PM PDT 24 | Aug 06 09:01:57 PM PDT 24 | 8054627155 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3860143337 | Aug 06 08:54:15 PM PDT 24 | Aug 06 08:57:27 PM PDT 24 | 16118036772 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1712757885 | Aug 06 08:49:56 PM PDT 24 | Aug 06 08:57:33 PM PDT 24 | 3256779279 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2157883618 | Aug 06 09:04:26 PM PDT 24 | Aug 06 09:05:29 PM PDT 24 | 5990729282 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1762346430 | Aug 06 09:00:58 PM PDT 24 | Aug 06 09:07:28 PM PDT 24 | 2721901520 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.954369407 | Aug 06 09:04:22 PM PDT 24 | Aug 06 09:07:36 PM PDT 24 | 4847600936 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/35.xbar_smoke.1329898569 | Aug 06 08:55:12 PM PDT 24 | Aug 06 08:55:19 PM PDT 24 | 42750064 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/32.xbar_random.2156503054 | Aug 06 08:54:45 PM PDT 24 | Aug 06 08:55:54 PM PDT 24 | 1723473576 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.564870141 | Aug 06 09:01:44 PM PDT 24 | Aug 06 09:03:06 PM PDT 24 | 7653578626 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2104633336 | Aug 06 08:53:31 PM PDT 24 | Aug 06 08:58:31 PM PDT 24 | 1546418601 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3526917319 | Aug 06 09:05:07 PM PDT 24 | Aug 06 09:05:14 PM PDT 24 | 50955159 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2281360188 | Aug 06 08:57:43 PM PDT 24 | Aug 06 08:57:53 PM PDT 24 | 65640427 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/74.xbar_random.858306359 | Aug 06 09:01:38 PM PDT 24 | Aug 06 09:01:46 PM PDT 24 | 151639995 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2192974088 | Aug 06 09:01:00 PM PDT 24 | Aug 06 09:24:02 PM PDT 24 | 79418284581 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1683669089 | Aug 06 08:58:28 PM PDT 24 | Aug 06 08:59:07 PM PDT 24 | 304239353 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2312016100 | Aug 06 08:55:36 PM PDT 24 | Aug 06 08:57:10 PM PDT 24 | 5305619702 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3239109215 | Aug 06 09:00:31 PM PDT 24 | Aug 06 09:00:40 PM PDT 24 | 63181436 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1371364677 | Aug 06 09:03:43 PM PDT 24 | Aug 06 09:04:11 PM PDT 24 | 589491038 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/10.xbar_error_random.4293851006 | Aug 06 08:48:33 PM PDT 24 | Aug 06 08:49:29 PM PDT 24 | 1470368128 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2087871502 | Aug 06 08:54:19 PM PDT 24 | Aug 06 08:57:54 PM PDT 24 | 5133045060 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2013792767 | Aug 06 08:58:36 PM PDT 24 | Aug 06 09:00:12 PM PDT 24 | 5372255462 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2071164420 | Aug 06 09:03:19 PM PDT 24 | Aug 06 09:17:43 PM PDT 24 | 50860955468 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/61.xbar_random.383507698 | Aug 06 08:59:31 PM PDT 24 | Aug 06 08:59:46 PM PDT 24 | 312307448 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1297972505 | Aug 06 08:48:01 PM PDT 24 | Aug 06 08:48:25 PM PDT 24 | 538923243 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1840401973 | Aug 06 08:46:19 PM PDT 24 | Aug 06 08:53:57 PM PDT 24 | 8137624781 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.3823963922 | Aug 06 09:02:53 PM PDT 24 | Aug 06 09:04:03 PM PDT 24 | 796646750 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/76.xbar_smoke.3465743887 | Aug 06 09:01:56 PM PDT 24 | Aug 06 09:02:06 PM PDT 24 | 231936052 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2989153818 | Aug 06 08:49:46 PM PDT 24 | Aug 06 08:49:53 PM PDT 24 | 31452761 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2691117528 | Aug 06 09:03:00 PM PDT 24 | Aug 06 09:03:23 PM PDT 24 | 66469301 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2641546111 | Aug 06 09:00:44 PM PDT 24 | Aug 06 09:02:16 PM PDT 24 | 2552056031 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1667975895 | Aug 06 08:56:45 PM PDT 24 | Aug 06 09:05:53 PM PDT 24 | 9092820714 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3532059806 | Aug 06 09:01:10 PM PDT 24 | Aug 06 09:22:21 PM PDT 24 | 67078522684 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/96.xbar_error_random.3067494858 | Aug 06 09:05:21 PM PDT 24 | Aug 06 09:05:43 PM PDT 24 | 589321450 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/7.xbar_same_source.1036898267 | Aug 06 08:46:57 PM PDT 24 | Aug 06 08:47:07 PM PDT 24 | 79999496 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/93.xbar_random.2434415929 | Aug 06 09:04:49 PM PDT 24 | Aug 06 09:05:09 PM PDT 24 | 195605491 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2892081499 | Aug 06 08:59:55 PM PDT 24 | Aug 06 09:01:02 PM PDT 24 | 968541923 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1855831129 | Aug 06 08:48:04 PM PDT 24 | Aug 06 08:58:53 PM PDT 24 | 5187749327 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/83.xbar_stress_all.1762021206 | Aug 06 09:03:11 PM PDT 24 | Aug 06 09:09:07 PM PDT 24 | 8238998516 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1940859417 | Aug 06 08:59:20 PM PDT 24 | Aug 06 09:00:07 PM PDT 24 | 1153376118 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/61.xbar_same_source.117299066 | Aug 06 08:59:36 PM PDT 24 | Aug 06 09:00:24 PM PDT 24 | 1478088826 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3664164308 | Aug 06 08:56:49 PM PDT 24 | Aug 06 09:02:11 PM PDT 24 | 31121839741 ps | ||
| T453 | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3859795959 | Aug 06 08:45:52 PM PDT 24 | Aug 06 09:58:29 PM PDT 24 | 30953988184 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2854323688 | Aug 06 08:53:16 PM PDT 24 | Aug 06 08:53:23 PM PDT 24 | 44806602 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/15.xbar_random.3839516386 | Aug 06 08:50:22 PM PDT 24 | Aug 06 08:51:28 PM PDT 24 | 1744760757 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.443093273 | Aug 06 08:57:12 PM PDT 24 | Aug 06 09:10:43 PM PDT 24 | 46457296007 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2970987929 | Aug 06 08:56:13 PM PDT 24 | Aug 06 09:05:33 PM PDT 24 | 13258724921 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.542109199 | Aug 06 08:58:14 PM PDT 24 | Aug 06 09:01:48 PM PDT 24 | 12018935972 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.979094710 | Aug 06 09:04:32 PM PDT 24 | Aug 06 09:16:23 PM PDT 24 | 39942644525 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1647867048 | Aug 06 09:01:31 PM PDT 24 | Aug 06 09:01:58 PM PDT 24 | 230545922 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.527297286 | Aug 06 08:41:45 PM PDT 24 | Aug 06 08:41:52 PM PDT 24 | 39815267 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3494833716 | Aug 06 08:55:57 PM PDT 24 | Aug 06 09:08:37 PM PDT 24 | 43929957221 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3573347453 | Aug 06 08:55:46 PM PDT 24 | Aug 06 08:56:44 PM PDT 24 | 711095654 ps | ||
| T923 | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3325848255 | Aug 06 09:02:22 PM PDT 24 | Aug 06 09:06:33 PM PDT 24 | 459426119 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1248048709 | Aug 06 08:57:25 PM PDT 24 | Aug 06 08:58:48 PM PDT 24 | 4750516063 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/57.xbar_random.1762969782 | Aug 06 08:59:05 PM PDT 24 | Aug 06 08:59:39 PM PDT 24 | 307290419 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.195719818 | Aug 06 08:52:07 PM PDT 24 | Aug 06 08:53:13 PM PDT 24 | 1357709450 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3300240204 | Aug 06 08:59:26 PM PDT 24 | Aug 06 09:07:38 PM PDT 24 | 8069457058 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4040419014 | Aug 06 08:56:29 PM PDT 24 | Aug 06 08:57:10 PM PDT 24 | 183914087 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.4031518553 | Aug 06 09:01:20 PM PDT 24 | Aug 06 09:17:47 PM PDT 24 | 56756496568 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2302514255 | Aug 06 09:04:57 PM PDT 24 | Aug 06 09:05:04 PM PDT 24 | 56059003 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3373857242 | Aug 06 08:50:07 PM PDT 24 | Aug 06 08:53:44 PM PDT 24 | 12061370505 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/9.xbar_stress_all.4186913035 | Aug 06 08:48:03 PM PDT 24 | Aug 06 08:59:59 PM PDT 24 | 15787817586 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/69.xbar_smoke.1451878676 | Aug 06 09:00:47 PM PDT 24 | Aug 06 09:00:54 PM PDT 24 | 58109222 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/42.xbar_same_source.2031051717 | Aug 06 08:56:38 PM PDT 24 | Aug 06 08:57:06 PM PDT 24 | 859789354 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.400840304 | Aug 06 08:58:19 PM PDT 24 | Aug 06 09:00:00 PM PDT 24 | 5819018403 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.328304609 | Aug 06 08:52:54 PM PDT 24 | Aug 06 08:56:38 PM PDT 24 | 366841751 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3460528158 | Aug 06 08:56:06 PM PDT 24 | Aug 06 09:16:10 PM PDT 24 | 67024939640 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3304432925 | Aug 06 09:05:22 PM PDT 24 | Aug 06 09:10:40 PM PDT 24 | 9526940003 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2441855317 | Aug 06 09:00:53 PM PDT 24 | Aug 06 09:17:58 PM PDT 24 | 101254662167 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2982097430 | Aug 06 09:03:42 PM PDT 24 | Aug 06 09:15:22 PM PDT 24 | 42042593471 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2124204523 | Aug 06 08:59:12 PM PDT 24 | Aug 06 09:13:03 PM PDT 24 | 45556373767 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1235072506 | Aug 06 09:03:00 PM PDT 24 | Aug 06 09:03:20 PM PDT 24 | 472645103 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/14.xbar_stress_all.766497111 | Aug 06 08:50:09 PM PDT 24 | Aug 06 08:53:53 PM PDT 24 | 2499598467 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/33.xbar_same_source.3605878221 | Aug 06 08:55:02 PM PDT 24 | Aug 06 08:55:55 PM PDT 24 | 1851569874 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/25.chip_tl_errors.1857298030 | Aug 06 08:53:17 PM PDT 24 | Aug 06 08:57:45 PM PDT 24 | 3390208312 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.114202956 | Aug 06 08:59:02 PM PDT 24 | Aug 06 09:00:25 PM PDT 24 | 8181062901 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1680795959 | Aug 06 09:02:44 PM PDT 24 | Aug 06 09:15:18 PM PDT 24 | 43813685237 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4147321991 | Aug 06 08:58:34 PM PDT 24 | Aug 06 09:02:32 PM PDT 24 | 4132234776 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4025521943 | Aug 06 08:59:26 PM PDT 24 | Aug 06 09:09:44 PM PDT 24 | 16563612408 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3615789019 | Aug 06 08:57:59 PM PDT 24 | Aug 06 08:58:13 PM PDT 24 | 271653783 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.80679280 | Aug 06 09:00:34 PM PDT 24 | Aug 06 09:06:35 PM PDT 24 | 4481559603 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2836991161 | Aug 06 09:04:17 PM PDT 24 | Aug 06 09:04:31 PM PDT 24 | 294645544 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1919291932 | Aug 06 08:57:06 PM PDT 24 | Aug 06 08:58:05 PM PDT 24 | 212483369 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/9.xbar_random.2517985349 | Aug 06 08:47:47 PM PDT 24 | Aug 06 08:48:40 PM PDT 24 | 1499856588 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1331595065 | Aug 06 08:53:46 PM PDT 24 | Aug 06 08:53:53 PM PDT 24 | 44816472 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3883720347 | Aug 06 08:54:13 PM PDT 24 | Aug 06 09:09:11 PM PDT 24 | 19597970089 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/3.xbar_random.465349928 | Aug 06 08:43:59 PM PDT 24 | Aug 06 08:44:31 PM PDT 24 | 321117280 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/35.xbar_stress_all.3027379822 | Aug 06 08:55:21 PM PDT 24 | Aug 06 09:03:01 PM PDT 24 | 10760355656 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2922515023 | Aug 06 08:50:28 PM PDT 24 | Aug 06 08:55:53 PM PDT 24 | 596077838 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.602430141 | Aug 06 08:54:57 PM PDT 24 | Aug 06 08:58:54 PM PDT 24 | 704919809 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/1.xbar_same_source.3505613537 | Aug 06 08:42:21 PM PDT 24 | Aug 06 08:42:33 PM PDT 24 | 140196512 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/24.xbar_error_random.538116917 | Aug 06 08:53:10 PM PDT 24 | Aug 06 08:53:35 PM PDT 24 | 666131023 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1666492642 | Aug 06 08:48:24 PM PDT 24 | Aug 06 09:01:26 PM PDT 24 | 44683653731 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.568348680 | Aug 06 08:58:34 PM PDT 24 | Aug 06 09:02:27 PM PDT 24 | 708166524 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2222043247 | Aug 06 08:51:10 PM PDT 24 | Aug 06 08:51:17 PM PDT 24 | 48473837 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1547604040 | Aug 06 08:49:48 PM PDT 24 | Aug 06 08:51:09 PM PDT 24 | 4565427868 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2267857045 | Aug 06 08:46:22 PM PDT 24 | Aug 06 08:54:16 PM PDT 24 | 6517137500 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3980944952 | Aug 06 08:59:05 PM PDT 24 | Aug 06 09:00:28 PM PDT 24 | 7963575862 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.3657845860 | Aug 06 08:45:35 PM PDT 24 | Aug 06 08:57:06 PM PDT 24 | 38290486083 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.580879505 | Aug 06 09:04:29 PM PDT 24 | Aug 06 09:13:30 PM PDT 24 | 51878506429 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3022414883 | Aug 06 08:41:53 PM PDT 24 | Aug 06 08:46:16 PM PDT 24 | 3282564933 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/13.xbar_random.3997019388 | Aug 06 08:49:47 PM PDT 24 | Aug 06 08:50:30 PM PDT 24 | 408739946 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1245603917 | Aug 06 08:48:26 PM PDT 24 | Aug 06 08:58:17 PM PDT 24 | 35275061819 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.241418472 | Aug 06 08:55:36 PM PDT 24 | Aug 06 08:56:18 PM PDT 24 | 491929286 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.108251492 | Aug 06 09:03:35 PM PDT 24 | Aug 06 09:10:44 PM PDT 24 | 3860683615 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2128431223 | Aug 06 08:55:46 PM PDT 24 | Aug 06 08:59:23 PM PDT 24 | 2896643596 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1839066971 | Aug 06 08:55:27 PM PDT 24 | Aug 06 08:56:48 PM PDT 24 | 7187454486 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2941994598 | Aug 06 09:05:15 PM PDT 24 | Aug 06 09:15:22 PM PDT 24 | 4277463637 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2401939286 | Aug 06 09:02:58 PM PDT 24 | Aug 06 09:10:47 PM PDT 24 | 4871600557 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2004215254 | Aug 06 09:03:34 PM PDT 24 | Aug 06 09:04:06 PM PDT 24 | 671140537 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1888423584 | Aug 06 08:45:58 PM PDT 24 | Aug 06 08:59:15 PM PDT 24 | 74391973154 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1320266964 | Aug 06 08:55:28 PM PDT 24 | Aug 06 09:02:39 PM PDT 24 | 7957455039 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/54.xbar_stress_all.4170479116 | Aug 06 08:58:36 PM PDT 24 | Aug 06 09:05:56 PM PDT 24 | 10925214049 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/38.xbar_error_random.455058069 | Aug 06 08:55:58 PM PDT 24 | Aug 06 08:56:53 PM PDT 24 | 631336450 ps | ||
| T671 | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1234219580 | Aug 06 08:58:09 PM PDT 24 | Aug 06 09:05:06 PM PDT 24 | 11435400860 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3389213397 | Aug 06 09:04:42 PM PDT 24 | Aug 06 09:43:33 PM PDT 24 | 134713141775 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/31.xbar_random.2436133981 | Aug 06 08:54:44 PM PDT 24 | Aug 06 08:55:05 PM PDT 24 | 239930517 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1377972785 | Aug 06 08:51:37 PM PDT 24 | Aug 06 09:16:50 PM PDT 24 | 85519238410 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.4154739297 | Aug 06 09:00:58 PM PDT 24 | Aug 06 09:03:09 PM PDT 24 | 7081185405 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/12.xbar_smoke.80895147 | Aug 06 08:49:10 PM PDT 24 | Aug 06 08:49:18 PM PDT 24 | 129449546 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.823403148 | Aug 06 08:54:56 PM PDT 24 | Aug 06 09:02:14 PM PDT 24 | 25105958594 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.1594941613 | Aug 06 08:59:47 PM PDT 24 | Aug 06 09:01:05 PM PDT 24 | 7259604909 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3910908615 | Aug 06 08:50:23 PM PDT 24 | Aug 06 08:53:12 PM PDT 24 | 9678902384 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/45.xbar_stress_all.378389838 | Aug 06 08:57:15 PM PDT 24 | Aug 06 09:00:17 PM PDT 24 | 1917968902 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3589496456 | Aug 06 08:53:44 PM PDT 24 | Aug 06 09:03:43 PM PDT 24 | 14714930277 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.4069884299 | Aug 06 08:58:04 PM PDT 24 | Aug 06 09:07:14 PM PDT 24 | 51864276638 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1399170174 | Aug 06 08:55:59 PM PDT 24 | Aug 06 09:03:49 PM PDT 24 | 9591762594 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1964237582 | Aug 06 08:50:49 PM PDT 24 | Aug 06 08:58:47 PM PDT 24 | 44714380370 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.788294740 | Aug 06 08:55:27 PM PDT 24 | Aug 06 09:02:23 PM PDT 24 | 10581455277 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/86.xbar_error_random.1398539695 | Aug 06 09:03:34 PM PDT 24 | Aug 06 09:04:47 PM PDT 24 | 2162720278 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2238247856 | Aug 06 08:55:54 PM PDT 24 | Aug 06 08:57:00 PM PDT 24 | 1324819545 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2995195335 | Aug 06 08:53:14 PM PDT 24 | Aug 06 08:54:27 PM PDT 24 | 740985306 ps | ||
| T26 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.237141663 | Aug 06 08:40:13 PM PDT 24 | Aug 06 08:44:44 PM PDT 24 | 4575299244 ps | ||
| T27 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3420465919 | Aug 06 08:40:00 PM PDT 24 | Aug 06 08:45:09 PM PDT 24 | 5527628594 ps | ||
| T28 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.598668445 | Aug 06 08:40:04 PM PDT 24 | Aug 06 08:44:33 PM PDT 24 | 5325613366 ps | ||
| T189 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3414783364 | Aug 06 08:40:07 PM PDT 24 | Aug 06 08:43:31 PM PDT 24 | 4769818113 ps | ||
| T190 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1948658276 | Aug 06 08:39:50 PM PDT 24 | Aug 06 08:45:30 PM PDT 24 | 4559882900 ps | ||
| T191 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2149797186 | Aug 06 08:39:47 PM PDT 24 | Aug 06 08:44:29 PM PDT 24 | 5491534508 ps | ||
| T192 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2530429001 | Aug 06 08:40:28 PM PDT 24 | Aug 06 08:44:51 PM PDT 24 | 4276649088 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1726404817 | Aug 06 08:40:47 PM PDT 24 | Aug 06 08:46:07 PM PDT 24 | 5262593925 ps | ||
| T194 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1244988702 | Aug 06 08:39:42 PM PDT 24 | Aug 06 08:45:09 PM PDT 24 | 4376770923 ps | ||
| T197 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1221262080 | Aug 06 08:39:57 PM PDT 24 | Aug 06 08:44:49 PM PDT 24 | 4526596866 ps |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.1313801164 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4693110060 ps |
| CPU time | 565.57 seconds |
| Started | Aug 06 08:42:37 PM PDT 24 |
| Finished | Aug 06 08:52:03 PM PDT 24 |
| Peak memory | 650100 kb |
| Host | smart-943dacfc-199c-4802-b2bb-4fb1c1d65a3c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1313801164 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.1313801164 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4088399610 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 11975349330 ps |
| CPU time | 913.32 seconds |
| Started | Aug 06 08:48:40 PM PDT 24 |
| Finished | Aug 06 09:03:53 PM PDT 24 |
| Peak memory | 641604 kb |
| Host | smart-2a00bc84-835b-482e-b50b-a78dd499b203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4088399610 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.4088399610 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.1492729357 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 16850279869 ps |
| CPU time | 636.3 seconds |
| Started | Aug 06 08:52:14 PM PDT 24 |
| Finished | Aug 06 09:02:50 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-1a8ea19d-a40b-4f16-9a20-7e88ca5eda20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492729357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.1492729357 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.2478666212 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 5087709320 ps |
| CPU time | 899.18 seconds |
| Started | Aug 06 08:36:11 PM PDT 24 |
| Finished | Aug 06 08:51:11 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-98045f5b-6e1f-426e-a81d-acf6ee5bd9a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478666212 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_20.2478666212 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.488976520 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 99655144818 ps |
| CPU time | 1774.77 seconds |
| Started | Aug 06 08:54:17 PM PDT 24 |
| Finished | Aug 06 09:23:52 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-ebddacbf-d3cf-41c9-95dc-324d949c8dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488976520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_d evice_slow_rsp.488976520 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.1639480282 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 18374922114 ps |
| CPU time | 2661.1 seconds |
| Started | Aug 06 08:10:45 PM PDT 24 |
| Finished | Aug 06 08:55:06 PM PDT 24 |
| Peak memory | 608192 kb |
| Host | smart-84223200-5ef5-40cb-9c04-fd68c28efdc6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639480282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.1639480282 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.237141663 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4575299244 ps |
| CPU time | 271.21 seconds |
| Started | Aug 06 08:40:13 PM PDT 24 |
| Finished | Aug 06 08:44:44 PM PDT 24 |
| Peak memory | 657380 kb |
| Host | smart-75141d3b-6900-4c94-acd0-5df52fd38189 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237141663 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 9.chip_padctrl_attributes.237141663 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.2360990243 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 152702320272 ps |
| CPU time | 2513.04 seconds |
| Started | Aug 06 09:03:13 PM PDT 24 |
| Finished | Aug 06 09:45:06 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-12f51dfc-b101-4801-928a-b2eada8a47ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360990243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_ device_slow_rsp.2360990243 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.204819881 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 98639670305 ps |
| CPU time | 1674.46 seconds |
| Started | Aug 06 08:52:28 PM PDT 24 |
| Finished | Aug 06 09:20:23 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-7b1bf344-2063-4691-b06e-5628afec1079 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204819881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_d evice_slow_rsp.204819881 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2175373630 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 3473296530 ps |
| CPU time | 309.1 seconds |
| Started | Aug 06 08:21:53 PM PDT 24 |
| Finished | Aug 06 08:27:02 PM PDT 24 |
| Peak memory | 610228 kb |
| Host | smart-49942f89-a2ba-4db7-a5ce-1a8d652fba2f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175 373630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.2175373630 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2792526556 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 11995817893 ps |
| CPU time | 1914.16 seconds |
| Started | Aug 06 08:21:34 PM PDT 24 |
| Finished | Aug 06 08:53:29 PM PDT 24 |
| Peak memory | 617920 kb |
| Host | smart-54da5f92-6372-459d-9f84-4c3029a77bfb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2792526556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.2792526556 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.676418092 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 22189983266 ps |
| CPU time | 1434.57 seconds |
| Started | Aug 06 08:38:42 PM PDT 24 |
| Finished | Aug 06 09:02:38 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-89c3e58b-dfe4-4797-8ddd-bab65f941e1d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 676418092 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.676418092 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.3514394905 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 49628965980 ps |
| CPU time | 6326.61 seconds |
| Started | Aug 06 08:23:15 PM PDT 24 |
| Finished | Aug 06 10:08:42 PM PDT 24 |
| Peak memory | 620848 kb |
| Host | smart-a0c4aea2-ec9e-4bb4-9ae9-369fb00109e0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514394905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_dev.3514394905 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.984674765 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 69804079230 ps |
| CPU time | 1179 seconds |
| Started | Aug 06 08:54:06 PM PDT 24 |
| Finished | Aug 06 09:13:46 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-f1ba4aad-d4c3-44c5-9710-9aa530595492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=984674765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_d evice_slow_rsp.984674765 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.616817138 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 6158377480 ps |
| CPU time | 1258.47 seconds |
| Started | Aug 06 08:23:56 PM PDT 24 |
| Finished | Aug 06 08:44:55 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-52b5c2a7-989f-4076-b4c5-1814dc69d1cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=616817138 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_plic_all_irqs_0.616817138 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.4222122942 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 89065402190 ps |
| CPU time | 1501.16 seconds |
| Started | Aug 06 08:55:25 PM PDT 24 |
| Finished | Aug 06 09:20:26 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-37831f01-2b33-43dc-af52-58179e05ddb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222122942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.4222122942 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.2952561319 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 5926983824 ps |
| CPU time | 1697.14 seconds |
| Started | Aug 06 08:29:33 PM PDT 24 |
| Finished | Aug 06 08:57:50 PM PDT 24 |
| Peak memory | 624924 kb |
| Host | smart-c7b7d4b3-cb6b-4bdc-bfcd-d84476840ffd |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2952561319 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.2952561319 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3643369717 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 11134448200 ps |
| CPU time | 1241.02 seconds |
| Started | Aug 06 08:25:04 PM PDT 24 |
| Finished | Aug 06 08:45:45 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-03ada09a-7e90-4b5f-b286-1329d5f43969 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643369717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.3643369717 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.3281513366 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 2767261120 ps |
| CPU time | 299.79 seconds |
| Started | Aug 06 08:24:15 PM PDT 24 |
| Finished | Aug 06 08:29:15 PM PDT 24 |
| Peak memory | 608808 kb |
| Host | smart-c0e59969-2c53-4248-ab35-cdbb874e96e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3281513366 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.3281513366 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3615360143 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 9650032746 ps |
| CPU time | 1283.03 seconds |
| Started | Aug 06 08:42:05 PM PDT 24 |
| Finished | Aug 06 09:03:28 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-6abf15cf-8705-478d-99e4-266bf78e9eeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615360143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.3615360143 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.70152393 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 152995610434 ps |
| CPU time | 2750.02 seconds |
| Started | Aug 06 09:05:07 PM PDT 24 |
| Finished | Aug 06 09:50:57 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-c448f971-525f-42ed-be35-9dc24141aaef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70152393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_de vice_slow_rsp.70152393 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3159574912 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 24288733604 ps |
| CPU time | 7544.02 seconds |
| Started | Aug 06 08:35:56 PM PDT 24 |
| Finished | Aug 06 10:41:41 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-fe1d0dd8-9395-45f2-aa8d-f3e903d3cc6f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3159574912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.3159574912 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1299158102 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5872041990 ps |
| CPU time | 495.76 seconds |
| Started | Aug 06 08:38:15 PM PDT 24 |
| Finished | Aug 06 08:46:31 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-cc4fa918-c4fb-4ca1-86f0-4a94720e9a58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1299158102 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.1299158102 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.1427948473 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3225975760 ps |
| CPU time | 568.05 seconds |
| Started | Aug 06 08:22:56 PM PDT 24 |
| Finished | Aug 06 08:32:25 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-b5d6dab2-d203-4120-85f6-d2beab63c0fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427948473 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.1427948473 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.4263227168 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3475674056 ps |
| CPU time | 391.69 seconds |
| Started | Aug 06 08:27:00 PM PDT 24 |
| Finished | Aug 06 08:33:32 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-cee3d984-ebf4-45bf-b265-b73bd6d76082 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263227168 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_gpio.4263227168 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.4094791822 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 5999740150 ps |
| CPU time | 1948.38 seconds |
| Started | Aug 06 08:24:48 PM PDT 24 |
| Finished | Aug 06 08:57:18 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-3c9f241f-52f3-4b8d-9114-3f18238726a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094791822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.4094791822 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1791758660 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 15511477444 ps |
| CPU time | 553.05 seconds |
| Started | Aug 06 08:57:04 PM PDT 24 |
| Finished | Aug 06 09:06:17 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-68bb7f06-90a4-4d6b-bad9-024aeb880bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791758660 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.1791758660 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3710063907 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 19079758598 ps |
| CPU time | 630.62 seconds |
| Started | Aug 06 09:02:34 PM PDT 24 |
| Finished | Aug 06 09:13:04 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-bc7f1e03-922f-4255-a921-0d3441398001 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710063907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.3710063907 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3824083576 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 29088152915 ps |
| CPU time | 3529.47 seconds |
| Started | Aug 06 08:51:28 PM PDT 24 |
| Finished | Aug 06 09:50:18 PM PDT 24 |
| Peak memory | 593324 kb |
| Host | smart-08246593-1a09-4dd4-8c23-9c5e796dd445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824083576 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3824083576 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3367126090 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 10270785710 ps |
| CPU time | 2012.98 seconds |
| Started | Aug 06 08:24:40 PM PDT 24 |
| Finished | Aug 06 08:58:13 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-a031b651-2a02-44c7-8818-0f390c078203 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33671 26090 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.3367126090 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.25176171 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 4474319106 ps |
| CPU time | 481.51 seconds |
| Started | Aug 06 08:53:47 PM PDT 24 |
| Finished | Aug 06 09:01:48 PM PDT 24 |
| Peak memory | 598544 kb |
| Host | smart-bf4cc233-471c-438a-be49-37578c11b578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25176171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.25176171 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.295766705 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3042811301 ps |
| CPU time | 313.36 seconds |
| Started | Aug 06 08:26:39 PM PDT 24 |
| Finished | Aug 06 08:31:52 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-3586f063-6439-435a-97a3-f463bdf271d0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957 66705 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.295766705 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.2416101048 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 20419216776 ps |
| CPU time | 3473.66 seconds |
| Started | Aug 06 08:31:18 PM PDT 24 |
| Finished | Aug 06 09:29:12 PM PDT 24 |
| Peak memory | 609604 kb |
| Host | smart-5386a4b3-c753-4cc8-babc-b615805a8c5a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416101048 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.2416101048 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.2193817987 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 44175876648 ps |
| CPU time | 5244.52 seconds |
| Started | Aug 06 08:22:15 PM PDT 24 |
| Finished | Aug 06 09:49:42 PM PDT 24 |
| Peak memory | 621056 kb |
| Host | smart-12417f97-beb5-4451-9176-86b4f5c09be3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2193817987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.2193817987 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3616163101 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 5455427080 ps |
| CPU time | 456.35 seconds |
| Started | Aug 06 08:25:42 PM PDT 24 |
| Finished | Aug 06 08:33:20 PM PDT 24 |
| Peak memory | 608744 kb |
| Host | smart-d8a3fdf8-7cd7-4451-9299-9df26a01c365 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36161631 01 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3616163101 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2590363335 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 12640650651 ps |
| CPU time | 1311.49 seconds |
| Started | Aug 06 08:10:36 PM PDT 24 |
| Finished | Aug 06 08:32:28 PM PDT 24 |
| Peak memory | 608132 kb |
| Host | smart-c1d66bae-85b6-49a9-94f1-01787d6abf40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590363335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2590363335 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.579270742 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 8218407051 ps |
| CPU time | 89.03 seconds |
| Started | Aug 06 08:52:36 PM PDT 24 |
| Finished | Aug 06 08:54:05 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e6c17d2b-2be1-431e-89b3-f551846beb49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579270742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.579270742 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.1997149711 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3595029396 ps |
| CPU time | 204.55 seconds |
| Started | Aug 06 08:42:58 PM PDT 24 |
| Finished | Aug 06 08:46:22 PM PDT 24 |
| Peak memory | 603560 kb |
| Host | smart-d398039f-c60b-45ee-9bac-a1d4628cef95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997149711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.1997149711 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.2114290877 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 3452247904 ps |
| CPU time | 400.08 seconds |
| Started | Aug 06 08:22:59 PM PDT 24 |
| Finished | Aug 06 08:29:39 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-c1743cb5-e25f-41eb-9e6c-add4e6a6c746 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114290877 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 0.chip_sw_alert_test.2114290877 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.3360460913 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 4019276056 ps |
| CPU time | 448.99 seconds |
| Started | Aug 06 08:46:03 PM PDT 24 |
| Finished | Aug 06 08:53:33 PM PDT 24 |
| Peak memory | 649340 kb |
| Host | smart-5ac37e7c-994b-492f-baa5-b0a936f0eb99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360460913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3360460913 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2344124600 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3027533520 ps |
| CPU time | 347.82 seconds |
| Started | Aug 06 08:27:31 PM PDT 24 |
| Finished | Aug 06 08:33:19 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-9d9d9ddc-0387-4d59-bb08-53453c2b8fde |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344 124600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.2344124600 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2760111233 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 6067468750 ps |
| CPU time | 635.55 seconds |
| Started | Aug 06 08:21:02 PM PDT 24 |
| Finished | Aug 06 08:31:39 PM PDT 24 |
| Peak memory | 611048 kb |
| Host | smart-4ae2ace7-631b-48bc-965f-a584bb834db5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2760111233 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.2760111233 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.4242769279 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 3860094415 ps |
| CPU time | 315.29 seconds |
| Started | Aug 06 08:21:57 PM PDT 24 |
| Finished | Aug 06 08:27:12 PM PDT 24 |
| Peak memory | 621304 kb |
| Host | smart-5cd97db0-8504-4e54-8026-8453f2e78bc5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42427692 79 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.4242769279 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.4134476284 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 326649036 ps |
| CPU time | 29.08 seconds |
| Started | Aug 06 08:59:25 PM PDT 24 |
| Finished | Aug 06 08:59:54 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-c3d13db3-4b1f-4ea3-b57b-8f720fe8980e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134476284 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.4134476284 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.4211146769 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 6844696180 ps |
| CPU time | 816.58 seconds |
| Started | Aug 06 08:23:43 PM PDT 24 |
| Finished | Aug 06 08:37:20 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-a2cad6c9-9cd2-4321-a32c-d6fa2403eb45 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=4211146769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.4211146769 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.4229229233 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 7271865108 ps |
| CPU time | 791.53 seconds |
| Started | Aug 06 09:05:13 PM PDT 24 |
| Finished | Aug 06 09:18:25 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-0fa78c1e-9022-42ec-8668-643564203161 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229229233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all _with_rand_reset.4229229233 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2291341449 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 3173468687 ps |
| CPU time | 307.39 seconds |
| Started | Aug 06 08:28:15 PM PDT 24 |
| Finished | Aug 06 08:33:23 PM PDT 24 |
| Peak memory | 619032 kb |
| Host | smart-8031c4ca-65a7-4035-ab65-78a42232bedc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291341449 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2291341449 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.193946907 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 5220310810 ps |
| CPU time | 465.78 seconds |
| Started | Aug 06 08:26:27 PM PDT 24 |
| Finished | Aug 06 08:34:14 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-43dd9fd8-204f-4227-97ef-57d7f657d0c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=193946907 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.193946907 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2500917066 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 6066494856 ps |
| CPU time | 662.51 seconds |
| Started | Aug 06 08:22:43 PM PDT 24 |
| Finished | Aug 06 08:33:47 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-378c6fd9-c705-4863-8a15-a2a3b49026ba |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 00917066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.2500917066 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.3188966742 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 44991303760 ps |
| CPU time | 5254.42 seconds |
| Started | Aug 06 08:22:50 PM PDT 24 |
| Finished | Aug 06 09:50:25 PM PDT 24 |
| Peak memory | 620028 kb |
| Host | smart-eff1e687-818c-4cd2-b847-02391c04c5e3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3188966742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.3188966742 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.3876484031 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 4181074000 ps |
| CPU time | 257.32 seconds |
| Started | Aug 06 08:52:05 PM PDT 24 |
| Finished | Aug 06 08:56:22 PM PDT 24 |
| Peak memory | 598700 kb |
| Host | smart-d49076a9-8906-4dde-9b4a-d3ecaddc9113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876484031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.3876484031 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.13482189 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3365412172 ps |
| CPU time | 291.33 seconds |
| Started | Aug 06 08:44:02 PM PDT 24 |
| Finished | Aug 06 08:48:53 PM PDT 24 |
| Peak memory | 648552 kb |
| Host | smart-cdc8a9fe-bfc4-4244-9728-7ebb5dc10ce2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13482189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw _alert_handler_lpg_sleep_mode_alerts.13482189 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2817063588 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 4139532778 ps |
| CPU time | 429.51 seconds |
| Started | Aug 06 08:45:09 PM PDT 24 |
| Finished | Aug 06 08:52:19 PM PDT 24 |
| Peak memory | 648416 kb |
| Host | smart-365ad242-0ad8-4a26-ba17-0fcaef84e52b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817063588 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2817063588 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.1159530262 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 4170340440 ps |
| CPU time | 504.72 seconds |
| Started | Aug 06 08:46:24 PM PDT 24 |
| Finished | Aug 06 08:54:49 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-704bbe65-e7cc-443a-af68-7be861bdae11 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1159530262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.1159530262 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.821344457 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 2939691794 ps |
| CPU time | 344.91 seconds |
| Started | Aug 06 08:42:26 PM PDT 24 |
| Finished | Aug 06 08:48:11 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-96c7faa3-426e-4dfe-8b30-8283cac830a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821344457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_rand_reset.821344457 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.4062465587 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 6109317640 ps |
| CPU time | 1135.67 seconds |
| Started | Aug 06 08:37:27 PM PDT 24 |
| Finished | Aug 06 08:56:24 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-0897d036-874f-40ae-a877-0d4970fc1c60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062465587 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.4062465587 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3926652944 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 6838548350 ps |
| CPU time | 1042.05 seconds |
| Started | Aug 06 08:35:19 PM PDT 24 |
| Finished | Aug 06 08:52:42 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-e7d0c499-d673-46e4-9736-ffde795dde86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39266529 44 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3926652944 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1966069780 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 31567584548 ps |
| CPU time | 6846.19 seconds |
| Started | Aug 06 08:21:04 PM PDT 24 |
| Finished | Aug 06 10:15:11 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-d9305909-3e6a-4318-8007-af476a0099ef |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1966069780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.1966069780 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.1561358789 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 3096232937 ps |
| CPU time | 224.52 seconds |
| Started | Aug 06 08:52:36 PM PDT 24 |
| Finished | Aug 06 08:56:21 PM PDT 24 |
| Peak memory | 598564 kb |
| Host | smart-8dddc2d0-263c-449b-a567-8985c41591fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561358789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.1561358789 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.916975438 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3944922806 ps |
| CPU time | 284.77 seconds |
| Started | Aug 06 08:25:05 PM PDT 24 |
| Finished | Aug 06 08:29:50 PM PDT 24 |
| Peak memory | 624872 kb |
| Host | smart-90352552-8045-484a-9037-54b719e02ddc |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916975438 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.916975438 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.576182080 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 4120558470 ps |
| CPU time | 389.58 seconds |
| Started | Aug 06 08:24:02 PM PDT 24 |
| Finished | Aug 06 08:30:32 PM PDT 24 |
| Peak memory | 609172 kb |
| Host | smart-12dafb5b-67a6-4f07-91b7-4bd69723816c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576182080 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.576182080 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.771492183 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3204310240 ps |
| CPU time | 256.87 seconds |
| Started | Aug 06 08:24:20 PM PDT 24 |
| Finished | Aug 06 08:28:37 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-fc834749-6d78-4644-bd61-c6ddb4d59b60 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771492183 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.771492183 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.1109211203 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 3535566968 ps |
| CPU time | 272.91 seconds |
| Started | Aug 06 08:27:20 PM PDT 24 |
| Finished | Aug 06 08:31:53 PM PDT 24 |
| Peak memory | 610244 kb |
| Host | smart-7809ef16-2fab-404b-9368-28231c849204 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109211203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.1109211203 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.3370348338 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 8971710498 ps |
| CPU time | 954 seconds |
| Started | Aug 06 08:23:09 PM PDT 24 |
| Finished | Aug 06 08:39:04 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-1ca519a5-51c1-43bb-a2ac-d85904fcf9fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370348338 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.3370348338 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3922985917 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 8556309829 ps |
| CPU time | 1326.73 seconds |
| Started | Aug 06 08:40:32 PM PDT 24 |
| Finished | Aug 06 09:02:40 PM PDT 24 |
| Peak memory | 618960 kb |
| Host | smart-0137f3b7-e82c-4f8b-9052-e04a481c0163 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922985917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3922985917 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.790942530 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 57545615626 ps |
| CPU time | 11004.1 seconds |
| Started | Aug 06 08:26:17 PM PDT 24 |
| Finished | Aug 06 11:29:42 PM PDT 24 |
| Peak memory | 624804 kb |
| Host | smart-29ae2c88-97c9-4dee-ac1a-f97882002016 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=790942530 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.790942530 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2345730015 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 14748140850 ps |
| CPU time | 2145.85 seconds |
| Started | Aug 06 08:48:41 PM PDT 24 |
| Finished | Aug 06 09:24:27 PM PDT 24 |
| Peak memory | 592928 kb |
| Host | smart-3738fcbf-adc2-47e0-a3b0-dbda07174a64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345730015 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 11.chip_same_csr_outstanding.2345730015 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.766492908 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 8054151472 ps |
| CPU time | 484.12 seconds |
| Started | Aug 06 08:44:29 PM PDT 24 |
| Finished | Aug 06 08:52:33 PM PDT 24 |
| Peak memory | 664064 kb |
| Host | smart-a8320e21-9ba8-45c3-a934-376afa9a26d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766492908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_re set.766492908 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.975138550 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 41847749055 ps |
| CPU time | 3927.18 seconds |
| Started | Aug 06 08:28:37 PM PDT 24 |
| Finished | Aug 06 09:34:05 PM PDT 24 |
| Peak memory | 612664 kb |
| Host | smart-08c4e749-9e0a-46a1-87b8-c49e650a21d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975138550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glitc h_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sl eep_power_glitch_reset.975138550 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.1398113738 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 8977545902 ps |
| CPU time | 562.51 seconds |
| Started | Aug 06 08:43:34 PM PDT 24 |
| Finished | Aug 06 08:52:57 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-d0ae9b97-a09f-48b1-aa32-9bcfca148d93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398113738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_ with_rand_reset.1398113738 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.3246345115 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 3427762155 ps |
| CPU time | 242.98 seconds |
| Started | Aug 06 08:50:36 PM PDT 24 |
| Finished | Aug 06 08:54:39 PM PDT 24 |
| Peak memory | 603764 kb |
| Host | smart-c453be82-aadf-4a2c-91b3-64678b02e1b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246345115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.3246345115 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1997581066 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 5526021572 ps |
| CPU time | 359.91 seconds |
| Started | Aug 06 08:52:12 PM PDT 24 |
| Finished | Aug 06 08:58:12 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-c64e2273-a007-431e-ba8d-08cbc661f04f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997581066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.1997581066 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.2670810238 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 6134161620 ps |
| CPU time | 1212.44 seconds |
| Started | Aug 06 08:22:17 PM PDT 24 |
| Finished | Aug 06 08:42:30 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-8d2a8728-cfa3-44b6-ae99-36690acf5d41 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670810238 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.2670810238 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.2644602332 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 9237533559 ps |
| CPU time | 915.65 seconds |
| Started | Aug 06 08:44:29 PM PDT 24 |
| Finished | Aug 06 08:59:44 PM PDT 24 |
| Peak memory | 646792 kb |
| Host | smart-4b40180b-af73-40d7-82fa-2a7121ee86d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644602332 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.2644602332 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.20150965 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 6100595201 ps |
| CPU time | 728.46 seconds |
| Started | Aug 06 09:00:00 PM PDT 24 |
| Finished | Aug 06 09:12:08 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-0b23dda1-dbfe-48c0-9df9-d2e58a41ba10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20150965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_w ith_rand_reset.20150965 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3367403755 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 7487859560 ps |
| CPU time | 530.6 seconds |
| Started | Aug 06 08:22:19 PM PDT 24 |
| Finished | Aug 06 08:31:11 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-dc116a24-d6e0-4dd1-8557-5ce41cf39afb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367403755 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.3367403755 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1179186605 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 6050021842 ps |
| CPU time | 432.42 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:10:21 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-36ce8f72-e130-4f72-9bfd-caffb1066be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179186605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all _with_rand_reset.1179186605 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.937813598 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4179605334 ps |
| CPU time | 747.68 seconds |
| Started | Aug 06 08:18:15 PM PDT 24 |
| Finished | Aug 06 08:30:44 PM PDT 24 |
| Peak memory | 623880 kb |
| Host | smart-bb012b1b-c505-4373-8586-2e35dd6f5b6c |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937813598 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.937813598 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2949674336 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5352151236 ps |
| CPU time | 641.34 seconds |
| Started | Aug 06 08:23:34 PM PDT 24 |
| Finished | Aug 06 08:34:16 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-4c87f53d-f2a4-42e7-81f4-d697fafcd7f9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29496743 36 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.2949674336 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.860838205 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 49710553991 ps |
| CPU time | 6090.96 seconds |
| Started | Aug 06 08:22:35 PM PDT 24 |
| Finished | Aug 06 10:04:07 PM PDT 24 |
| Peak memory | 620956 kb |
| Host | smart-3717b581-888a-45c3-a3e3-ea638f372842 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860838205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_prod.860838205 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1262002241 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 3653553080 ps |
| CPU time | 483.28 seconds |
| Started | Aug 06 08:26:49 PM PDT 24 |
| Finished | Aug 06 08:34:53 PM PDT 24 |
| Peak memory | 619720 kb |
| Host | smart-907aaa05-3f80-47c5-9551-e82a2d249b71 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 262002241 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.1262002241 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3225326394 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 3153557614 ps |
| CPU time | 429.83 seconds |
| Started | Aug 06 08:27:54 PM PDT 24 |
| Finished | Aug 06 08:35:04 PM PDT 24 |
| Peak memory | 608984 kb |
| Host | smart-3f1c55f6-9735-4bb0-b0de-2cf7421787f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32253263 94 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.3225326394 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.2638322031 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 5252864312 ps |
| CPU time | 604.91 seconds |
| Started | Aug 06 08:48:41 PM PDT 24 |
| Finished | Aug 06 08:58:46 PM PDT 24 |
| Peak memory | 603620 kb |
| Host | smart-b7642497-536a-4ae7-9d65-90c7ff68f456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638322031 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.2638322031 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.977097340 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 4891076600 ps |
| CPU time | 723.62 seconds |
| Started | Aug 06 08:27:15 PM PDT 24 |
| Finished | Aug 06 08:39:19 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-9b4021d6-a688-4f06-adb2-976cd7252208 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977097340 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_20.977097340 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.2781849417 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 6269498523 ps |
| CPU time | 794.99 seconds |
| Started | Aug 06 08:46:16 PM PDT 24 |
| Finished | Aug 06 08:59:32 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-da21993e-93c5-4923-a497-ea3b333f07c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781849417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_ with_rand_reset.2781849417 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.1244988702 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 4376770923 ps |
| CPU time | 326.7 seconds |
| Started | Aug 06 08:39:42 PM PDT 24 |
| Finished | Aug 06 08:45:09 PM PDT 24 |
| Peak memory | 656340 kb |
| Host | smart-8cdef8b2-353e-4b8e-b25a-e81df2832f5f |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244988702 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 0.chip_padctrl_attributes.1244988702 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.3428417991 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 11535920941 ps |
| CPU time | 693.64 seconds |
| Started | Aug 06 08:55:02 PM PDT 24 |
| Finished | Aug 06 09:06:36 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-db6612df-0109-4019-ba91-7c075c2a62da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428417991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.3428417991 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3880527937 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 4633703730 ps |
| CPU time | 842.97 seconds |
| Started | Aug 06 08:21:36 PM PDT 24 |
| Finished | Aug 06 08:35:40 PM PDT 24 |
| Peak memory | 624188 kb |
| Host | smart-92cb43f6-6c9c-47d8-9643-2eb04ac42b43 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880527937 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.3880527937 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2149354546 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 18380214326 ps |
| CPU time | 2784.71 seconds |
| Started | Aug 06 08:22:29 PM PDT 24 |
| Finished | Aug 06 09:08:55 PM PDT 24 |
| Peak memory | 611144 kb |
| Host | smart-81108130-73a2-422b-ab11-33ebb8323b37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149354546 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.2149354546 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.516273748 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2798440379 ps |
| CPU time | 195.65 seconds |
| Started | Aug 06 08:48:09 PM PDT 24 |
| Finished | Aug 06 08:51:24 PM PDT 24 |
| Peak memory | 598672 kb |
| Host | smart-b3616901-c20a-47d3-a3ba-1d60077a20ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516273748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.516273748 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.4173502508 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 10617023831 ps |
| CPU time | 589.99 seconds |
| Started | Aug 06 08:44:24 PM PDT 24 |
| Finished | Aug 06 08:54:14 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-f887be45-6400-44ff-a587-90fcfc65ad94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173502508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.4173502508 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.1935565643 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5216349584 ps |
| CPU time | 865.36 seconds |
| Started | Aug 06 08:22:11 PM PDT 24 |
| Finished | Aug 06 08:36:37 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-40b97f0f-61ee-474b-abd1-75ab7f771c58 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935565643 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1935565643 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.636738800 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 8958866424 ps |
| CPU time | 1779.39 seconds |
| Started | Aug 06 08:22:52 PM PDT 24 |
| Finished | Aug 06 08:52:32 PM PDT 24 |
| Peak memory | 623256 kb |
| Host | smart-ce3154b9-19c3-4d9c-a23f-63b486f07e41 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=636738800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.636738800 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2905619347 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 42928522800 ps |
| CPU time | 5357.85 seconds |
| Started | Aug 06 08:23:40 PM PDT 24 |
| Finished | Aug 06 09:52:59 PM PDT 24 |
| Peak memory | 621152 kb |
| Host | smart-84047ce4-541d-438f-ace4-adb964c2bcc3 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2905619347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.2905619347 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.1094698626 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 2847441948 ps |
| CPU time | 252.74 seconds |
| Started | Aug 06 08:52:29 PM PDT 24 |
| Finished | Aug 06 08:56:42 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-9c90f40d-76e3-4b65-9f6b-f7ec82bffe57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094698626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.1094698626 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.2352056020 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2110951405 ps |
| CPU time | 73.3 seconds |
| Started | Aug 06 08:55:39 PM PDT 24 |
| Finished | Aug 06 08:56:52 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-91bdc2e2-37d5-48b0-94ad-831b6011731a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352056020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.2352056020 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.165170969 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 4209052480 ps |
| CPU time | 673.73 seconds |
| Started | Aug 06 08:25:52 PM PDT 24 |
| Finished | Aug 06 08:37:06 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-febec5f5-3656-44ac-b3f4-c25da0be1cdc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165170969 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_10.165170969 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.770887786 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 5536326004 ps |
| CPU time | 605.13 seconds |
| Started | Aug 06 08:24:20 PM PDT 24 |
| Finished | Aug 06 08:34:25 PM PDT 24 |
| Peak memory | 649788 kb |
| Host | smart-14078156-2d7b-44e9-bd34-1e40eb2d893a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 770887786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.770887786 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.937116881 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 3662108280 ps |
| CPU time | 654.55 seconds |
| Started | Aug 06 08:24:25 PM PDT 24 |
| Finished | Aug 06 08:35:20 PM PDT 24 |
| Peak memory | 612104 kb |
| Host | smart-22e55cf7-bd47-49e7-aa8e-ee4a8ba5ee90 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937116881 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.937116881 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.1473761198 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 1163335723 ps |
| CPU time | 360.45 seconds |
| Started | Aug 06 09:01:05 PM PDT 24 |
| Finished | Aug 06 09:07:06 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-579a2d19-a714-451b-bc8e-99d4eded29f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473761198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all _with_rand_reset.1473761198 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3403350497 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3342523200 ps |
| CPU time | 206.51 seconds |
| Started | Aug 06 08:23:20 PM PDT 24 |
| Finished | Aug 06 08:26:47 PM PDT 24 |
| Peak memory | 609116 kb |
| Host | smart-8c471741-957a-4e45-b8cf-77b1126f6223 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3403350497 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3403350497 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.1084494591 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 4089815848 ps |
| CPU time | 669.7 seconds |
| Started | Aug 06 08:37:46 PM PDT 24 |
| Finished | Aug 06 08:48:56 PM PDT 24 |
| Peak memory | 608540 kb |
| Host | smart-fc36c40f-990b-4c0a-aa2e-d9f41e9f3f42 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084494591 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.1084494591 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.909011454 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 5037803654 ps |
| CPU time | 651.24 seconds |
| Started | Aug 06 08:42:38 PM PDT 24 |
| Finished | Aug 06 08:53:30 PM PDT 24 |
| Peak memory | 649816 kb |
| Host | smart-b7267d98-7550-4897-9921-f6be34f0b366 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 909011454 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.909011454 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.1736413971 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 304610993 ps |
| CPU time | 67.27 seconds |
| Started | Aug 06 08:54:22 PM PDT 24 |
| Finished | Aug 06 08:55:30 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-6523d39c-f1a8-41ca-818a-a40936370541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736413971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.1736413971 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.490856842 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2008311367 ps |
| CPU time | 111.42 seconds |
| Started | Aug 06 08:27:45 PM PDT 24 |
| Finished | Aug 06 08:29:37 PM PDT 24 |
| Peak memory | 622988 kb |
| Host | smart-23800347-eb4d-471b-8bdd-4e03135f6a78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490856842 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.490856842 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1756966728 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 4265902420 ps |
| CPU time | 598.48 seconds |
| Started | Aug 06 08:21:29 PM PDT 24 |
| Finished | Aug 06 08:31:29 PM PDT 24 |
| Peak memory | 608600 kb |
| Host | smart-eff4f237-1b27-4a32-a397-df258bae1d8e |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175696 6728 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.1756966728 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.1104022626 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 18554659045 ps |
| CPU time | 714.56 seconds |
| Started | Aug 06 08:57:33 PM PDT 24 |
| Finished | Aug 06 09:09:27 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-7c09005a-a7c2-41b8-aeda-a298ec7c4e60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104022626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.1104022626 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.3441567736 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 6077953484 ps |
| CPU time | 902.45 seconds |
| Started | Aug 06 08:57:49 PM PDT 24 |
| Finished | Aug 06 09:12:51 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-10f084e1-1d55-4e39-b3d8-8d6343ac0a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441567736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all _with_rand_reset.3441567736 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2420651486 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 4935693900 ps |
| CPU time | 636.32 seconds |
| Started | Aug 06 08:26:25 PM PDT 24 |
| Finished | Aug 06 08:37:01 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-143fd0ba-7fb0-4022-982e-fc91589c7a8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2420651486 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.2420651486 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.1398476817 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 3738402888 ps |
| CPU time | 403.66 seconds |
| Started | Aug 06 08:42:47 PM PDT 24 |
| Finished | Aug 06 08:49:31 PM PDT 24 |
| Peak memory | 648640 kb |
| Host | smart-5cb836b7-a4ad-4b7a-8e9d-becc07ddffd8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398476817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1398476817 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3034942908 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 7094462952 ps |
| CPU time | 507.85 seconds |
| Started | Aug 06 08:32:27 PM PDT 24 |
| Finished | Aug 06 08:40:56 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-993e3551-9c8e-42f3-b1fb-407f35863505 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034942908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3034942908 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.3031687443 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 5546389550 ps |
| CPU time | 547.55 seconds |
| Started | Aug 06 08:42:52 PM PDT 24 |
| Finished | Aug 06 08:51:59 PM PDT 24 |
| Peak memory | 649992 kb |
| Host | smart-ab8c87e4-d1cd-4210-8e51-c1c2966fd003 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3031687443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.3031687443 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.3866079046 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 6239823368 ps |
| CPU time | 321.75 seconds |
| Started | Aug 06 08:56:13 PM PDT 24 |
| Finished | Aug 06 09:01:34 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-d22def6b-1efe-442f-a014-5c0ef271776d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866079046 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.3866079046 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.282150789 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 11444456750 ps |
| CPU time | 1820.21 seconds |
| Started | Aug 06 08:25:31 PM PDT 24 |
| Finished | Aug 06 08:55:52 PM PDT 24 |
| Peak memory | 611008 kb |
| Host | smart-8abcf9c5-818d-4876-b2ba-8537a4c171dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=282150789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.282150789 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.2371801867 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 3599576648 ps |
| CPU time | 330.59 seconds |
| Started | Aug 06 08:52:54 PM PDT 24 |
| Finished | Aug 06 08:58:25 PM PDT 24 |
| Peak memory | 598552 kb |
| Host | smart-804aa227-1d40-4469-ada6-c0e2cb1f53ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371801867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.2371801867 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.928188600 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 4007198144 ps |
| CPU time | 469.41 seconds |
| Started | Aug 06 08:43:40 PM PDT 24 |
| Finished | Aug 06 08:51:30 PM PDT 24 |
| Peak memory | 648776 kb |
| Host | smart-ff24a805-a8c2-4c8a-bbd9-4d2c968d243d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928188600 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_s w_alert_handler_lpg_sleep_mode_alerts.928188600 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.954240047 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 4527737410 ps |
| CPU time | 724.79 seconds |
| Started | Aug 06 08:41:40 PM PDT 24 |
| Finished | Aug 06 08:53:45 PM PDT 24 |
| Peak memory | 650476 kb |
| Host | smart-770e26f8-92a1-4afe-82ad-f5b9db90e013 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 954240047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.954240047 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.1002041484 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 5957254625 ps |
| CPU time | 401.84 seconds |
| Started | Aug 06 08:42:32 PM PDT 24 |
| Finished | Aug 06 08:49:14 PM PDT 24 |
| Peak memory | 664620 kb |
| Host | smart-2990394f-b9de-40fa-b5fa-a214b0ce618b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002041484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.1002041484 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.1703820157 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 271367038 ps |
| CPU time | 107.93 seconds |
| Started | Aug 06 08:52:31 PM PDT 24 |
| Finished | Aug 06 08:54:19 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-6f27f563-4882-4fe8-86ad-20dd10d7f2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703820157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.1703820157 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1354191371 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 4079433724 ps |
| CPU time | 358.11 seconds |
| Started | Aug 06 08:26:07 PM PDT 24 |
| Finished | Aug 06 08:32:07 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-9d884913-c40a-4f19-9efe-7651e97bcb8d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354191371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_alert_handler_lpg_sleep_mode_alerts.1354191371 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3838352565 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 3714444666 ps |
| CPU time | 433.62 seconds |
| Started | Aug 06 08:24:54 PM PDT 24 |
| Finished | Aug 06 08:32:08 PM PDT 24 |
| Peak memory | 648416 kb |
| Host | smart-52792bf3-55a3-445f-8fbe-61dd4d004f13 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838352565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.3838352565 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.3959428231 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 4711293104 ps |
| CPU time | 606.63 seconds |
| Started | Aug 06 08:24:45 PM PDT 24 |
| Finished | Aug 06 08:34:52 PM PDT 24 |
| Peak memory | 650188 kb |
| Host | smart-5b41e277-f55a-45a4-a54c-668fcafaa48b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3959428231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.3959428231 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3016032049 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 3896015136 ps |
| CPU time | 407.8 seconds |
| Started | Aug 06 08:41:59 PM PDT 24 |
| Finished | Aug 06 08:48:47 PM PDT 24 |
| Peak memory | 648936 kb |
| Host | smart-45d17284-2504-466c-8976-4fa4c52d1e1e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016032049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3016032049 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.1006954320 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5972655898 ps |
| CPU time | 627.27 seconds |
| Started | Aug 06 08:41:46 PM PDT 24 |
| Finished | Aug 06 08:52:14 PM PDT 24 |
| Peak memory | 649596 kb |
| Host | smart-47c1a5c8-8de1-46a0-a23f-ec0fb0e356bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1006954320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.1006954320 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.1861195647 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 5578515256 ps |
| CPU time | 831.56 seconds |
| Started | Aug 06 08:41:24 PM PDT 24 |
| Finished | Aug 06 08:55:15 PM PDT 24 |
| Peak memory | 649880 kb |
| Host | smart-777686de-644d-4e32-ba28-d7e9e9e95ed6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1861195647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.1861195647 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.2940862743 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 4482510200 ps |
| CPU time | 664.65 seconds |
| Started | Aug 06 08:43:09 PM PDT 24 |
| Finished | Aug 06 08:54:15 PM PDT 24 |
| Peak memory | 649640 kb |
| Host | smart-3945ec49-7e80-4499-9431-ef7325148509 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2940862743 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.2940862743 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2984221283 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 3480323008 ps |
| CPU time | 525.39 seconds |
| Started | Aug 06 08:42:17 PM PDT 24 |
| Finished | Aug 06 08:51:03 PM PDT 24 |
| Peak memory | 649024 kb |
| Host | smart-9226f808-30b6-4f06-8499-0ca4aa83c036 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984221283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2984221283 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.2980753835 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 5008470800 ps |
| CPU time | 710.67 seconds |
| Started | Aug 06 08:44:27 PM PDT 24 |
| Finished | Aug 06 08:56:19 PM PDT 24 |
| Peak memory | 649980 kb |
| Host | smart-ff7406a7-28d1-498b-a3e7-5f71a6e2cc96 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2980753835 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2980753835 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.830592993 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3782107704 ps |
| CPU time | 443.26 seconds |
| Started | Aug 06 08:42:05 PM PDT 24 |
| Finished | Aug 06 08:49:29 PM PDT 24 |
| Peak memory | 648756 kb |
| Host | smart-7590f7ec-ca66-4dc1-922b-9b91c727ebce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830592993 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_s w_alert_handler_lpg_sleep_mode_alerts.830592993 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.1932124418 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 5915533080 ps |
| CPU time | 950.88 seconds |
| Started | Aug 06 08:42:36 PM PDT 24 |
| Finished | Aug 06 08:58:28 PM PDT 24 |
| Peak memory | 649936 kb |
| Host | smart-373047a4-1842-44d5-9c16-2f2804672e3a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1932124418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.1932124418 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830087565 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 3783690800 ps |
| CPU time | 351.89 seconds |
| Started | Aug 06 08:41:47 PM PDT 24 |
| Finished | Aug 06 08:47:40 PM PDT 24 |
| Peak memory | 648792 kb |
| Host | smart-bd6a725a-37f0-470e-b8d4-73f4a88b7b72 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830087565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3830087565 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.414416700 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 5238590010 ps |
| CPU time | 570.13 seconds |
| Started | Aug 06 08:43:08 PM PDT 24 |
| Finished | Aug 06 08:52:38 PM PDT 24 |
| Peak memory | 650212 kb |
| Host | smart-d3f395e4-8fa2-4c0a-a0ef-7062751ac673 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 414416700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.414416700 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.884650995 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 3841242008 ps |
| CPU time | 395.92 seconds |
| Started | Aug 06 08:41:59 PM PDT 24 |
| Finished | Aug 06 08:48:35 PM PDT 24 |
| Peak memory | 648708 kb |
| Host | smart-98ab6f75-8aae-466f-9fe5-e19628c824d5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884650995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_s w_alert_handler_lpg_sleep_mode_alerts.884650995 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.3363327998 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 4930668944 ps |
| CPU time | 577.08 seconds |
| Started | Aug 06 08:43:32 PM PDT 24 |
| Finished | Aug 06 08:53:09 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-a3389a76-459d-4930-a35a-1529fbdf040f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3363327998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.3363327998 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.63537488 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 3246469608 ps |
| CPU time | 495.36 seconds |
| Started | Aug 06 08:45:38 PM PDT 24 |
| Finished | Aug 06 08:53:54 PM PDT 24 |
| Peak memory | 648672 kb |
| Host | smart-a85c26c9-6b53-4749-9595-8aeccc561fc7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63537488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw _alert_handler_lpg_sleep_mode_alerts.63537488 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.4149171117 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 3935187126 ps |
| CPU time | 396.94 seconds |
| Started | Aug 06 08:35:09 PM PDT 24 |
| Finished | Aug 06 08:41:46 PM PDT 24 |
| Peak memory | 648704 kb |
| Host | smart-7b4ba030-9f53-4b71-8e0a-0a7a92963dbc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149171117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.4149171117 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.3770136438 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 6039753328 ps |
| CPU time | 804.98 seconds |
| Started | Aug 06 08:24:23 PM PDT 24 |
| Finished | Aug 06 08:37:49 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-e416b08a-0a3d-49ae-84e8-a8e838fa667f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3770136438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.3770136438 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.234243505 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4001746018 ps |
| CPU time | 453.23 seconds |
| Started | Aug 06 08:43:09 PM PDT 24 |
| Finished | Aug 06 08:50:42 PM PDT 24 |
| Peak memory | 648804 kb |
| Host | smart-326ffa51-0620-4aac-a9b6-68d9bd21863b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234243505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_s w_alert_handler_lpg_sleep_mode_alerts.234243505 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.201565691 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 5370821470 ps |
| CPU time | 656.52 seconds |
| Started | Aug 06 08:42:40 PM PDT 24 |
| Finished | Aug 06 08:53:37 PM PDT 24 |
| Peak memory | 649820 kb |
| Host | smart-abb8bbb1-e252-413c-9df2-03daf1be45a5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 201565691 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.201565691 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.347431251 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4447773112 ps |
| CPU time | 532.67 seconds |
| Started | Aug 06 08:42:11 PM PDT 24 |
| Finished | Aug 06 08:51:04 PM PDT 24 |
| Peak memory | 648952 kb |
| Host | smart-38c92b36-950b-4f89-9599-cdc76316d705 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347431251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_s w_alert_handler_lpg_sleep_mode_alerts.347431251 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.1850407688 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 6339454570 ps |
| CPU time | 742.23 seconds |
| Started | Aug 06 08:44:04 PM PDT 24 |
| Finished | Aug 06 08:56:26 PM PDT 24 |
| Peak memory | 650088 kb |
| Host | smart-5dd3caa6-b2fd-4273-8718-473a58f293cb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1850407688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.1850407688 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.1476487308 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 5392620794 ps |
| CPU time | 619.99 seconds |
| Started | Aug 06 08:42:50 PM PDT 24 |
| Finished | Aug 06 08:53:10 PM PDT 24 |
| Peak memory | 649932 kb |
| Host | smart-666324cc-ab6c-4400-b89a-b229ad009dd5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1476487308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.1476487308 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.4098665061 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 4911231380 ps |
| CPU time | 720.05 seconds |
| Started | Aug 06 08:42:36 PM PDT 24 |
| Finished | Aug 06 08:54:36 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-b85c19a1-316f-4b99-8025-c8f83d460030 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4098665061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.4098665061 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.893660438 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3586295752 ps |
| CPU time | 296.45 seconds |
| Started | Aug 06 08:44:21 PM PDT 24 |
| Finished | Aug 06 08:49:17 PM PDT 24 |
| Peak memory | 648720 kb |
| Host | smart-4b5c8b2e-0099-4d52-bf5b-3c29bf208d74 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893660438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_s w_alert_handler_lpg_sleep_mode_alerts.893660438 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1221188860 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 3483721892 ps |
| CPU time | 364.77 seconds |
| Started | Aug 06 08:43:10 PM PDT 24 |
| Finished | Aug 06 08:49:15 PM PDT 24 |
| Peak memory | 648820 kb |
| Host | smart-bb306388-dd35-4383-ac3b-621790fe72f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221188860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1221188860 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.3347024186 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 5557918300 ps |
| CPU time | 546.92 seconds |
| Started | Aug 06 08:40:13 PM PDT 24 |
| Finished | Aug 06 08:49:20 PM PDT 24 |
| Peak memory | 649936 kb |
| Host | smart-aa4f31bc-ceb3-41f7-bf37-a25074a9cb7c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3347024186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.3347024186 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3518417417 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 3422318562 ps |
| CPU time | 359.52 seconds |
| Started | Aug 06 08:46:56 PM PDT 24 |
| Finished | Aug 06 08:52:55 PM PDT 24 |
| Peak memory | 650252 kb |
| Host | smart-e537dd5b-712f-41e9-a163-7c813fc4dd97 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518417417 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3518417417 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.1277529765 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 5958908496 ps |
| CPU time | 783.1 seconds |
| Started | Aug 06 08:43:56 PM PDT 24 |
| Finished | Aug 06 08:56:59 PM PDT 24 |
| Peak memory | 650004 kb |
| Host | smart-86365c4d-3346-4225-87d1-235c7b4afd59 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1277529765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.1277529765 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2265639762 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 4023055420 ps |
| CPU time | 404.81 seconds |
| Started | Aug 06 08:47:05 PM PDT 24 |
| Finished | Aug 06 08:53:49 PM PDT 24 |
| Peak memory | 648716 kb |
| Host | smart-e2def0aa-9467-421c-beef-4f17fd35fbdd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265639762 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2265639762 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.4251166554 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 5492437080 ps |
| CPU time | 701.29 seconds |
| Started | Aug 06 08:45:00 PM PDT 24 |
| Finished | Aug 06 08:56:42 PM PDT 24 |
| Peak memory | 649896 kb |
| Host | smart-dbb6d760-1375-46d1-901f-6fffcadffc98 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4251166554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.4251166554 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.300782981 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 3928233000 ps |
| CPU time | 483.57 seconds |
| Started | Aug 06 08:43:49 PM PDT 24 |
| Finished | Aug 06 08:51:53 PM PDT 24 |
| Peak memory | 648684 kb |
| Host | smart-1406d034-1f9f-4323-bcde-3a34ed257bf4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300782981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_s w_alert_handler_lpg_sleep_mode_alerts.300782981 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.3035567060 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 5376891854 ps |
| CPU time | 835.2 seconds |
| Started | Aug 06 08:43:52 PM PDT 24 |
| Finished | Aug 06 08:57:47 PM PDT 24 |
| Peak memory | 649540 kb |
| Host | smart-6a7f1854-ce90-4715-a70f-441e9bb3ced9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3035567060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.3035567060 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3995771264 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 3052330792 ps |
| CPU time | 370.38 seconds |
| Started | Aug 06 08:43:48 PM PDT 24 |
| Finished | Aug 06 08:49:58 PM PDT 24 |
| Peak memory | 648428 kb |
| Host | smart-7a1dff8d-0a2b-422d-ae9f-429411958096 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995771264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3995771264 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2319849612 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 4452475872 ps |
| CPU time | 408.86 seconds |
| Started | Aug 06 08:43:12 PM PDT 24 |
| Finished | Aug 06 08:50:01 PM PDT 24 |
| Peak memory | 649040 kb |
| Host | smart-91148713-35c3-400b-926e-3ccb1b6ae9f6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319849612 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2319849612 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.1055623228 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 5587043912 ps |
| CPU time | 622.87 seconds |
| Started | Aug 06 08:42:18 PM PDT 24 |
| Finished | Aug 06 08:52:41 PM PDT 24 |
| Peak memory | 649768 kb |
| Host | smart-ae40d0c2-d7f2-441e-9044-56e34fdb52fd |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1055623228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.1055623228 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.3829822570 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 4365907898 ps |
| CPU time | 572.8 seconds |
| Started | Aug 06 08:40:13 PM PDT 24 |
| Finished | Aug 06 08:49:47 PM PDT 24 |
| Peak memory | 649744 kb |
| Host | smart-b8149f5a-a73a-410a-8d85-176a8002900e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3829822570 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.3829822570 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388803271 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3199186332 ps |
| CPU time | 515.53 seconds |
| Started | Aug 06 08:44:28 PM PDT 24 |
| Finished | Aug 06 08:53:04 PM PDT 24 |
| Peak memory | 648784 kb |
| Host | smart-6729ae5a-46cc-41d8-96b0-68353dcecf8c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388803271 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3388803271 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.1498596921 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 5165633984 ps |
| CPU time | 675.73 seconds |
| Started | Aug 06 08:44:19 PM PDT 24 |
| Finished | Aug 06 08:55:35 PM PDT 24 |
| Peak memory | 649672 kb |
| Host | smart-da0ea7e5-5fd0-4bdf-80e6-b3741a4aa5dc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1498596921 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.1498596921 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.969917816 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 3907379952 ps |
| CPU time | 456.04 seconds |
| Started | Aug 06 08:43:57 PM PDT 24 |
| Finished | Aug 06 08:51:33 PM PDT 24 |
| Peak memory | 648908 kb |
| Host | smart-39f969e6-1641-45f7-9183-f7bc3fb5c619 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=969917816 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_s w_alert_handler_lpg_sleep_mode_alerts.969917816 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2895996473 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 4244181710 ps |
| CPU time | 468.54 seconds |
| Started | Aug 06 08:44:46 PM PDT 24 |
| Finished | Aug 06 08:52:34 PM PDT 24 |
| Peak memory | 648752 kb |
| Host | smart-8a59cff0-bae8-4118-821b-8f7e10d3bd6b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895996473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2895996473 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3118244545 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 4417068620 ps |
| CPU time | 365.62 seconds |
| Started | Aug 06 08:43:36 PM PDT 24 |
| Finished | Aug 06 08:49:41 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-1298bc5f-9f6c-4536-8945-ae10460c1d69 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118244545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3118244545 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2576352475 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3584679674 ps |
| CPU time | 396.11 seconds |
| Started | Aug 06 08:43:53 PM PDT 24 |
| Finished | Aug 06 08:50:29 PM PDT 24 |
| Peak memory | 648688 kb |
| Host | smart-c57ebab8-4926-4d19-b678-e1461c774962 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2576352475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2576352475 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.196381655 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 4128444854 ps |
| CPU time | 476.9 seconds |
| Started | Aug 06 08:43:27 PM PDT 24 |
| Finished | Aug 06 08:51:24 PM PDT 24 |
| Peak memory | 648660 kb |
| Host | smart-f0bd1e5c-ee5d-4d8d-9632-d352a075a7a1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196381655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_s w_alert_handler_lpg_sleep_mode_alerts.196381655 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.3647720133 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 6162645908 ps |
| CPU time | 708.05 seconds |
| Started | Aug 06 08:44:23 PM PDT 24 |
| Finished | Aug 06 08:56:11 PM PDT 24 |
| Peak memory | 649988 kb |
| Host | smart-180a5185-ff5b-41fb-876e-2962dd8f1423 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3647720133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.3647720133 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1452823188 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 3408486120 ps |
| CPU time | 431.12 seconds |
| Started | Aug 06 08:50:14 PM PDT 24 |
| Finished | Aug 06 08:57:25 PM PDT 24 |
| Peak memory | 648672 kb |
| Host | smart-af013504-7d50-4f23-8bcc-847d9af0b750 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452823188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1452823188 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.484491723 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 5698207550 ps |
| CPU time | 640.86 seconds |
| Started | Aug 06 08:45:43 PM PDT 24 |
| Finished | Aug 06 08:56:24 PM PDT 24 |
| Peak memory | 649584 kb |
| Host | smart-f4deb65a-cdd9-4881-bf96-a31f8943fa3a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 484491723 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.484491723 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852088991 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 3439831554 ps |
| CPU time | 337.14 seconds |
| Started | Aug 06 08:44:32 PM PDT 24 |
| Finished | Aug 06 08:50:09 PM PDT 24 |
| Peak memory | 648792 kb |
| Host | smart-3bf9fd08-3bea-479f-bded-cf2cd34ed4f3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852088991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1852088991 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.3227528419 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 6144831928 ps |
| CPU time | 845.68 seconds |
| Started | Aug 06 08:46:35 PM PDT 24 |
| Finished | Aug 06 09:00:41 PM PDT 24 |
| Peak memory | 649588 kb |
| Host | smart-3285a784-4af2-4955-811f-91062adf4a01 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3227528419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.3227528419 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.994281244 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 4346313438 ps |
| CPU time | 390.29 seconds |
| Started | Aug 06 08:43:53 PM PDT 24 |
| Finished | Aug 06 08:50:24 PM PDT 24 |
| Peak memory | 649156 kb |
| Host | smart-df74e92b-a496-4238-bdc1-68a3436fa0ad |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994281244 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_s w_alert_handler_lpg_sleep_mode_alerts.994281244 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.39349578 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 4834570856 ps |
| CPU time | 666.05 seconds |
| Started | Aug 06 08:44:29 PM PDT 24 |
| Finished | Aug 06 08:55:35 PM PDT 24 |
| Peak memory | 649976 kb |
| Host | smart-ac44f5ca-d416-43c1-87b9-365f15c36bdf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 39349578 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.39349578 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.4213492262 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 4607317212 ps |
| CPU time | 584.72 seconds |
| Started | Aug 06 08:45:53 PM PDT 24 |
| Finished | Aug 06 08:55:38 PM PDT 24 |
| Peak memory | 649952 kb |
| Host | smart-1be00aef-1cc9-4f9e-8777-fab3bafe7376 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4213492262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.4213492262 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.1839004634 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 5400903738 ps |
| CPU time | 619.22 seconds |
| Started | Aug 06 08:40:24 PM PDT 24 |
| Finished | Aug 06 08:50:44 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-92c027c4-43e4-4d67-9179-88e55bc6c888 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1839004634 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.1839004634 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.3357286975 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 5679970088 ps |
| CPU time | 693.07 seconds |
| Started | Aug 06 08:45:31 PM PDT 24 |
| Finished | Aug 06 08:57:04 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-65398fda-6c67-4a78-aaae-a6b6b7e5d503 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3357286975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.3357286975 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398041158 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4471005564 ps |
| CPU time | 393.51 seconds |
| Started | Aug 06 08:44:18 PM PDT 24 |
| Finished | Aug 06 08:50:52 PM PDT 24 |
| Peak memory | 648920 kb |
| Host | smart-de72c102-e722-4a60-8077-8f68117796e6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398041158 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3398041158 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461837482 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 3750600008 ps |
| CPU time | 507.83 seconds |
| Started | Aug 06 08:41:30 PM PDT 24 |
| Finished | Aug 06 08:49:58 PM PDT 24 |
| Peak memory | 648392 kb |
| Host | smart-ab39583d-e420-4eff-8b3a-8f63acfeafda |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461837482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_s w_alert_handler_lpg_sleep_mode_alerts.3461837482 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.1811781957 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 5253068364 ps |
| CPU time | 623.37 seconds |
| Started | Aug 06 08:46:45 PM PDT 24 |
| Finished | Aug 06 08:57:09 PM PDT 24 |
| Peak memory | 649632 kb |
| Host | smart-f7bc9090-e58a-4824-b6f6-87e246eeaf76 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1811781957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.1811781957 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2950133038 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 5036049016 ps |
| CPU time | 589.88 seconds |
| Started | Aug 06 08:47:07 PM PDT 24 |
| Finished | Aug 06 08:56:57 PM PDT 24 |
| Peak memory | 650184 kb |
| Host | smart-f43ccd2c-10a8-4c7a-af31-036757fd5f76 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2950133038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2950133038 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3659491860 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 5702348980 ps |
| CPU time | 716.19 seconds |
| Started | Aug 06 08:45:39 PM PDT 24 |
| Finished | Aug 06 08:57:36 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-6e13c45c-d4ed-467e-99b8-d9e61838a9de |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3659491860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3659491860 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.1622084443 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 5798188060 ps |
| CPU time | 609.3 seconds |
| Started | Aug 06 08:46:46 PM PDT 24 |
| Finished | Aug 06 08:56:55 PM PDT 24 |
| Peak memory | 649844 kb |
| Host | smart-8f2c4f6b-a125-4857-95df-96b3d236f799 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1622084443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.1622084443 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3820926980 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 4326234700 ps |
| CPU time | 492.95 seconds |
| Started | Aug 06 08:53:05 PM PDT 24 |
| Finished | Aug 06 09:01:18 PM PDT 24 |
| Peak memory | 598908 kb |
| Host | smart-cb780663-c367-4ef5-a573-ee34d61eda92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820926980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3820926980 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1112728768 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4143266368 ps |
| CPU time | 380.33 seconds |
| Started | Aug 06 08:21:37 PM PDT 24 |
| Finished | Aug 06 08:27:58 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-31a3ace2-2504-4c2e-b0f2-9a12c00cd175 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1112728768 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.1112728768 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.826276720 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 6835429926 ps |
| CPU time | 480.08 seconds |
| Started | Aug 06 08:25:38 PM PDT 24 |
| Finished | Aug 06 08:33:40 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-e3c7ba1f-4131-443f-b71c-d52147012d9a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=826276720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_sl eep_wake_up.826276720 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.2406296527 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 3244944971 ps |
| CPU time | 333.21 seconds |
| Started | Aug 06 08:23:05 PM PDT 24 |
| Finished | Aug 06 08:28:39 PM PDT 24 |
| Peak memory | 613084 kb |
| Host | smart-2b0ca261-16fd-4083-a68a-a3a8d82cf4d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406296527 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.2406296527 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.440038191 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 4896983570 ps |
| CPU time | 529.59 seconds |
| Started | Aug 06 08:21:51 PM PDT 24 |
| Finished | Aug 06 08:30:41 PM PDT 24 |
| Peak memory | 624228 kb |
| Host | smart-4c1e2bf0-35a1-4c58-b504-21615895a8a2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440038191 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.440038191 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.4259293122 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 3202695128 ps |
| CPU time | 450.94 seconds |
| Started | Aug 06 08:24:54 PM PDT 24 |
| Finished | Aug 06 08:32:25 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-da41a7a7-f1a5-45d2-969e-e3f058c27be5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259293122 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.4259293122 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.461668573 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 7918059890 ps |
| CPU time | 557.83 seconds |
| Started | Aug 06 08:24:06 PM PDT 24 |
| Finished | Aug 06 08:33:25 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-c642356b-228d-474a-abb5-e23fe8d5378f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461668573 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.461668573 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1428712464 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3650657320 ps |
| CPU time | 478.42 seconds |
| Started | Aug 06 08:26:40 PM PDT 24 |
| Finished | Aug 06 08:34:39 PM PDT 24 |
| Peak memory | 619168 kb |
| Host | smart-471143e5-5c88-4f95-92ad-5aa6c65f11a1 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142871 2464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1428712464 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.31898922 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 26158302400 ps |
| CPU time | 6547.12 seconds |
| Started | Aug 06 08:29:36 PM PDT 24 |
| Finished | Aug 06 10:18:44 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-213d3da5-4362-476e-a4ab-7cc92697f29c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31898922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.31898922 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1910227727 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 32824658693 ps |
| CPU time | 616.78 seconds |
| Started | Aug 06 08:41:30 PM PDT 24 |
| Finished | Aug 06 08:51:48 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-72789e8f-2d23-434a-89e7-5b08ea693613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910227727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1910227727 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.1024299380 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 28320918734 ps |
| CPU time | 3166.2 seconds |
| Started | Aug 06 08:48:10 PM PDT 24 |
| Finished | Aug 06 09:40:56 PM PDT 24 |
| Peak memory | 592988 kb |
| Host | smart-0262d0f2-90cb-4e8f-a003-60381a10944d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024299380 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.1024299380 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.4071210886 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 8143664913 ps |
| CPU time | 371.81 seconds |
| Started | Aug 06 08:51:20 PM PDT 24 |
| Finished | Aug 06 08:57:32 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-d436d317-6a6e-4f52-986e-3213d22e5af1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4071210886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.4071210886 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.444197273 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 6185816416 ps |
| CPU time | 1660.26 seconds |
| Started | Aug 06 08:26:32 PM PDT 24 |
| Finished | Aug 06 08:54:13 PM PDT 24 |
| Peak memory | 609200 kb |
| Host | smart-c9a61f3f-684f-47f2-ac25-88da9060c480 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=444197273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.444197273 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1248226760 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 4728484470 ps |
| CPU time | 745.95 seconds |
| Started | Aug 06 08:24:48 PM PDT 24 |
| Finished | Aug 06 08:37:15 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-a4dc06bc-0af6-47db-a7bd-71d0366b0670 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1248226760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1248226760 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.897097055 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4529224946 ps |
| CPU time | 838.72 seconds |
| Started | Aug 06 08:23:09 PM PDT 24 |
| Finished | Aug 06 08:37:08 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-02ff9911-af97-47b8-8941-72fc46e7f010 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897097055 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.897097055 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2657577756 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 19491434070 ps |
| CPU time | 594.14 seconds |
| Started | Aug 06 08:20:21 PM PDT 24 |
| Finished | Aug 06 08:30:16 PM PDT 24 |
| Peak memory | 619728 kb |
| Host | smart-c85426d5-e438-476c-86dd-6ba1bd494e8e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2657577756 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2657577756 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3357080962 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 2810654451 ps |
| CPU time | 336.62 seconds |
| Started | Aug 06 08:23:05 PM PDT 24 |
| Finished | Aug 06 08:28:42 PM PDT 24 |
| Peak memory | 622896 kb |
| Host | smart-ac17dea8-29e2-4b68-ada5-aa22bc36f27c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357080962 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3357080962 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.1016258031 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 2776246484 ps |
| CPU time | 234.76 seconds |
| Started | Aug 06 08:23:31 PM PDT 24 |
| Finished | Aug 06 08:27:27 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-57e611a4-7b1a-4f67-83e6-a587ccbaabbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016258031 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_plic_sw_irq.1016258031 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2350391535 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 24937043072 ps |
| CPU time | 6341.8 seconds |
| Started | Aug 06 08:26:40 PM PDT 24 |
| Finished | Aug 06 10:12:22 PM PDT 24 |
| Peak memory | 610048 kb |
| Host | smart-9670c911-b688-4811-9992-50c2cd6c8232 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2350391535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2350391535 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1874903643 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 11849666201 ps |
| CPU time | 615.26 seconds |
| Started | Aug 06 08:40:27 PM PDT 24 |
| Finished | Aug 06 08:50:43 PM PDT 24 |
| Peak memory | 591296 kb |
| Host | smart-850dfb83-644a-422c-865a-420532bd5caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874903643 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1874903643 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2419501081 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 5351396464 ps |
| CPU time | 419.92 seconds |
| Started | Aug 06 08:25:41 PM PDT 24 |
| Finished | Aug 06 08:32:41 PM PDT 24 |
| Peak memory | 620416 kb |
| Host | smart-3bfe8863-e42f-4322-ad28-b720a9ece318 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2419501081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.2419501081 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2379952129 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4721577748 ps |
| CPU time | 489.98 seconds |
| Started | Aug 06 08:24:11 PM PDT 24 |
| Finished | Aug 06 08:32:22 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-9980c018-2d1f-4a31-8b9d-f111739331b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379952129 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2379952129 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1674629677 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 5925992784 ps |
| CPU time | 610.79 seconds |
| Started | Aug 06 08:26:47 PM PDT 24 |
| Finished | Aug 06 08:36:58 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-ee8babe2-f5f1-4e01-9a3d-bc6780235e09 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1674629677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1674629677 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1408938354 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 25134550033 ps |
| CPU time | 3996.58 seconds |
| Started | Aug 06 08:21:49 PM PDT 24 |
| Finished | Aug 06 09:28:27 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-6fee8f0e-05e1-4f68-9c3c-3398e556c71b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408938354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1408938354 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.46166406 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 12232074032 ps |
| CPU time | 1014.88 seconds |
| Started | Aug 06 08:41:33 PM PDT 24 |
| Finished | Aug 06 08:58:28 PM PDT 24 |
| Peak memory | 652852 kb |
| Host | smart-343020b4-2c6f-409a-b10e-8f49a169ec9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46166406 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v db -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.46166406 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.2448545758 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3291424523 ps |
| CPU time | 337.82 seconds |
| Started | Aug 06 08:41:53 PM PDT 24 |
| Finished | Aug 06 08:47:31 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-adefbbb4-b3f9-4a08-9ba0-610f25c6c013 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448545758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.2448545758 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.2738285070 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 8612555054 ps |
| CPU time | 347.35 seconds |
| Started | Aug 06 08:50:17 PM PDT 24 |
| Finished | Aug 06 08:56:04 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-53a24392-0e3d-49a3-a5e0-8a117d7c6db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738285070 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.2738285070 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.3231338081 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 3613709841 ps |
| CPU time | 275.56 seconds |
| Started | Aug 06 08:50:15 PM PDT 24 |
| Finished | Aug 06 08:54:50 PM PDT 24 |
| Peak memory | 603740 kb |
| Host | smart-274e9cd9-71b1-4919-abfe-b6026b3fec01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231338081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3231338081 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.3815078223 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 15357509153 ps |
| CPU time | 649.91 seconds |
| Started | Aug 06 08:52:22 PM PDT 24 |
| Finished | Aug 06 09:03:12 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-925c3d84-4962-46b4-9c59-4d6d51b2dda5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815078223 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.3815078223 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.3128172837 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 9974753113 ps |
| CPU time | 408.17 seconds |
| Started | Aug 06 08:52:47 PM PDT 24 |
| Finished | Aug 06 08:59:35 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-b998ef2f-7217-4c91-aaff-9979ed4c41ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128172837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.3128172837 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.30750924 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3972879389 ps |
| CPU time | 527.21 seconds |
| Started | Aug 06 08:53:57 PM PDT 24 |
| Finished | Aug 06 09:02:45 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-a7742434-822a-4892-b5af-3fb2328aa44b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30750924 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_ with_reset_error.30750924 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.4066068881 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 774756016 ps |
| CPU time | 248.6 seconds |
| Started | Aug 06 08:57:59 PM PDT 24 |
| Finished | Aug 06 09:02:08 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-4cd86be1-f27c-4618-a565-38b01b5cd9f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066068881 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_al l_with_reset_error.4066068881 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.1234219580 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 11435400860 ps |
| CPU time | 416.56 seconds |
| Started | Aug 06 08:58:09 PM PDT 24 |
| Finished | Aug 06 09:05:06 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-31f18343-a3ea-4739-811d-aee70963356d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234219580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.1234219580 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3971665227 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 10062199042 ps |
| CPU time | 623.67 seconds |
| Started | Aug 06 08:58:17 PM PDT 24 |
| Finished | Aug 06 09:08:41 PM PDT 24 |
| Peak memory | 577376 kb |
| Host | smart-e1f9a242-86c0-4fe2-9484-6f3f15631817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971665227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.3971665227 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1368243101 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 95503179 ps |
| CPU time | 19.63 seconds |
| Started | Aug 06 08:59:16 PM PDT 24 |
| Finished | Aug 06 08:59:36 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-6b1c19d5-a0e0-4d46-b609-24a9b6221d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368243101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1368243101 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.3999156160 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 3302218257 ps |
| CPU time | 289.72 seconds |
| Started | Aug 06 09:00:41 PM PDT 24 |
| Finished | Aug 06 09:05:31 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-429f3319-e1f1-4c61-a0a7-8bf085a8cf28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999156160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.3999156160 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.461622857 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 3720984074 ps |
| CPU time | 293.43 seconds |
| Started | Aug 06 08:21:53 PM PDT 24 |
| Finished | Aug 06 08:26:47 PM PDT 24 |
| Peak memory | 608596 kb |
| Host | smart-2f84c0a4-2e20-4a15-831e-5cf6f2fd6fe4 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461622857 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.461622857 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.391782033 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4682832086 ps |
| CPU time | 771.22 seconds |
| Started | Aug 06 08:21:12 PM PDT 24 |
| Finished | Aug 06 08:34:04 PM PDT 24 |
| Peak memory | 609576 kb |
| Host | smart-5ad4d538-99fd-44aa-bbf7-964defd50b71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391782033 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.391782033 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1611483813 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 5274870048 ps |
| CPU time | 949.28 seconds |
| Started | Aug 06 08:20:40 PM PDT 24 |
| Finished | Aug 06 08:36:31 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-ad7d0ffa-a44f-4183-82da-a07aa50f6b6e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611483813 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.1611483813 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1726737268 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 4581958296 ps |
| CPU time | 903.93 seconds |
| Started | Aug 06 08:26:04 PM PDT 24 |
| Finished | Aug 06 08:41:08 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-dd23b5ab-77ae-408e-bab6-cd0ef8680e6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17267 37268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1726737268 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.145328414 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4211715068 ps |
| CPU time | 474.66 seconds |
| Started | Aug 06 08:23:17 PM PDT 24 |
| Finished | Aug 06 08:31:12 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-a5916a1a-3d31-4dd9-b3eb-89f151b169f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145328414 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.145328414 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.3510333585 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 6717405732 ps |
| CPU time | 642.64 seconds |
| Started | Aug 06 08:21:59 PM PDT 24 |
| Finished | Aug 06 08:32:42 PM PDT 24 |
| Peak memory | 633108 kb |
| Host | smart-63337c34-440f-43e4-ab4f-3af899bb82ef |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510333585 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.3510333585 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.1890095963 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2735621458 ps |
| CPU time | 538.62 seconds |
| Started | Aug 06 08:21:45 PM PDT 24 |
| Finished | Aug 06 08:30:44 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-1b82451d-d321-4959-81da-df80fc424935 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890095963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ boot_mode.1890095963 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1467190976 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 6592022404 ps |
| CPU time | 1436.63 seconds |
| Started | Aug 06 08:26:14 PM PDT 24 |
| Finished | Aug 06 08:50:10 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-2a902250-e05d-4cf5-ab3d-e0079a8e195a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146719 0976 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1467190976 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2938081548 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 12945173532 ps |
| CPU time | 3897.5 seconds |
| Started | Aug 06 08:23:34 PM PDT 24 |
| Finished | Aug 06 09:28:32 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-8d2bcc93-0f84-4078-b9ff-51fe45ad7726 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29380 81548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2938081548 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2801423621 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2516534803 ps |
| CPU time | 121.41 seconds |
| Started | Aug 06 08:22:18 PM PDT 24 |
| Finished | Aug 06 08:24:20 PM PDT 24 |
| Peak memory | 622040 kb |
| Host | smart-634be992-7505-4263-ab7b-41c974db9fd2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801423621 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.2801423621 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.955471694 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 5264900648 ps |
| CPU time | 568.68 seconds |
| Started | Aug 06 08:24:20 PM PDT 24 |
| Finished | Aug 06 08:33:49 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-48709351-aced-4222-8564-412536bd6163 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955471694 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.955471694 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.1727547199 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2388806528 ps |
| CPU time | 169.84 seconds |
| Started | Aug 06 08:23:40 PM PDT 24 |
| Finished | Aug 06 08:26:30 PM PDT 24 |
| Peak memory | 609772 kb |
| Host | smart-e652a047-9ea3-4002-92af-c167d4e57aba |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727547199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_lockstep_glitch.1727547199 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.3351246354 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 32107178980 ps |
| CPU time | 3353.49 seconds |
| Started | Aug 06 08:40:21 PM PDT 24 |
| Finished | Aug 06 09:36:16 PM PDT 24 |
| Peak memory | 593080 kb |
| Host | smart-c1dd5234-78fe-47c7-9d79-463d7e033be4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351246354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.3351246354 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.2330748382 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 4297668556 ps |
| CPU time | 357.23 seconds |
| Started | Aug 06 08:41:32 PM PDT 24 |
| Finished | Aug 06 08:47:29 PM PDT 24 |
| Peak memory | 597056 kb |
| Host | smart-bc2ba8b5-6675-43f9-b6da-ad04b6ba061f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330748382 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2330748382 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2636663300 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 5912861634 ps |
| CPU time | 272.09 seconds |
| Started | Aug 06 08:40:22 PM PDT 24 |
| Finished | Aug 06 08:44:54 PM PDT 24 |
| Peak memory | 589764 kb |
| Host | smart-99fa2d40-62ea-4651-8fda-4836351a515f |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636663300 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.2636663300 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.3509912440 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 15674952267 ps |
| CPU time | 2286.91 seconds |
| Started | Aug 06 08:40:21 PM PDT 24 |
| Finished | Aug 06 09:18:28 PM PDT 24 |
| Peak memory | 592976 kb |
| Host | smart-b139d1de-a848-4466-9c73-cbfdb20caa8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509912440 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.3509912440 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.3708808175 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 2395252462 ps |
| CPU time | 122.61 seconds |
| Started | Aug 06 08:40:36 PM PDT 24 |
| Finished | Aug 06 08:42:39 PM PDT 24 |
| Peak memory | 603760 kb |
| Host | smart-77f767d2-62b4-4d22-a72c-240f3703100a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708808175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.3708808175 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2782760071 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 221842561 ps |
| CPU time | 18.45 seconds |
| Started | Aug 06 08:41:04 PM PDT 24 |
| Finished | Aug 06 08:41:22 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-c803fb12-cece-46ea-8fe0-3e8a3cd998a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782760071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2782760071 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.806515937 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 53019835416 ps |
| CPU time | 938.27 seconds |
| Started | Aug 06 08:41:04 PM PDT 24 |
| Finished | Aug 06 08:56:42 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-ad5bb93b-3e8e-4452-8ff4-0e1c42c4b22d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806515937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_de vice_slow_rsp.806515937 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.2233472965 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 819587324 ps |
| CPU time | 37.04 seconds |
| Started | Aug 06 08:41:38 PM PDT 24 |
| Finished | Aug 06 08:42:15 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-1c0e5e63-8ec2-4af7-9cda-b685b319c78f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233472965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr .2233472965 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.3276400533 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 1697845506 ps |
| CPU time | 69.17 seconds |
| Started | Aug 06 08:41:54 PM PDT 24 |
| Finished | Aug 06 08:43:03 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-a8a2f9fa-8ca8-4719-b512-b844a26fa186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276400533 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.3276400533 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.2319320321 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 320732950 ps |
| CPU time | 37.11 seconds |
| Started | Aug 06 08:40:37 PM PDT 24 |
| Finished | Aug 06 08:41:14 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-a1e6e708-2d1f-40c5-b220-63d894257c15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319320321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.2319320321 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3613644690 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 3914988582 ps |
| CPU time | 44.41 seconds |
| Started | Aug 06 08:40:46 PM PDT 24 |
| Finished | Aug 06 08:41:31 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ad4ff210-c883-48cf-9190-57cc3d8d3ccc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613644690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.3613644690 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.2856578372 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 419849155 ps |
| CPU time | 44.12 seconds |
| Started | Aug 06 08:40:33 PM PDT 24 |
| Finished | Aug 06 08:41:17 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-4e42a712-f894-4319-98f4-b884f18c1221 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2856578372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.2856578372 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.2087740909 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 1366446771 ps |
| CPU time | 44.16 seconds |
| Started | Aug 06 08:41:28 PM PDT 24 |
| Finished | Aug 06 08:42:14 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-0349ea54-d1fc-40ce-97a0-982bc0644b76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087740909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.2087740909 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.3986849869 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 149207488 ps |
| CPU time | 9.72 seconds |
| Started | Aug 06 08:40:32 PM PDT 24 |
| Finished | Aug 06 08:40:42 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-5b63e5db-13dd-4305-b698-8151928767fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986849869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.3986849869 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.3494541899 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 8010434533 ps |
| CPU time | 89.16 seconds |
| Started | Aug 06 08:40:43 PM PDT 24 |
| Finished | Aug 06 08:42:13 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-7ea96056-ef85-418d-99c6-c64d14ca068e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494541899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.3494541899 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.3126525748 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 5912682218 ps |
| CPU time | 114.32 seconds |
| Started | Aug 06 08:40:38 PM PDT 24 |
| Finished | Aug 06 08:42:32 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-edc23994-e4ea-4c12-b91b-2b194d63d244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126525748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.3126525748 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.1951476892 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 46520650 ps |
| CPU time | 6.66 seconds |
| Started | Aug 06 08:40:36 PM PDT 24 |
| Finished | Aug 06 08:40:43 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-fa589502-372a-46dd-aa14-13d8571b57d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951476892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .1951476892 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.755005013 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 2349736766 ps |
| CPU time | 106.21 seconds |
| Started | Aug 06 08:41:54 PM PDT 24 |
| Finished | Aug 06 08:43:41 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-f4777c3b-b73c-4507-bab4-498e71578707 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755005013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.755005013 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4045471752 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 67132730 ps |
| CPU time | 34.82 seconds |
| Started | Aug 06 08:41:32 PM PDT 24 |
| Finished | Aug 06 08:42:07 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-b6b81187-bfef-4cd9-a6a5-9c9c62730060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045471752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.4045471752 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.2285167250 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 75652185 ps |
| CPU time | 12.14 seconds |
| Started | Aug 06 08:41:25 PM PDT 24 |
| Finished | Aug 06 08:41:38 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-04986a74-79dc-4b2b-91f9-8c2af5d2e4f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285167250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.2285167250 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.1754204157 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 69077442664 ps |
| CPU time | 10141 seconds |
| Started | Aug 06 08:41:44 PM PDT 24 |
| Finished | Aug 06 11:30:45 PM PDT 24 |
| Peak memory | 642576 kb |
| Host | smart-5a85391f-390f-493c-afd3-e65028910db1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754204157 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 1.chip_csr_aliasing.1754204157 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4255220115 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 5631375570 ps |
| CPU time | 565.1 seconds |
| Started | Aug 06 08:41:40 PM PDT 24 |
| Finished | Aug 06 08:51:06 PM PDT 24 |
| Peak memory | 592768 kb |
| Host | smart-d4239157-baca-41ec-9f89-4f6afb6b5040 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255220115 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.4255220115 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2297040112 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 7297462408 ps |
| CPU time | 723.4 seconds |
| Started | Aug 06 08:42:39 PM PDT 24 |
| Finished | Aug 06 08:54:43 PM PDT 24 |
| Peak memory | 638724 kb |
| Host | smart-95c64b30-e69f-48d5-9b5f-271f2f495cad |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297040112 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.2297040112 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.2306626231 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 5988950008 ps |
| CPU time | 650.1 seconds |
| Started | Aug 06 08:42:33 PM PDT 24 |
| Finished | Aug 06 08:53:24 PM PDT 24 |
| Peak memory | 599320 kb |
| Host | smart-75bb9530-f5d4-499a-aaf6-32bd8b1f6a53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306626231 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.2306626231 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.563386532 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 7635039972 ps |
| CPU time | 399.07 seconds |
| Started | Aug 06 08:41:50 PM PDT 24 |
| Finished | Aug 06 08:48:30 PM PDT 24 |
| Peak memory | 591436 kb |
| Host | smart-7faaa164-6433-4929-94ff-6623036ba830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563386532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1 .chip_prim_tl_access.563386532 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.992609173 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 16914825327 ps |
| CPU time | 528.86 seconds |
| Started | Aug 06 08:41:47 PM PDT 24 |
| Finished | Aug 06 08:50:36 PM PDT 24 |
| Peak memory | 591328 kb |
| Host | smart-c634d1bb-1354-43d6-ae5a-673d13cdc739 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992609173 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 1.chip_rv_dm_lc_disabled.992609173 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.1546996115 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 26285197603 ps |
| CPU time | 3175.64 seconds |
| Started | Aug 06 08:41:48 PM PDT 24 |
| Finished | Aug 06 09:34:44 PM PDT 24 |
| Peak memory | 592984 kb |
| Host | smart-faaa113c-c38c-4af9-ae60-aaf0cb4ef5fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546996115 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 1.chip_same_csr_outstanding.1546996115 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.3022414883 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 3282564933 ps |
| CPU time | 263.21 seconds |
| Started | Aug 06 08:41:53 PM PDT 24 |
| Finished | Aug 06 08:46:16 PM PDT 24 |
| Peak memory | 603660 kb |
| Host | smart-1ff0ef9b-00b0-4d9c-95e7-37f111baab39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022414883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.3022414883 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.791561217 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 3198363179 ps |
| CPU time | 148.2 seconds |
| Started | Aug 06 08:42:17 PM PDT 24 |
| Finished | Aug 06 08:44:46 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-b78b8207-6b09-4cdf-8469-ca1f936d6685 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791561217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device.791561217 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.815763777 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 38220852582 ps |
| CPU time | 699.11 seconds |
| Started | Aug 06 08:42:25 PM PDT 24 |
| Finished | Aug 06 08:54:05 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-30b07116-e587-45ed-9f3a-dade23e43dce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815763777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_de vice_slow_rsp.815763777 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.2170373834 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 1162053544 ps |
| CPU time | 57.46 seconds |
| Started | Aug 06 08:43:05 PM PDT 24 |
| Finished | Aug 06 08:44:04 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-c638bd55-1c0f-4202-b391-5951646d0a9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170373834 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .2170373834 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.3073176301 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 1526733341 ps |
| CPU time | 68.15 seconds |
| Started | Aug 06 08:42:38 PM PDT 24 |
| Finished | Aug 06 08:43:46 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-d5f70615-ec86-45a0-9966-958d67fb89ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073176301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.3073176301 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.1730034185 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2596691181 ps |
| CPU time | 109.08 seconds |
| Started | Aug 06 08:42:10 PM PDT 24 |
| Finished | Aug 06 08:43:59 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-33fab454-d3eb-44b0-9a12-39c3766078fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730034185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.1730034185 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.1893768964 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 79565281454 ps |
| CPU time | 821.14 seconds |
| Started | Aug 06 08:42:24 PM PDT 24 |
| Finished | Aug 06 08:56:05 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-eab184ed-0842-4a39-ae26-95d0b84a6806 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893768964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.1893768964 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1287467359 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 30781452124 ps |
| CPU time | 565.79 seconds |
| Started | Aug 06 08:42:10 PM PDT 24 |
| Finished | Aug 06 08:51:36 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-29f144d4-465a-4405-b715-9bef64eee5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287467359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.1287467359 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.1619016027 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 412031820 ps |
| CPU time | 33.73 seconds |
| Started | Aug 06 08:42:11 PM PDT 24 |
| Finished | Aug 06 08:42:45 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-8dec4efd-9248-4e03-9809-07ea7d3dce54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619016027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.1619016027 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.3505613537 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 140196512 ps |
| CPU time | 11.98 seconds |
| Started | Aug 06 08:42:21 PM PDT 24 |
| Finished | Aug 06 08:42:33 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-68e94218-e20d-44c9-b45e-21485a388152 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505613537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.3505613537 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.1306179548 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 40403650 ps |
| CPU time | 6.51 seconds |
| Started | Aug 06 08:41:45 PM PDT 24 |
| Finished | Aug 06 08:41:52 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-0e81a230-5267-404d-9e6d-e665b07c9820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306179548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.1306179548 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3989524546 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 8778109132 ps |
| CPU time | 95.69 seconds |
| Started | Aug 06 08:41:57 PM PDT 24 |
| Finished | Aug 06 08:43:33 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-3f142af1-0d56-49c6-9f24-c2ece031c266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989524546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3989524546 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.3129575093 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 3388188674 ps |
| CPU time | 59.71 seconds |
| Started | Aug 06 08:42:11 PM PDT 24 |
| Finished | Aug 06 08:43:11 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-e37ebf28-6d37-470c-981a-3a4f23444766 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129575093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.3129575093 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.527297286 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 39815267 ps |
| CPU time | 6.81 seconds |
| Started | Aug 06 08:41:45 PM PDT 24 |
| Finished | Aug 06 08:41:52 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-cacefde8-499d-49d3-aa57-277c8e73f4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527297286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 527297286 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.2845637320 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 8979007690 ps |
| CPU time | 382.11 seconds |
| Started | Aug 06 08:42:40 PM PDT 24 |
| Finished | Aug 06 08:49:03 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-3e986dbd-a9b8-4221-b44f-55dd3d983f5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845637320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.2845637320 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.834050089 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 200722411 ps |
| CPU time | 8.62 seconds |
| Started | Aug 06 08:42:27 PM PDT 24 |
| Finished | Aug 06 08:42:35 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-13468e76-c8d7-43f7-b3bd-fc7cbfa16289 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834050089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.834050089 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.1440475528 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 76052232 ps |
| CPU time | 50.96 seconds |
| Started | Aug 06 08:42:32 PM PDT 24 |
| Finished | Aug 06 08:43:23 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-04818d08-b154-4fe5-b775-7b4c075baebf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440475528 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.1440475528 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.3392013350 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 210363494 ps |
| CPU time | 13.17 seconds |
| Started | Aug 06 08:42:16 PM PDT 24 |
| Finished | Aug 06 08:42:30 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-64b78901-5221-421b-afa7-44db5ca4cc8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392013350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.3392013350 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.2646057761 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 5971248784 ps |
| CPU time | 677.57 seconds |
| Started | Aug 06 08:48:39 PM PDT 24 |
| Finished | Aug 06 08:59:57 PM PDT 24 |
| Peak memory | 598452 kb |
| Host | smart-b0f9d2b4-090f-402e-b05b-6d91d6988fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646057761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.2646057761 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.2774373407 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 470207308 ps |
| CPU time | 26.81 seconds |
| Started | Aug 06 08:48:23 PM PDT 24 |
| Finished | Aug 06 08:48:50 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-7120718b-6854-4d97-999b-7119ba7398f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774373407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device .2774373407 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.1666492642 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 44683653731 ps |
| CPU time | 782.54 seconds |
| Started | Aug 06 08:48:24 PM PDT 24 |
| Finished | Aug 06 09:01:26 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-759430f0-ce85-4dae-8c08-ecf40f1fcb42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666492642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_ device_slow_rsp.1666492642 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.1313832278 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 232638774 ps |
| CPU time | 13.53 seconds |
| Started | Aug 06 08:48:30 PM PDT 24 |
| Finished | Aug 06 08:48:44 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-d78e828d-d3f8-4e05-99ae-659226daa373 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313832278 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_add r.1313832278 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.4293851006 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 1470368128 ps |
| CPU time | 55.39 seconds |
| Started | Aug 06 08:48:33 PM PDT 24 |
| Finished | Aug 06 08:49:29 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-4996c6b4-1b46-45ed-92a2-ad4cbbe96e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293851006 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.4293851006 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.1569863855 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 1420683416 ps |
| CPU time | 58.75 seconds |
| Started | Aug 06 08:48:14 PM PDT 24 |
| Finished | Aug 06 08:49:12 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-ad429b3d-5800-4ce1-a6ac-58ed0be75106 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569863855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.1569863855 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.1809994543 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 45057169360 ps |
| CPU time | 458.24 seconds |
| Started | Aug 06 08:48:20 PM PDT 24 |
| Finished | Aug 06 08:55:58 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-3b4e1f42-cbaa-47d3-8c1f-620475396813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809994543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.1809994543 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1245603917 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 35275061819 ps |
| CPU time | 590.82 seconds |
| Started | Aug 06 08:48:26 PM PDT 24 |
| Finished | Aug 06 08:58:17 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-7e13c159-06da-41f3-a407-19c049b9b41b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245603917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1245603917 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.1647265056 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 191261942 ps |
| CPU time | 23.88 seconds |
| Started | Aug 06 08:48:19 PM PDT 24 |
| Finished | Aug 06 08:48:43 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-e144d279-743f-40fd-b392-e9722cada8a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647265056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.1647265056 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3975051598 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 440492387 ps |
| CPU time | 37.09 seconds |
| Started | Aug 06 08:48:25 PM PDT 24 |
| Finished | Aug 06 08:49:02 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-7ec1bddc-1aea-4a57-83f6-9c6a709db2e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975051598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3975051598 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.3472120895 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 223670531 ps |
| CPU time | 10.66 seconds |
| Started | Aug 06 08:48:14 PM PDT 24 |
| Finished | Aug 06 08:48:25 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-6670c503-38e0-4a9b-9a83-463161ef887c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472120895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.3472120895 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.71121719 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 5026944026 ps |
| CPU time | 54.84 seconds |
| Started | Aug 06 08:48:13 PM PDT 24 |
| Finished | Aug 06 08:49:08 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-25b6bd0f-2cea-4067-941d-dd0210247ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71121719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.71121719 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.1583468614 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 4296569593 ps |
| CPU time | 74.49 seconds |
| Started | Aug 06 08:48:14 PM PDT 24 |
| Finished | Aug 06 08:49:28 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-c32bc05b-6525-434c-9a61-b305819baad2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1583468614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.1583468614 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.3947597786 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 47204898 ps |
| CPU time | 6.78 seconds |
| Started | Aug 06 08:48:13 PM PDT 24 |
| Finished | Aug 06 08:48:20 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-0cfde5a0-25ab-4786-b141-1fd369033aae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947597786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delay s.3947597786 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.3691620598 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 766619438 ps |
| CPU time | 27.07 seconds |
| Started | Aug 06 08:48:34 PM PDT 24 |
| Finished | Aug 06 08:49:01 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-a6ebc8b5-c8e2-4ec6-b26d-673e9716269a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691620598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.3691620598 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.525487979 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 3193289284 ps |
| CPU time | 121.27 seconds |
| Started | Aug 06 08:48:31 PM PDT 24 |
| Finished | Aug 06 08:50:32 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-db8bc5ab-cbf9-409c-8542-79e9e0a33d30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525487979 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.525487979 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2955155048 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 231252091 ps |
| CPU time | 92.12 seconds |
| Started | Aug 06 08:48:31 PM PDT 24 |
| Finished | Aug 06 08:50:04 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-ccacd580-5216-476b-bbb9-2da3cca2003c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955155048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.2955155048 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.630581298 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 82895295 ps |
| CPU time | 61.19 seconds |
| Started | Aug 06 08:48:33 PM PDT 24 |
| Finished | Aug 06 08:49:34 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-3c7ca802-0e25-47c2-ba57-dd67b7462d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630581298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_reset_error.630581298 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.3519662920 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 52298945 ps |
| CPU time | 6.3 seconds |
| Started | Aug 06 08:48:31 PM PDT 24 |
| Finished | Aug 06 08:48:38 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-9628eb5c-066a-4b82-97f5-c35e62606578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519662920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.3519662920 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.617695509 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 9333967320 ps |
| CPU time | 1102.08 seconds |
| Started | Aug 06 08:49:11 PM PDT 24 |
| Finished | Aug 06 09:07:33 PM PDT 24 |
| Peak memory | 652940 kb |
| Host | smart-f469d418-fb52-460b-aa58-e70f19f77109 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617695509 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.617695509 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2584512837 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 5335064008 ps |
| CPU time | 718.62 seconds |
| Started | Aug 06 08:49:07 PM PDT 24 |
| Finished | Aug 06 09:01:06 PM PDT 24 |
| Peak memory | 598768 kb |
| Host | smart-31d3cbff-3157-40ac-9b9e-9614f9a90cac |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584512837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2584512837 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.2177906378 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 934708479 ps |
| CPU time | 74.55 seconds |
| Started | Aug 06 08:48:53 PM PDT 24 |
| Finished | Aug 06 08:50:07 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-e87f69ad-9170-4df1-a7cb-8dc7c202402e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177906378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .2177906378 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.2789635842 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 92073878042 ps |
| CPU time | 1553.31 seconds |
| Started | Aug 06 08:48:58 PM PDT 24 |
| Finished | Aug 06 09:14:52 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-ee900d7c-e449-45c2-b370-b7763d273ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789635842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.2789635842 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3335803519 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 77058425 ps |
| CPU time | 13.29 seconds |
| Started | Aug 06 08:48:58 PM PDT 24 |
| Finished | Aug 06 08:49:11 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-17cfa73f-639a-42a1-b560-84c01673e28b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335803519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.3335803519 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.2902941582 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 441502307 ps |
| CPU time | 45.96 seconds |
| Started | Aug 06 08:48:58 PM PDT 24 |
| Finished | Aug 06 08:49:44 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9a813fa7-13a1-43f0-bd88-2f94e1f91657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902941582 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2902941582 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.1950316655 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 1245101012 ps |
| CPU time | 48.9 seconds |
| Started | Aug 06 08:48:48 PM PDT 24 |
| Finished | Aug 06 08:49:37 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-3b7ba977-8fb4-4457-bb68-32820765a28d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1950316655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.1950316655 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.2905031395 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 102141742858 ps |
| CPU time | 1079.29 seconds |
| Started | Aug 06 08:48:52 PM PDT 24 |
| Finished | Aug 06 09:06:52 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-5fcaa29a-7a15-42ee-9c59-1a343d0a22db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905031395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.2905031395 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.3010475789 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 5648567630 ps |
| CPU time | 96.6 seconds |
| Started | Aug 06 08:48:52 PM PDT 24 |
| Finished | Aug 06 08:50:29 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-0805c325-859c-47db-9dec-227429d1aba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3010475789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.3010475789 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.725166226 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 482762755 ps |
| CPU time | 38.99 seconds |
| Started | Aug 06 08:48:47 PM PDT 24 |
| Finished | Aug 06 08:49:26 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-bcc556b0-a966-42e1-b6e0-5e7ff9c2434e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725166226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_dela ys.725166226 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.371926408 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 1863939659 ps |
| CPU time | 60.28 seconds |
| Started | Aug 06 08:48:57 PM PDT 24 |
| Finished | Aug 06 08:49:57 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-828c67ae-39dc-4a6e-b972-bf3b9f92de59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371926408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.371926408 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.1626486995 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 46916528 ps |
| CPU time | 7.06 seconds |
| Started | Aug 06 08:48:39 PM PDT 24 |
| Finished | Aug 06 08:48:46 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-7930a3ca-c71c-4b23-9ce1-8bc51ef79cd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626486995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.1626486995 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2392178748 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 7392213539 ps |
| CPU time | 80.45 seconds |
| Started | Aug 06 08:48:46 PM PDT 24 |
| Finished | Aug 06 08:50:06 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-784c76ba-a893-411c-968a-4885c59090bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2392178748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2392178748 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.51751452 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 5539303720 ps |
| CPU time | 98.86 seconds |
| Started | Aug 06 08:48:46 PM PDT 24 |
| Finished | Aug 06 08:50:25 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-785d40cb-7807-464c-bdc9-097d7d662171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51751452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.51751452 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.1267790927 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 39884393 ps |
| CPU time | 6.35 seconds |
| Started | Aug 06 08:48:45 PM PDT 24 |
| Finished | Aug 06 08:48:51 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-cc73034c-99ff-494c-ba50-a504ada40466 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267790927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delay s.1267790927 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.1428365572 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 3611186643 ps |
| CPU time | 138.33 seconds |
| Started | Aug 06 08:49:04 PM PDT 24 |
| Finished | Aug 06 08:51:22 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-8f16a557-b637-4c17-9d35-f4c1a7570852 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428365572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.1428365572 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.2564848057 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 3212866706 ps |
| CPU time | 133.32 seconds |
| Started | Aug 06 08:49:05 PM PDT 24 |
| Finished | Aug 06 08:51:18 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d5439255-5d18-41f3-843c-9bcc58e774b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564848057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.2564848057 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.3341953079 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 119456776 ps |
| CPU time | 85.08 seconds |
| Started | Aug 06 08:49:05 PM PDT 24 |
| Finished | Aug 06 08:50:31 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-1249cba0-904b-4522-9c10-2b1391571d7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341953079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.3341953079 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2494617158 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 2783576080 ps |
| CPU time | 211.25 seconds |
| Started | Aug 06 08:49:06 PM PDT 24 |
| Finished | Aug 06 08:52:38 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-7330d7fa-ef0d-482c-ad10-dc1f735555ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494617158 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2494617158 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.3601683893 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 1108333317 ps |
| CPU time | 52.8 seconds |
| Started | Aug 06 08:49:00 PM PDT 24 |
| Finished | Aug 06 08:49:53 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-db74f4c3-8929-482d-8db9-4843de7c5b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601683893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.3601683893 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3061306128 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 11634842510 ps |
| CPU time | 903.73 seconds |
| Started | Aug 06 08:49:41 PM PDT 24 |
| Finished | Aug 06 09:04:45 PM PDT 24 |
| Peak memory | 652964 kb |
| Host | smart-2e870abf-f749-43d1-af11-5c5fd7a4c907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061306128 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.3061306128 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1227215919 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 4408260337 ps |
| CPU time | 362.6 seconds |
| Started | Aug 06 08:49:38 PM PDT 24 |
| Finished | Aug 06 08:55:41 PM PDT 24 |
| Peak memory | 598072 kb |
| Host | smart-52b05a7e-1cd4-4d48-ac1c-f6d5cc82c648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227215919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1227215919 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.1238999161 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 15067942053 ps |
| CPU time | 1939.19 seconds |
| Started | Aug 06 08:49:10 PM PDT 24 |
| Finished | Aug 06 09:21:30 PM PDT 24 |
| Peak memory | 593152 kb |
| Host | smart-d6ce09ce-e5e9-4367-9d85-348be42f3aea |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238999161 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.1238999161 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.2828412922 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 2621570884 ps |
| CPU time | 110.77 seconds |
| Started | Aug 06 08:49:11 PM PDT 24 |
| Finished | Aug 06 08:51:02 PM PDT 24 |
| Peak memory | 603664 kb |
| Host | smart-bab94b72-9874-4efd-98c6-0963c3271179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828412922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.2828412922 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.1219884642 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 110846250 ps |
| CPU time | 13.56 seconds |
| Started | Aug 06 08:49:23 PM PDT 24 |
| Finished | Aug 06 08:49:37 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-db10d519-6895-441d-a956-b89a45c6b453 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219884642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device .1219884642 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.4117127138 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 73373431289 ps |
| CPU time | 1254.36 seconds |
| Started | Aug 06 08:49:28 PM PDT 24 |
| Finished | Aug 06 09:10:23 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-f8fdc248-e902-4aa9-a098-330fbe29fbb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117127138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.4117127138 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.1604146380 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 20618783 ps |
| CPU time | 5.67 seconds |
| Started | Aug 06 08:49:34 PM PDT 24 |
| Finished | Aug 06 08:49:39 PM PDT 24 |
| Peak memory | 574296 kb |
| Host | smart-4005c443-0795-4ed1-9375-15cde18d4805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604146380 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_add r.1604146380 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1527536738 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 582644077 ps |
| CPU time | 52.35 seconds |
| Started | Aug 06 08:49:34 PM PDT 24 |
| Finished | Aug 06 08:50:26 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-4ef66c61-ece7-4737-a31c-e6912845f1ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527536738 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1527536738 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.803080484 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 461870720 ps |
| CPU time | 49.13 seconds |
| Started | Aug 06 08:49:28 PM PDT 24 |
| Finished | Aug 06 08:50:17 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-b7f5213f-329f-40ec-a7d5-6469c50ee99f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803080484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.803080484 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.1397417017 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 107892987309 ps |
| CPU time | 1120.29 seconds |
| Started | Aug 06 08:49:22 PM PDT 24 |
| Finished | Aug 06 09:08:02 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-1fe234c7-632a-4acd-94dd-d776b0265566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397417017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.1397417017 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1157983654 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 33250154752 ps |
| CPU time | 565.16 seconds |
| Started | Aug 06 08:49:24 PM PDT 24 |
| Finished | Aug 06 08:58:49 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-4f3ddafa-5a78-4205-9975-284d10c014ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1157983654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1157983654 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3252106815 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 79459281 ps |
| CPU time | 10.47 seconds |
| Started | Aug 06 08:49:25 PM PDT 24 |
| Finished | Aug 06 08:49:35 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-d0a22725-fe24-4170-9782-f1db2eea0ae0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252106815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.3252106815 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.2288243326 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 1711022674 ps |
| CPU time | 56.79 seconds |
| Started | Aug 06 08:49:31 PM PDT 24 |
| Finished | Aug 06 08:50:28 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-a12854ca-6eed-42e9-9613-cddab192d290 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288243326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.2288243326 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.80895147 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 129449546 ps |
| CPU time | 7.76 seconds |
| Started | Aug 06 08:49:10 PM PDT 24 |
| Finished | Aug 06 08:49:18 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-dae9e96d-079e-4b8e-b0b5-34051eeb38e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80895147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.80895147 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.269672921 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 10853673287 ps |
| CPU time | 119.53 seconds |
| Started | Aug 06 08:49:19 PM PDT 24 |
| Finished | Aug 06 08:51:18 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-5e3a2282-f472-4653-8b0d-d55e88658e4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269672921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.269672921 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2175547695 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 6456095002 ps |
| CPU time | 117.94 seconds |
| Started | Aug 06 08:49:17 PM PDT 24 |
| Finished | Aug 06 08:51:15 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-fcd0a78b-f746-4619-b7bf-57865f87e168 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175547695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2175547695 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2613669280 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 47381233 ps |
| CPU time | 7.16 seconds |
| Started | Aug 06 08:49:18 PM PDT 24 |
| Finished | Aug 06 08:49:26 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-7ed47d14-b9aa-4131-866e-bbe81fd77ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613669280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.2613669280 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.487597052 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 13829261852 ps |
| CPU time | 563.57 seconds |
| Started | Aug 06 08:49:31 PM PDT 24 |
| Finished | Aug 06 08:58:54 PM PDT 24 |
| Peak memory | 576688 kb |
| Host | smart-ced379be-2056-4684-abde-a43bc0d35203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=487597052 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.487597052 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.1354324111 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 10964572231 ps |
| CPU time | 355.51 seconds |
| Started | Aug 06 08:49:38 PM PDT 24 |
| Finished | Aug 06 08:55:34 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-2286613a-ac7f-4fc2-b0a7-dd068805c8fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1354324111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.1354324111 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.1220417126 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 144769102 ps |
| CPU time | 63.77 seconds |
| Started | Aug 06 08:49:29 PM PDT 24 |
| Finished | Aug 06 08:50:33 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-af09027e-26d4-435f-ba3c-4293ee8190c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220417126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.1220417126 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.3127465312 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 6421165635 ps |
| CPU time | 739.25 seconds |
| Started | Aug 06 08:49:39 PM PDT 24 |
| Finished | Aug 06 09:01:58 PM PDT 24 |
| Peak memory | 582768 kb |
| Host | smart-28dc9a9b-7238-42f2-8643-4b7dc0f5c7eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127465312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.3127465312 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.489460619 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 145724073 ps |
| CPU time | 20.28 seconds |
| Started | Aug 06 08:49:32 PM PDT 24 |
| Finished | Aug 06 08:49:52 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-0f611e8a-c28b-48b3-a807-de97038418fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489460619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.489460619 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.415919262 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 10133503763 ps |
| CPU time | 911.14 seconds |
| Started | Aug 06 08:50:06 PM PDT 24 |
| Finished | Aug 06 09:05:17 PM PDT 24 |
| Peak memory | 647820 kb |
| Host | smart-1d465bbd-7a79-4d53-bcb7-1aa105af12b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415919262 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.415919262 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.2406906729 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 5702370569 ps |
| CPU time | 574.73 seconds |
| Started | Aug 06 08:49:56 PM PDT 24 |
| Finished | Aug 06 08:59:31 PM PDT 24 |
| Peak memory | 598768 kb |
| Host | smart-967f97f8-3f95-4a61-b5fc-dc1a9d3b509c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2406906729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.2406906729 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.1569214426 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 33496456794 ps |
| CPU time | 3604.63 seconds |
| Started | Aug 06 08:49:38 PM PDT 24 |
| Finished | Aug 06 09:49:43 PM PDT 24 |
| Peak memory | 593548 kb |
| Host | smart-99d4159f-ac62-4f89-9e1c-669d51f874d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569214426 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 13.chip_same_csr_outstanding.1569214426 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.1374144683 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 2280081408 ps |
| CPU time | 94.63 seconds |
| Started | Aug 06 08:49:38 PM PDT 24 |
| Finished | Aug 06 08:51:13 PM PDT 24 |
| Peak memory | 599608 kb |
| Host | smart-3d4f183d-bf38-4706-a1f3-5f2a2fbfc265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374144683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.1374144683 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.2966686464 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 1744414173 ps |
| CPU time | 95.39 seconds |
| Started | Aug 06 08:49:47 PM PDT 24 |
| Finished | Aug 06 08:51:23 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-e63a5ef4-78bb-45d9-964b-2ecd5e1d2fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966686464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device .2966686464 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.1576918367 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 82865599101 ps |
| CPU time | 1461.1 seconds |
| Started | Aug 06 08:49:47 PM PDT 24 |
| Finished | Aug 06 09:14:08 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-2b35494a-84a4-4af8-9063-3236a87eff0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576918367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.1576918367 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3592906808 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 482246954 ps |
| CPU time | 23.66 seconds |
| Started | Aug 06 08:49:57 PM PDT 24 |
| Finished | Aug 06 08:50:21 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-201d0466-f608-4032-94c1-1ba105285655 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592906808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3592906808 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.3793581853 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 465404722 ps |
| CPU time | 47.29 seconds |
| Started | Aug 06 08:49:48 PM PDT 24 |
| Finished | Aug 06 08:50:35 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-6ce2d0ba-d2dc-476c-bac9-b80c5751cfa5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793581853 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3793581853 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.3997019388 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 408739946 ps |
| CPU time | 43.06 seconds |
| Started | Aug 06 08:49:47 PM PDT 24 |
| Finished | Aug 06 08:50:30 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-2c6e0c07-9191-4993-8b44-44d29bea592b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997019388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.3997019388 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.1213847562 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 56403435182 ps |
| CPU time | 577.74 seconds |
| Started | Aug 06 08:49:46 PM PDT 24 |
| Finished | Aug 06 08:59:24 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-a709673c-733e-43ba-afcb-1fb1bc2d47d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213847562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.1213847562 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2769859624 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 34030389677 ps |
| CPU time | 616.03 seconds |
| Started | Aug 06 08:49:47 PM PDT 24 |
| Finished | Aug 06 09:00:03 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-3b24d2e7-6d44-4fdd-a805-8a06cd0b11c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769859624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2769859624 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.2989153818 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 31452761 ps |
| CPU time | 6.71 seconds |
| Started | Aug 06 08:49:46 PM PDT 24 |
| Finished | Aug 06 08:49:53 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-93261e4f-0831-4dbb-ac40-a409bfe8282f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989153818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.2989153818 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.2742567516 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 1015622338 ps |
| CPU time | 33.72 seconds |
| Started | Aug 06 08:49:47 PM PDT 24 |
| Finished | Aug 06 08:50:21 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-ef0b3334-b0d1-4d03-85f0-f48d2d485895 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742567516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.2742567516 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.669995426 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 203298485 ps |
| CPU time | 9.9 seconds |
| Started | Aug 06 08:49:38 PM PDT 24 |
| Finished | Aug 06 08:49:47 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-4aefe82e-8e1b-4868-85b5-81dbd676e820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669995426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.669995426 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.1353023298 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 6493699750 ps |
| CPU time | 76.3 seconds |
| Started | Aug 06 08:49:38 PM PDT 24 |
| Finished | Aug 06 08:50:55 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4ef425f5-a79c-4a5d-81bc-507692492aaf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1353023298 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.1353023298 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.1547604040 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 4565427868 ps |
| CPU time | 81.6 seconds |
| Started | Aug 06 08:49:48 PM PDT 24 |
| Finished | Aug 06 08:51:09 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-0352d919-0c1a-4e03-8807-28ec75f7b8e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547604040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.1547604040 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3019106255 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 43812095 ps |
| CPU time | 6.9 seconds |
| Started | Aug 06 08:49:39 PM PDT 24 |
| Finished | Aug 06 08:49:46 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-1a1cf48f-d703-4934-b90b-615dc4b31850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019106255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.3019106255 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.2333568451 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1782452499 ps |
| CPU time | 165.09 seconds |
| Started | Aug 06 08:49:55 PM PDT 24 |
| Finished | Aug 06 08:52:40 PM PDT 24 |
| Peak memory | 576516 kb |
| Host | smart-c76c52fa-c15c-4a2d-b93d-46105066b4b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333568451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.2333568451 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3884686587 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 2550086785 ps |
| CPU time | 234.82 seconds |
| Started | Aug 06 08:49:55 PM PDT 24 |
| Finished | Aug 06 08:53:49 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-7a2a74fe-8e3b-4cf3-912b-5bd75739fab1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884686587 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.3884686587 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.1712757885 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 3256779279 ps |
| CPU time | 456.05 seconds |
| Started | Aug 06 08:49:56 PM PDT 24 |
| Finished | Aug 06 08:57:33 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-ecd08543-fcf5-4d49-b265-4f49f09509fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712757885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.1712757885 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.3428086365 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 3175257928 ps |
| CPU time | 249.14 seconds |
| Started | Aug 06 08:49:54 PM PDT 24 |
| Finished | Aug 06 08:54:04 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-c4103816-1520-40d9-af4d-152db9879d76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428086365 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.3428086365 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.3691824463 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 35871355 ps |
| CPU time | 7.39 seconds |
| Started | Aug 06 08:49:57 PM PDT 24 |
| Finished | Aug 06 08:50:04 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-2c0932ac-b31a-4381-9055-e7fef18aa237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691824463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.3691824463 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.3816703680 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 8099412006 ps |
| CPU time | 601.28 seconds |
| Started | Aug 06 08:50:15 PM PDT 24 |
| Finished | Aug 06 09:00:16 PM PDT 24 |
| Peak memory | 639592 kb |
| Host | smart-18686777-ed83-4d49-be01-9aad83012637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816703680 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.3816703680 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.307007269 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 3727362438 ps |
| CPU time | 410.71 seconds |
| Started | Aug 06 08:50:18 PM PDT 24 |
| Finished | Aug 06 08:57:09 PM PDT 24 |
| Peak memory | 598948 kb |
| Host | smart-793688ef-c123-4d64-ab1e-1131613dbf24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307007269 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.307007269 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.239026671 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 16849098306 ps |
| CPU time | 1751.08 seconds |
| Started | Aug 06 08:50:01 PM PDT 24 |
| Finished | Aug 06 09:19:12 PM PDT 24 |
| Peak memory | 593368 kb |
| Host | smart-bcec2c7e-a641-479a-a9fa-6bca13760905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239026671 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.239026671 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.1484498847 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3205926028 ps |
| CPU time | 176.41 seconds |
| Started | Aug 06 08:50:00 PM PDT 24 |
| Finished | Aug 06 08:52:57 PM PDT 24 |
| Peak memory | 603744 kb |
| Host | smart-7f3a646e-2b59-4539-8603-b1665d1db34b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484498847 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.1484498847 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2328978290 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 1802036458 ps |
| CPU time | 84.36 seconds |
| Started | Aug 06 08:50:08 PM PDT 24 |
| Finished | Aug 06 08:51:33 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-69c4cca5-51b0-4bc1-a98e-a2ace4ecc93b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328978290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device .2328978290 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.3373857242 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 12061370505 ps |
| CPU time | 216.31 seconds |
| Started | Aug 06 08:50:07 PM PDT 24 |
| Finished | Aug 06 08:53:44 PM PDT 24 |
| Peak memory | 574504 kb |
| Host | smart-983b9ed3-25a3-4e89-8c73-a866e20f34b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373857242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.3373857242 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.821146028 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 329427449 ps |
| CPU time | 41.35 seconds |
| Started | Aug 06 08:50:07 PM PDT 24 |
| Finished | Aug 06 08:50:49 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-a269c6c3-50fc-4237-852c-28f568c4c526 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821146028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .821146028 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.1919281666 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 235187336 ps |
| CPU time | 11.66 seconds |
| Started | Aug 06 08:50:09 PM PDT 24 |
| Finished | Aug 06 08:50:21 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-bd259775-0406-4460-871c-75a975653186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919281666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.1919281666 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.3307584027 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 1248868948 ps |
| CPU time | 53.12 seconds |
| Started | Aug 06 08:50:02 PM PDT 24 |
| Finished | Aug 06 08:50:55 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-61ab2c9b-2090-4a68-8f5c-a9d6ab866211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307584027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.3307584027 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.2197701226 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 69449114998 ps |
| CPU time | 754.74 seconds |
| Started | Aug 06 08:50:02 PM PDT 24 |
| Finished | Aug 06 09:02:36 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-85d0a722-411d-459d-9243-c39bf552b4af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197701226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.2197701226 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.647704610 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 13774913087 ps |
| CPU time | 235.32 seconds |
| Started | Aug 06 08:50:01 PM PDT 24 |
| Finished | Aug 06 08:53:56 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-0dea86c7-325d-4276-89b5-69566aac5955 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647704610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.647704610 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.3080219306 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 463814914 ps |
| CPU time | 41.74 seconds |
| Started | Aug 06 08:50:01 PM PDT 24 |
| Finished | Aug 06 08:50:43 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-a369f66f-f0f6-426d-a15e-e8bee194452d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080219306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_del ays.3080219306 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.2330928946 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 91135856 ps |
| CPU time | 10.12 seconds |
| Started | Aug 06 08:50:09 PM PDT 24 |
| Finished | Aug 06 08:50:19 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-9e28dc0f-f94a-4a75-8d7a-40545f24301d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330928946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.2330928946 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.3301401534 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 213470474 ps |
| CPU time | 10.2 seconds |
| Started | Aug 06 08:50:01 PM PDT 24 |
| Finished | Aug 06 08:50:12 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-cc16b3e6-ca22-48e5-bfe0-163c474e75e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3301401534 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3301401534 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.4079449419 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 3954700220 ps |
| CPU time | 42.64 seconds |
| Started | Aug 06 08:50:05 PM PDT 24 |
| Finished | Aug 06 08:50:48 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-340b4acc-7a8a-40e4-986d-f702c2c6e1ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079449419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.4079449419 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1161973876 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 5150940942 ps |
| CPU time | 92.3 seconds |
| Started | Aug 06 08:50:03 PM PDT 24 |
| Finished | Aug 06 08:51:35 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-5c84ebf5-cba4-45f0-8305-2943832cc768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161973876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1161973876 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.3198182563 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 47505659 ps |
| CPU time | 7.08 seconds |
| Started | Aug 06 08:50:03 PM PDT 24 |
| Finished | Aug 06 08:50:10 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-bf2fc08c-c36a-4890-a547-c598a94f34dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198182563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delay s.3198182563 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.766497111 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 2499598467 ps |
| CPU time | 224.28 seconds |
| Started | Aug 06 08:50:09 PM PDT 24 |
| Finished | Aug 06 08:53:53 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-f4bc1342-3470-4a98-95ab-7ba06952c322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766497111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.766497111 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.316967822 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 4654400293 ps |
| CPU time | 376.99 seconds |
| Started | Aug 06 08:50:15 PM PDT 24 |
| Finished | Aug 06 08:56:32 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-7fbf83e1-5ade-42c8-a5f4-de04424af901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316967822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_ with_rand_reset.316967822 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.733621781 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 774189648 ps |
| CPU time | 210.77 seconds |
| Started | Aug 06 08:50:16 PM PDT 24 |
| Finished | Aug 06 08:53:47 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-61336041-a6bb-4e13-a8c2-27bc72640e1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733621781 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_reset_error.733621781 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.2418554787 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 572074954 ps |
| CPU time | 27.36 seconds |
| Started | Aug 06 08:50:08 PM PDT 24 |
| Finished | Aug 06 08:50:36 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-ae7bda1e-36d0-4388-860c-3a3a9599e3c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418554787 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.2418554787 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.2799149286 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 9018365720 ps |
| CPU time | 971.22 seconds |
| Started | Aug 06 08:50:37 PM PDT 24 |
| Finished | Aug 06 09:06:49 PM PDT 24 |
| Peak memory | 652932 kb |
| Host | smart-baf11db6-ff33-48fd-a1d6-40564e2aba8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799149286 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.2799149286 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.606386524 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 4789009109 ps |
| CPU time | 481.78 seconds |
| Started | Aug 06 08:50:38 PM PDT 24 |
| Finished | Aug 06 08:58:40 PM PDT 24 |
| Peak memory | 596856 kb |
| Host | smart-27586912-99e7-4c86-927c-0aeafd659dd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606386524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.606386524 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.550280942 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 32262869246 ps |
| CPU time | 3244.17 seconds |
| Started | Aug 06 08:50:17 PM PDT 24 |
| Finished | Aug 06 09:44:21 PM PDT 24 |
| Peak memory | 593448 kb |
| Host | smart-bebbdb0d-331d-4627-9eb0-1f10790be797 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550280942 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 15.chip_same_csr_outstanding.550280942 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.782174647 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 900780703 ps |
| CPU time | 87 seconds |
| Started | Aug 06 08:50:34 PM PDT 24 |
| Finished | Aug 06 08:52:01 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-bbebb53d-df81-4bea-93a9-7794910cc04c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782174647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device. 782174647 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.614552175 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 68731215465 ps |
| CPU time | 1209.52 seconds |
| Started | Aug 06 08:50:31 PM PDT 24 |
| Finished | Aug 06 09:10:41 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-c0346904-5875-4f2a-8e83-a24bd1266f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614552175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_d evice_slow_rsp.614552175 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2781105173 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 627920098 ps |
| CPU time | 28.75 seconds |
| Started | Aug 06 08:50:32 PM PDT 24 |
| Finished | Aug 06 08:51:01 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-a0cf40bb-af82-4f9e-a003-84112bc7505f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781105173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2781105173 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.2139213705 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 1671418830 ps |
| CPU time | 64.13 seconds |
| Started | Aug 06 08:50:28 PM PDT 24 |
| Finished | Aug 06 08:51:32 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-c21abf69-bfb6-41c4-b1e6-13e5593a4d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139213705 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.2139213705 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.3839516386 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 1744760757 ps |
| CPU time | 65.84 seconds |
| Started | Aug 06 08:50:22 PM PDT 24 |
| Finished | Aug 06 08:51:28 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-7602646b-363a-4878-9fc5-3799fac6eb38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839516386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.3839516386 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.1223448065 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 89165354097 ps |
| CPU time | 969.52 seconds |
| Started | Aug 06 08:50:23 PM PDT 24 |
| Finished | Aug 06 09:06:33 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-a01b8978-5129-44b2-8293-e765d335fd93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223448065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.1223448065 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.3910908615 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 9678902384 ps |
| CPU time | 169.38 seconds |
| Started | Aug 06 08:50:23 PM PDT 24 |
| Finished | Aug 06 08:53:12 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-2d597008-2d84-491d-9fee-9a2c959bc838 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910908615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.3910908615 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.686886265 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 414727084 ps |
| CPU time | 40.73 seconds |
| Started | Aug 06 08:50:26 PM PDT 24 |
| Finished | Aug 06 08:51:07 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-f0563b15-a243-412f-b39e-d31cd4967c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686886265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_dela ys.686886265 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.326477385 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 823008400 ps |
| CPU time | 25.72 seconds |
| Started | Aug 06 08:50:29 PM PDT 24 |
| Finished | Aug 06 08:50:55 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-a65ed556-7324-41a8-93ef-44e48f303aed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326477385 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.326477385 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.611244736 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 50606362 ps |
| CPU time | 7.33 seconds |
| Started | Aug 06 08:50:17 PM PDT 24 |
| Finished | Aug 06 08:50:24 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-8c83f715-a4b3-47d6-836a-629ae61ca34b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611244736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.611244736 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.2337384315 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 8148233094 ps |
| CPU time | 90.6 seconds |
| Started | Aug 06 08:50:23 PM PDT 24 |
| Finished | Aug 06 08:51:54 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-24df64de-b324-4d5c-b878-54160dbdc266 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337384315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.2337384315 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.3778758813 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 4183261877 ps |
| CPU time | 74.46 seconds |
| Started | Aug 06 08:50:25 PM PDT 24 |
| Finished | Aug 06 08:51:39 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-70ae6039-4b45-40a7-968d-432b921f0e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778758813 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.3778758813 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.2679383946 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 45118856 ps |
| CPU time | 6.5 seconds |
| Started | Aug 06 08:50:17 PM PDT 24 |
| Finished | Aug 06 08:50:24 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-e3dba28d-3f78-431e-8f34-20a5654bbc42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679383946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delay s.2679383946 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.2486803509 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 9670241651 ps |
| CPU time | 357.36 seconds |
| Started | Aug 06 08:50:32 PM PDT 24 |
| Finished | Aug 06 08:56:29 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-cad83ff7-93ff-4819-9e93-752a8f566139 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486803509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.2486803509 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.2251907473 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 2692675741 ps |
| CPU time | 107.33 seconds |
| Started | Aug 06 08:50:36 PM PDT 24 |
| Finished | Aug 06 08:52:24 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-099ab855-b68d-472d-bca3-98184391e4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251907473 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.2251907473 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.2922515023 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 596077838 ps |
| CPU time | 324.41 seconds |
| Started | Aug 06 08:50:28 PM PDT 24 |
| Finished | Aug 06 08:55:53 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-5635ae18-9c9d-434c-9b49-fa7ca012b968 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922515023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.2922515023 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.1166321103 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 376643261 ps |
| CPU time | 108.06 seconds |
| Started | Aug 06 08:50:38 PM PDT 24 |
| Finished | Aug 06 08:52:26 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-d705109b-9f7e-4e45-930f-f8bdc39e3a79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166321103 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_al l_with_reset_error.1166321103 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.1337257503 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 1381617765 ps |
| CPU time | 74.74 seconds |
| Started | Aug 06 08:50:33 PM PDT 24 |
| Finished | Aug 06 08:51:48 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-64811096-9a48-44bb-956d-02ae68c17bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337257503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.1337257503 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.1886274554 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 9775112500 ps |
| CPU time | 834.18 seconds |
| Started | Aug 06 08:51:03 PM PDT 24 |
| Finished | Aug 06 09:04:57 PM PDT 24 |
| Peak memory | 646696 kb |
| Host | smart-3f32d186-2a81-485f-9d5b-978fbcb7a3f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886274554 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.1886274554 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.1936508069 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 4232787360 ps |
| CPU time | 354.15 seconds |
| Started | Aug 06 08:51:05 PM PDT 24 |
| Finished | Aug 06 08:56:59 PM PDT 24 |
| Peak memory | 598856 kb |
| Host | smart-3df8299b-1990-4bd4-b075-052a817e7b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936508069 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.1936508069 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.71286911 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 29230187179 ps |
| CPU time | 3447.08 seconds |
| Started | Aug 06 08:50:37 PM PDT 24 |
| Finished | Aug 06 09:48:05 PM PDT 24 |
| Peak memory | 593756 kb |
| Host | smart-85ea426a-833c-4ec4-9e83-633131a4c048 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=71286911 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm _log /dev/null -cm_name 16.chip_same_csr_outstanding.71286911 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.4005353533 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 282474899 ps |
| CPU time | 30.83 seconds |
| Started | Aug 06 08:50:47 PM PDT 24 |
| Finished | Aug 06 08:51:18 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-2a1575f1-78f0-42db-839f-fe12a1911692 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005353533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device .4005353533 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.1306246316 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 150842717191 ps |
| CPU time | 2625.76 seconds |
| Started | Aug 06 08:51:03 PM PDT 24 |
| Finished | Aug 06 09:34:49 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-56cf8a12-9fc3-4119-975c-e1b6870769cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306246316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.1306246316 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3782455584 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 1265322547 ps |
| CPU time | 51.85 seconds |
| Started | Aug 06 08:50:58 PM PDT 24 |
| Finished | Aug 06 08:51:49 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-5a773db4-f73c-4e3f-afed-906b105df81f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782455584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3782455584 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.2149104915 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 1793285737 ps |
| CPU time | 71.73 seconds |
| Started | Aug 06 08:50:59 PM PDT 24 |
| Finished | Aug 06 08:52:11 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-5cc40402-5ed3-4e26-a39f-73bb6a689bbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149104915 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.2149104915 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.1251945319 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 465299757 ps |
| CPU time | 18.99 seconds |
| Started | Aug 06 08:50:50 PM PDT 24 |
| Finished | Aug 06 08:51:09 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-8148c8c9-7483-4f4c-8c2e-571898225257 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251945319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1251945319 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.1964237582 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 44714380370 ps |
| CPU time | 478.51 seconds |
| Started | Aug 06 08:50:49 PM PDT 24 |
| Finished | Aug 06 08:58:47 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-e2187cc6-d3a0-4d53-ba3d-8a0db1d5bc90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964237582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.1964237582 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.2142686481 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 24926855435 ps |
| CPU time | 446.22 seconds |
| Started | Aug 06 08:50:47 PM PDT 24 |
| Finished | Aug 06 08:58:13 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-9bdf9968-0153-4290-a5ba-6006cfcf2c6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142686481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.2142686481 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.58917206 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 201534834 ps |
| CPU time | 23.55 seconds |
| Started | Aug 06 08:50:49 PM PDT 24 |
| Finished | Aug 06 08:51:12 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-001afd35-e9ff-4b7d-b505-870ae06c2c0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58917206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_delay s.58917206 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.2718177857 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 1403703658 ps |
| CPU time | 44.43 seconds |
| Started | Aug 06 08:51:02 PM PDT 24 |
| Finished | Aug 06 08:51:47 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-9e0a4c78-d6f3-4c98-80d2-d92cfd15a31f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718177857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.2718177857 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.3426913960 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 212835756 ps |
| CPU time | 10.44 seconds |
| Started | Aug 06 08:50:48 PM PDT 24 |
| Finished | Aug 06 08:50:59 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-103d266a-2d2b-4a35-b5b4-3569da71304e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426913960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3426913960 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.2628379238 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 5995197780 ps |
| CPU time | 66.71 seconds |
| Started | Aug 06 08:50:47 PM PDT 24 |
| Finished | Aug 06 08:51:54 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-22ca9143-2625-435c-a0aa-d2e95a38ffc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628379238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.2628379238 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.1948295591 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 3268969404 ps |
| CPU time | 57.24 seconds |
| Started | Aug 06 08:50:47 PM PDT 24 |
| Finished | Aug 06 08:51:44 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5dcd3683-cb3d-4e07-9e80-e2ff255023be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948295591 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.1948295591 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.247561352 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 49046647 ps |
| CPU time | 6.94 seconds |
| Started | Aug 06 08:50:48 PM PDT 24 |
| Finished | Aug 06 08:50:55 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-6c17e3c0-6eae-456d-93dd-71cf3c6a03f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247561352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delays .247561352 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.3621268467 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 4116233483 ps |
| CPU time | 312.1 seconds |
| Started | Aug 06 08:50:58 PM PDT 24 |
| Finished | Aug 06 08:56:11 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-db267c7e-8302-4fe8-a348-ee1730f2b617 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621268467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.3621268467 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.4017517798 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 8345439460 ps |
| CPU time | 339.91 seconds |
| Started | Aug 06 08:51:03 PM PDT 24 |
| Finished | Aug 06 08:56:43 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-53396788-8368-4cb6-a0c9-69fb9d082c2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4017517798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.4017517798 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.307147198 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 212347213 ps |
| CPU time | 137.54 seconds |
| Started | Aug 06 08:51:02 PM PDT 24 |
| Finished | Aug 06 08:53:20 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-6af53f6a-0456-49ce-84bc-c00df3ffeb83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307147198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.307147198 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.3214731526 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 76924462 ps |
| CPU time | 19.86 seconds |
| Started | Aug 06 08:51:03 PM PDT 24 |
| Finished | Aug 06 08:51:23 PM PDT 24 |
| Peak memory | 573952 kb |
| Host | smart-5bce7aaa-c5b9-409a-a2eb-c3bd9abd0165 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214731526 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.3214731526 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.1093759700 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 1108163389 ps |
| CPU time | 46.54 seconds |
| Started | Aug 06 08:50:58 PM PDT 24 |
| Finished | Aug 06 08:51:45 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-1d0ace8c-7659-4aed-89c5-898386c70cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093759700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.1093759700 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.235021945 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 5409932130 ps |
| CPU time | 499.86 seconds |
| Started | Aug 06 08:51:28 PM PDT 24 |
| Finished | Aug 06 08:59:48 PM PDT 24 |
| Peak memory | 639668 kb |
| Host | smart-e616f03e-5f6d-498d-ab42-13725ce8c413 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235021945 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.235021945 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.3053623879 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 5551927400 ps |
| CPU time | 705.1 seconds |
| Started | Aug 06 08:51:28 PM PDT 24 |
| Finished | Aug 06 09:03:13 PM PDT 24 |
| Peak memory | 599452 kb |
| Host | smart-e8f4a2de-506f-45fb-ae15-2877a49412d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053623879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.3053623879 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.3234298868 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 31257698118 ps |
| CPU time | 3991.16 seconds |
| Started | Aug 06 08:51:03 PM PDT 24 |
| Finished | Aug 06 09:57:35 PM PDT 24 |
| Peak memory | 593668 kb |
| Host | smart-2b8f092e-75b9-4f7f-b56a-199ed12ca216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234298868 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.3234298868 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.88102717 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 3139356915 ps |
| CPU time | 123 seconds |
| Started | Aug 06 08:51:01 PM PDT 24 |
| Finished | Aug 06 08:53:04 PM PDT 24 |
| Peak memory | 598604 kb |
| Host | smart-937f0f25-9b6f-4215-9951-95afaf8c8146 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88102717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.88102717 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.3251533598 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 1293780676 ps |
| CPU time | 60.56 seconds |
| Started | Aug 06 08:51:11 PM PDT 24 |
| Finished | Aug 06 08:52:12 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-2037121b-3055-4b18-89e0-0f783f11a5b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251533598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device .3251533598 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2301119262 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 96694147217 ps |
| CPU time | 1775.96 seconds |
| Started | Aug 06 08:51:13 PM PDT 24 |
| Finished | Aug 06 09:20:49 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-a51515c0-7dd5-4ab5-a825-4aad04b34d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301119262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.2301119262 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.725825848 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 144999969 ps |
| CPU time | 10.17 seconds |
| Started | Aug 06 08:51:18 PM PDT 24 |
| Finished | Aug 06 08:51:29 PM PDT 24 |
| Peak memory | 573788 kb |
| Host | smart-51c92ce5-7f46-4f30-9f7c-f25d4640a2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725825848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_addr .725825848 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.244830173 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 399059584 ps |
| CPU time | 16.37 seconds |
| Started | Aug 06 08:51:19 PM PDT 24 |
| Finished | Aug 06 08:51:36 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-b73cc6e9-8d24-47c0-969f-a2d7f2a0373c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244830173 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.244830173 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.4044622057 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 324330726 ps |
| CPU time | 30.71 seconds |
| Started | Aug 06 08:51:13 PM PDT 24 |
| Finished | Aug 06 08:51:43 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-5628fc90-019f-4489-9659-4b6814107389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044622057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.4044622057 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.4057864447 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 63878991965 ps |
| CPU time | 635.9 seconds |
| Started | Aug 06 08:51:10 PM PDT 24 |
| Finished | Aug 06 09:01:46 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-d4051a5a-1b17-4a7c-ae2f-e059a00312f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057864447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.4057864447 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.2932063079 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 40360494893 ps |
| CPU time | 685.54 seconds |
| Started | Aug 06 08:51:11 PM PDT 24 |
| Finished | Aug 06 09:02:37 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-40f75f27-3691-4062-b5cf-7cb406bcc9c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932063079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.2932063079 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.651281215 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 533741153 ps |
| CPU time | 57.15 seconds |
| Started | Aug 06 08:51:11 PM PDT 24 |
| Finished | Aug 06 08:52:08 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-27dd360a-d19e-449d-978f-905d69b0fc70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651281215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela ys.651281215 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.1934818864 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 435134465 ps |
| CPU time | 34.92 seconds |
| Started | Aug 06 08:51:19 PM PDT 24 |
| Finished | Aug 06 08:51:54 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-f7ab488c-3d08-4fc5-9218-3ad74254d197 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934818864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.1934818864 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.3756136893 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 240749567 ps |
| CPU time | 10.52 seconds |
| Started | Aug 06 08:51:13 PM PDT 24 |
| Finished | Aug 06 08:51:23 PM PDT 24 |
| Peak memory | 573664 kb |
| Host | smart-fc1aa176-d554-4c60-a687-b069b2215952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756136893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.3756136893 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.2980419429 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 10239331826 ps |
| CPU time | 111.55 seconds |
| Started | Aug 06 08:51:12 PM PDT 24 |
| Finished | Aug 06 08:53:04 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-c300133e-90a6-4465-818b-55495b08828c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980419429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.2980419429 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.2512596094 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 5258578634 ps |
| CPU time | 103.21 seconds |
| Started | Aug 06 08:51:09 PM PDT 24 |
| Finished | Aug 06 08:52:52 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-03a8e7f3-9d7e-4d8f-90eb-82ee7e015bcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512596094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.2512596094 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.2222043247 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 48473837 ps |
| CPU time | 6.73 seconds |
| Started | Aug 06 08:51:10 PM PDT 24 |
| Finished | Aug 06 08:51:17 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-cb7307a5-12f3-4298-ad1f-6474e6833b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222043247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.2222043247 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.3824174895 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 1558637920 ps |
| CPU time | 159.13 seconds |
| Started | Aug 06 08:51:18 PM PDT 24 |
| Finished | Aug 06 08:53:57 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-aa1022cf-0320-4694-bb1f-8c8432288d59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824174895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.3824174895 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.1308695679 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 158407582 ps |
| CPU time | 8.42 seconds |
| Started | Aug 06 08:51:29 PM PDT 24 |
| Finished | Aug 06 08:51:37 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-1d93c3fa-9446-4107-8f88-a06b6553e8b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308695679 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.1308695679 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.473305957 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 5096109664 ps |
| CPU time | 324.52 seconds |
| Started | Aug 06 08:51:34 PM PDT 24 |
| Finished | Aug 06 08:56:59 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-2c9e4ce0-5c70-429c-8485-8f3fb18b7407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473305957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_reset_error.473305957 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.411854364 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 1074558141 ps |
| CPU time | 50.62 seconds |
| Started | Aug 06 08:51:19 PM PDT 24 |
| Finished | Aug 06 08:52:10 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-5d964ba6-5472-4150-afdb-a6e77d97b61d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411854364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.411854364 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.640102090 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 11145408938 ps |
| CPU time | 875.63 seconds |
| Started | Aug 06 08:51:45 PM PDT 24 |
| Finished | Aug 06 09:06:21 PM PDT 24 |
| Peak memory | 652380 kb |
| Host | smart-4f741e74-bcf5-4bb8-adfb-3efde311b9cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640102090 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.640102090 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.1732433222 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 4332523492 ps |
| CPU time | 374.98 seconds |
| Started | Aug 06 08:51:46 PM PDT 24 |
| Finished | Aug 06 08:58:02 PM PDT 24 |
| Peak memory | 598716 kb |
| Host | smart-c69cbe17-804a-4812-b248-cb059f147a72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732433222 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1732433222 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.1737532550 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 3606347432 ps |
| CPU time | 218.12 seconds |
| Started | Aug 06 08:51:27 PM PDT 24 |
| Finished | Aug 06 08:55:06 PM PDT 24 |
| Peak memory | 603704 kb |
| Host | smart-0582e207-aeed-4353-b93d-00a041863137 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737532550 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.1737532550 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.261872179 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 951364338 ps |
| CPU time | 99.3 seconds |
| Started | Aug 06 08:51:39 PM PDT 24 |
| Finished | Aug 06 08:53:19 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-7cd56e68-081a-44de-aca1-48f0cc99589f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261872179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device. 261872179 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1377972785 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 85519238410 ps |
| CPU time | 1512.86 seconds |
| Started | Aug 06 08:51:37 PM PDT 24 |
| Finished | Aug 06 09:16:50 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-3e0ae7da-3660-4e85-b5a4-805e1ecf925f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377972785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.1377972785 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.707755237 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 210063826 ps |
| CPU time | 25.87 seconds |
| Started | Aug 06 08:51:38 PM PDT 24 |
| Finished | Aug 06 08:52:04 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-04ff07fd-b075-410e-902c-448799ee03a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707755237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_addr .707755237 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.2044375170 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 1117962734 ps |
| CPU time | 50.09 seconds |
| Started | Aug 06 08:51:38 PM PDT 24 |
| Finished | Aug 06 08:52:28 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-071dce9a-c1f1-4103-89ed-e0b2cadb0203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044375170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.2044375170 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.507691663 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 211716821 ps |
| CPU time | 22.52 seconds |
| Started | Aug 06 08:51:29 PM PDT 24 |
| Finished | Aug 06 08:51:51 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-ae0a5c5f-59d4-47cf-8030-b8dbe3b2a6b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507691663 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.507691663 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1484889580 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 4633255708 ps |
| CPU time | 49.67 seconds |
| Started | Aug 06 08:51:38 PM PDT 24 |
| Finished | Aug 06 08:52:28 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-b6daf4e0-49b5-412b-9e70-10888e290015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484889580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.1484889580 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.2746283456 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 47768232452 ps |
| CPU time | 859.1 seconds |
| Started | Aug 06 08:51:37 PM PDT 24 |
| Finished | Aug 06 09:05:57 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-901d6677-c36a-4727-b7a9-366d727b7c52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746283456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.2746283456 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3171000578 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 291315323 ps |
| CPU time | 30.89 seconds |
| Started | Aug 06 08:51:29 PM PDT 24 |
| Finished | Aug 06 08:52:00 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-dbfa05b5-13ce-4a10-bd8d-c92964ea79d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171000578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3171000578 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.3459083370 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 507944100 ps |
| CPU time | 39.31 seconds |
| Started | Aug 06 08:51:36 PM PDT 24 |
| Finished | Aug 06 08:52:16 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-40bcdf04-0a85-4f5c-ad35-97a0d3fff64e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3459083370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.3459083370 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.2033792092 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 195025166 ps |
| CPU time | 9.66 seconds |
| Started | Aug 06 08:51:29 PM PDT 24 |
| Finished | Aug 06 08:51:39 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-3f098057-a2f5-4ea3-a493-32a108a0b7c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033792092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.2033792092 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.3296182400 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 9755945293 ps |
| CPU time | 110.01 seconds |
| Started | Aug 06 08:51:27 PM PDT 24 |
| Finished | Aug 06 08:53:17 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-6b51b5e8-95ab-489e-9855-36ad63cc4252 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296182400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.3296182400 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.4289342640 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 4963901423 ps |
| CPU time | 86.63 seconds |
| Started | Aug 06 08:51:28 PM PDT 24 |
| Finished | Aug 06 08:52:55 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-e00bfa24-c155-4a6e-9586-4a4297409a92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289342640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.4289342640 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.880712920 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 59104460 ps |
| CPU time | 8 seconds |
| Started | Aug 06 08:51:30 PM PDT 24 |
| Finished | Aug 06 08:51:38 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-4582c04d-dcf1-414e-a26d-4bd86c1e113e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880712920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delays .880712920 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.2812292367 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 2567132017 ps |
| CPU time | 227.15 seconds |
| Started | Aug 06 08:51:39 PM PDT 24 |
| Finished | Aug 06 08:55:27 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-68592c0a-d86a-424b-be2e-980c2cf2b033 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812292367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.2812292367 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.988156538 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 5582252905 ps |
| CPU time | 231.33 seconds |
| Started | Aug 06 08:51:51 PM PDT 24 |
| Finished | Aug 06 08:55:43 PM PDT 24 |
| Peak memory | 576452 kb |
| Host | smart-01f5f0b8-ac25-4432-add1-e9a13a4e2fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988156538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.988156538 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.4263944645 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 7930508462 ps |
| CPU time | 474.79 seconds |
| Started | Aug 06 08:51:46 PM PDT 24 |
| Finished | Aug 06 08:59:40 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-4093e5b6-a695-470b-ac52-820127d0ddbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263944645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.4263944645 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3908204527 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 11292978312 ps |
| CPU time | 574.22 seconds |
| Started | Aug 06 08:51:43 PM PDT 24 |
| Finished | Aug 06 09:01:17 PM PDT 24 |
| Peak memory | 576720 kb |
| Host | smart-b42cbe44-fcf0-4de1-b7d3-df4ebd7866da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908204527 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_al l_with_reset_error.3908204527 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.400329156 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 938484622 ps |
| CPU time | 46.34 seconds |
| Started | Aug 06 08:51:39 PM PDT 24 |
| Finished | Aug 06 08:52:25 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-006b9e15-8d59-4385-8183-06e75735bc0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400329156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.400329156 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.3991806432 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 12479531756 ps |
| CPU time | 1018.48 seconds |
| Started | Aug 06 08:52:06 PM PDT 24 |
| Finished | Aug 06 09:09:05 PM PDT 24 |
| Peak memory | 641672 kb |
| Host | smart-e6150bab-0426-4ebf-8af7-71a41f5c78fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991806432 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.3991806432 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.443257166 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 4589218728 ps |
| CPU time | 329.95 seconds |
| Started | Aug 06 08:52:01 PM PDT 24 |
| Finished | Aug 06 08:57:31 PM PDT 24 |
| Peak memory | 597152 kb |
| Host | smart-9b46997c-cb0d-42e6-aa06-0e74cca84b1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443257166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.443257166 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.1143136142 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 29040279662 ps |
| CPU time | 3391.53 seconds |
| Started | Aug 06 08:51:50 PM PDT 24 |
| Finished | Aug 06 09:48:22 PM PDT 24 |
| Peak memory | 593340 kb |
| Host | smart-96086e39-2bab-4bcc-9a13-e374b5a0f100 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143136142 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.1143136142 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.162050726 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 3797536920 ps |
| CPU time | 224.93 seconds |
| Started | Aug 06 08:51:47 PM PDT 24 |
| Finished | Aug 06 08:55:32 PM PDT 24 |
| Peak memory | 598608 kb |
| Host | smart-4916065e-b2d4-4fc2-8292-101908fc343a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162050726 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.162050726 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.2076077984 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 2804979453 ps |
| CPU time | 135.98 seconds |
| Started | Aug 06 08:51:51 PM PDT 24 |
| Finished | Aug 06 08:54:07 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-d9c84e4a-0da5-4957-a423-3d8ecf39f5aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076077984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .2076077984 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.620136441 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 36143694705 ps |
| CPU time | 666.71 seconds |
| Started | Aug 06 08:51:52 PM PDT 24 |
| Finished | Aug 06 09:02:59 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-84c3f9e4-bd01-4fb0-9ab2-dbd7aa48fee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620136441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_d evice_slow_rsp.620136441 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.136079404 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 195435782 ps |
| CPU time | 26.61 seconds |
| Started | Aug 06 08:52:01 PM PDT 24 |
| Finished | Aug 06 08:52:28 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-6c9486e1-dd25-46f5-9c5f-7c55336f7105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136079404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_addr .136079404 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.3668640663 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 960744802 ps |
| CPU time | 35 seconds |
| Started | Aug 06 08:52:07 PM PDT 24 |
| Finished | Aug 06 08:52:42 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-06b368d1-44ef-45fd-8fe5-156227f03bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668640663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.3668640663 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.343197000 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 527368898 ps |
| CPU time | 43.2 seconds |
| Started | Aug 06 08:51:50 PM PDT 24 |
| Finished | Aug 06 08:52:33 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-11a689c9-ba1e-465c-9151-f2b4b53e3951 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343197000 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.343197000 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.797553967 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 56116776610 ps |
| CPU time | 580.27 seconds |
| Started | Aug 06 08:51:54 PM PDT 24 |
| Finished | Aug 06 09:01:34 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-66a2c47f-f993-46fe-9b37-c33819fcca3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797553967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.797553967 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.4120877811 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 13127328288 ps |
| CPU time | 234.1 seconds |
| Started | Aug 06 08:51:51 PM PDT 24 |
| Finished | Aug 06 08:55:45 PM PDT 24 |
| Peak memory | 576088 kb |
| Host | smart-5604d36e-55d9-4e67-aab1-aa4fad2527d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120877811 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.4120877811 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.3110554285 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 371135340 ps |
| CPU time | 35.03 seconds |
| Started | Aug 06 08:51:54 PM PDT 24 |
| Finished | Aug 06 08:52:29 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-21ffd21f-c27e-4a8d-93db-f4332e3a31ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110554285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.3110554285 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.920182266 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 2406143775 ps |
| CPU time | 88.92 seconds |
| Started | Aug 06 08:51:52 PM PDT 24 |
| Finished | Aug 06 08:53:20 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-7f9170c3-478c-4171-b52a-a2ca1f5c5db7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920182266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.920182266 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.1889431882 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 46593007 ps |
| CPU time | 6.64 seconds |
| Started | Aug 06 08:51:47 PM PDT 24 |
| Finished | Aug 06 08:51:54 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-d0e94569-3484-4f8d-be05-42b2b11f4d1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889431882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.1889431882 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.2584389977 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 7945632472 ps |
| CPU time | 85.83 seconds |
| Started | Aug 06 08:51:47 PM PDT 24 |
| Finished | Aug 06 08:53:13 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-f89616ca-0c17-4408-9385-c6106759063e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584389977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.2584389977 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2654812294 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 5161296433 ps |
| CPU time | 95.24 seconds |
| Started | Aug 06 08:51:46 PM PDT 24 |
| Finished | Aug 06 08:53:21 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-337a0c0e-3a69-471e-ab79-a82f4f3751ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654812294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.2654812294 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.2298764057 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 46672859 ps |
| CPU time | 6.95 seconds |
| Started | Aug 06 08:51:47 PM PDT 24 |
| Finished | Aug 06 08:51:54 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-8a6aba28-fab2-4511-8e12-56a3a3119464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298764057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.2298764057 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.2265216061 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 5400590949 ps |
| CPU time | 469.04 seconds |
| Started | Aug 06 08:51:59 PM PDT 24 |
| Finished | Aug 06 08:59:48 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-d30190c3-6629-4fd2-bbb7-62b002fea468 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265216061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.2265216061 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.3023533014 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 1999070061 ps |
| CPU time | 186.35 seconds |
| Started | Aug 06 08:51:58 PM PDT 24 |
| Finished | Aug 06 08:55:04 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-7b905de5-289a-4bf9-82a1-cf8e80774478 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023533014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.3023533014 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.682762066 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 7448265156 ps |
| CPU time | 538.08 seconds |
| Started | Aug 06 08:51:58 PM PDT 24 |
| Finished | Aug 06 09:00:56 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-b6832cb9-597e-425e-8a1d-bfdc1800c591 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682762066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_ with_rand_reset.682762066 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3035297775 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 199740576 ps |
| CPU time | 119.22 seconds |
| Started | Aug 06 08:52:00 PM PDT 24 |
| Finished | Aug 06 08:53:59 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-4f252142-ce27-4274-966e-a0c88fc9c540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035297775 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3035297775 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.195719818 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 1357709450 ps |
| CPU time | 66.73 seconds |
| Started | Aug 06 08:52:07 PM PDT 24 |
| Finished | Aug 06 08:53:13 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-693e0648-5d19-4d29-b9f4-0d8c8993aff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195719818 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.195719818 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.385367642 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 37876399889 ps |
| CPU time | 4890.81 seconds |
| Started | Aug 06 08:42:57 PM PDT 24 |
| Finished | Aug 06 10:04:29 PM PDT 24 |
| Peak memory | 593988 kb |
| Host | smart-590d9d69-9ed5-4b42-b55a-a23850dfb3d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385367642 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 2.chip_csr_aliasing.385367642 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1662244135 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 31469270250 ps |
| CPU time | 3215.33 seconds |
| Started | Aug 06 08:42:44 PM PDT 24 |
| Finished | Aug 06 09:36:20 PM PDT 24 |
| Peak memory | 592708 kb |
| Host | smart-9dc46cef-2818-4460-b2c9-5cca05e9476f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662244135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1662244135 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.1614449136 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 4411772766 ps |
| CPU time | 323.77 seconds |
| Started | Aug 06 08:43:57 PM PDT 24 |
| Finished | Aug 06 08:49:21 PM PDT 24 |
| Peak memory | 662496 kb |
| Host | smart-55dc5800-2bf6-4baa-8fba-d26dca8eb0c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614449136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.1614449136 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.1703660943 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 13151080732 ps |
| CPU time | 1026.47 seconds |
| Started | Aug 06 08:43:45 PM PDT 24 |
| Finished | Aug 06 09:00:52 PM PDT 24 |
| Peak memory | 652932 kb |
| Host | smart-46d626a8-90d0-452a-9967-b3ea9101d5b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703660943 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.1703660943 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.2660619652 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 4391995280 ps |
| CPU time | 360.32 seconds |
| Started | Aug 06 08:43:41 PM PDT 24 |
| Finished | Aug 06 08:49:41 PM PDT 24 |
| Peak memory | 597616 kb |
| Host | smart-f870c2cf-6831-419b-bbf6-b6b5a4353e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660619652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.2660619652 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1905252597 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 7489077127 ps |
| CPU time | 397.6 seconds |
| Started | Aug 06 08:43:02 PM PDT 24 |
| Finished | Aug 06 08:49:40 PM PDT 24 |
| Peak memory | 591456 kb |
| Host | smart-98b85831-e96f-4191-8821-442c59fb49cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905252597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.1905252597 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.831386893 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 10044856270 ps |
| CPU time | 427.73 seconds |
| Started | Aug 06 08:43:05 PM PDT 24 |
| Finished | Aug 06 08:50:13 PM PDT 24 |
| Peak memory | 590292 kb |
| Host | smart-2bf11f07-eb84-4486-acc0-3a4dfa44404a |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831386893 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.chip_rv_dm_lc_disabled.831386893 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1815109502 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 17091397364 ps |
| CPU time | 1719.51 seconds |
| Started | Aug 06 08:42:54 PM PDT 24 |
| Finished | Aug 06 09:11:34 PM PDT 24 |
| Peak memory | 593284 kb |
| Host | smart-ccd7c16f-bada-4b00-8a7c-5d1910269f48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815109502 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.1815109502 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.2507286003 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 677580091 ps |
| CPU time | 60.67 seconds |
| Started | Aug 06 08:43:31 PM PDT 24 |
| Finished | Aug 06 08:44:32 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-1c62d5b5-54d7-4d34-9b89-b712d4fa7750 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507286003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 2507286003 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.4005128481 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 89342580568 ps |
| CPU time | 1638.39 seconds |
| Started | Aug 06 08:43:43 PM PDT 24 |
| Finished | Aug 06 09:11:02 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-8e2bb81a-4b62-49f6-a035-1eac60402ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005128481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.4005128481 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.3282897298 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 467948238 ps |
| CPU time | 23.66 seconds |
| Started | Aug 06 08:43:38 PM PDT 24 |
| Finished | Aug 06 08:44:02 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-267ab7f4-2c88-46d2-9f07-658b6cf23b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282897298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .3282897298 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.700872829 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 307678848 ps |
| CPU time | 28.79 seconds |
| Started | Aug 06 08:43:35 PM PDT 24 |
| Finished | Aug 06 08:44:04 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-332ea8e5-fcd4-4de0-aa7b-aef89baa1dec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700872829 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.700872829 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1676633009 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 563358361 ps |
| CPU time | 52.93 seconds |
| Started | Aug 06 08:43:18 PM PDT 24 |
| Finished | Aug 06 08:44:11 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-83fa9047-6201-43b0-96e1-78e8d53f23ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676633009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1676633009 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2523143722 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 12374173477 ps |
| CPU time | 133.14 seconds |
| Started | Aug 06 08:43:23 PM PDT 24 |
| Finished | Aug 06 08:45:36 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-aacec833-1c01-4e99-854f-8e4be871008b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523143722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2523143722 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.1877650689 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 43015103426 ps |
| CPU time | 777.59 seconds |
| Started | Aug 06 08:43:27 PM PDT 24 |
| Finished | Aug 06 08:56:25 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-decdf79c-8aaa-4838-b22e-a7aa011f1619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877650689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.1877650689 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1529096910 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 251467353 ps |
| CPU time | 27.4 seconds |
| Started | Aug 06 08:43:19 PM PDT 24 |
| Finished | Aug 06 08:43:46 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-c92d166c-28e0-4963-b2b5-46a974874699 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529096910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.1529096910 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.3478223541 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 568865839 ps |
| CPU time | 48.29 seconds |
| Started | Aug 06 08:43:33 PM PDT 24 |
| Finished | Aug 06 08:44:22 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-55bdd37e-0db1-48f9-9379-6fb01071f744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478223541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3478223541 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.2328949444 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 129105740 ps |
| CPU time | 8.37 seconds |
| Started | Aug 06 08:43:02 PM PDT 24 |
| Finished | Aug 06 08:43:11 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-4f514c15-0414-4d25-8502-e1052de780bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328949444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.2328949444 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.3192701509 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 9054141876 ps |
| CPU time | 95.58 seconds |
| Started | Aug 06 08:43:12 PM PDT 24 |
| Finished | Aug 06 08:44:47 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-42ba92ca-e38c-4d84-ae37-31ad971fcc6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192701509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.3192701509 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.1576623874 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 5728325352 ps |
| CPU time | 104.73 seconds |
| Started | Aug 06 08:43:22 PM PDT 24 |
| Finished | Aug 06 08:45:07 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-5a494367-bd1d-4e39-89f3-a8393aee5548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576623874 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.1576623874 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.149582632 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 42121658 ps |
| CPU time | 6.58 seconds |
| Started | Aug 06 08:43:12 PM PDT 24 |
| Finished | Aug 06 08:43:19 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-b67aafc0-256b-4aec-84aa-c86ba622f32b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149582632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays. 149582632 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.1242480656 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2245654125 ps |
| CPU time | 194.22 seconds |
| Started | Aug 06 08:43:38 PM PDT 24 |
| Finished | Aug 06 08:46:53 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-cb876913-d10b-4e16-850d-9ff6c92a0177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242480656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.1242480656 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.1115850940 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 10389978986 ps |
| CPU time | 438.18 seconds |
| Started | Aug 06 08:44:05 PM PDT 24 |
| Finished | Aug 06 08:51:24 PM PDT 24 |
| Peak memory | 576152 kb |
| Host | smart-c026f09e-c9d6-401d-872b-da2dd0dfd56e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115850940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.1115850940 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4093825140 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 155305593 ps |
| CPU time | 28.21 seconds |
| Started | Aug 06 08:43:38 PM PDT 24 |
| Finished | Aug 06 08:44:06 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-56491d0d-54df-419e-9751-a0d70035a4a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093825140 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.4093825140 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3038266901 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 656695776 ps |
| CPU time | 37.3 seconds |
| Started | Aug 06 08:43:33 PM PDT 24 |
| Finished | Aug 06 08:44:10 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-464ac733-4a1b-461a-b1e5-3fd0323c11fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038266901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3038266901 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.794790304 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 484876925 ps |
| CPU time | 22.32 seconds |
| Started | Aug 06 08:52:15 PM PDT 24 |
| Finished | Aug 06 08:52:37 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-0941d222-6851-4318-be58-6cedc96bc403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794790304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device. 794790304 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.3466010068 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 152071791139 ps |
| CPU time | 2582.67 seconds |
| Started | Aug 06 08:52:14 PM PDT 24 |
| Finished | Aug 06 09:35:17 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-d4d5fc2a-7125-47ea-ae06-d0d88a89be20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466010068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_ device_slow_rsp.3466010068 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3017886983 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 841450123 ps |
| CPU time | 40.31 seconds |
| Started | Aug 06 08:52:15 PM PDT 24 |
| Finished | Aug 06 08:52:55 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-5c3cd841-ac30-483d-b05f-d6c3886d0b4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017886983 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.3017886983 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.170332003 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 2078657557 ps |
| CPU time | 72.05 seconds |
| Started | Aug 06 08:52:14 PM PDT 24 |
| Finished | Aug 06 08:53:26 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-9e487508-4ef9-41e0-9dcc-c5b6d25dda4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170332003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.170332003 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.2141310423 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 1913250559 ps |
| CPU time | 65.95 seconds |
| Started | Aug 06 08:52:05 PM PDT 24 |
| Finished | Aug 06 08:53:11 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-51299e47-b487-4530-ac9b-7a4a18fe066d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141310423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.2141310423 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.4291547862 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 84931056840 ps |
| CPU time | 945.42 seconds |
| Started | Aug 06 08:52:05 PM PDT 24 |
| Finished | Aug 06 09:07:51 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-1ed1f4cf-a9d0-48b3-928f-aa872a3598f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4291547862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.4291547862 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.3226983084 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 13716966497 ps |
| CPU time | 253.7 seconds |
| Started | Aug 06 08:52:15 PM PDT 24 |
| Finished | Aug 06 08:56:29 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-583c84b6-7d9b-4f6b-af9e-2fd3529fd192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226983084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.3226983084 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.3444548510 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 191984085 ps |
| CPU time | 21.52 seconds |
| Started | Aug 06 08:52:06 PM PDT 24 |
| Finished | Aug 06 08:52:27 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-2702f1d7-a089-4e09-8c3d-7c0e5271fa4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444548510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_del ays.3444548510 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.1228270442 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 520289469 ps |
| CPU time | 36.87 seconds |
| Started | Aug 06 08:52:14 PM PDT 24 |
| Finished | Aug 06 08:52:51 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-7821397d-480f-4eef-b9de-553f5c0d0bba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228270442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.1228270442 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.101396456 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 209080351 ps |
| CPU time | 9.89 seconds |
| Started | Aug 06 08:52:08 PM PDT 24 |
| Finished | Aug 06 08:52:17 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-838228e8-1141-408d-8716-b49b9d6bb6d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101396456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.101396456 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.2099601720 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 8247914107 ps |
| CPU time | 93.28 seconds |
| Started | Aug 06 08:52:07 PM PDT 24 |
| Finished | Aug 06 08:53:40 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-e777ea41-c6ff-4107-93e2-96675a2d832f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099601720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.2099601720 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.863504001 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 3688878860 ps |
| CPU time | 62.2 seconds |
| Started | Aug 06 08:52:07 PM PDT 24 |
| Finished | Aug 06 08:53:09 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-26c4a02e-3a7b-4216-9770-a107c55aae2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863504001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.863504001 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3825126915 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 46625645 ps |
| CPU time | 7.33 seconds |
| Started | Aug 06 08:52:07 PM PDT 24 |
| Finished | Aug 06 08:52:14 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-e6dd42de-8af9-4234-90b9-cee8064428d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825126915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.3825126915 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.1351997227 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 9859309810 ps |
| CPU time | 503.61 seconds |
| Started | Aug 06 08:52:20 PM PDT 24 |
| Finished | Aug 06 09:00:43 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-0987a365-611b-465c-afad-7846c00efc71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351997227 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.1351997227 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.398058078 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 329277487 ps |
| CPU time | 37.94 seconds |
| Started | Aug 06 08:52:14 PM PDT 24 |
| Finished | Aug 06 08:52:52 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-dd37af14-8a44-4861-95ca-6ef46fd6a871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398058078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.398058078 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3922872032 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 4929826598 ps |
| CPU time | 440.37 seconds |
| Started | Aug 06 08:52:26 PM PDT 24 |
| Finished | Aug 06 08:59:47 PM PDT 24 |
| Peak memory | 598676 kb |
| Host | smart-7474e95e-c9db-49eb-bf40-d102f8bc90fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922872032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3922872032 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.427824697 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 92169605 ps |
| CPU time | 8.53 seconds |
| Started | Aug 06 08:52:29 PM PDT 24 |
| Finished | Aug 06 08:52:37 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-4e2b57cd-f15a-4266-a6a0-adb1933ff204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427824697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device. 427824697 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.1554892470 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 1065283953 ps |
| CPU time | 47.14 seconds |
| Started | Aug 06 08:52:29 PM PDT 24 |
| Finished | Aug 06 08:53:16 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-1b1f1af6-c791-472e-9dd3-33ea59a3e398 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554892470 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.1554892470 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.1283278064 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 2695749584 ps |
| CPU time | 97.88 seconds |
| Started | Aug 06 08:52:28 PM PDT 24 |
| Finished | Aug 06 08:54:06 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-9ccb6bb1-d51c-4c1d-a234-1eaf16e24749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283278064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.1283278064 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.239195496 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2130591109 ps |
| CPU time | 86.45 seconds |
| Started | Aug 06 08:52:28 PM PDT 24 |
| Finished | Aug 06 08:53:55 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-2ddbdb81-7047-4eef-b6fd-43abd23086b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239195496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.239195496 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.916359408 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 16211923661 ps |
| CPU time | 188.51 seconds |
| Started | Aug 06 08:52:29 PM PDT 24 |
| Finished | Aug 06 08:55:37 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-84c9b487-bee7-4059-9861-0b1f98c2046c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916359408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.916359408 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3789168843 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 52693501424 ps |
| CPU time | 1006.41 seconds |
| Started | Aug 06 08:52:27 PM PDT 24 |
| Finished | Aug 06 09:09:14 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-96959c64-ba90-47b4-9a6b-f0255e4e8b67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789168843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.3789168843 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3153609413 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 417347796 ps |
| CPU time | 40.97 seconds |
| Started | Aug 06 08:52:29 PM PDT 24 |
| Finished | Aug 06 08:53:10 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-d8a129b3-638d-4814-b8ed-fc2790eb4677 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153609413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3153609413 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.1647048642 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 136212364 ps |
| CPU time | 12.96 seconds |
| Started | Aug 06 08:52:28 PM PDT 24 |
| Finished | Aug 06 08:52:41 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-b75cee4d-14a5-4b34-a3e4-32ed280f05ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647048642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.1647048642 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.1526728238 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 228111559 ps |
| CPU time | 9.7 seconds |
| Started | Aug 06 08:52:20 PM PDT 24 |
| Finished | Aug 06 08:52:30 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-035bc257-26ab-4a66-b0ed-cb33de58d752 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526728238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1526728238 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.2709561260 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 9182096758 ps |
| CPU time | 95.87 seconds |
| Started | Aug 06 08:52:24 PM PDT 24 |
| Finished | Aug 06 08:54:00 PM PDT 24 |
| Peak memory | 574580 kb |
| Host | smart-e7b2aeb2-4f37-4842-a6dd-c63ec8ddf9b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709561260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.2709561260 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1231673633 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 6586704615 ps |
| CPU time | 111.14 seconds |
| Started | Aug 06 08:52:24 PM PDT 24 |
| Finished | Aug 06 08:54:15 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-99cac48f-a66b-4bec-8fe7-f549bcf46280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231673633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.1231673633 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.3323958845 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 41598092 ps |
| CPU time | 6.68 seconds |
| Started | Aug 06 08:52:22 PM PDT 24 |
| Finished | Aug 06 08:52:28 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-ccc18abc-30f6-48bb-a64d-1dc1c8b2e378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323958845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.3323958845 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1337831487 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 2199724063 ps |
| CPU time | 203.34 seconds |
| Started | Aug 06 08:52:30 PM PDT 24 |
| Finished | Aug 06 08:55:53 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-e1e682d7-3ba1-4bc1-b0f0-486cfc150c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337831487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1337831487 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2648665751 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 206208861 ps |
| CPU time | 65.45 seconds |
| Started | Aug 06 08:52:35 PM PDT 24 |
| Finished | Aug 06 08:53:41 PM PDT 24 |
| Peak memory | 576596 kb |
| Host | smart-eabeb4ae-6813-4fea-a6fd-2f9065e0902c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648665751 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_al l_with_reset_error.2648665751 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.3920837020 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 235747339 ps |
| CPU time | 32.08 seconds |
| Started | Aug 06 08:52:28 PM PDT 24 |
| Finished | Aug 06 08:53:00 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-b78574c2-707e-4164-b541-047e08a95580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920837020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.3920837020 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.2430226515 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 2042900776 ps |
| CPU time | 105.71 seconds |
| Started | Aug 06 08:52:48 PM PDT 24 |
| Finished | Aug 06 08:54:34 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-3e8cb081-2725-40ff-a9da-7c74e035d4c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430226515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .2430226515 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.4160952875 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 17985347147 ps |
| CPU time | 332.18 seconds |
| Started | Aug 06 08:52:43 PM PDT 24 |
| Finished | Aug 06 08:58:16 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-bf8b81fa-cb60-4cef-aaea-a410ebdd6656 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160952875 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.4160952875 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.980585704 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 26973973 ps |
| CPU time | 6.28 seconds |
| Started | Aug 06 08:52:45 PM PDT 24 |
| Finished | Aug 06 08:52:51 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-c7177009-4a8b-4f5e-b24a-61c1c55f2f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980585704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_addr .980585704 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.2012237371 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 115443556 ps |
| CPU time | 8.35 seconds |
| Started | Aug 06 08:52:45 PM PDT 24 |
| Finished | Aug 06 08:52:53 PM PDT 24 |
| Peak memory | 573940 kb |
| Host | smart-400ffea2-57e3-4c23-8786-016a71c14f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012237371 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.2012237371 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.4128081466 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 1531853562 ps |
| CPU time | 63.96 seconds |
| Started | Aug 06 08:52:35 PM PDT 24 |
| Finished | Aug 06 08:53:39 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-586ec5a9-d375-45ac-ae7a-c59418281d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128081466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.4128081466 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1169667036 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 101093767098 ps |
| CPU time | 1134.72 seconds |
| Started | Aug 06 08:52:35 PM PDT 24 |
| Finished | Aug 06 09:11:30 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-002554e1-caa7-45ec-8af4-312037f28742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169667036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1169667036 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2874771006 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 2784975762 ps |
| CPU time | 48.69 seconds |
| Started | Aug 06 08:52:48 PM PDT 24 |
| Finished | Aug 06 08:53:36 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-c9a71069-6849-49aa-a2c0-11094f49e6df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874771006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2874771006 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.1276022653 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 128428550 ps |
| CPU time | 15.56 seconds |
| Started | Aug 06 08:52:35 PM PDT 24 |
| Finished | Aug 06 08:52:51 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0656c289-d62a-4fbe-b2e7-f457792f78e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276022653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.1276022653 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.1551580965 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2173440725 ps |
| CPU time | 68 seconds |
| Started | Aug 06 08:52:45 PM PDT 24 |
| Finished | Aug 06 08:53:54 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-7018765b-72c2-40dc-87eb-494e65703138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551580965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.1551580965 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.162230990 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 235383763 ps |
| CPU time | 10.8 seconds |
| Started | Aug 06 08:52:37 PM PDT 24 |
| Finished | Aug 06 08:52:47 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-d4979ac0-e92d-4498-9b8e-1a6ce7fab05d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162230990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.162230990 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.778835633 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 5272421356 ps |
| CPU time | 92.74 seconds |
| Started | Aug 06 08:52:38 PM PDT 24 |
| Finished | Aug 06 08:54:11 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-e8ceefd2-a1e5-476c-bc26-242ea43b5335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778835633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.778835633 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.1707560784 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 42277791 ps |
| CPU time | 6.78 seconds |
| Started | Aug 06 08:52:36 PM PDT 24 |
| Finished | Aug 06 08:52:43 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-853c2ddb-836f-4aa7-97d2-78f9aa6007be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707560784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.1707560784 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.3419432372 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 2972135297 ps |
| CPU time | 329.94 seconds |
| Started | Aug 06 08:52:47 PM PDT 24 |
| Finished | Aug 06 08:58:17 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-bcc465ba-c91d-4a0c-b0fe-63b12c0d8825 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419432372 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.3419432372 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1431391564 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 2101117228 ps |
| CPU time | 407.12 seconds |
| Started | Aug 06 08:52:46 PM PDT 24 |
| Finished | Aug 06 08:59:34 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-adce1886-9b71-4ebd-a05c-93ff6bb7d2b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431391564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1431391564 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.328304609 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 366841751 ps |
| CPU time | 223.92 seconds |
| Started | Aug 06 08:52:54 PM PDT 24 |
| Finished | Aug 06 08:56:38 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-ca3a6acc-9d91-4faf-b7e2-2d82d8d49a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328304609 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_reset_error.328304609 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.3979071539 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 120990810 ps |
| CPU time | 16.35 seconds |
| Started | Aug 06 08:52:44 PM PDT 24 |
| Finished | Aug 06 08:53:00 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-7c123269-3db1-43c1-8fc7-1ead892ce7ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979071539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.3979071539 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.3834539747 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 842642470 ps |
| CPU time | 35.42 seconds |
| Started | Aug 06 08:52:56 PM PDT 24 |
| Finished | Aug 06 08:53:31 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-6af623da-2aeb-4f81-8d6d-803a3021fa6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834539747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .3834539747 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1119037756 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 111452044664 ps |
| CPU time | 1878.91 seconds |
| Started | Aug 06 08:52:58 PM PDT 24 |
| Finished | Aug 06 09:24:17 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-4c84411a-f1d4-477b-b9f4-06c6cbc1df96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119037756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1119037756 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1100524300 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 170001290 ps |
| CPU time | 23.26 seconds |
| Started | Aug 06 08:53:04 PM PDT 24 |
| Finished | Aug 06 08:53:28 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-0d64f0a5-791c-490d-b7d6-d735375d690f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100524300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.1100524300 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.2746321562 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 588468302 ps |
| CPU time | 24.37 seconds |
| Started | Aug 06 08:52:58 PM PDT 24 |
| Finished | Aug 06 08:53:22 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-4e611c4d-a4ff-4806-9494-68f62593d347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746321562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.2746321562 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.3158462055 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 513080905 ps |
| CPU time | 21.57 seconds |
| Started | Aug 06 08:52:54 PM PDT 24 |
| Finished | Aug 06 08:53:16 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-4aa1930d-9300-41a3-b41e-cecc421455ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158462055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.3158462055 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.3026630208 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 27050637609 ps |
| CPU time | 298.32 seconds |
| Started | Aug 06 08:52:57 PM PDT 24 |
| Finished | Aug 06 08:57:56 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-41d1b877-7856-4774-8092-3520d45bea3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026630208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.3026630208 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3737583633 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 64424325772 ps |
| CPU time | 1054.15 seconds |
| Started | Aug 06 08:52:55 PM PDT 24 |
| Finished | Aug 06 09:10:30 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-90de82cc-ba6c-47d2-8fe4-95250ca515af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3737583633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3737583633 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.1141139041 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 92638081 ps |
| CPU time | 11.58 seconds |
| Started | Aug 06 08:52:55 PM PDT 24 |
| Finished | Aug 06 08:53:06 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-d72d5048-1b76-46ed-8b2c-44643fed733c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141139041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_del ays.1141139041 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.3224758061 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 143916927 ps |
| CPU time | 14.18 seconds |
| Started | Aug 06 08:52:55 PM PDT 24 |
| Finished | Aug 06 08:53:09 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-5cb13c52-fba3-4a45-9c70-e76efe4bc5bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224758061 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.3224758061 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.3230253128 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 54406152 ps |
| CPU time | 7.08 seconds |
| Started | Aug 06 08:52:55 PM PDT 24 |
| Finished | Aug 06 08:53:02 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-9b482da6-30e8-4d0c-bc00-742c4cefcdab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230253128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3230253128 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2529721368 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 7989018175 ps |
| CPU time | 89.37 seconds |
| Started | Aug 06 08:52:54 PM PDT 24 |
| Finished | Aug 06 08:54:24 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-79d59aa7-c2ab-4b5a-bbfb-04800bc8cf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529721368 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.2529721368 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.3087038554 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 5788206363 ps |
| CPU time | 102.13 seconds |
| Started | Aug 06 08:52:54 PM PDT 24 |
| Finished | Aug 06 08:54:36 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-3bd428aa-e68a-45bb-bbdf-d23081a7a824 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087038554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.3087038554 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1594586259 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 42926673 ps |
| CPU time | 6.92 seconds |
| Started | Aug 06 08:52:56 PM PDT 24 |
| Finished | Aug 06 08:53:03 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-f5171018-7dc9-4e33-b381-c759cdb8c94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594586259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.1594586259 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.1997425885 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 3806510182 ps |
| CPU time | 165.84 seconds |
| Started | Aug 06 08:53:02 PM PDT 24 |
| Finished | Aug 06 08:55:48 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-f5aee865-2005-4cf5-8473-93628119f5db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997425885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.1997425885 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.2968406499 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 927552923 ps |
| CPU time | 82.04 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:54:32 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-ff340565-0c93-4235-ba80-66613f6e5006 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968406499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.2968406499 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.3219965283 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 4035476827 ps |
| CPU time | 545.2 seconds |
| Started | Aug 06 08:53:03 PM PDT 24 |
| Finished | Aug 06 09:02:08 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-e9935ce2-804c-407c-8939-2fb04a1f9feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219965283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.3219965283 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1072807595 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 8552764029 ps |
| CPU time | 464.26 seconds |
| Started | Aug 06 08:53:04 PM PDT 24 |
| Finished | Aug 06 09:00:48 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-e70303ec-188b-45fe-b824-17011474f3f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072807595 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1072807595 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.2197737093 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 101871930 ps |
| CPU time | 8.04 seconds |
| Started | Aug 06 08:52:55 PM PDT 24 |
| Finished | Aug 06 08:53:03 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-ea603969-43c7-4ffc-8b12-7ddf169b3183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197737093 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.2197737093 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2995353196 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 16314790 ps |
| CPU time | 6.87 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:53:17 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-fc9ea342-a615-4328-9be0-047d720c3a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995353196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2995353196 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1171435878 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 35666276096 ps |
| CPU time | 619.72 seconds |
| Started | Aug 06 08:53:08 PM PDT 24 |
| Finished | Aug 06 09:03:28 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-560033fd-10d4-408a-b8ac-2cdc5206e6db |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171435878 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.1171435878 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.1379804930 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 146752663 ps |
| CPU time | 19.81 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:53:30 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-97c0082a-c8fe-4cbf-b416-f2550420fe7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379804930 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.1379804930 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.538116917 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 666131023 ps |
| CPU time | 24.94 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:53:35 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-9f894d65-06ca-49d3-a07e-b3bc92f82a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538116917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.538116917 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.4198882481 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 2375128080 ps |
| CPU time | 88.55 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:54:38 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-9e42aca8-c5f8-4cba-8b04-2d004813f6a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198882481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.4198882481 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1806357277 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 103945034582 ps |
| CPU time | 1045.82 seconds |
| Started | Aug 06 08:53:02 PM PDT 24 |
| Finished | Aug 06 09:10:27 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-9c5bc5f3-4a16-46c8-b473-4a2dd4c4b7c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806357277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1806357277 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.278087265 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 41362348844 ps |
| CPU time | 712.63 seconds |
| Started | Aug 06 08:53:05 PM PDT 24 |
| Finished | Aug 06 09:04:58 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-b90439b4-f547-4a16-8173-5fae365dd9dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278087265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.278087265 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.4091318329 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 258788047 ps |
| CPU time | 26.98 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:53:37 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-c7f04e8b-1d08-4e9f-96cd-220c2ef3f8a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091318329 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_del ays.4091318329 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.1204770030 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 108769192 ps |
| CPU time | 12.38 seconds |
| Started | Aug 06 08:53:08 PM PDT 24 |
| Finished | Aug 06 08:53:21 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-f9e407e4-956a-49a1-b366-149336cc6164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204770030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.1204770030 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.453672317 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 190320856 ps |
| CPU time | 9.33 seconds |
| Started | Aug 06 08:53:05 PM PDT 24 |
| Finished | Aug 06 08:53:14 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-a43040e5-071a-45e6-bc81-b045400f302f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453672317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.453672317 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2225579893 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 8629219724 ps |
| CPU time | 89.58 seconds |
| Started | Aug 06 08:53:02 PM PDT 24 |
| Finished | Aug 06 08:54:32 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-b4264fb6-2a32-4b44-8f7a-6144ce509f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225579893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.2225579893 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.571181408 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 6029052398 ps |
| CPU time | 109.39 seconds |
| Started | Aug 06 08:53:04 PM PDT 24 |
| Finished | Aug 06 08:54:53 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-db6847ee-10c7-4255-9ecf-567f60e93019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571181408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.571181408 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1096677489 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 49651408 ps |
| CPU time | 7.29 seconds |
| Started | Aug 06 08:53:05 PM PDT 24 |
| Finished | Aug 06 08:53:13 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-f11859cf-9feb-4baf-8aae-a4bbe9ce79bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096677489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.1096677489 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.1694478564 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2865844585 ps |
| CPU time | 302.01 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:58:12 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-4187a7e7-f2d3-43cc-a148-a690fab515e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694478564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.1694478564 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.2995195335 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 740985306 ps |
| CPU time | 72.75 seconds |
| Started | Aug 06 08:53:14 PM PDT 24 |
| Finished | Aug 06 08:54:27 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-ba814833-7cb7-4908-bcb4-565f50a2299f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995195335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.2995195335 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.582648476 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 3387075394 ps |
| CPU time | 411.12 seconds |
| Started | Aug 06 08:53:15 PM PDT 24 |
| Finished | Aug 06 09:00:06 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-d54ca6f4-1b23-410e-be34-2ae3b00640c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582648476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.582648476 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.560879237 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 134531081 ps |
| CPU time | 31.24 seconds |
| Started | Aug 06 08:53:16 PM PDT 24 |
| Finished | Aug 06 08:53:47 PM PDT 24 |
| Peak memory | 575996 kb |
| Host | smart-b0a8defd-c468-474e-8d6c-bc851c524ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560879237 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all _with_reset_error.560879237 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.2351805322 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 313929946 ps |
| CPU time | 37.51 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 08:53:47 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-5be2040b-98ce-4ce8-98cd-a4c6eb3975ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2351805322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.2351805322 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.1857298030 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 3390208312 ps |
| CPU time | 268.24 seconds |
| Started | Aug 06 08:53:17 PM PDT 24 |
| Finished | Aug 06 08:57:45 PM PDT 24 |
| Peak memory | 598632 kb |
| Host | smart-12f3ab95-f136-40b9-be3d-f81a52e1820b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857298030 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1857298030 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.3375017183 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 849782045 ps |
| CPU time | 44.76 seconds |
| Started | Aug 06 08:53:32 PM PDT 24 |
| Finished | Aug 06 08:54:16 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-f9d8493e-ca9c-413c-aeef-f9261a19d20c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375017183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .3375017183 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.1675257572 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 75856082710 ps |
| CPU time | 1291.83 seconds |
| Started | Aug 06 08:53:30 PM PDT 24 |
| Finished | Aug 06 09:15:02 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-78d9ec15-f6c3-4b20-a977-221378ccde1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675257572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_ device_slow_rsp.1675257572 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.3711565455 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 280573461 ps |
| CPU time | 32.4 seconds |
| Started | Aug 06 08:53:29 PM PDT 24 |
| Finished | Aug 06 08:54:02 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-52a615b8-6065-4f4d-a562-6c85cd92efd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711565455 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_add r.3711565455 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.515420164 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 108785510 ps |
| CPU time | 7.43 seconds |
| Started | Aug 06 08:53:32 PM PDT 24 |
| Finished | Aug 06 08:53:39 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-760c5cb0-2e4a-4a20-a1e0-9e744a125538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515420164 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.515420164 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.1159991376 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 636222083 ps |
| CPU time | 28.51 seconds |
| Started | Aug 06 08:53:22 PM PDT 24 |
| Finished | Aug 06 08:53:51 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-03d06efe-d5ae-4acb-8e79-1831ec5d0c04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159991376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.1159991376 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.38335902 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 63994357945 ps |
| CPU time | 633.31 seconds |
| Started | Aug 06 08:53:25 PM PDT 24 |
| Finished | Aug 06 09:03:58 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-440c6c8a-6085-413c-a95f-46dd23cd9ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38335902 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.38335902 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.2624994597 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 43102797431 ps |
| CPU time | 758.63 seconds |
| Started | Aug 06 08:53:23 PM PDT 24 |
| Finished | Aug 06 09:06:02 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-99823a54-9e08-4ea2-afb2-5fed75033076 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624994597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.2624994597 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.2471019064 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 421536510 ps |
| CPU time | 41.6 seconds |
| Started | Aug 06 08:53:22 PM PDT 24 |
| Finished | Aug 06 08:54:03 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-e5d47b43-49bf-4ff9-9338-3a7d964356e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471019064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_del ays.2471019064 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.291263554 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 432540246 ps |
| CPU time | 33.82 seconds |
| Started | Aug 06 08:53:30 PM PDT 24 |
| Finished | Aug 06 08:54:04 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-9694e505-38f0-4531-a01f-74dfcc752974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291263554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.291263554 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.698919945 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 40727001 ps |
| CPU time | 6.21 seconds |
| Started | Aug 06 08:53:17 PM PDT 24 |
| Finished | Aug 06 08:53:23 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-2b5d0e6b-ebbf-43d5-a86b-de11d16f6327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698919945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.698919945 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.2156350110 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 4942911131 ps |
| CPU time | 54.55 seconds |
| Started | Aug 06 08:53:17 PM PDT 24 |
| Finished | Aug 06 08:54:11 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-0006f280-ba0e-4be7-8ac6-ac9f50e87bfd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156350110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.2156350110 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.3685930533 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 3288490730 ps |
| CPU time | 58.75 seconds |
| Started | Aug 06 08:53:21 PM PDT 24 |
| Finished | Aug 06 08:54:20 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-d0843b6f-82ed-4f14-a966-5c67a57c4fc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685930533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.3685930533 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.2854323688 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 44806602 ps |
| CPU time | 6.42 seconds |
| Started | Aug 06 08:53:16 PM PDT 24 |
| Finished | Aug 06 08:53:23 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-d88cb7f5-6110-40a0-9e82-2563011cb391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854323688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delay s.2854323688 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.1488142492 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 3569167371 ps |
| CPU time | 327.45 seconds |
| Started | Aug 06 08:53:30 PM PDT 24 |
| Finished | Aug 06 08:58:58 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-586c6bcf-298c-49d3-a72e-b84bd986db8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488142492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.1488142492 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.219273684 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 83517648 ps |
| CPU time | 9.52 seconds |
| Started | Aug 06 08:53:33 PM PDT 24 |
| Finished | Aug 06 08:53:43 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-ddd90b71-d0ff-407a-986a-d86c61348000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219273684 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.219273684 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.2005991019 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 884964212 ps |
| CPU time | 164.5 seconds |
| Started | Aug 06 08:53:31 PM PDT 24 |
| Finished | Aug 06 08:56:16 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-b776c8e1-93da-45bd-ae16-7547ad29dcc3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005991019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all _with_rand_reset.2005991019 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.2104633336 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 1546418601 ps |
| CPU time | 300.09 seconds |
| Started | Aug 06 08:53:31 PM PDT 24 |
| Finished | Aug 06 08:58:31 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-0b7b6213-be18-46ad-b984-a866ac558a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104633336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.2104633336 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.265600944 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 221114083 ps |
| CPU time | 27.15 seconds |
| Started | Aug 06 08:53:31 PM PDT 24 |
| Finished | Aug 06 08:53:59 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-032b0807-0b38-4a15-8b87-611b53961744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265600944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.265600944 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.506930304 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 4122403260 ps |
| CPU time | 453.76 seconds |
| Started | Aug 06 08:53:34 PM PDT 24 |
| Finished | Aug 06 09:01:07 PM PDT 24 |
| Peak memory | 598572 kb |
| Host | smart-f2559de8-0138-45d3-91ce-b1e7bd7e53b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506930304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.506930304 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.3927228799 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 2529478240 ps |
| CPU time | 98.83 seconds |
| Started | Aug 06 08:53:42 PM PDT 24 |
| Finished | Aug 06 08:55:21 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-47861771-1adf-47bc-a457-5699e3875276 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927228799 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .3927228799 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2061336820 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 79044647222 ps |
| CPU time | 1371.08 seconds |
| Started | Aug 06 08:53:38 PM PDT 24 |
| Finished | Aug 06 09:16:30 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-c148c184-2f33-4932-a0e7-b3bf029bbf00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061336820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.2061336820 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.2372408972 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 172561817 ps |
| CPU time | 23.58 seconds |
| Started | Aug 06 08:53:43 PM PDT 24 |
| Finished | Aug 06 08:54:07 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-68fecbe9-82ab-4519-8a57-dc60ef3ea21d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372408972 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.2372408972 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.3128330405 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 88769681 ps |
| CPU time | 10.74 seconds |
| Started | Aug 06 08:53:40 PM PDT 24 |
| Finished | Aug 06 08:53:51 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-324fcdef-6786-4cd1-8a39-ef84443eac66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128330405 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3128330405 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.356905068 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 110634850 ps |
| CPU time | 13.58 seconds |
| Started | Aug 06 08:53:38 PM PDT 24 |
| Finished | Aug 06 08:53:51 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-0dd27cf5-1f1a-41a2-ac98-905589f7fa1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=356905068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.356905068 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.246960687 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 64492208181 ps |
| CPU time | 688.02 seconds |
| Started | Aug 06 08:53:42 PM PDT 24 |
| Finished | Aug 06 09:05:10 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-ce102aa7-0e1d-44e3-a50c-e0b07155f2f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246960687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.246960687 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1921371657 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 35361809037 ps |
| CPU time | 605.17 seconds |
| Started | Aug 06 08:53:38 PM PDT 24 |
| Finished | Aug 06 09:03:43 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-dd0a5969-169d-41d4-9e18-5cea0b7d292a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921371657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1921371657 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.451139887 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 93224407 ps |
| CPU time | 12.72 seconds |
| Started | Aug 06 08:53:41 PM PDT 24 |
| Finished | Aug 06 08:53:54 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-f116a9c1-e5af-4f3c-8071-c6e4e6d3e0e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451139887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_dela ys.451139887 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.378761452 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 739199823 ps |
| CPU time | 25.22 seconds |
| Started | Aug 06 08:53:41 PM PDT 24 |
| Finished | Aug 06 08:54:06 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-be0e5cc2-dffa-499b-892a-d98ed450ba85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378761452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.378761452 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.4164652215 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 51225271 ps |
| CPU time | 6.95 seconds |
| Started | Aug 06 08:53:30 PM PDT 24 |
| Finished | Aug 06 08:53:37 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-8a15bc6f-48c0-4a10-a9d2-c6364f9c1cfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164652215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.4164652215 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.2322625512 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 8628533186 ps |
| CPU time | 93.53 seconds |
| Started | Aug 06 08:53:32 PM PDT 24 |
| Finished | Aug 06 08:55:05 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-78094d90-0542-4582-92ff-02937a4f7c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322625512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.2322625512 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.3526467209 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 4968016656 ps |
| CPU time | 92.17 seconds |
| Started | Aug 06 08:53:42 PM PDT 24 |
| Finished | Aug 06 08:55:14 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c3861fc2-9e83-4a13-91e9-85e137b2ef66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526467209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.3526467209 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3431332691 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 38102824 ps |
| CPU time | 6.66 seconds |
| Started | Aug 06 08:53:31 PM PDT 24 |
| Finished | Aug 06 08:53:37 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-0cbf8059-1b05-4ca3-80cd-3a0caf7f86d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3431332691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.3431332691 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.1325068056 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 858080495 ps |
| CPU time | 99.62 seconds |
| Started | Aug 06 08:53:47 PM PDT 24 |
| Finished | Aug 06 08:55:27 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-cbd11e6c-231e-4bda-a4ce-1c40490d6854 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325068056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1325068056 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.3589496456 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 14714930277 ps |
| CPU time | 598.81 seconds |
| Started | Aug 06 08:53:44 PM PDT 24 |
| Finished | Aug 06 09:03:43 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-578059fc-366c-4c22-8b1c-018883540e66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589496456 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.3589496456 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.597178199 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 740122592 ps |
| CPU time | 197.68 seconds |
| Started | Aug 06 08:53:45 PM PDT 24 |
| Finished | Aug 06 08:57:03 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-eced55a2-0e83-42e7-bf1a-5f50a831f645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597178199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_ with_rand_reset.597178199 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.4187761100 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 135455996 ps |
| CPU time | 40.08 seconds |
| Started | Aug 06 08:53:44 PM PDT 24 |
| Finished | Aug 06 08:54:24 PM PDT 24 |
| Peak memory | 576072 kb |
| Host | smart-8cd19257-e504-4b0b-93c5-6af39299d4a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187761100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.4187761100 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.2613044773 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 320275852 ps |
| CPU time | 19.02 seconds |
| Started | Aug 06 08:53:46 PM PDT 24 |
| Finished | Aug 06 08:54:05 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-3ee96c0f-42e4-4efd-890b-11195bcf7e90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613044773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.2613044773 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.2007951180 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 814070113 ps |
| CPU time | 75.58 seconds |
| Started | Aug 06 08:53:53 PM PDT 24 |
| Finished | Aug 06 08:55:08 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-3af99958-a4d1-4a83-9f5c-c73c198154d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007951180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .2007951180 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.1873992603 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 48958278915 ps |
| CPU time | 884.66 seconds |
| Started | Aug 06 08:53:51 PM PDT 24 |
| Finished | Aug 06 09:08:36 PM PDT 24 |
| Peak memory | 576084 kb |
| Host | smart-85875ccb-79ba-47a4-a732-1c950b684116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873992603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.1873992603 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.2888454722 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 454679293 ps |
| CPU time | 22.72 seconds |
| Started | Aug 06 08:53:57 PM PDT 24 |
| Finished | Aug 06 08:54:19 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-d88a84bc-08b0-4ca2-86f8-490c36a1cd2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888454722 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.2888454722 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.3062125717 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 540942037 ps |
| CPU time | 46.01 seconds |
| Started | Aug 06 08:53:54 PM PDT 24 |
| Finished | Aug 06 08:54:41 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-2b339551-798a-4c7b-bdaf-d5ac23a3bd3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3062125717 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.3062125717 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.1958277270 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 1977545445 ps |
| CPU time | 72.91 seconds |
| Started | Aug 06 08:53:51 PM PDT 24 |
| Finished | Aug 06 08:55:04 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-1f1ec8d1-15b7-4e35-8731-0b06b6446c64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1958277270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1958277270 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.383218700 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 110535366486 ps |
| CPU time | 1249.91 seconds |
| Started | Aug 06 08:53:51 PM PDT 24 |
| Finished | Aug 06 09:14:41 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-bda7f8bd-456e-4bd8-a56c-dd4423a53c8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383218700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.383218700 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2130688469 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 14761793896 ps |
| CPU time | 252.21 seconds |
| Started | Aug 06 08:53:51 PM PDT 24 |
| Finished | Aug 06 08:58:03 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-0ae0a846-cc4e-4940-8171-67b3827ee705 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2130688469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2130688469 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.1152978626 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 408733895 ps |
| CPU time | 41.65 seconds |
| Started | Aug 06 08:53:50 PM PDT 24 |
| Finished | Aug 06 08:54:32 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-b3131142-650c-492f-97d3-5f1fcd7192c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152978626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.1152978626 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.3716461733 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 513086128 ps |
| CPU time | 39.22 seconds |
| Started | Aug 06 08:53:51 PM PDT 24 |
| Finished | Aug 06 08:54:30 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-11b642b7-72d6-4d19-b3fe-d71dc63b89d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716461733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.3716461733 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.3340659767 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 186141810 ps |
| CPU time | 9.48 seconds |
| Started | Aug 06 08:53:44 PM PDT 24 |
| Finished | Aug 06 08:53:54 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-29cae2e2-46f5-46c7-8a29-e745af9c4f49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340659767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.3340659767 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.1035348235 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 9165464364 ps |
| CPU time | 94.53 seconds |
| Started | Aug 06 08:53:44 PM PDT 24 |
| Finished | Aug 06 08:55:18 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-98e88a6c-9340-4d8d-a605-00733fc08a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035348235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.1035348235 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.89557015 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 5094254733 ps |
| CPU time | 93.33 seconds |
| Started | Aug 06 08:53:46 PM PDT 24 |
| Finished | Aug 06 08:55:19 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-dd80f124-d532-42b5-867c-5d889dcea2a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89557015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.89557015 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.1331595065 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 44816472 ps |
| CPU time | 6.03 seconds |
| Started | Aug 06 08:53:46 PM PDT 24 |
| Finished | Aug 06 08:53:53 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-182bd3e5-0454-4a51-831a-77d94d0a39fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331595065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.1331595065 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.2826349989 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 3358797251 ps |
| CPU time | 340.72 seconds |
| Started | Aug 06 08:53:57 PM PDT 24 |
| Finished | Aug 06 08:59:38 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-c2ff02c9-5271-48cb-913e-34158ffa61c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826349989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2826349989 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.528969060 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 2177801692 ps |
| CPU time | 74.46 seconds |
| Started | Aug 06 08:53:56 PM PDT 24 |
| Finished | Aug 06 08:55:11 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-75d4c83a-c5a1-4730-ab2e-54fe0dc423e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528969060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.528969060 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3231217690 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 4806224900 ps |
| CPU time | 272.85 seconds |
| Started | Aug 06 08:53:56 PM PDT 24 |
| Finished | Aug 06 08:58:29 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-b30b25bf-5563-4cd3-8fda-2410dd7c455c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231217690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.3231217690 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.677799090 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 585914905 ps |
| CPU time | 29.2 seconds |
| Started | Aug 06 08:53:57 PM PDT 24 |
| Finished | Aug 06 08:54:26 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-ba14d0dc-c7d6-447d-b6cf-5e836595e584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677799090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.677799090 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.1222349428 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 3676104665 ps |
| CPU time | 308.17 seconds |
| Started | Aug 06 08:53:57 PM PDT 24 |
| Finished | Aug 06 08:59:05 PM PDT 24 |
| Peak memory | 598628 kb |
| Host | smart-ad65669d-8182-4d7f-906f-55e60479e7b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1222349428 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.1222349428 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.3542522109 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 2714433028 ps |
| CPU time | 142.67 seconds |
| Started | Aug 06 08:54:07 PM PDT 24 |
| Finished | Aug 06 08:56:30 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-d8d74067-ce36-43e5-816d-1d5260d2c8cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542522109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .3542522109 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.4044166566 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 655456284 ps |
| CPU time | 28.68 seconds |
| Started | Aug 06 08:54:08 PM PDT 24 |
| Finished | Aug 06 08:54:37 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-966088e6-82f5-4645-a01a-2e8f17d4548d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044166566 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_add r.4044166566 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.925564937 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 412954419 ps |
| CPU time | 40.16 seconds |
| Started | Aug 06 08:54:09 PM PDT 24 |
| Finished | Aug 06 08:54:49 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-ccb110a2-60ea-4d7d-9ff6-cd54cdf64236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925564937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.925564937 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.2742060340 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 556879051 ps |
| CPU time | 25.93 seconds |
| Started | Aug 06 08:54:05 PM PDT 24 |
| Finished | Aug 06 08:54:31 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-f50e1c45-7cc9-4161-b640-218c458f821c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742060340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.2742060340 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.1066900388 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 66957152305 ps |
| CPU time | 716.41 seconds |
| Started | Aug 06 08:54:07 PM PDT 24 |
| Finished | Aug 06 09:06:03 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-a48c6ee2-a666-4dee-8058-65c26faed118 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066900388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.1066900388 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.3428613694 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 1533663219 ps |
| CPU time | 27 seconds |
| Started | Aug 06 08:54:06 PM PDT 24 |
| Finished | Aug 06 08:54:33 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-1328cdad-fc7f-4c29-9d57-c3f0f06cdbc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428613694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.3428613694 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.3054041134 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 358379494 ps |
| CPU time | 32.35 seconds |
| Started | Aug 06 08:54:02 PM PDT 24 |
| Finished | Aug 06 08:54:34 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-d5c59867-f850-4e08-b9dd-9731788366d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054041134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.3054041134 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.3392142469 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 1925294875 ps |
| CPU time | 68.69 seconds |
| Started | Aug 06 08:54:06 PM PDT 24 |
| Finished | Aug 06 08:55:15 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-991a4e31-3a52-4816-ab7d-5df2c780de88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392142469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.3392142469 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.956357525 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 159781057 ps |
| CPU time | 9.22 seconds |
| Started | Aug 06 08:53:58 PM PDT 24 |
| Finished | Aug 06 08:54:07 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-34975dee-56a5-45bb-9bc6-b2c7b9f51b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956357525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.956357525 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.2423757587 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 10255779571 ps |
| CPU time | 108.82 seconds |
| Started | Aug 06 08:54:06 PM PDT 24 |
| Finished | Aug 06 08:55:55 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-ef22956a-a28e-41e6-91b7-23ab31516f1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423757587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.2423757587 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.155541316 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 3948734600 ps |
| CPU time | 73.63 seconds |
| Started | Aug 06 08:54:03 PM PDT 24 |
| Finished | Aug 06 08:55:17 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-43e37085-ddb3-45f4-be2e-5f12229eb04e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155541316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.155541316 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.2409382956 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 42747802 ps |
| CPU time | 6.49 seconds |
| Started | Aug 06 08:54:01 PM PDT 24 |
| Finished | Aug 06 08:54:08 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-1593bf59-71fd-4dd7-9c69-93071dd9c9cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409382956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delay s.2409382956 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.319991269 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 2369528347 ps |
| CPU time | 105.49 seconds |
| Started | Aug 06 08:54:08 PM PDT 24 |
| Finished | Aug 06 08:55:53 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-383c43f8-1cc2-41f4-8b8f-9e405121ef3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319991269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.319991269 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.1980677375 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 17041640470 ps |
| CPU time | 641.25 seconds |
| Started | Aug 06 08:54:13 PM PDT 24 |
| Finished | Aug 06 09:04:55 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-c12d03f2-e504-446f-aa4a-bd155baedc3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980677375 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.1980677375 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.3883720347 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 19597970089 ps |
| CPU time | 897.08 seconds |
| Started | Aug 06 08:54:13 PM PDT 24 |
| Finished | Aug 06 09:09:11 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-9f1608e5-e69b-4343-a6af-a36700cda8b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883720347 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.3883720347 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.3009095133 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 4155305618 ps |
| CPU time | 610.82 seconds |
| Started | Aug 06 08:54:13 PM PDT 24 |
| Finished | Aug 06 09:04:24 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-fea10515-a565-4acf-9590-cfe60d2925d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3009095133 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.3009095133 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1318831636 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 189647947 ps |
| CPU time | 28.57 seconds |
| Started | Aug 06 08:54:07 PM PDT 24 |
| Finished | Aug 06 08:54:36 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-48eb2740-32cb-4e97-b04e-296f3d27329d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318831636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.1318831636 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3870869190 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 2894622510 ps |
| CPU time | 177.29 seconds |
| Started | Aug 06 08:54:13 PM PDT 24 |
| Finished | Aug 06 08:57:10 PM PDT 24 |
| Peak memory | 598604 kb |
| Host | smart-b609ac04-84f1-474b-8b31-56b61fd7f477 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3870869190 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3870869190 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.1358898362 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 1812134906 ps |
| CPU time | 67.88 seconds |
| Started | Aug 06 08:54:17 PM PDT 24 |
| Finished | Aug 06 08:55:25 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-4a6a5ead-b8b2-4072-b920-65b420b7e0f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358898362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .1358898362 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.85257870 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 1308774683 ps |
| CPU time | 50.86 seconds |
| Started | Aug 06 08:54:19 PM PDT 24 |
| Finished | Aug 06 08:55:10 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-2db947ea-abbf-4321-942b-8aafb884a7fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85257870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_addr.85257870 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.4036374766 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 713382292 ps |
| CPU time | 26.64 seconds |
| Started | Aug 06 08:54:19 PM PDT 24 |
| Finished | Aug 06 08:54:46 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-84d2d573-a94b-47af-8f34-b8109bdb53f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036374766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.4036374766 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.1974479911 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 702910235 ps |
| CPU time | 31.9 seconds |
| Started | Aug 06 08:54:16 PM PDT 24 |
| Finished | Aug 06 08:54:48 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-33bb19fa-43d1-4ff2-8d12-dbb0a4810c29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974479911 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.1974479911 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.3860143337 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 16118036772 ps |
| CPU time | 191.56 seconds |
| Started | Aug 06 08:54:15 PM PDT 24 |
| Finished | Aug 06 08:57:27 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-14304937-795a-46ab-b2aa-3a8f62722965 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860143337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.3860143337 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.2110471393 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 35249322480 ps |
| CPU time | 642.74 seconds |
| Started | Aug 06 08:54:13 PM PDT 24 |
| Finished | Aug 06 09:04:55 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-ec46e470-c801-4a77-8287-99c9e6d8d813 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110471393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.2110471393 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.2195689726 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 465125193 ps |
| CPU time | 45.25 seconds |
| Started | Aug 06 08:54:17 PM PDT 24 |
| Finished | Aug 06 08:55:02 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-c27b9462-e6c5-4e7c-8118-ef6349631d13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195689726 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.2195689726 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1765297528 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1608730870 ps |
| CPU time | 46.45 seconds |
| Started | Aug 06 08:54:12 PM PDT 24 |
| Finished | Aug 06 08:54:58 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-5a733830-80a4-407e-a263-46c545461ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765297528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1765297528 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.172881285 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 226029452 ps |
| CPU time | 9.6 seconds |
| Started | Aug 06 08:54:11 PM PDT 24 |
| Finished | Aug 06 08:54:21 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-8eed1e9c-9d87-4539-803f-79c1ea6fed42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172881285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.172881285 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3262637937 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 8773891827 ps |
| CPU time | 97.28 seconds |
| Started | Aug 06 08:54:12 PM PDT 24 |
| Finished | Aug 06 08:55:50 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-b8ca5dc0-dc96-4e2d-b57d-94957e037a9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262637937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3262637937 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3837497225 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 5980037073 ps |
| CPU time | 109.58 seconds |
| Started | Aug 06 08:54:15 PM PDT 24 |
| Finished | Aug 06 08:56:04 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-921379ef-e653-40dc-a6bb-957e628db263 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837497225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3837497225 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.3680806065 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 45860343 ps |
| CPU time | 7.06 seconds |
| Started | Aug 06 08:54:12 PM PDT 24 |
| Finished | Aug 06 08:54:20 PM PDT 24 |
| Peak memory | 573668 kb |
| Host | smart-c763e6bb-a50d-4d99-9739-c07962a4194c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680806065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delay s.3680806065 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.4194755083 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 15684521544 ps |
| CPU time | 582.77 seconds |
| Started | Aug 06 08:54:18 PM PDT 24 |
| Finished | Aug 06 09:04:01 PM PDT 24 |
| Peak memory | 576056 kb |
| Host | smart-909bbe2a-c1a0-47fa-b2b2-8cdea9e096b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194755083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.4194755083 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.1845469211 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 11356931190 ps |
| CPU time | 418.4 seconds |
| Started | Aug 06 08:54:19 PM PDT 24 |
| Finished | Aug 06 09:01:18 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-7aede1ad-2245-4751-afff-b4b253e01768 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845469211 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.1845469211 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.2087871502 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 5133045060 ps |
| CPU time | 215.54 seconds |
| Started | Aug 06 08:54:19 PM PDT 24 |
| Finished | Aug 06 08:57:54 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-bc7a9997-68ff-4773-8ffa-ba55e2c1cb72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087871502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.2087871502 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.4089414044 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 18134643 ps |
| CPU time | 6.03 seconds |
| Started | Aug 06 08:54:18 PM PDT 24 |
| Finished | Aug 06 08:54:24 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-279983ad-0d2b-4f77-bbea-bcbd168e27be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089414044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.4089414044 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.2114474841 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 4881691775 ps |
| CPU time | 455.82 seconds |
| Started | Aug 06 08:43:45 PM PDT 24 |
| Finished | Aug 06 08:51:21 PM PDT 24 |
| Peak memory | 592360 kb |
| Host | smart-bcefb1ad-8aae-40ad-b1cb-1678239989eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114474841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.2114474841 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.1858498145 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 4344540196 ps |
| CPU time | 518 seconds |
| Started | Aug 06 08:44:59 PM PDT 24 |
| Finished | Aug 06 08:53:37 PM PDT 24 |
| Peak memory | 598652 kb |
| Host | smart-a0ec17cd-068f-46e5-85e4-9cd630ba5254 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858498145 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.1858498145 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1529121274 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 26757018207 ps |
| CPU time | 3739.85 seconds |
| Started | Aug 06 08:43:46 PM PDT 24 |
| Finished | Aug 06 09:46:07 PM PDT 24 |
| Peak memory | 593464 kb |
| Host | smart-61825f5d-bb70-436c-bd97-0300b775bbb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529121274 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.1529121274 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.200057364 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 2918132583 ps |
| CPU time | 202.45 seconds |
| Started | Aug 06 08:43:50 PM PDT 24 |
| Finished | Aug 06 08:47:13 PM PDT 24 |
| Peak memory | 601784 kb |
| Host | smart-fd07809c-423c-4c87-b104-35fba0dd75ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200057364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.200057364 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.725598041 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 2643814102 ps |
| CPU time | 120.9 seconds |
| Started | Aug 06 08:44:16 PM PDT 24 |
| Finished | Aug 06 08:46:17 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-72dc07f5-bbe4-48ff-9327-4d8699e5428d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725598041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device.725598041 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.1951885631 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 11197853672 ps |
| CPU time | 211.19 seconds |
| Started | Aug 06 08:44:14 PM PDT 24 |
| Finished | Aug 06 08:47:45 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-9150ddf2-ea72-42de-a37b-020bc1e19ff1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1951885631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_d evice_slow_rsp.1951885631 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3190007160 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 344807708 ps |
| CPU time | 18.32 seconds |
| Started | Aug 06 08:44:13 PM PDT 24 |
| Finished | Aug 06 08:44:31 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-86480118-1379-4a01-a342-3a10a6207764 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190007160 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .3190007160 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.2268228891 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 915466404 ps |
| CPU time | 34.03 seconds |
| Started | Aug 06 08:44:16 PM PDT 24 |
| Finished | Aug 06 08:44:50 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-5536987d-a084-4e8e-83c2-726a4d2ccaad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2268228891 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.2268228891 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.465349928 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 321117280 ps |
| CPU time | 31.78 seconds |
| Started | Aug 06 08:43:59 PM PDT 24 |
| Finished | Aug 06 08:44:31 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-185937ec-dc32-4a5c-afd4-bb0e8943d138 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465349928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.465349928 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.1182607179 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 71994893779 ps |
| CPU time | 767.82 seconds |
| Started | Aug 06 08:44:06 PM PDT 24 |
| Finished | Aug 06 08:56:54 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-2a84f1b1-2c01-4fd0-a0c7-6fe613ca7cb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182607179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.1182607179 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3978492079 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 28098116319 ps |
| CPU time | 495.31 seconds |
| Started | Aug 06 08:44:14 PM PDT 24 |
| Finished | Aug 06 08:52:29 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-187791f1-590c-4b14-9911-d7577e869346 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978492079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.3978492079 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.1158931835 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 435966980 ps |
| CPU time | 41.96 seconds |
| Started | Aug 06 08:44:07 PM PDT 24 |
| Finished | Aug 06 08:44:49 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-3a231c81-e0f6-4852-b01b-333d42eff5a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158931835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.1158931835 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.2095971693 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 434511028 ps |
| CPU time | 16.43 seconds |
| Started | Aug 06 08:44:16 PM PDT 24 |
| Finished | Aug 06 08:44:33 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-dfc86a46-f87e-4e2d-a404-af3b7655409c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2095971693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.2095971693 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.3609778687 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 247656141 ps |
| CPU time | 11.17 seconds |
| Started | Aug 06 08:43:52 PM PDT 24 |
| Finished | Aug 06 08:44:03 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-7ac05196-e255-427d-b5d9-1aefd76c9cc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609778687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.3609778687 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.689639430 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 7070423838 ps |
| CPU time | 73.92 seconds |
| Started | Aug 06 08:44:02 PM PDT 24 |
| Finished | Aug 06 08:45:16 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-13307a95-31e5-4437-9fb0-e0d322532d6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689639430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.689639430 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.1058046078 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 4751273008 ps |
| CPU time | 84.82 seconds |
| Started | Aug 06 08:43:59 PM PDT 24 |
| Finished | Aug 06 08:45:24 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-bbb3c6f0-716f-436c-83de-cecb12a13e09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058046078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.1058046078 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2472178487 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 41562749 ps |
| CPU time | 6.59 seconds |
| Started | Aug 06 08:43:53 PM PDT 24 |
| Finished | Aug 06 08:44:00 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-63c869ef-9f65-4c05-9981-bb740e8fd7ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472178487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .2472178487 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2412222322 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 4080239069 ps |
| CPU time | 160.47 seconds |
| Started | Aug 06 08:44:18 PM PDT 24 |
| Finished | Aug 06 08:46:59 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-6723ecca-7f21-4b72-990c-61b45a2b7d16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412222322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2412222322 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.3845171503 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 4846945476 ps |
| CPU time | 188.41 seconds |
| Started | Aug 06 08:44:32 PM PDT 24 |
| Finished | Aug 06 08:47:40 PM PDT 24 |
| Peak memory | 576564 kb |
| Host | smart-da1d003c-02a7-4885-b3b1-a61f3aab20ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845171503 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.3845171503 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.27747487 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 314643054 ps |
| CPU time | 78.59 seconds |
| Started | Aug 06 08:44:27 PM PDT 24 |
| Finished | Aug 06 08:45:46 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-2d0e18d5-1438-4db6-9ba8-f9d1f2d0b150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27747487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_w ith_reset_error.27747487 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2013391136 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 554242408 ps |
| CPU time | 28.86 seconds |
| Started | Aug 06 08:44:13 PM PDT 24 |
| Finished | Aug 06 08:44:42 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-cb2caf02-fc9f-42d9-9ae0-890dac26f7e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013391136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2013391136 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.4042010227 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 3353605944 ps |
| CPU time | 156.68 seconds |
| Started | Aug 06 08:54:21 PM PDT 24 |
| Finished | Aug 06 08:56:57 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-95ed4615-b7e8-4b51-8eb0-d1e0796cb2ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042010227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device .4042010227 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.4080581700 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 112998773989 ps |
| CPU time | 2047.78 seconds |
| Started | Aug 06 08:54:25 PM PDT 24 |
| Finished | Aug 06 09:28:33 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-c81e6bbf-738c-49b6-a585-c73817ab8154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4080581700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.4080581700 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2339200723 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 1039368920 ps |
| CPU time | 45.66 seconds |
| Started | Aug 06 08:54:28 PM PDT 24 |
| Finished | Aug 06 08:55:14 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-64ff4025-0ceb-4023-9173-f353b88aa730 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339200723 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.2339200723 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.31901614 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 149678904 ps |
| CPU time | 17.36 seconds |
| Started | Aug 06 08:54:27 PM PDT 24 |
| Finished | Aug 06 08:54:44 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-c576a763-e144-481d-ab80-68fefd6ceff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31901614 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.31901614 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.2891381738 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 304920268 ps |
| CPU time | 15.5 seconds |
| Started | Aug 06 08:54:26 PM PDT 24 |
| Finished | Aug 06 08:54:42 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-3090a6c1-9f04-4698-85da-e1cc1eb0d14b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891381738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.2891381738 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.166266903 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 81596952022 ps |
| CPU time | 882.02 seconds |
| Started | Aug 06 08:54:24 PM PDT 24 |
| Finished | Aug 06 09:09:06 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-95206aed-6206-4879-a5e2-c80023ca665c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166266903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.166266903 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.3746283169 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 22143378659 ps |
| CPU time | 407.2 seconds |
| Started | Aug 06 08:54:23 PM PDT 24 |
| Finished | Aug 06 09:01:11 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-e3df9d5d-9dd3-412d-94e9-16f7ac690eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746283169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.3746283169 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2683541462 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 184306063 ps |
| CPU time | 18.85 seconds |
| Started | Aug 06 08:54:29 PM PDT 24 |
| Finished | Aug 06 08:54:48 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-c52d8bc3-df3e-4fe4-bfdf-4ae3fb84d77b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683541462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_del ays.2683541462 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.2431022375 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 775144281 ps |
| CPU time | 27.48 seconds |
| Started | Aug 06 08:54:27 PM PDT 24 |
| Finished | Aug 06 08:54:55 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-6571c943-76d1-403f-83f9-85b9692d936f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431022375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.2431022375 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.1498661498 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 47141326 ps |
| CPU time | 6.94 seconds |
| Started | Aug 06 08:54:18 PM PDT 24 |
| Finished | Aug 06 08:54:25 PM PDT 24 |
| Peak memory | 574428 kb |
| Host | smart-6904f7d9-9062-4638-bc68-f1d27af9c55b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498661498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1498661498 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1397488096 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 8152527904 ps |
| CPU time | 89.31 seconds |
| Started | Aug 06 08:54:29 PM PDT 24 |
| Finished | Aug 06 08:55:58 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-3f8826eb-82e5-4903-857b-8a9f2232fbeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397488096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1397488096 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3559155079 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 4889178714 ps |
| CPU time | 92.39 seconds |
| Started | Aug 06 08:54:22 PM PDT 24 |
| Finished | Aug 06 08:55:55 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-b1509ea8-316f-4be4-b518-40643e6575f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559155079 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3559155079 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.2721820634 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 52097152 ps |
| CPU time | 7.53 seconds |
| Started | Aug 06 08:54:25 PM PDT 24 |
| Finished | Aug 06 08:54:33 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-56c0be9f-800b-48f2-9c9e-5a74fa51c311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721820634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.2721820634 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.1069035481 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 3106205954 ps |
| CPU time | 142.51 seconds |
| Started | Aug 06 08:54:28 PM PDT 24 |
| Finished | Aug 06 08:56:51 PM PDT 24 |
| Peak memory | 576120 kb |
| Host | smart-3704db23-a4b9-4c86-b697-34fcd0b806e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069035481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.1069035481 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1509722413 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 2103125752 ps |
| CPU time | 164.53 seconds |
| Started | Aug 06 08:54:34 PM PDT 24 |
| Finished | Aug 06 08:57:19 PM PDT 24 |
| Peak memory | 576248 kb |
| Host | smart-11059eb7-e9e9-4a79-9559-187f3501d702 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509722413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.1509722413 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1538907023 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 7702521171 ps |
| CPU time | 450.25 seconds |
| Started | Aug 06 08:54:27 PM PDT 24 |
| Finished | Aug 06 09:01:57 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-db31eb1f-4e3a-4405-8cee-d9ee17f41e55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538907023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1538907023 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.2559683110 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 2994892545 ps |
| CPU time | 246.34 seconds |
| Started | Aug 06 08:54:35 PM PDT 24 |
| Finished | Aug 06 08:58:42 PM PDT 24 |
| Peak memory | 576732 kb |
| Host | smart-ec1789df-7d14-4467-be83-3e30a44ff25b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559683110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.2559683110 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.1833229449 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 697923550 ps |
| CPU time | 34.36 seconds |
| Started | Aug 06 08:54:28 PM PDT 24 |
| Finished | Aug 06 08:55:02 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-201dc4da-4e0c-4e1c-bd4f-866808085932 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833229449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.1833229449 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.3970225909 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 829428297 ps |
| CPU time | 63.4 seconds |
| Started | Aug 06 08:54:36 PM PDT 24 |
| Finished | Aug 06 08:55:40 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-1706ecda-f7ae-470f-a6b1-6bf23329e07e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970225909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .3970225909 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.123219157 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 13404945311 ps |
| CPU time | 247.75 seconds |
| Started | Aug 06 08:54:44 PM PDT 24 |
| Finished | Aug 06 08:58:52 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-2acd05de-6969-4830-b9e2-7cb694212dc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123219157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.123219157 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1910583619 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 203506313 ps |
| CPU time | 9.96 seconds |
| Started | Aug 06 08:54:44 PM PDT 24 |
| Finished | Aug 06 08:54:54 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-aa4aa9f4-26b6-4f8e-8eed-405442c9fead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910583619 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1910583619 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.2957932686 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 548201106 ps |
| CPU time | 25.43 seconds |
| Started | Aug 06 08:54:37 PM PDT 24 |
| Finished | Aug 06 08:55:03 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d0a10a65-8b67-410b-8946-93418c2cc509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957932686 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.2957932686 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.2436133981 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 239930517 ps |
| CPU time | 20.91 seconds |
| Started | Aug 06 08:54:44 PM PDT 24 |
| Finished | Aug 06 08:55:05 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-14df426e-f001-4d0a-a0dd-56819be88308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436133981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.2436133981 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.421948217 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 16633695662 ps |
| CPU time | 181.17 seconds |
| Started | Aug 06 08:54:37 PM PDT 24 |
| Finished | Aug 06 08:57:39 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-84311283-98cf-4d83-ba53-3e7f9fe5c475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421948217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.421948217 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.1777052310 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 53298027730 ps |
| CPU time | 880.39 seconds |
| Started | Aug 06 08:54:45 PM PDT 24 |
| Finished | Aug 06 09:09:25 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-05b91894-c15c-4655-aff1-8b5588130b8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1777052310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.1777052310 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.2578259038 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 483771518 ps |
| CPU time | 52.72 seconds |
| Started | Aug 06 08:54:38 PM PDT 24 |
| Finished | Aug 06 08:55:31 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-fa6f14b8-d5b6-4e12-95d3-83eb84eadd71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578259038 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.2578259038 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.4084782460 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 577128705 ps |
| CPU time | 21.54 seconds |
| Started | Aug 06 08:54:45 PM PDT 24 |
| Finished | Aug 06 08:55:07 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-57dd3000-ec00-4caa-aa5d-afc1aa1fbd20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084782460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.4084782460 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.83971827 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 148533262 ps |
| CPU time | 8.68 seconds |
| Started | Aug 06 08:54:37 PM PDT 24 |
| Finished | Aug 06 08:54:45 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-83667257-6f55-46fd-af5a-bcb68f1536ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83971827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.83971827 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.3270901593 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 9362206006 ps |
| CPU time | 96.11 seconds |
| Started | Aug 06 08:54:35 PM PDT 24 |
| Finished | Aug 06 08:56:11 PM PDT 24 |
| Peak memory | 574544 kb |
| Host | smart-1c794210-7925-4cf6-b090-1fb4cbd1f55f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270901593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.3270901593 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1158966578 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 5651729728 ps |
| CPU time | 101.12 seconds |
| Started | Aug 06 08:54:44 PM PDT 24 |
| Finished | Aug 06 08:56:26 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-eeffd2f5-65a9-4874-b94c-f0c62f9f25a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158966578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1158966578 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.893064592 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 51449702 ps |
| CPU time | 6.41 seconds |
| Started | Aug 06 08:54:33 PM PDT 24 |
| Finished | Aug 06 08:54:39 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-72a24011-469f-45b2-8f2c-e4d87b949de9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893064592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delays .893064592 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.1359568576 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 6092691937 ps |
| CPU time | 252.43 seconds |
| Started | Aug 06 08:54:37 PM PDT 24 |
| Finished | Aug 06 08:58:50 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-cecc427f-bab6-4098-89fb-58e303b68ad4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359568576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.1359568576 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.4144866327 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 1005692352 ps |
| CPU time | 78.43 seconds |
| Started | Aug 06 08:54:37 PM PDT 24 |
| Finished | Aug 06 08:55:56 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-838d77bc-975a-45a8-a3f3-cfd9375646fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144866327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.4144866327 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.2101640320 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 5191184108 ps |
| CPU time | 375.28 seconds |
| Started | Aug 06 08:54:37 PM PDT 24 |
| Finished | Aug 06 09:00:52 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-b725befb-cc21-4067-b0c5-ce92b7ad4274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101640320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_rand_reset.2101640320 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.3242725791 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 7646242361 ps |
| CPU time | 548.14 seconds |
| Started | Aug 06 08:54:47 PM PDT 24 |
| Finished | Aug 06 09:03:55 PM PDT 24 |
| Peak memory | 577708 kb |
| Host | smart-e546324f-9c3d-414f-9d31-d2f5697bf970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242725791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_al l_with_reset_error.3242725791 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1264899824 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 375649035 ps |
| CPU time | 18.6 seconds |
| Started | Aug 06 08:54:38 PM PDT 24 |
| Finished | Aug 06 08:54:57 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-a4a5259f-fa99-48f4-a7b9-9410ea3632dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264899824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1264899824 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.401172446 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 998808573 ps |
| CPU time | 48.56 seconds |
| Started | Aug 06 08:54:50 PM PDT 24 |
| Finished | Aug 06 08:55:39 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-8f8b1038-eeab-44fa-9a74-9ff1925267e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401172446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device. 401172446 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.546976893 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 155493387954 ps |
| CPU time | 2806.58 seconds |
| Started | Aug 06 08:54:52 PM PDT 24 |
| Finished | Aug 06 09:41:39 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-816e94a9-b425-46c1-a798-d2bfa4b647bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546976893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_d evice_slow_rsp.546976893 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.620062231 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 1133793448 ps |
| CPU time | 50.07 seconds |
| Started | Aug 06 08:54:51 PM PDT 24 |
| Finished | Aug 06 08:55:41 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-250982e1-42af-4c9d-b83e-de2ac8b90a1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620062231 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_addr .620062231 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.1154369949 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 943415917 ps |
| CPU time | 36.45 seconds |
| Started | Aug 06 08:54:49 PM PDT 24 |
| Finished | Aug 06 08:55:26 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-9f5016a5-c227-4ba0-b304-9c22643004c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154369949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.1154369949 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.2156503054 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 1723473576 ps |
| CPU time | 69.33 seconds |
| Started | Aug 06 08:54:45 PM PDT 24 |
| Finished | Aug 06 08:55:54 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-2e489b3c-8ddc-4dcf-8dc4-99ea7d82f059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156503054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.2156503054 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.765391208 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 48172881465 ps |
| CPU time | 530.15 seconds |
| Started | Aug 06 08:54:50 PM PDT 24 |
| Finished | Aug 06 09:03:40 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-0e13a879-dbc5-4984-9563-6324f5fb1a25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765391208 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.765391208 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.1585235353 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 33702970158 ps |
| CPU time | 563 seconds |
| Started | Aug 06 08:54:49 PM PDT 24 |
| Finished | Aug 06 09:04:12 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-aa4c125e-6654-4e40-857a-d327b910dd9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585235353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.1585235353 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.1634204023 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 155021139 ps |
| CPU time | 17.53 seconds |
| Started | Aug 06 08:54:47 PM PDT 24 |
| Finished | Aug 06 08:55:05 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-0623272d-326a-4fe4-9456-258b469558f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1634204023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_del ays.1634204023 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.3025631054 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 371705219 ps |
| CPU time | 15.44 seconds |
| Started | Aug 06 08:54:50 PM PDT 24 |
| Finished | Aug 06 08:55:05 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-637feb7b-3c82-47cf-87f0-a039f80f432b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025631054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.3025631054 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.3996544487 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 175182594 ps |
| CPU time | 8.85 seconds |
| Started | Aug 06 08:54:45 PM PDT 24 |
| Finished | Aug 06 08:54:54 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-4cf4aefe-0760-4b3f-9ab2-600dcdb32c39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996544487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.3996544487 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.324779956 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 8068768484 ps |
| CPU time | 92.63 seconds |
| Started | Aug 06 08:54:42 PM PDT 24 |
| Finished | Aug 06 08:56:15 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-eb1458a8-1481-442d-acbf-9c515c9b0183 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=324779956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.324779956 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.3436526643 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 4610541038 ps |
| CPU time | 82.22 seconds |
| Started | Aug 06 08:54:42 PM PDT 24 |
| Finished | Aug 06 08:56:04 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-c21c9e3c-5c3d-4a4b-85a4-4b09e49bc063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3436526643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.3436526643 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3978675854 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 37216110 ps |
| CPU time | 6.45 seconds |
| Started | Aug 06 08:54:45 PM PDT 24 |
| Finished | Aug 06 08:54:51 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-433d760e-29fb-45c2-bdff-d90f25d0b117 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978675854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3978675854 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.1996994514 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 7520356435 ps |
| CPU time | 283.94 seconds |
| Started | Aug 06 08:54:49 PM PDT 24 |
| Finished | Aug 06 08:59:33 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-152b2bb7-3689-4fd2-aa16-94eaf7b389d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996994514 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.1996994514 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.1946825047 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 495195077 ps |
| CPU time | 37.69 seconds |
| Started | Aug 06 08:55:00 PM PDT 24 |
| Finished | Aug 06 08:55:38 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-f09a134b-c52a-43f5-8783-6197582d33c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946825047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.1946825047 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.602430141 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 704919809 ps |
| CPU time | 237.21 seconds |
| Started | Aug 06 08:54:57 PM PDT 24 |
| Finished | Aug 06 08:58:54 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-de8a7f5e-66d2-4275-a5d8-20e9b93c42ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602430141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_ with_rand_reset.602430141 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.3452761847 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 1023452540 ps |
| CPU time | 332.47 seconds |
| Started | Aug 06 08:54:56 PM PDT 24 |
| Finished | Aug 06 09:00:29 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-a855f40d-771f-4751-bc1f-45f7a0b38b4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452761847 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.3452761847 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.3437058979 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 998233001 ps |
| CPU time | 49.47 seconds |
| Started | Aug 06 08:54:49 PM PDT 24 |
| Finished | Aug 06 08:55:39 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-bbf6c78e-17c3-4f1d-a504-8eb7dcaff6b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437058979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.3437058979 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.1756803393 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 1748725935 ps |
| CPU time | 79.15 seconds |
| Started | Aug 06 08:54:56 PM PDT 24 |
| Finished | Aug 06 08:56:15 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-b746b9df-f5bf-425c-86be-488d8622ff37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756803393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device .1756803393 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.1632290154 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 115849856269 ps |
| CPU time | 1834.81 seconds |
| Started | Aug 06 08:54:57 PM PDT 24 |
| Finished | Aug 06 09:25:32 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-1c82cfa2-3e9f-4d9e-9f09-4f646a741d91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632290154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.1632290154 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.1701686071 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 81906220 ps |
| CPU time | 7.7 seconds |
| Started | Aug 06 08:55:02 PM PDT 24 |
| Finished | Aug 06 08:55:10 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-d60f63c3-1c38-4b4b-9e5a-88484f83cf50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701686071 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.1701686071 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.4116338327 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 587370438 ps |
| CPU time | 54.64 seconds |
| Started | Aug 06 08:55:02 PM PDT 24 |
| Finished | Aug 06 08:55:57 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-40c5275c-ea59-4b86-9fe2-4a3b262b4359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116338327 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.4116338327 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.1260738866 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 533723909 ps |
| CPU time | 53.97 seconds |
| Started | Aug 06 08:54:53 PM PDT 24 |
| Finished | Aug 06 08:55:47 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-aa328531-44f3-4c00-b014-99c472e4feb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260738866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.1260738866 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.4280053528 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 87510364868 ps |
| CPU time | 939.23 seconds |
| Started | Aug 06 08:54:58 PM PDT 24 |
| Finished | Aug 06 09:10:37 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-0a4018c4-9730-40a9-830e-e7e222073a06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280053528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.4280053528 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.823403148 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 25105958594 ps |
| CPU time | 437.86 seconds |
| Started | Aug 06 08:54:56 PM PDT 24 |
| Finished | Aug 06 09:02:14 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-3b57e1ab-2633-44c2-9758-dcca8c856c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823403148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.823403148 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.799010327 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 34482065 ps |
| CPU time | 6.62 seconds |
| Started | Aug 06 08:55:00 PM PDT 24 |
| Finished | Aug 06 08:55:06 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-028e51dd-8586-425a-9801-e6769153b8ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799010327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_dela ys.799010327 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3605878221 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 1851569874 ps |
| CPU time | 52.96 seconds |
| Started | Aug 06 08:55:02 PM PDT 24 |
| Finished | Aug 06 08:55:55 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-ebaee45c-9280-470c-aa77-79f6d36f154d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605878221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3605878221 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.2590867126 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 187526721 ps |
| CPU time | 8.65 seconds |
| Started | Aug 06 08:54:56 PM PDT 24 |
| Finished | Aug 06 08:55:05 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-29b35a9c-082f-4ace-94ae-8461d8850a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590867126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.2590867126 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.2315406894 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 9220047169 ps |
| CPU time | 97.78 seconds |
| Started | Aug 06 08:54:55 PM PDT 24 |
| Finished | Aug 06 08:56:33 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-2a061c3c-78ac-4871-87b0-75ca9d25b8da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315406894 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.2315406894 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.2331217384 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 5926036346 ps |
| CPU time | 110.17 seconds |
| Started | Aug 06 08:54:56 PM PDT 24 |
| Finished | Aug 06 08:56:46 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-67520fd9-ab1f-45fe-8dac-b43dea15755e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331217384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.2331217384 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.3012547764 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 48350154 ps |
| CPU time | 6.74 seconds |
| Started | Aug 06 08:54:58 PM PDT 24 |
| Finished | Aug 06 08:55:04 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-d2b63ac8-d63a-432e-b1b0-6e8ff6fac66f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012547764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.3012547764 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.3341267290 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2224148543 ps |
| CPU time | 77.98 seconds |
| Started | Aug 06 08:55:06 PM PDT 24 |
| Finished | Aug 06 08:56:24 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-033c818a-6368-4a1b-9923-0c76e6996584 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3341267290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.3341267290 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.2791521057 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 13005080088 ps |
| CPU time | 525.16 seconds |
| Started | Aug 06 08:55:01 PM PDT 24 |
| Finished | Aug 06 09:03:47 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-3dbfc6be-2fd6-4727-9cf9-7ccdfde91ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791521057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.2791521057 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.3814029342 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 912983399 ps |
| CPU time | 292.03 seconds |
| Started | Aug 06 08:55:07 PM PDT 24 |
| Finished | Aug 06 08:59:59 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-9983f1a6-2357-495e-861e-111ac7d36a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814029342 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.3814029342 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.668421122 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 104822414 ps |
| CPU time | 15.84 seconds |
| Started | Aug 06 08:55:03 PM PDT 24 |
| Finished | Aug 06 08:55:19 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-20e600cc-ec90-4b9f-9417-3110d6a82277 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668421122 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.668421122 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.1977534684 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 994045490 ps |
| CPU time | 86.63 seconds |
| Started | Aug 06 08:55:06 PM PDT 24 |
| Finished | Aug 06 08:56:33 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-7395a7c5-4cf1-480f-bc14-00b12a188b9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977534684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .1977534684 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.1597518727 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 1214615012 ps |
| CPU time | 50.4 seconds |
| Started | Aug 06 08:55:24 PM PDT 24 |
| Finished | Aug 06 08:56:14 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-febd3376-4895-4c00-b03d-4f7c11346658 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597518727 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.1597518727 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.2012025737 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 133310369 ps |
| CPU time | 15.04 seconds |
| Started | Aug 06 08:55:25 PM PDT 24 |
| Finished | Aug 06 08:55:40 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-4a3d0c36-de51-4165-8505-46ecee9b9c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012025737 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.2012025737 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.1952977840 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 1335989414 ps |
| CPU time | 53.41 seconds |
| Started | Aug 06 08:55:23 PM PDT 24 |
| Finished | Aug 06 08:56:17 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-9fadc303-4001-481c-90e3-ebcab5413db8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952977840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1952977840 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2142693897 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 76394779347 ps |
| CPU time | 837.75 seconds |
| Started | Aug 06 08:55:24 PM PDT 24 |
| Finished | Aug 06 09:09:22 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-0630f64d-cec3-48e0-81b3-216ad80f23e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142693897 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2142693897 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.2721630065 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 59228513944 ps |
| CPU time | 1123.94 seconds |
| Started | Aug 06 08:55:06 PM PDT 24 |
| Finished | Aug 06 09:13:50 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-04f37f63-601a-400f-ac67-728aedd77ffd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721630065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.2721630065 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.2902209314 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 533657673 ps |
| CPU time | 57.38 seconds |
| Started | Aug 06 08:55:25 PM PDT 24 |
| Finished | Aug 06 08:56:22 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-3e07f6f4-9f0c-41fd-a901-306180947585 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902209314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_del ays.2902209314 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.1261229266 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 38631076 ps |
| CPU time | 5.5 seconds |
| Started | Aug 06 08:55:25 PM PDT 24 |
| Finished | Aug 06 08:55:30 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-6cf0991c-2838-4726-aa89-a683239f8b27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261229266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.1261229266 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.53261541 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 56382066 ps |
| CPU time | 6.94 seconds |
| Started | Aug 06 08:55:08 PM PDT 24 |
| Finished | Aug 06 08:55:14 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-8b0b3545-fb09-412b-bf3c-1c3cff159304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53261541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.53261541 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2648155350 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 10598299405 ps |
| CPU time | 119.51 seconds |
| Started | Aug 06 08:55:05 PM PDT 24 |
| Finished | Aug 06 08:57:05 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-91eecb45-b7a2-4579-abf5-ed5b54c31dcb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648155350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.2648155350 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.113247778 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2885725422 ps |
| CPU time | 51.64 seconds |
| Started | Aug 06 08:55:07 PM PDT 24 |
| Finished | Aug 06 08:55:58 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-fd36e3e3-ed3a-4d3a-91d1-6c516c742875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113247778 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.113247778 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.118307756 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 43163738 ps |
| CPU time | 6.41 seconds |
| Started | Aug 06 08:55:05 PM PDT 24 |
| Finished | Aug 06 08:55:12 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-fce7f378-ab53-4373-8667-055ab190870d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118307756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delays .118307756 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1364497410 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 10669163735 ps |
| CPU time | 364.27 seconds |
| Started | Aug 06 08:55:10 PM PDT 24 |
| Finished | Aug 06 09:01:14 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-789dc78d-fddd-4af1-ae6c-137a789ce2e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364497410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1364497410 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.4198562413 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 3075755437 ps |
| CPU time | 317.64 seconds |
| Started | Aug 06 08:55:12 PM PDT 24 |
| Finished | Aug 06 09:00:30 PM PDT 24 |
| Peak memory | 576068 kb |
| Host | smart-dd3814ff-668c-4b2a-bc63-8e54ca430a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198562413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.4198562413 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.80171220 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 66240162 ps |
| CPU time | 24.41 seconds |
| Started | Aug 06 08:55:12 PM PDT 24 |
| Finished | Aug 06 08:55:36 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-6e97c2ab-ffd2-4a0a-999a-0465b80e592d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80171220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_w ith_rand_reset.80171220 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.2168753919 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 7478720132 ps |
| CPU time | 416.9 seconds |
| Started | Aug 06 08:55:12 PM PDT 24 |
| Finished | Aug 06 09:02:09 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-28c6988a-8161-466c-b62e-97198bd66d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168753919 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.2168753919 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.300477957 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 212228437 ps |
| CPU time | 29.93 seconds |
| Started | Aug 06 08:55:05 PM PDT 24 |
| Finished | Aug 06 08:55:35 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-9aa5eeda-9d03-4d29-9f1c-cebd4a925d57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300477957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.300477957 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.2686206054 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 698298747 ps |
| CPU time | 57.83 seconds |
| Started | Aug 06 08:55:16 PM PDT 24 |
| Finished | Aug 06 08:56:14 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-4203a915-2062-4870-8298-ec00a0bfe026 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686206054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .2686206054 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.2333137859 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 72220749826 ps |
| CPU time | 1277.73 seconds |
| Started | Aug 06 08:55:16 PM PDT 24 |
| Finished | Aug 06 09:16:34 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-3a849e9d-6f7e-49c1-a234-524eba2f601b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333137859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_ device_slow_rsp.2333137859 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.861142514 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 408969756 ps |
| CPU time | 19.57 seconds |
| Started | Aug 06 08:55:23 PM PDT 24 |
| Finished | Aug 06 08:55:43 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-9149e679-f108-4692-9482-e0a019af29d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861142514 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_addr .861142514 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.1462732403 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 933945689 ps |
| CPU time | 36.45 seconds |
| Started | Aug 06 08:55:23 PM PDT 24 |
| Finished | Aug 06 08:56:00 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-251f985e-ea99-4b71-88a7-3c480ec2802a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462732403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.1462732403 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.1499851796 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 413487157 ps |
| CPU time | 45.57 seconds |
| Started | Aug 06 08:55:15 PM PDT 24 |
| Finished | Aug 06 08:56:01 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-7d898aeb-dcaf-4317-ac35-9ce2958c4111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499851796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.1499851796 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.3241762980 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 53618629798 ps |
| CPU time | 610.42 seconds |
| Started | Aug 06 08:55:16 PM PDT 24 |
| Finished | Aug 06 09:05:27 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-9478752a-4a47-4ecb-a742-11a6efef2335 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241762980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.3241762980 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.2779466953 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 53656271984 ps |
| CPU time | 911.5 seconds |
| Started | Aug 06 08:55:14 PM PDT 24 |
| Finished | Aug 06 09:10:26 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-5f91ddda-b920-43c7-af39-50e23bbd450c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779466953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.2779466953 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.3734258933 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 486877631 ps |
| CPU time | 42.64 seconds |
| Started | Aug 06 08:55:17 PM PDT 24 |
| Finished | Aug 06 08:56:00 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-7bec347e-ef39-4c2d-b801-caf1ecd4926a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3734258933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.3734258933 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1648178156 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 38601061 ps |
| CPU time | 6.49 seconds |
| Started | Aug 06 08:55:22 PM PDT 24 |
| Finished | Aug 06 08:55:29 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-26586513-47cc-44ee-a046-8f40d0275036 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648178156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1648178156 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.1329898569 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 42750064 ps |
| CPU time | 6.51 seconds |
| Started | Aug 06 08:55:12 PM PDT 24 |
| Finished | Aug 06 08:55:19 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-3a5dc145-fcc4-48bc-92c7-39dd6c6ea5c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329898569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.1329898569 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.1241792658 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 6966316390 ps |
| CPU time | 81.69 seconds |
| Started | Aug 06 08:55:16 PM PDT 24 |
| Finished | Aug 06 08:56:38 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-2a4c29ba-6330-421b-a6e7-870c2989ce8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241792658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.1241792658 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.2652833851 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 5649465093 ps |
| CPU time | 102.7 seconds |
| Started | Aug 06 08:55:17 PM PDT 24 |
| Finished | Aug 06 08:57:00 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-1c790e48-c879-46f0-97c4-516d310314e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652833851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.2652833851 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.2780253594 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 53315912 ps |
| CPU time | 7.84 seconds |
| Started | Aug 06 08:55:13 PM PDT 24 |
| Finished | Aug 06 08:55:21 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-b2d7d29c-4f5e-4ac0-acaf-d06876d8b205 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780253594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delay s.2780253594 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.3027379822 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 10760355656 ps |
| CPU time | 459.62 seconds |
| Started | Aug 06 08:55:21 PM PDT 24 |
| Finished | Aug 06 09:03:01 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-a4be51cb-06f4-45bb-9e47-a08dd5fbba96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3027379822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.3027379822 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.788294740 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 10581455277 ps |
| CPU time | 416.06 seconds |
| Started | Aug 06 08:55:27 PM PDT 24 |
| Finished | Aug 06 09:02:23 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-f9862c7d-d88d-4344-8894-d470d6eccd3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788294740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.788294740 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1624455327 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 214263133 ps |
| CPU time | 57.85 seconds |
| Started | Aug 06 08:55:26 PM PDT 24 |
| Finished | Aug 06 08:56:24 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-5cf2a285-ad00-47f7-9905-ce94eb77c69c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624455327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1624455327 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1320266964 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 7957455039 ps |
| CPU time | 431.15 seconds |
| Started | Aug 06 08:55:28 PM PDT 24 |
| Finished | Aug 06 09:02:39 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-576c4434-3793-4986-a9c8-f616cfdad8e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320266964 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.1320266964 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.3352543095 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 649421711 ps |
| CPU time | 31.46 seconds |
| Started | Aug 06 08:55:23 PM PDT 24 |
| Finished | Aug 06 08:55:54 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-835e526e-5f4e-4e04-9082-d13a46c02ca9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352543095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.3352543095 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.662508123 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 1131235360 ps |
| CPU time | 95.15 seconds |
| Started | Aug 06 08:55:31 PM PDT 24 |
| Finished | Aug 06 08:57:06 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-6b539734-a169-42eb-a793-2584a497beb4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662508123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device. 662508123 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2663166852 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 30945916651 ps |
| CPU time | 556.66 seconds |
| Started | Aug 06 08:55:35 PM PDT 24 |
| Finished | Aug 06 09:04:52 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-4c5693e7-d60c-4fb4-914e-e6936b65f811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663166852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_ device_slow_rsp.2663166852 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2170903719 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 1137335023 ps |
| CPU time | 49.39 seconds |
| Started | Aug 06 08:55:32 PM PDT 24 |
| Finished | Aug 06 08:56:21 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-234b9d23-4596-43ed-ade5-fc5bccca651f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170903719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_add r.2170903719 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1390935480 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 395207168 ps |
| CPU time | 19.66 seconds |
| Started | Aug 06 08:55:28 PM PDT 24 |
| Finished | Aug 06 08:55:48 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-d1356254-5e30-43b4-9a2d-95f4ff5fc7bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390935480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1390935480 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.4016749536 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 77554290422 ps |
| CPU time | 831.34 seconds |
| Started | Aug 06 08:55:35 PM PDT 24 |
| Finished | Aug 06 09:09:26 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-e57159c2-ff12-4ef5-bdee-7b27ce4f86a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016749536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.4016749536 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.3433840790 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 34740452742 ps |
| CPU time | 645.92 seconds |
| Started | Aug 06 08:55:32 PM PDT 24 |
| Finished | Aug 06 09:06:18 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-a875bb0e-4c09-4b27-90a6-39fa2ac6e9a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433840790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.3433840790 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.2687195285 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 577870677 ps |
| CPU time | 56.08 seconds |
| Started | Aug 06 08:55:28 PM PDT 24 |
| Finished | Aug 06 08:56:24 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-0852afa8-6220-4ecc-a090-92128f62f4f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687195285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.2687195285 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.4137965916 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 2015567755 ps |
| CPU time | 61.97 seconds |
| Started | Aug 06 08:55:36 PM PDT 24 |
| Finished | Aug 06 08:56:38 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-0c38a952-ca2c-4660-85d5-1f8fbc5d29ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4137965916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.4137965916 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.3284668483 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 124294746 ps |
| CPU time | 7.92 seconds |
| Started | Aug 06 08:55:29 PM PDT 24 |
| Finished | Aug 06 08:55:37 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-4efda420-707a-49c4-845c-025392ec93b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284668483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.3284668483 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.1839066971 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 7187454486 ps |
| CPU time | 80.88 seconds |
| Started | Aug 06 08:55:27 PM PDT 24 |
| Finished | Aug 06 08:56:48 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-3269eecf-9824-421d-9d87-7cd0c13a6fab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839066971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.1839066971 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.1394597660 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 4527387748 ps |
| CPU time | 82.64 seconds |
| Started | Aug 06 08:55:28 PM PDT 24 |
| Finished | Aug 06 08:56:51 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-21c155f5-411a-4e52-a5e8-8c91ec585d09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394597660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.1394597660 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.3617898652 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 44165601 ps |
| CPU time | 6.1 seconds |
| Started | Aug 06 08:55:26 PM PDT 24 |
| Finished | Aug 06 08:55:32 PM PDT 24 |
| Peak memory | 573640 kb |
| Host | smart-6f8042e2-f64e-4f1b-8f1c-b39163c8fc6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617898652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delay s.3617898652 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.3814693364 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 14682311542 ps |
| CPU time | 612.47 seconds |
| Started | Aug 06 08:55:33 PM PDT 24 |
| Finished | Aug 06 09:05:45 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-674cc9c9-264a-4598-ad83-d0c302322eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814693364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.3814693364 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.841165894 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 1077283932 ps |
| CPU time | 93.49 seconds |
| Started | Aug 06 08:55:39 PM PDT 24 |
| Finished | Aug 06 08:57:12 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-f2432745-de53-479e-a9d1-428eb58648f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841165894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.841165894 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.135575579 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 410008818 ps |
| CPU time | 179.95 seconds |
| Started | Aug 06 08:55:38 PM PDT 24 |
| Finished | Aug 06 08:58:38 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-8e525e24-5f35-4791-8a4e-151f3472f01f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135575579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_ with_rand_reset.135575579 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1273678406 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 166793224 ps |
| CPU time | 41.48 seconds |
| Started | Aug 06 08:55:37 PM PDT 24 |
| Finished | Aug 06 08:56:19 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-0f879fa3-225c-4daf-b709-e66acf3c740d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273678406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_al l_with_reset_error.1273678406 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.3849433058 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 385046855 ps |
| CPU time | 22.06 seconds |
| Started | Aug 06 08:55:39 PM PDT 24 |
| Finished | Aug 06 08:56:01 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-10c8b5a2-194c-4061-8b9d-26ba5c90e07c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849433058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.3849433058 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.3573347453 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 711095654 ps |
| CPU time | 57.99 seconds |
| Started | Aug 06 08:55:46 PM PDT 24 |
| Finished | Aug 06 08:56:44 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-246ea43e-574c-4cfa-8ab7-4cfe75de0b09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3573347453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device .3573347453 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.3800135398 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 158211070429 ps |
| CPU time | 2836.22 seconds |
| Started | Aug 06 08:55:44 PM PDT 24 |
| Finished | Aug 06 09:43:01 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-cb2929d0-8867-4c5c-bb24-01d0aee6041d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800135398 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.3800135398 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.3553004285 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 280097410 ps |
| CPU time | 14.33 seconds |
| Started | Aug 06 08:55:46 PM PDT 24 |
| Finished | Aug 06 08:56:00 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-68e9b9bf-6686-4fd3-8f66-b23f944fe4b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553004285 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.3553004285 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2332661739 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 284627718 ps |
| CPU time | 26.53 seconds |
| Started | Aug 06 08:55:43 PM PDT 24 |
| Finished | Aug 06 08:56:10 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-0530d4fc-9d94-4d70-b8ee-cb5558311e05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332661739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2332661739 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.1723284351 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 922576912 ps |
| CPU time | 35.84 seconds |
| Started | Aug 06 08:55:38 PM PDT 24 |
| Finished | Aug 06 08:56:14 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-b9fc57fd-2347-4324-8b6e-dcf6b762e91d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723284351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1723284351 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.101395833 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 100154010732 ps |
| CPU time | 1114.2 seconds |
| Started | Aug 06 08:55:44 PM PDT 24 |
| Finished | Aug 06 09:14:18 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-df2025ad-f30b-41a1-8176-5f7e630e7475 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101395833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.101395833 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2994436855 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 32297338813 ps |
| CPU time | 535.82 seconds |
| Started | Aug 06 08:55:44 PM PDT 24 |
| Finished | Aug 06 09:04:39 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-42b4e115-e9ef-4ef2-9a55-af35a2029f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994436855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2994436855 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.241418472 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 491929286 ps |
| CPU time | 42.46 seconds |
| Started | Aug 06 08:55:36 PM PDT 24 |
| Finished | Aug 06 08:56:18 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-9c69ff0f-c2cd-42bb-8603-c7621fbd2d5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241418472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_dela ys.241418472 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.2809794187 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 2518837917 ps |
| CPU time | 76.43 seconds |
| Started | Aug 06 08:55:43 PM PDT 24 |
| Finished | Aug 06 08:56:59 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-de5bda75-3b52-4512-9686-c54c4228f5d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809794187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.2809794187 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2320301928 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 230390097 ps |
| CPU time | 10.24 seconds |
| Started | Aug 06 08:55:36 PM PDT 24 |
| Finished | Aug 06 08:55:46 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-2cbd1684-d177-42a2-96b5-a816a2618e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320301928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2320301928 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.1076718517 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 9472296158 ps |
| CPU time | 104.16 seconds |
| Started | Aug 06 08:55:36 PM PDT 24 |
| Finished | Aug 06 08:57:20 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-72adbcd2-d896-48a7-a99a-7290d5ee2116 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076718517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.1076718517 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.2312016100 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 5305619702 ps |
| CPU time | 93.93 seconds |
| Started | Aug 06 08:55:36 PM PDT 24 |
| Finished | Aug 06 08:57:10 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-6d831ac4-d9e1-4562-bb77-d83b84821fdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2312016100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.2312016100 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2963286063 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 38518808 ps |
| CPU time | 6.47 seconds |
| Started | Aug 06 08:55:39 PM PDT 24 |
| Finished | Aug 06 08:55:46 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-756690d5-dd0d-42ed-ac46-c6be9eb18b20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963286063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2963286063 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.3519741176 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 3624934744 ps |
| CPU time | 317.23 seconds |
| Started | Aug 06 08:55:43 PM PDT 24 |
| Finished | Aug 06 09:01:00 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-da8585e8-e190-4e3c-93df-f8b576a89392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519741176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.3519741176 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.287792960 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 5417737707 ps |
| CPU time | 231.6 seconds |
| Started | Aug 06 08:55:53 PM PDT 24 |
| Finished | Aug 06 08:59:44 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-67839e5a-891f-4b45-9109-106e9428f3b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287792960 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.287792960 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.2128431223 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 2896643596 ps |
| CPU time | 217.05 seconds |
| Started | Aug 06 08:55:46 PM PDT 24 |
| Finished | Aug 06 08:59:23 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-f29f4913-5706-474f-99d5-b5b7926703e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128431223 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.2128431223 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2620676216 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 8974190559 ps |
| CPU time | 524.19 seconds |
| Started | Aug 06 08:55:50 PM PDT 24 |
| Finished | Aug 06 09:04:34 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-b575ee89-1b5f-418b-a03a-45752ba9c5fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620676216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.2620676216 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.3826045247 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 973803035 ps |
| CPU time | 37.43 seconds |
| Started | Aug 06 08:55:44 PM PDT 24 |
| Finished | Aug 06 08:56:21 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-473e6026-e9ce-49c6-8f89-463174ba54ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826045247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.3826045247 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.2238247856 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 1324819545 ps |
| CPU time | 66.89 seconds |
| Started | Aug 06 08:55:54 PM PDT 24 |
| Finished | Aug 06 08:57:00 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-9cbca82c-9a65-4cb7-ae6e-82653e1c6fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238247856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .2238247856 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.628294039 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 22137858269 ps |
| CPU time | 403.93 seconds |
| Started | Aug 06 08:55:56 PM PDT 24 |
| Finished | Aug 06 09:02:40 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-454b059d-ec35-4fea-8471-e3db8312c737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628294039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_d evice_slow_rsp.628294039 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3749801181 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 261052455 ps |
| CPU time | 29.27 seconds |
| Started | Aug 06 08:55:57 PM PDT 24 |
| Finished | Aug 06 08:56:27 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-51b6aed1-5251-4f8d-81b5-cc508a16a34d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749801181 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.3749801181 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.455058069 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 631336450 ps |
| CPU time | 55.66 seconds |
| Started | Aug 06 08:55:58 PM PDT 24 |
| Finished | Aug 06 08:56:53 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-40f36b8f-f48d-48b7-a5e6-67a098b17b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455058069 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.455058069 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.447881981 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 479895522 ps |
| CPU time | 44.16 seconds |
| Started | Aug 06 08:55:55 PM PDT 24 |
| Finished | Aug 06 08:56:39 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-ad0676db-b325-4ce9-890b-052ba18424cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447881981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.447881981 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.1993922140 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 64900603982 ps |
| CPU time | 684.87 seconds |
| Started | Aug 06 08:55:57 PM PDT 24 |
| Finished | Aug 06 09:07:22 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-c64590b9-b0cd-4de3-a689-12679d454185 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1993922140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.1993922140 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3494833716 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 43929957221 ps |
| CPU time | 759.34 seconds |
| Started | Aug 06 08:55:57 PM PDT 24 |
| Finished | Aug 06 09:08:37 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-2aca2ebf-e3ff-49dd-96b6-2b8a56c96ea9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494833716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3494833716 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.2506568918 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 535387719 ps |
| CPU time | 54.88 seconds |
| Started | Aug 06 08:55:50 PM PDT 24 |
| Finished | Aug 06 08:56:45 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-e65299f3-1b2a-476b-b346-81471b141c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506568918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.2506568918 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.3754975585 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2239019707 ps |
| CPU time | 74.68 seconds |
| Started | Aug 06 08:55:57 PM PDT 24 |
| Finished | Aug 06 08:57:12 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-44e94125-e402-4ad5-a0b8-192f7fadcbe1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754975585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.3754975585 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.2705956990 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 44410303 ps |
| CPU time | 6.86 seconds |
| Started | Aug 06 08:55:53 PM PDT 24 |
| Finished | Aug 06 08:56:00 PM PDT 24 |
| Peak memory | 573680 kb |
| Host | smart-b095d92e-2f12-46ba-a49a-f9846dcb6979 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705956990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.2705956990 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.2193373415 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 6911071376 ps |
| CPU time | 80.92 seconds |
| Started | Aug 06 08:55:53 PM PDT 24 |
| Finished | Aug 06 08:57:14 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-da004713-cf05-4e1d-b249-a253d494466b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193373415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.2193373415 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2011952325 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 5528149882 ps |
| CPU time | 97.45 seconds |
| Started | Aug 06 08:55:52 PM PDT 24 |
| Finished | Aug 06 08:57:30 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-da056950-bc13-4bcf-9064-4e5094a63f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011952325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2011952325 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2227072371 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 47708083 ps |
| CPU time | 6.6 seconds |
| Started | Aug 06 08:55:53 PM PDT 24 |
| Finished | Aug 06 08:55:59 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-1df2baf8-1053-44f3-8ab9-7592fce0d07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227072371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.2227072371 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.2350011725 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 5845041405 ps |
| CPU time | 233.8 seconds |
| Started | Aug 06 08:55:59 PM PDT 24 |
| Finished | Aug 06 08:59:53 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-27a17fc9-e6a6-4515-974a-28dcf24ab010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350011725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2350011725 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.3945245943 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 5821368135 ps |
| CPU time | 225.78 seconds |
| Started | Aug 06 08:56:05 PM PDT 24 |
| Finished | Aug 06 08:59:51 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-2169c817-4b0f-428c-a45b-99cc63d3d016 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945245943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.3945245943 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.1399170174 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 9591762594 ps |
| CPU time | 470.8 seconds |
| Started | Aug 06 08:55:59 PM PDT 24 |
| Finished | Aug 06 09:03:49 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-9a6e920f-86d9-46f3-8805-2568c8e04c59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399170174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.1399170174 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2456858097 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 3695744697 ps |
| CPU time | 308.35 seconds |
| Started | Aug 06 08:56:04 PM PDT 24 |
| Finished | Aug 06 09:01:13 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-191cec38-f6f0-4f30-a42e-2f975113f3dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456858097 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2456858097 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.707106428 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 1169472399 ps |
| CPU time | 57.65 seconds |
| Started | Aug 06 08:55:58 PM PDT 24 |
| Finished | Aug 06 08:56:55 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-22d7d40c-ced8-489d-922f-3ca24745c27b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707106428 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.707106428 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.2176822020 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 1128747583 ps |
| CPU time | 98.29 seconds |
| Started | Aug 06 08:56:08 PM PDT 24 |
| Finished | Aug 06 08:57:46 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-876ba302-b156-4928-830b-32870b1fe3f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176822020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .2176822020 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.68625525 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 97183416492 ps |
| CPU time | 1795.31 seconds |
| Started | Aug 06 08:56:09 PM PDT 24 |
| Finished | Aug 06 09:26:04 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-07dd7938-6389-45ce-878c-f1a83421568e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68625525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_de vice_slow_rsp.68625525 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.3281537022 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 516118192 ps |
| CPU time | 23.76 seconds |
| Started | Aug 06 08:56:06 PM PDT 24 |
| Finished | Aug 06 08:56:29 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-54c56f10-22ac-4deb-853d-e70318daf427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281537022 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.3281537022 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.550115390 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 373245717 ps |
| CPU time | 16.19 seconds |
| Started | Aug 06 08:56:08 PM PDT 24 |
| Finished | Aug 06 08:56:24 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-6b5abe38-aa6e-4fed-9f15-e5b179db350b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550115390 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.550115390 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.1724579932 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 302424200 ps |
| CPU time | 33.4 seconds |
| Started | Aug 06 08:56:05 PM PDT 24 |
| Finished | Aug 06 08:56:39 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-4e8d35ec-d297-48ef-86de-4280f347e688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724579932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.1724579932 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.287830025 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 39756456149 ps |
| CPU time | 452.35 seconds |
| Started | Aug 06 08:56:05 PM PDT 24 |
| Finished | Aug 06 09:03:38 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-b90a1dbc-92d9-47bd-a646-e30805a8944f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287830025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.287830025 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3460528158 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 67024939640 ps |
| CPU time | 1204.2 seconds |
| Started | Aug 06 08:56:06 PM PDT 24 |
| Finished | Aug 06 09:16:10 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-40e217e5-5d61-4ed6-a278-82f186626f6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460528158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3460528158 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.3110061369 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 196235394 ps |
| CPU time | 21.68 seconds |
| Started | Aug 06 08:56:06 PM PDT 24 |
| Finished | Aug 06 08:56:27 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-3269b7a7-d543-49f5-8b60-92f09d1e5956 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110061369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.3110061369 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.3833528710 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 277757341 ps |
| CPU time | 21.74 seconds |
| Started | Aug 06 08:56:06 PM PDT 24 |
| Finished | Aug 06 08:56:28 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-fb606b37-772d-48e6-80be-30406c04624a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833528710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.3833528710 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.336765623 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 189094742 ps |
| CPU time | 9.87 seconds |
| Started | Aug 06 08:56:08 PM PDT 24 |
| Finished | Aug 06 08:56:18 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-cebf9089-8680-414f-b904-b9f690183e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=336765623 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.336765623 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.874977616 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 7707321310 ps |
| CPU time | 85.1 seconds |
| Started | Aug 06 08:56:08 PM PDT 24 |
| Finished | Aug 06 08:57:33 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-b7b54fe1-a356-4359-aba8-95caac8e63c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874977616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.874977616 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.1994706140 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 4486786449 ps |
| CPU time | 78.32 seconds |
| Started | Aug 06 08:56:07 PM PDT 24 |
| Finished | Aug 06 08:57:26 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-d6db8f02-c1db-4318-951c-0b8c8b212113 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994706140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.1994706140 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.1467909307 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 52435592 ps |
| CPU time | 7.21 seconds |
| Started | Aug 06 08:56:08 PM PDT 24 |
| Finished | Aug 06 08:56:15 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-d3f9e869-7068-4fc5-8983-4aea60f0b467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467909307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delay s.1467909307 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3139293868 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 3219179985 ps |
| CPU time | 122.89 seconds |
| Started | Aug 06 08:56:07 PM PDT 24 |
| Finished | Aug 06 08:58:10 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-47d81f9a-3779-43e2-a394-db5602ddb2b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139293868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3139293868 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.3534800882 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 2502535336 ps |
| CPU time | 201.01 seconds |
| Started | Aug 06 08:56:12 PM PDT 24 |
| Finished | Aug 06 08:59:34 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-7c45007a-ad96-4658-88f8-087633e54a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534800882 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.3534800882 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.2970987929 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 13258724921 ps |
| CPU time | 560.02 seconds |
| Started | Aug 06 08:56:13 PM PDT 24 |
| Finished | Aug 06 09:05:33 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-af846dee-9e06-4515-aa54-5df58e77c00f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970987929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.2970987929 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.1707323487 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 85274104 ps |
| CPU time | 14.74 seconds |
| Started | Aug 06 08:56:08 PM PDT 24 |
| Finished | Aug 06 08:56:22 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-949eece6-ffa8-4187-bcee-8de3b41f5ba1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707323487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.1707323487 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.943025020 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 53800640752 ps |
| CPU time | 8902.58 seconds |
| Started | Aug 06 08:44:39 PM PDT 24 |
| Finished | Aug 06 11:13:03 PM PDT 24 |
| Peak memory | 639952 kb |
| Host | smart-9610965f-059d-440c-a4ef-9c898695e352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943025020 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 4.chip_csr_aliasing.943025020 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.1868352086 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 4344490818 ps |
| CPU time | 484.51 seconds |
| Started | Aug 06 08:44:39 PM PDT 24 |
| Finished | Aug 06 08:52:44 PM PDT 24 |
| Peak memory | 592776 kb |
| Host | smart-103871f8-8aa3-44a4-a338-543a49d4603c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1868352086 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.1868352086 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.940018540 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 7718385232 ps |
| CPU time | 457.72 seconds |
| Started | Aug 06 08:45:06 PM PDT 24 |
| Finished | Aug 06 08:52:44 PM PDT 24 |
| Peak memory | 664716 kb |
| Host | smart-a5e3a822-7de7-4d4b-9ac3-b3afaf821a9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940018540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re set.940018540 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.2207739276 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 12089895928 ps |
| CPU time | 801.24 seconds |
| Started | Aug 06 08:45:10 PM PDT 24 |
| Finished | Aug 06 08:58:31 PM PDT 24 |
| Peak memory | 652836 kb |
| Host | smart-b63dfa07-7d20-476c-8436-e217f619742a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207739276 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.2207739276 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.141469915 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 5498299448 ps |
| CPU time | 666.27 seconds |
| Started | Aug 06 08:45:10 PM PDT 24 |
| Finished | Aug 06 08:56:17 PM PDT 24 |
| Peak memory | 599288 kb |
| Host | smart-f0f510dc-1e03-4cc8-a9be-5f89323f80c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141469915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.141469915 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.2448517140 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 27510579852 ps |
| CPU time | 3375.48 seconds |
| Started | Aug 06 08:44:35 PM PDT 24 |
| Finished | Aug 06 09:40:51 PM PDT 24 |
| Peak memory | 593340 kb |
| Host | smart-cff4a0b6-f319-4567-adff-eb9709849607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448517140 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.2448517140 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.2339166027 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 3964721220 ps |
| CPU time | 321.69 seconds |
| Started | Aug 06 08:44:44 PM PDT 24 |
| Finished | Aug 06 08:50:05 PM PDT 24 |
| Peak memory | 603692 kb |
| Host | smart-d3c08c3e-bdb7-454d-8747-746a6bf77db0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339166027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.2339166027 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.889767747 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 569153483 ps |
| CPU time | 49.86 seconds |
| Started | Aug 06 08:44:56 PM PDT 24 |
| Finished | Aug 06 08:45:46 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-8045ca62-b5e0-435e-a9c8-51dffa3b25f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889767747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device.889767747 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3707051168 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 142431627125 ps |
| CPU time | 2571.65 seconds |
| Started | Aug 06 08:44:56 PM PDT 24 |
| Finished | Aug 06 09:27:48 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-7fa878f5-39b6-494f-878d-40388b12ed6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707051168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.3707051168 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.1841885457 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 580650261 ps |
| CPU time | 29.49 seconds |
| Started | Aug 06 08:45:02 PM PDT 24 |
| Finished | Aug 06 08:45:31 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-fa905551-f1ed-46f5-8655-1ccddf675af2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841885457 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .1841885457 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.2656882054 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 497149090 ps |
| CPU time | 20.51 seconds |
| Started | Aug 06 08:45:01 PM PDT 24 |
| Finished | Aug 06 08:45:22 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-4afd6646-328f-4958-b242-c533bc5b1394 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656882054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.2656882054 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.2534382207 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 300352499 ps |
| CPU time | 32.32 seconds |
| Started | Aug 06 08:44:55 PM PDT 24 |
| Finished | Aug 06 08:45:27 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-35f1bd1a-c0be-4023-9403-aef34fc3451e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534382207 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.2534382207 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.983236829 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 13527986550 ps |
| CPU time | 152.64 seconds |
| Started | Aug 06 08:44:54 PM PDT 24 |
| Finished | Aug 06 08:47:27 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-f4008e75-7b18-4bc3-b788-e79832ab99f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983236829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.983236829 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.2985569617 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 39864006766 ps |
| CPU time | 685.81 seconds |
| Started | Aug 06 08:44:54 PM PDT 24 |
| Finished | Aug 06 08:56:19 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-d096a1b2-4fa9-4e9b-9b42-347800ef2245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2985569617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.2985569617 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.3185160681 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 447392766 ps |
| CPU time | 55.61 seconds |
| Started | Aug 06 08:44:51 PM PDT 24 |
| Finished | Aug 06 08:45:47 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-c747dc0e-d9bd-4c3a-a24e-0c39c2f64570 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185160681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_dela ys.3185160681 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.259427666 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 330217316 ps |
| CPU time | 14.15 seconds |
| Started | Aug 06 08:45:02 PM PDT 24 |
| Finished | Aug 06 08:45:16 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-aa469e4f-0901-4789-9989-a7157d9dfaa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259427666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.259427666 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.4251016621 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 49223122 ps |
| CPU time | 7.06 seconds |
| Started | Aug 06 08:44:43 PM PDT 24 |
| Finished | Aug 06 08:44:50 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-c9972bbe-21d7-4b6c-8a63-838f0f990790 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251016621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.4251016621 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1046361744 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 6889165946 ps |
| CPU time | 78.31 seconds |
| Started | Aug 06 08:44:54 PM PDT 24 |
| Finished | Aug 06 08:46:13 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-77d63801-bf83-4a78-a969-730abee3ce61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046361744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.1046361744 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.754810737 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 6966826941 ps |
| CPU time | 125.67 seconds |
| Started | Aug 06 08:44:50 PM PDT 24 |
| Finished | Aug 06 08:46:55 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-406dcb4c-94bb-40a1-899f-570609318841 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754810737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.754810737 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.442930532 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 46004972 ps |
| CPU time | 6.98 seconds |
| Started | Aug 06 08:44:43 PM PDT 24 |
| Finished | Aug 06 08:44:50 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-3d42b034-ed2f-4188-bfad-5f23248c22f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442930532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays. 442930532 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.956650995 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 5855585492 ps |
| CPU time | 270.79 seconds |
| Started | Aug 06 08:45:04 PM PDT 24 |
| Finished | Aug 06 08:49:35 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-80625867-3574-433f-aabf-20685f879660 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956650995 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.956650995 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.3743133907 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 8858796538 ps |
| CPU time | 413.97 seconds |
| Started | Aug 06 08:45:08 PM PDT 24 |
| Finished | Aug 06 08:52:02 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-a9db157f-806c-40bf-b2a8-aa5812036938 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743133907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.3743133907 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2539834727 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 2467002011 ps |
| CPU time | 486.25 seconds |
| Started | Aug 06 08:45:07 PM PDT 24 |
| Finished | Aug 06 08:53:14 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-b584d79f-00e1-4670-83d7-679df46f57a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539834727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2539834727 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.2100656500 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 497466210 ps |
| CPU time | 174.12 seconds |
| Started | Aug 06 08:45:09 PM PDT 24 |
| Finished | Aug 06 08:48:04 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-fffd5f4c-3f4f-4748-b2c0-f1ab43611f32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100656500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all _with_reset_error.2100656500 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.2049239024 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 166182722 ps |
| CPU time | 10.61 seconds |
| Started | Aug 06 08:45:02 PM PDT 24 |
| Finished | Aug 06 08:45:12 PM PDT 24 |
| Peak memory | 573824 kb |
| Host | smart-816d738d-871c-44d0-bd63-f5f021686659 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049239024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2049239024 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.1770756754 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 2266383493 ps |
| CPU time | 99.94 seconds |
| Started | Aug 06 08:56:15 PM PDT 24 |
| Finished | Aug 06 08:57:55 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-2610b946-63a1-4f1c-8340-3f6b84cf9b89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770756754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .1770756754 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3983739427 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 135564417519 ps |
| CPU time | 2296.5 seconds |
| Started | Aug 06 08:56:25 PM PDT 24 |
| Finished | Aug 06 09:34:41 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-cdca0289-c4bb-46a4-9f61-b184f4f7a3f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983739427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3983739427 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.1303584673 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 32226139 ps |
| CPU time | 7.25 seconds |
| Started | Aug 06 08:56:22 PM PDT 24 |
| Finished | Aug 06 08:56:30 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-79967e26-8acd-45e4-8f17-14237ba9a6de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303584673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.1303584673 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.886976904 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 416450413 ps |
| CPU time | 14.9 seconds |
| Started | Aug 06 08:56:25 PM PDT 24 |
| Finished | Aug 06 08:56:40 PM PDT 24 |
| Peak memory | 575224 kb |
| Host | smart-39769fe9-527c-4e2a-8a16-b6454bf22862 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886976904 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.886976904 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.693023987 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 2408054709 ps |
| CPU time | 84.74 seconds |
| Started | Aug 06 08:56:14 PM PDT 24 |
| Finished | Aug 06 08:57:38 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-84afb965-d413-48a1-9d99-093f928aaf77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693023987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.693023987 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.1452393736 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 84921046184 ps |
| CPU time | 847.57 seconds |
| Started | Aug 06 08:56:18 PM PDT 24 |
| Finished | Aug 06 09:10:26 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-a58a9e6b-2553-4df1-a126-b1912a886a06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452393736 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.1452393736 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.3453423918 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 36098905659 ps |
| CPU time | 573.43 seconds |
| Started | Aug 06 08:56:25 PM PDT 24 |
| Finished | Aug 06 09:05:58 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-4218c8c1-e3b7-4069-bacb-d9e0ddbb82a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3453423918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.3453423918 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.1171139280 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 334142990 ps |
| CPU time | 32.5 seconds |
| Started | Aug 06 08:56:17 PM PDT 24 |
| Finished | Aug 06 08:56:49 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-56a88603-4ec4-4181-8bb7-076a4e596d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171139280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.1171139280 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.403192395 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 522706542 ps |
| CPU time | 47.25 seconds |
| Started | Aug 06 08:56:15 PM PDT 24 |
| Finished | Aug 06 08:57:02 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-a7118b06-308a-414a-814e-8dd0cdaedcb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403192395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.403192395 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.3727545968 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 141934531 ps |
| CPU time | 7.86 seconds |
| Started | Aug 06 08:56:11 PM PDT 24 |
| Finished | Aug 06 08:56:19 PM PDT 24 |
| Peak memory | 573896 kb |
| Host | smart-26da4091-907e-4b92-8ab0-b6bc31b12e33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727545968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.3727545968 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.2637481884 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 7133643371 ps |
| CPU time | 78.28 seconds |
| Started | Aug 06 08:56:11 PM PDT 24 |
| Finished | Aug 06 08:57:29 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-2e4b69b1-f379-467b-aed2-0aab384e7f53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637481884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.2637481884 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.482643707 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 5874703201 ps |
| CPU time | 101.2 seconds |
| Started | Aug 06 08:56:09 PM PDT 24 |
| Finished | Aug 06 08:57:51 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-d97ad16f-6642-4bd0-9817-1140036abec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=482643707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.482643707 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.2758982563 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 41137954 ps |
| CPU time | 6.92 seconds |
| Started | Aug 06 08:56:11 PM PDT 24 |
| Finished | Aug 06 08:56:18 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-425221c1-6cd1-465f-a646-d42b3f243dc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758982563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.2758982563 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.3808300491 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 14684267216 ps |
| CPU time | 627.31 seconds |
| Started | Aug 06 08:56:22 PM PDT 24 |
| Finished | Aug 06 09:06:49 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-27818a77-cc68-45c9-8081-1e1ed46af9f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808300491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.3808300491 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.900793654 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 3984485425 ps |
| CPU time | 358.52 seconds |
| Started | Aug 06 08:56:21 PM PDT 24 |
| Finished | Aug 06 09:02:20 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-5bbe3381-815f-4e30-ae10-50dc7de32111 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900793654 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.900793654 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.4223459021 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 3853889072 ps |
| CPU time | 560.1 seconds |
| Started | Aug 06 08:56:20 PM PDT 24 |
| Finished | Aug 06 09:05:40 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-b0111342-511b-4eb0-b8ab-5d495d3c69c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223459021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all _with_rand_reset.4223459021 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3504010082 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 1593832945 ps |
| CPU time | 129.62 seconds |
| Started | Aug 06 08:56:21 PM PDT 24 |
| Finished | Aug 06 08:58:30 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-36d08a1f-ffa8-45c4-aa98-3196731164a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504010082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3504010082 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.2467510497 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 101125451 ps |
| CPU time | 13.6 seconds |
| Started | Aug 06 08:56:21 PM PDT 24 |
| Finished | Aug 06 08:56:34 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-bf4be3c6-0c3c-4097-9bb3-0e54ff237042 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467510497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.2467510497 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.3790973824 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 2108622999 ps |
| CPU time | 90.64 seconds |
| Started | Aug 06 08:56:30 PM PDT 24 |
| Finished | Aug 06 08:58:01 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-3a087e52-2a29-4b1e-8d38-9bb892c87509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790973824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .3790973824 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2888364939 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 26753646335 ps |
| CPU time | 497.45 seconds |
| Started | Aug 06 08:56:30 PM PDT 24 |
| Finished | Aug 06 09:04:47 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-be93ddc8-a84a-4d5b-b9a5-31b0037620f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888364939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2888364939 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.3539222852 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 91409938 ps |
| CPU time | 13.06 seconds |
| Started | Aug 06 08:56:29 PM PDT 24 |
| Finished | Aug 06 08:56:42 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-bbd3e47e-6aff-4cd5-a4f4-232e51373186 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539222852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.3539222852 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.1482217450 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 1800574978 ps |
| CPU time | 64.45 seconds |
| Started | Aug 06 08:56:33 PM PDT 24 |
| Finished | Aug 06 08:57:37 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-280a7134-276d-49f9-9f2d-580048bd3238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482217450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.1482217450 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.4059653949 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 1318666068 ps |
| CPU time | 49.09 seconds |
| Started | Aug 06 08:56:29 PM PDT 24 |
| Finished | Aug 06 08:57:18 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-b4f615f5-8fba-4198-8a0a-c6afab27fcbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4059653949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.4059653949 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.752341506 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 94019471764 ps |
| CPU time | 948.32 seconds |
| Started | Aug 06 08:56:29 PM PDT 24 |
| Finished | Aug 06 09:12:17 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-7371a044-f921-4d8b-adc4-fec748205159 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752341506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.752341506 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.4155860493 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 18338569580 ps |
| CPU time | 318.2 seconds |
| Started | Aug 06 08:56:29 PM PDT 24 |
| Finished | Aug 06 09:01:47 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-e756d79a-fc2e-4287-ac49-3ccf23b1cc97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155860493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.4155860493 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.2313295705 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 408868335 ps |
| CPU time | 42.54 seconds |
| Started | Aug 06 08:56:26 PM PDT 24 |
| Finished | Aug 06 08:57:09 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-0e150d2f-c7ff-428b-97f3-bac929c79d7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313295705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.2313295705 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.145542496 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 2194480469 ps |
| CPU time | 77.79 seconds |
| Started | Aug 06 08:56:35 PM PDT 24 |
| Finished | Aug 06 08:57:53 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-181200b3-d9c0-4f45-8739-f902ada29a2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=145542496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.145542496 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.3660090311 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 48105875 ps |
| CPU time | 7.6 seconds |
| Started | Aug 06 08:56:24 PM PDT 24 |
| Finished | Aug 06 08:56:32 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-77e6ca71-b724-4b63-9459-ff2b761e03d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660090311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.3660090311 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.4270149336 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 8469272018 ps |
| CPU time | 93.79 seconds |
| Started | Aug 06 08:56:26 PM PDT 24 |
| Finished | Aug 06 08:57:59 PM PDT 24 |
| Peak memory | 575104 kb |
| Host | smart-bda6042f-d379-4e12-a9b4-c4554cd84602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270149336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.4270149336 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.118181457 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 4770986942 ps |
| CPU time | 81.01 seconds |
| Started | Aug 06 08:56:25 PM PDT 24 |
| Finished | Aug 06 08:57:46 PM PDT 24 |
| Peak memory | 575108 kb |
| Host | smart-08984757-24ab-4e53-852c-41919acf4041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118181457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.118181457 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2699092324 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 49048906 ps |
| CPU time | 6.84 seconds |
| Started | Aug 06 08:56:24 PM PDT 24 |
| Finished | Aug 06 08:56:30 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-2b2b78e9-375e-4d7b-8fa6-53d66bc837e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699092324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2699092324 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.871636111 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 8818198249 ps |
| CPU time | 333.39 seconds |
| Started | Aug 06 08:56:32 PM PDT 24 |
| Finished | Aug 06 09:02:06 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-926f64ed-752b-4199-ba5e-17755caa7bb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871636111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.871636111 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.2787117795 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 1232848702 ps |
| CPU time | 103.89 seconds |
| Started | Aug 06 08:56:31 PM PDT 24 |
| Finished | Aug 06 08:58:14 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-4cb0d08c-16e4-4ad1-90b9-148fff3fd907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787117795 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.2787117795 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3559423469 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 461161478 ps |
| CPU time | 134.91 seconds |
| Started | Aug 06 08:56:32 PM PDT 24 |
| Finished | Aug 06 08:58:47 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-8a22991e-e11e-40ee-a8f7-0c010dd987e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559423469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3559423469 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.4040419014 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 183914087 ps |
| CPU time | 40.65 seconds |
| Started | Aug 06 08:56:29 PM PDT 24 |
| Finished | Aug 06 08:57:10 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-5cbff62d-677f-467a-8e6e-bf9c936df2c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040419014 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.4040419014 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.525043661 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 39519918 ps |
| CPU time | 5.92 seconds |
| Started | Aug 06 08:56:29 PM PDT 24 |
| Finished | Aug 06 08:56:35 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-7e5a22ed-dcf2-4d0f-8d32-399d4c48f098 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=525043661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.525043661 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.3425484836 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 867269608 ps |
| CPU time | 42.66 seconds |
| Started | Aug 06 08:56:37 PM PDT 24 |
| Finished | Aug 06 08:57:20 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-347ad43d-3ebe-440c-9983-53c8a70eb105 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425484836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .3425484836 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.3349523084 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 17482994822 ps |
| CPU time | 297.74 seconds |
| Started | Aug 06 08:56:40 PM PDT 24 |
| Finished | Aug 06 09:01:38 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-fbb61a78-0c3c-432f-af6e-f8a83cb57392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349523084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_ device_slow_rsp.3349523084 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.866924334 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 198130827 ps |
| CPU time | 26.96 seconds |
| Started | Aug 06 08:56:42 PM PDT 24 |
| Finished | Aug 06 08:57:09 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-c35a1154-8e43-449a-9711-04500335a292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866924334 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr .866924334 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.2301192247 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 609458611 ps |
| CPU time | 56.98 seconds |
| Started | Aug 06 08:56:36 PM PDT 24 |
| Finished | Aug 06 08:57:33 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-97994bc8-feb0-4720-8658-59fe9898d857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301192247 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2301192247 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3282193033 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 61470423 ps |
| CPU time | 8.81 seconds |
| Started | Aug 06 08:56:35 PM PDT 24 |
| Finished | Aug 06 08:56:44 PM PDT 24 |
| Peak memory | 574380 kb |
| Host | smart-d92b560e-857c-4db5-81d2-a3f4aa9799f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282193033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3282193033 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.1850924336 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 54546314323 ps |
| CPU time | 575.13 seconds |
| Started | Aug 06 08:56:40 PM PDT 24 |
| Finished | Aug 06 09:06:15 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-9474616b-d3f6-407e-8046-b941d0576000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850924336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1850924336 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2963124948 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 30373889423 ps |
| CPU time | 518.53 seconds |
| Started | Aug 06 08:56:34 PM PDT 24 |
| Finished | Aug 06 09:05:13 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-c77b6830-aa86-4d83-a836-7f2864e9499a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963124948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2963124948 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.3413544312 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 130550263 ps |
| CPU time | 14.86 seconds |
| Started | Aug 06 08:56:40 PM PDT 24 |
| Finished | Aug 06 08:56:55 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-5058fb52-5b9c-4d5c-8070-9ddc2e21a1a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413544312 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.3413544312 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2031051717 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 859789354 ps |
| CPU time | 27.94 seconds |
| Started | Aug 06 08:56:38 PM PDT 24 |
| Finished | Aug 06 08:57:06 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-4ef7ff11-0fa6-4fe2-aa23-c7e6e60102f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031051717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2031051717 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.1223917053 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 52935822 ps |
| CPU time | 7.2 seconds |
| Started | Aug 06 08:56:37 PM PDT 24 |
| Finished | Aug 06 08:56:44 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-84014b7d-7243-438c-9e04-f310deaaba6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223917053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.1223917053 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.977060323 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 6439797393 ps |
| CPU time | 73.11 seconds |
| Started | Aug 06 08:56:35 PM PDT 24 |
| Finished | Aug 06 08:57:49 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-27056b69-4122-4137-b1bf-511bb50cc07f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977060323 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.977060323 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.3306190505 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 5294299292 ps |
| CPU time | 98.55 seconds |
| Started | Aug 06 08:56:37 PM PDT 24 |
| Finished | Aug 06 08:58:15 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-e8dea739-a5df-4f7e-ba42-88030dd99885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306190505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.3306190505 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.2204359504 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 49156664 ps |
| CPU time | 6.67 seconds |
| Started | Aug 06 08:56:35 PM PDT 24 |
| Finished | Aug 06 08:56:42 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-994c16c3-3da0-4b1e-8e74-326e484775fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204359504 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.2204359504 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.2951836889 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 3743547145 ps |
| CPU time | 339.09 seconds |
| Started | Aug 06 08:56:44 PM PDT 24 |
| Finished | Aug 06 09:02:23 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-bfb0ae1b-29c9-4809-82f4-3fc4abab83ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951836889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.2951836889 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3116822256 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 788164351 ps |
| CPU time | 38.31 seconds |
| Started | Aug 06 08:56:39 PM PDT 24 |
| Finished | Aug 06 08:57:18 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-e824046b-fd8b-4994-98fa-7b8b35414f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116822256 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.3116822256 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.2461406837 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 4673250169 ps |
| CPU time | 228.86 seconds |
| Started | Aug 06 08:56:40 PM PDT 24 |
| Finished | Aug 06 09:00:29 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-7460255c-cd44-4ca0-aafe-0c2321b74308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461406837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all _with_rand_reset.2461406837 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.1667975895 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 9092820714 ps |
| CPU time | 547.74 seconds |
| Started | Aug 06 08:56:45 PM PDT 24 |
| Finished | Aug 06 09:05:53 PM PDT 24 |
| Peak memory | 577728 kb |
| Host | smart-dd07bf19-3eb6-414f-99fd-d9c1ce8dd5cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667975895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.1667975895 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2879343464 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 1084645676 ps |
| CPU time | 54.52 seconds |
| Started | Aug 06 08:56:37 PM PDT 24 |
| Finished | Aug 06 08:57:32 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-4e25fd54-ac20-46d4-885a-dc72e9d25122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879343464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.2879343464 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.878014569 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 237692544 ps |
| CPU time | 27.94 seconds |
| Started | Aug 06 08:56:48 PM PDT 24 |
| Finished | Aug 06 08:57:16 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-d991d6c0-83ee-4c67-92fa-299519313b8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878014569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device. 878014569 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.1006872933 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 127057163210 ps |
| CPU time | 2077 seconds |
| Started | Aug 06 08:56:48 PM PDT 24 |
| Finished | Aug 06 09:31:25 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-0f5a0f0b-ebc2-4045-bb79-89e7e7be2aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006872933 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_ device_slow_rsp.1006872933 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.2337009213 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 975271581 ps |
| CPU time | 41.9 seconds |
| Started | Aug 06 08:56:54 PM PDT 24 |
| Finished | Aug 06 08:57:36 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-55e6b94e-2dcc-400e-9cfe-bf8e0694cad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337009213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.2337009213 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.1069300157 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 494043574 ps |
| CPU time | 22.65 seconds |
| Started | Aug 06 08:56:55 PM PDT 24 |
| Finished | Aug 06 08:57:18 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-938b11f8-8791-4de5-9a8e-a86f7119f08d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069300157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.1069300157 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.1408720499 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 225833261 ps |
| CPU time | 22.28 seconds |
| Started | Aug 06 08:56:41 PM PDT 24 |
| Finished | Aug 06 08:57:04 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-0a2f0be7-2505-48f2-ab7b-928eee4a5df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408720499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.1408720499 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.3664164308 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 31121839741 ps |
| CPU time | 321.66 seconds |
| Started | Aug 06 08:56:49 PM PDT 24 |
| Finished | Aug 06 09:02:11 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-02e38bba-2b5d-4253-a45f-2b761627e13c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664164308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.3664164308 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.427994311 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 38823565267 ps |
| CPU time | 651.82 seconds |
| Started | Aug 06 08:56:47 PM PDT 24 |
| Finished | Aug 06 09:07:39 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-046c2ea6-1905-4a91-8a29-22e355b47eda |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427994311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.427994311 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.3744011768 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 98203489 ps |
| CPU time | 10.74 seconds |
| Started | Aug 06 08:56:49 PM PDT 24 |
| Finished | Aug 06 08:57:00 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-2fccc2a6-99e3-4100-bb7c-1f80344bac3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744011768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_del ays.3744011768 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.3004909110 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 90676090 ps |
| CPU time | 10.1 seconds |
| Started | Aug 06 08:56:47 PM PDT 24 |
| Finished | Aug 06 08:56:58 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-85b42a8c-cc89-4b2a-b5f9-e31ce6517f5a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3004909110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.3004909110 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.187222711 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 192144025 ps |
| CPU time | 9.77 seconds |
| Started | Aug 06 08:56:40 PM PDT 24 |
| Finished | Aug 06 08:56:50 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-c6318ebb-ac57-472f-80bc-298f3bd52d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187222711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.187222711 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.1001137973 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 10268700367 ps |
| CPU time | 118.25 seconds |
| Started | Aug 06 08:56:41 PM PDT 24 |
| Finished | Aug 06 08:58:40 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-f5ea5236-0f87-4332-8551-8cadb8274c0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001137973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.1001137973 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2227501738 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 5683055078 ps |
| CPU time | 98.66 seconds |
| Started | Aug 06 08:56:45 PM PDT 24 |
| Finished | Aug 06 08:58:23 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-83bda6ec-952d-4f61-bb1c-c84e9cc9cc81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2227501738 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.2227501738 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.2487096170 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 51782341 ps |
| CPU time | 6.74 seconds |
| Started | Aug 06 08:56:42 PM PDT 24 |
| Finished | Aug 06 08:56:49 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-4f8d45a9-81db-4050-bca9-9cbeecd4bbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487096170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.2487096170 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.639900881 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 8054627155 ps |
| CPU time | 303.11 seconds |
| Started | Aug 06 08:56:54 PM PDT 24 |
| Finished | Aug 06 09:01:57 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-5e1090e7-ca61-47e9-adf9-4262f84db42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639900881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.639900881 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.2766941827 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 2300497574 ps |
| CPU time | 90.91 seconds |
| Started | Aug 06 08:56:54 PM PDT 24 |
| Finished | Aug 06 08:58:24 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-134c66b4-248d-4960-8257-434844b8056a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766941827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.2766941827 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.2585908313 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 4484296495 ps |
| CPU time | 188.5 seconds |
| Started | Aug 06 08:56:53 PM PDT 24 |
| Finished | Aug 06 09:00:02 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-7b32ac9c-f926-4619-a874-ef7391c8a135 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585908313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.2585908313 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.2240239505 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 158780316 ps |
| CPU time | 24.52 seconds |
| Started | Aug 06 08:56:55 PM PDT 24 |
| Finished | Aug 06 08:57:20 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-6bb04a88-039d-4728-8f2c-c4c37b03208a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240239505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.2240239505 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.1038260452 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 159912552 ps |
| CPU time | 22.1 seconds |
| Started | Aug 06 08:56:51 PM PDT 24 |
| Finished | Aug 06 08:57:14 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-61c9224e-d3f3-4c56-b708-a9272b1856e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038260452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.1038260452 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.1730935286 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 207911873 ps |
| CPU time | 38.2 seconds |
| Started | Aug 06 08:56:57 PM PDT 24 |
| Finished | Aug 06 08:57:35 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-dc66373e-cc5b-4795-b50c-efb39e6d5b1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730935286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .1730935286 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2810870098 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 119787452560 ps |
| CPU time | 2053.34 seconds |
| Started | Aug 06 08:56:57 PM PDT 24 |
| Finished | Aug 06 09:31:10 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-172e1700-99ed-4430-86a7-2f29b19fc975 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810870098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2810870098 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.1109500239 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 931220627 ps |
| CPU time | 39.31 seconds |
| Started | Aug 06 08:56:58 PM PDT 24 |
| Finished | Aug 06 08:57:37 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-3acb970b-492b-4207-9c77-85cac82bcdd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109500239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.1109500239 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.751355556 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 411193186 ps |
| CPU time | 36.49 seconds |
| Started | Aug 06 08:56:58 PM PDT 24 |
| Finished | Aug 06 08:57:35 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-67e03346-34e1-4b49-8382-6f5c6956f132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751355556 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.751355556 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.3159739760 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 367625317 ps |
| CPU time | 33.62 seconds |
| Started | Aug 06 08:57:00 PM PDT 24 |
| Finished | Aug 06 08:57:34 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-d999e553-dbb7-4d99-ae8a-a5d4cc6e0d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159739760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.3159739760 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.4170317551 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 85470612686 ps |
| CPU time | 846.14 seconds |
| Started | Aug 06 08:56:58 PM PDT 24 |
| Finished | Aug 06 09:11:04 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-a99b8485-2a64-4ca4-9b4f-4944dd0f0541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170317551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.4170317551 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.4049828774 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 43424906718 ps |
| CPU time | 716.93 seconds |
| Started | Aug 06 08:57:02 PM PDT 24 |
| Finished | Aug 06 09:08:59 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-cd411dbf-d179-437f-bfe4-8dc7570e47c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049828774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.4049828774 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.3046093924 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 209095493 ps |
| CPU time | 21.48 seconds |
| Started | Aug 06 08:56:59 PM PDT 24 |
| Finished | Aug 06 08:57:20 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-ef40c076-9ebc-4680-a0db-f5eb936ee704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046093924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.3046093924 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.3714425262 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 1691176655 ps |
| CPU time | 51.34 seconds |
| Started | Aug 06 08:57:01 PM PDT 24 |
| Finished | Aug 06 08:57:52 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-202cef7e-be48-4906-be53-6e035fdc5cc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714425262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.3714425262 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.4162780928 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 41852869 ps |
| CPU time | 6.7 seconds |
| Started | Aug 06 08:56:56 PM PDT 24 |
| Finished | Aug 06 08:57:03 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-73387701-ce8a-401f-a7fe-84f9434fc5aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162780928 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.4162780928 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.834704273 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 8669391742 ps |
| CPU time | 91.56 seconds |
| Started | Aug 06 08:56:55 PM PDT 24 |
| Finished | Aug 06 08:58:27 PM PDT 24 |
| Peak memory | 574500 kb |
| Host | smart-d1b48d0b-4d91-4660-a083-794616a332c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834704273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.834704273 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.191122662 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 5726835601 ps |
| CPU time | 98.98 seconds |
| Started | Aug 06 08:56:52 PM PDT 24 |
| Finished | Aug 06 08:58:31 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-ecacdd80-5317-48bc-96b8-e250bb3e8002 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191122662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.191122662 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.1842838481 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 45608875 ps |
| CPU time | 6.16 seconds |
| Started | Aug 06 08:56:52 PM PDT 24 |
| Finished | Aug 06 08:56:59 PM PDT 24 |
| Peak memory | 573884 kb |
| Host | smart-e7ef96f8-6cd5-4e1c-84f3-b9a3db3016dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842838481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.1842838481 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.2675319305 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 8894330527 ps |
| CPU time | 325.8 seconds |
| Started | Aug 06 08:57:00 PM PDT 24 |
| Finished | Aug 06 09:02:26 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-c1ccac73-271e-4441-88f8-53c32237540b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675319305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.2675319305 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.330106851 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 8820873083 ps |
| CPU time | 1088.84 seconds |
| Started | Aug 06 08:56:59 PM PDT 24 |
| Finished | Aug 06 09:15:08 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-bc388654-7208-49f6-983e-1c078de70293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330106851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_ with_rand_reset.330106851 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.1919291932 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 212483369 ps |
| CPU time | 58.63 seconds |
| Started | Aug 06 08:57:06 PM PDT 24 |
| Finished | Aug 06 08:58:05 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-c8501b5c-5549-4f28-b0bb-c174169aad63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919291932 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.1919291932 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.439718123 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 287288606 ps |
| CPU time | 35.1 seconds |
| Started | Aug 06 08:57:00 PM PDT 24 |
| Finished | Aug 06 08:57:35 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-6b3a3e94-c5e1-4b2a-86b0-72fec8952004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=439718123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.439718123 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.2794042309 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 524461176 ps |
| CPU time | 57.49 seconds |
| Started | Aug 06 08:57:17 PM PDT 24 |
| Finished | Aug 06 08:58:14 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-d150b5a1-1b47-409b-b5af-639599f35788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794042309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .2794042309 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.719938890 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 25605912993 ps |
| CPU time | 475.16 seconds |
| Started | Aug 06 08:57:26 PM PDT 24 |
| Finished | Aug 06 09:05:21 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-5ef6e7bb-cb0f-4493-b479-062c55a43d2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719938890 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_d evice_slow_rsp.719938890 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.4156818557 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 274766670 ps |
| CPU time | 13.78 seconds |
| Started | Aug 06 08:57:17 PM PDT 24 |
| Finished | Aug 06 08:57:31 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-dc054a44-a6a3-459b-aaa1-e4a8d2e871a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156818557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_add r.4156818557 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3920946677 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 171146246 ps |
| CPU time | 17.36 seconds |
| Started | Aug 06 08:57:15 PM PDT 24 |
| Finished | Aug 06 08:57:32 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-7fed5731-50db-4935-8ac4-e887d0d7b4d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920946677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3920946677 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.2583509640 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 1960088834 ps |
| CPU time | 78.63 seconds |
| Started | Aug 06 08:57:05 PM PDT 24 |
| Finished | Aug 06 08:58:24 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-1d3df078-d09e-42e5-89f8-1f97747eb604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583509640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.2583509640 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.1671208622 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 66068688365 ps |
| CPU time | 773.5 seconds |
| Started | Aug 06 08:57:09 PM PDT 24 |
| Finished | Aug 06 09:10:03 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-35a0db6a-ed4d-478f-881a-66a5c61302f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671208622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.1671208622 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.443093273 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 46457296007 ps |
| CPU time | 811.21 seconds |
| Started | Aug 06 08:57:12 PM PDT 24 |
| Finished | Aug 06 09:10:43 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-d91fb2b0-15af-4cce-8d4c-e391d7641a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443093273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.443093273 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.591326054 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 471808144 ps |
| CPU time | 42.22 seconds |
| Started | Aug 06 08:57:04 PM PDT 24 |
| Finished | Aug 06 08:57:46 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-a1b4f931-8ce1-4f4a-9e12-ff95c4211d15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591326054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_dela ys.591326054 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.3075853919 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 414451634 ps |
| CPU time | 37.26 seconds |
| Started | Aug 06 08:57:16 PM PDT 24 |
| Finished | Aug 06 08:57:54 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-164fcbac-1843-4b64-9878-55590a64ce38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075853919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.3075853919 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.1384322646 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 49770377 ps |
| CPU time | 6.89 seconds |
| Started | Aug 06 08:57:04 PM PDT 24 |
| Finished | Aug 06 08:57:11 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-b815966c-0794-4b79-a36e-13dbc8a13ae4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384322646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.1384322646 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.2173699846 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 8139690444 ps |
| CPU time | 89.15 seconds |
| Started | Aug 06 08:57:03 PM PDT 24 |
| Finished | Aug 06 08:58:32 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-d1566d3c-ccf8-4263-91ec-cca92b9cda90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173699846 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.2173699846 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.579530138 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 4366808173 ps |
| CPU time | 76.01 seconds |
| Started | Aug 06 08:57:03 PM PDT 24 |
| Finished | Aug 06 08:58:19 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-bb2ddf3b-bd1d-4135-9d18-ed4e3651dfbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579530138 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.579530138 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.880955901 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 50545404 ps |
| CPU time | 6.7 seconds |
| Started | Aug 06 08:57:05 PM PDT 24 |
| Finished | Aug 06 08:57:12 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-23630916-fb44-434f-bca3-38924de33c41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880955901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .880955901 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.378389838 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 1917968902 ps |
| CPU time | 182.4 seconds |
| Started | Aug 06 08:57:15 PM PDT 24 |
| Finished | Aug 06 09:00:17 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-72acf09c-ed9c-4e73-b49e-97d1f069a929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378389838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.378389838 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1769012677 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 4320620403 ps |
| CPU time | 366.52 seconds |
| Started | Aug 06 08:57:12 PM PDT 24 |
| Finished | Aug 06 09:03:19 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-d443eb7f-d7d0-4273-baad-acd67a19fd11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769012677 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1769012677 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.3882278491 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 2156058166 ps |
| CPU time | 315.09 seconds |
| Started | Aug 06 08:57:17 PM PDT 24 |
| Finished | Aug 06 09:02:32 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-16be1fdd-351f-4b45-bedc-9e4bc80d2a6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882278491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.3882278491 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.1188768518 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 2390368149 ps |
| CPU time | 280.25 seconds |
| Started | Aug 06 08:57:22 PM PDT 24 |
| Finished | Aug 06 09:02:02 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-1f8db96a-3ae2-4e07-91af-5b24ae6b4805 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188768518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_al l_with_reset_error.1188768518 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.458120543 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 127138606 ps |
| CPU time | 16.55 seconds |
| Started | Aug 06 08:57:17 PM PDT 24 |
| Finished | Aug 06 08:57:34 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-0639660d-d233-49e9-8a29-60d9a697c8ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458120543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.458120543 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.4037473167 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 285979023 ps |
| CPU time | 15.08 seconds |
| Started | Aug 06 08:57:22 PM PDT 24 |
| Finished | Aug 06 08:57:37 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-2ddbc6a2-6dac-48fc-b0c7-0289264ccc5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037473167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .4037473167 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2965086523 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 123563569166 ps |
| CPU time | 2290.04 seconds |
| Started | Aug 06 08:57:19 PM PDT 24 |
| Finished | Aug 06 09:35:29 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-8e89490a-e073-4890-9fe4-34b9b01218ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965086523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2965086523 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4020050540 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 286546982 ps |
| CPU time | 33.43 seconds |
| Started | Aug 06 08:57:23 PM PDT 24 |
| Finished | Aug 06 08:57:57 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-8120d93b-b8da-41e3-b18b-7b8cd89f1084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020050540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.4020050540 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.1316739702 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 2223371286 ps |
| CPU time | 80.19 seconds |
| Started | Aug 06 08:57:22 PM PDT 24 |
| Finished | Aug 06 08:58:43 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-32b98347-4276-45a4-bc8e-2817dd0502da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316739702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.1316739702 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.4277704879 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 251053532 ps |
| CPU time | 25.02 seconds |
| Started | Aug 06 08:57:20 PM PDT 24 |
| Finished | Aug 06 08:57:45 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-a738dad4-21bf-4f1a-b63b-4a1fb454f5c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277704879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.4277704879 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.79656346 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 7130686882 ps |
| CPU time | 73.62 seconds |
| Started | Aug 06 08:57:23 PM PDT 24 |
| Finished | Aug 06 08:58:37 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-8fdb691c-c10a-4c6c-997b-72fcbcac642a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79656346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.79656346 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.1904026955 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 21104331369 ps |
| CPU time | 366.27 seconds |
| Started | Aug 06 08:57:21 PM PDT 24 |
| Finished | Aug 06 09:03:27 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-93f572b1-7726-430d-8ccc-41faf70be24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904026955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.1904026955 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.32904161 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 386068892 ps |
| CPU time | 40.43 seconds |
| Started | Aug 06 08:57:18 PM PDT 24 |
| Finished | Aug 06 08:57:58 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-cec3268f-5a9f-4e66-89e2-99a44eaadd27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32904161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_delay s.32904161 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.1902182694 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 280729903 ps |
| CPU time | 23.59 seconds |
| Started | Aug 06 08:57:21 PM PDT 24 |
| Finished | Aug 06 08:57:44 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-dd695b11-e95d-4340-be4e-fa669e0d6a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902182694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.1902182694 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.3594651608 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 251199010 ps |
| CPU time | 11.12 seconds |
| Started | Aug 06 08:57:20 PM PDT 24 |
| Finished | Aug 06 08:57:31 PM PDT 24 |
| Peak memory | 574440 kb |
| Host | smart-587e64be-3ef8-4e4e-b580-ae2a73cfa78b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594651608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.3594651608 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1808619689 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 6403540602 ps |
| CPU time | 69.63 seconds |
| Started | Aug 06 08:57:19 PM PDT 24 |
| Finished | Aug 06 08:58:29 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-eeb67e7d-8b21-4313-a856-7055188f78bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808619689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.1808619689 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.3929440362 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 5599096676 ps |
| CPU time | 104.2 seconds |
| Started | Aug 06 08:57:19 PM PDT 24 |
| Finished | Aug 06 08:59:04 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-46a0f186-a7ad-44a3-8e1a-585e24fd4179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3929440362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.3929440362 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.1165179711 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 50528752 ps |
| CPU time | 7.47 seconds |
| Started | Aug 06 08:57:20 PM PDT 24 |
| Finished | Aug 06 08:57:27 PM PDT 24 |
| Peak memory | 574604 kb |
| Host | smart-dfea3283-7c4b-402b-bca4-24510ab1ed60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165179711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delay s.1165179711 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.928317018 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 4497930134 ps |
| CPU time | 188.14 seconds |
| Started | Aug 06 08:57:23 PM PDT 24 |
| Finished | Aug 06 09:00:31 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-306bbd6e-9fbb-4935-9778-417363aabbcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928317018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.928317018 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.2038892675 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 3438860935 ps |
| CPU time | 133.19 seconds |
| Started | Aug 06 08:57:26 PM PDT 24 |
| Finished | Aug 06 08:59:40 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-6d3679bb-52bb-4b01-9253-10f15a663490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038892675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.2038892675 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.1006424029 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 2144334103 ps |
| CPU time | 353.05 seconds |
| Started | Aug 06 08:57:26 PM PDT 24 |
| Finished | Aug 06 09:03:19 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-f40efff9-5bea-4d5c-b730-fab4546deac8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006424029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.1006424029 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1966946831 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 534145243 ps |
| CPU time | 34.07 seconds |
| Started | Aug 06 08:57:24 PM PDT 24 |
| Finished | Aug 06 08:57:58 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-c22309c2-906e-4ede-90a5-768c563c52cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966946831 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1966946831 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.140463421 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 217097377 ps |
| CPU time | 22.4 seconds |
| Started | Aug 06 08:57:24 PM PDT 24 |
| Finished | Aug 06 08:57:47 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-d736bfc6-fa80-416a-9699-9125ac93061f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140463421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.140463421 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.222884011 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 3552915714 ps |
| CPU time | 133.59 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 08:59:42 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-3f31460a-9a3f-4f27-bef7-56b00ebb284c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222884011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device. 222884011 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2146053222 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 43266858490 ps |
| CPU time | 782.07 seconds |
| Started | Aug 06 08:57:31 PM PDT 24 |
| Finished | Aug 06 09:10:33 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-40ee03fd-e987-49f5-a225-5dde0e103e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146053222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2146053222 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.3946341540 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 1258465932 ps |
| CPU time | 54.89 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 08:58:24 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f9a7089e-2499-478e-a1c0-5b5e7177ff0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946341540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.3946341540 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.4015753177 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 358223215 ps |
| CPU time | 31.34 seconds |
| Started | Aug 06 08:57:35 PM PDT 24 |
| Finished | Aug 06 08:58:06 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-73266908-3329-41fd-9215-b5696b63bda0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015753177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.4015753177 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.3222854363 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 2068896389 ps |
| CPU time | 77.18 seconds |
| Started | Aug 06 08:57:33 PM PDT 24 |
| Finished | Aug 06 08:58:50 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-03f8a211-fd46-4c4e-811d-514a62091619 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222854363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.3222854363 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.2243619981 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 67511497426 ps |
| CPU time | 679.05 seconds |
| Started | Aug 06 08:57:22 PM PDT 24 |
| Finished | Aug 06 09:08:41 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-b20ccc74-5bbb-48b5-956a-a9e6189b210a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243619981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.2243619981 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2105256467 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 51577777818 ps |
| CPU time | 885.95 seconds |
| Started | Aug 06 08:57:32 PM PDT 24 |
| Finished | Aug 06 09:12:18 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-fd82f41f-45a7-49f0-9d9c-8b2ada0e39ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105256467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.2105256467 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.2208661251 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 233411253 ps |
| CPU time | 23.31 seconds |
| Started | Aug 06 08:57:22 PM PDT 24 |
| Finished | Aug 06 08:57:46 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-871fa624-d4fc-4d5b-b0d6-7a8b800dfeb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208661251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.2208661251 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.874978259 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 1874052558 ps |
| CPU time | 59.7 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 08:58:29 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-f7e5dda3-9a70-42d1-bd6f-2ef3be35e864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874978259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.874978259 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.1850599401 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 39396971 ps |
| CPU time | 6 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 08:57:35 PM PDT 24 |
| Peak memory | 574412 kb |
| Host | smart-c52ffa64-264f-40e4-8d87-26f8ec97766b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850599401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.1850599401 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.2889862415 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 8584851038 ps |
| CPU time | 90.24 seconds |
| Started | Aug 06 08:57:24 PM PDT 24 |
| Finished | Aug 06 08:58:54 PM PDT 24 |
| Peak memory | 574540 kb |
| Host | smart-2d7d4cc4-2432-41bd-8e14-35c5627d841f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889862415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.2889862415 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.1248048709 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 4750516063 ps |
| CPU time | 82.82 seconds |
| Started | Aug 06 08:57:25 PM PDT 24 |
| Finished | Aug 06 08:58:48 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-deddc823-6a5e-438e-8d40-2786a117888f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248048709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.1248048709 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.491256281 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 33570578 ps |
| CPU time | 6.21 seconds |
| Started | Aug 06 08:57:22 PM PDT 24 |
| Finished | Aug 06 08:57:28 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-40b9a4eb-f00c-4f2a-a79a-a76a7a989465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491256281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays .491256281 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.529228714 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 18399441067 ps |
| CPU time | 810.76 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 09:11:00 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-b833ada1-23b5-406a-a8d9-80d4fd34236f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529228714 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.529228714 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.2582938304 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 2320609028 ps |
| CPU time | 328.35 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 09:02:57 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-244da563-22f7-49bd-8da7-22a7706b55ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2582938304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.2582938304 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.4152545348 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 756805618 ps |
| CPU time | 72.9 seconds |
| Started | Aug 06 08:57:35 PM PDT 24 |
| Finished | Aug 06 08:58:48 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-dbd42f14-aecc-4ecc-89d8-7493151330c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152545348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.4152545348 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.784472931 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 334214954 ps |
| CPU time | 42.24 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 08:58:11 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-65c28998-31e1-49c9-a60d-40b4c2e90742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=784472931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.784472931 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2238584068 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 298403459 ps |
| CPU time | 36.28 seconds |
| Started | Aug 06 08:57:35 PM PDT 24 |
| Finished | Aug 06 08:58:11 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-c0e1bf2a-3ebd-4598-a339-658f11122913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238584068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .2238584068 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.1728100296 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 138740411541 ps |
| CPU time | 2349.29 seconds |
| Started | Aug 06 08:57:33 PM PDT 24 |
| Finished | Aug 06 09:36:43 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-32e5ff5c-7476-4231-a29f-11665fa2555a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728100296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.1728100296 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.3093477491 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 112585102 ps |
| CPU time | 15.49 seconds |
| Started | Aug 06 08:57:37 PM PDT 24 |
| Finished | Aug 06 08:57:53 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-41bd0882-fc02-415e-a21c-a4d6cc1b03c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093477491 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.3093477491 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.2833151234 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 323509409 ps |
| CPU time | 29.75 seconds |
| Started | Aug 06 08:57:41 PM PDT 24 |
| Finished | Aug 06 08:58:10 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-819d98b3-1232-4983-9395-b2225daf732c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833151234 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2833151234 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.1639818944 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 243932409 ps |
| CPU time | 12.26 seconds |
| Started | Aug 06 08:57:35 PM PDT 24 |
| Finished | Aug 06 08:57:47 PM PDT 24 |
| Peak memory | 573816 kb |
| Host | smart-c3ea5674-6b22-48d5-a2e9-4a564d9ff31f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639818944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.1639818944 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3391130866 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 32542076424 ps |
| CPU time | 343.1 seconds |
| Started | Aug 06 08:57:33 PM PDT 24 |
| Finished | Aug 06 09:03:16 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-c25c4f80-6b84-4553-8f9b-4b630c1735e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391130866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3391130866 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.1192774431 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 13927170791 ps |
| CPU time | 257.65 seconds |
| Started | Aug 06 08:57:37 PM PDT 24 |
| Finished | Aug 06 09:01:55 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-9951c23b-34fb-4eab-8dea-5be33ef434fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192774431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.1192774431 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.1995724977 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 260174719 ps |
| CPU time | 29.2 seconds |
| Started | Aug 06 08:57:37 PM PDT 24 |
| Finished | Aug 06 08:58:06 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-82bc1f86-e344-47a4-8788-3e0e2e9420f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995724977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.1995724977 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.3140484620 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 1851772376 ps |
| CPU time | 59.26 seconds |
| Started | Aug 06 08:57:34 PM PDT 24 |
| Finished | Aug 06 08:58:33 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-cfdde644-70cc-4aa2-9466-0d1c9f80339c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140484620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.3140484620 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.2345529618 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 205913703 ps |
| CPU time | 9.16 seconds |
| Started | Aug 06 08:57:29 PM PDT 24 |
| Finished | Aug 06 08:57:39 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-db268897-de6b-4ef6-9ca0-75801f0aa690 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345529618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.2345529618 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.4229423422 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 4504658079 ps |
| CPU time | 49.08 seconds |
| Started | Aug 06 08:57:32 PM PDT 24 |
| Finished | Aug 06 08:58:21 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-c2b115c7-bb4f-4540-be9c-79a6314969cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229423422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.4229423422 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.18247910 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 5169077682 ps |
| CPU time | 87.49 seconds |
| Started | Aug 06 08:57:33 PM PDT 24 |
| Finished | Aug 06 08:59:01 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-7c547098-9150-459e-a2cc-580c89f67c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18247910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.18247910 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.178331806 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 52673215 ps |
| CPU time | 7.65 seconds |
| Started | Aug 06 08:57:37 PM PDT 24 |
| Finished | Aug 06 08:57:44 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-d0fed43d-79aa-4d99-aa16-9e9def5866c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178331806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delays .178331806 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.115660365 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 5641584 ps |
| CPU time | 3.99 seconds |
| Started | Aug 06 08:57:38 PM PDT 24 |
| Finished | Aug 06 08:57:42 PM PDT 24 |
| Peak memory | 565940 kb |
| Host | smart-d680e1cc-5c14-4a3d-874b-efb6381eb60a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115660365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.115660365 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.2081750730 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 12448326369 ps |
| CPU time | 455.14 seconds |
| Started | Aug 06 08:57:40 PM PDT 24 |
| Finished | Aug 06 09:05:15 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-3f7f6b48-bb3b-40f3-8d22-b5a2f7c61e10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081750730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.2081750730 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.4244926798 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 770617444 ps |
| CPU time | 304.31 seconds |
| Started | Aug 06 08:57:44 PM PDT 24 |
| Finished | Aug 06 09:02:48 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-d26e308a-7bea-4f57-80f2-34d39e4afadf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4244926798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.4244926798 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.3700065977 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 620407191 ps |
| CPU time | 200.18 seconds |
| Started | Aug 06 08:57:39 PM PDT 24 |
| Finished | Aug 06 09:00:59 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-058b4fc0-b525-4fe4-ad7a-79f0e77c9bae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700065977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.3700065977 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.4260646409 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 258105333 ps |
| CPU time | 36.82 seconds |
| Started | Aug 06 08:57:39 PM PDT 24 |
| Finished | Aug 06 08:58:16 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-49e6939c-8f08-4305-8a1c-86ee1d00396b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260646409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.4260646409 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.2495713344 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 373798360 ps |
| CPU time | 32.03 seconds |
| Started | Aug 06 08:57:43 PM PDT 24 |
| Finished | Aug 06 08:58:15 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-090fdc55-11f7-4de1-860d-43b6291e9abe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2495713344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .2495713344 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1017684010 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 106421891404 ps |
| CPU time | 1830.68 seconds |
| Started | Aug 06 08:57:45 PM PDT 24 |
| Finished | Aug 06 09:28:16 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-09dac1bc-1d75-4668-abbf-476822634535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017684010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1017684010 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.72634623 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 114607143 ps |
| CPU time | 15.92 seconds |
| Started | Aug 06 08:57:50 PM PDT 24 |
| Finished | Aug 06 08:58:06 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-2d37e19b-d06a-4316-b552-1c7ca6ad412f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72634623 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr.72634623 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.290755517 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 1803600616 ps |
| CPU time | 69.91 seconds |
| Started | Aug 06 08:57:49 PM PDT 24 |
| Finished | Aug 06 08:58:59 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-481c18b0-f231-4291-8e71-4ee5a47de674 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290755517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.290755517 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.4159656616 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 1945916644 ps |
| CPU time | 81.92 seconds |
| Started | Aug 06 08:57:42 PM PDT 24 |
| Finished | Aug 06 08:59:04 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-285741d8-ee38-451d-bce9-d2291f7138f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4159656616 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.4159656616 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.3480771078 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 84642444821 ps |
| CPU time | 894.7 seconds |
| Started | Aug 06 08:57:49 PM PDT 24 |
| Finished | Aug 06 09:12:44 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-8d0433a2-ec84-4cde-9ad2-54c68bd9f847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480771078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.3480771078 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.1025387728 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 65301774526 ps |
| CPU time | 1079.06 seconds |
| Started | Aug 06 08:57:44 PM PDT 24 |
| Finished | Aug 06 09:15:44 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-1d32b8f4-4d72-48f9-a50c-43a6b6e96192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025387728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.1025387728 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2281360188 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 65640427 ps |
| CPU time | 9.85 seconds |
| Started | Aug 06 08:57:43 PM PDT 24 |
| Finished | Aug 06 08:57:53 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-11c74de3-3c00-4807-a4bd-6ccfe66c06b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281360188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_del ays.2281360188 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.1997866462 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2155121258 ps |
| CPU time | 77.32 seconds |
| Started | Aug 06 08:57:44 PM PDT 24 |
| Finished | Aug 06 08:59:02 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-2f183584-cec3-4b56-a3fc-84209595bb8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997866462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.1997866462 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.3156623992 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 203460276 ps |
| CPU time | 9.7 seconds |
| Started | Aug 06 08:57:40 PM PDT 24 |
| Finished | Aug 06 08:57:50 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-ecf7eaa2-9db9-4833-a736-d71d94ec854b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156623992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.3156623992 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.282297997 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 8393457432 ps |
| CPU time | 88.99 seconds |
| Started | Aug 06 08:57:43 PM PDT 24 |
| Finished | Aug 06 08:59:12 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-7fb8469a-df4e-4741-ac06-9e67357d0e98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282297997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.282297997 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.184995023 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 5311716163 ps |
| CPU time | 90.86 seconds |
| Started | Aug 06 08:57:42 PM PDT 24 |
| Finished | Aug 06 08:59:13 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-001731e8-1bdd-41ab-889a-d23283ce0e8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184995023 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.184995023 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3805230569 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 52866037 ps |
| CPU time | 6.74 seconds |
| Started | Aug 06 08:57:43 PM PDT 24 |
| Finished | Aug 06 08:57:50 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-dc71141b-6534-4750-b16a-9b3083bb8fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805230569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.3805230569 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.2077629125 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 10908463237 ps |
| CPU time | 464.5 seconds |
| Started | Aug 06 08:57:49 PM PDT 24 |
| Finished | Aug 06 09:05:33 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-e51c16f2-fb79-4195-8128-41589c73b240 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077629125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.2077629125 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.3441522287 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 2999299115 ps |
| CPU time | 120.78 seconds |
| Started | Aug 06 08:57:48 PM PDT 24 |
| Finished | Aug 06 08:59:49 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-185a82fe-1be1-4597-80d1-cfb928c8f463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441522287 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.3441522287 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.3606372121 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 540023594 ps |
| CPU time | 210.44 seconds |
| Started | Aug 06 08:57:49 PM PDT 24 |
| Finished | Aug 06 09:01:19 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-d6761e50-c70c-4e54-9603-a9fd90ce26fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606372121 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.3606372121 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.230613393 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 132663255 ps |
| CPU time | 19.69 seconds |
| Started | Aug 06 08:57:44 PM PDT 24 |
| Finished | Aug 06 08:58:04 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-8686ee2e-5109-4706-b44a-7f0b9cf3a4df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=230613393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.230613393 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.2567348450 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 6580738810 ps |
| CPU time | 457.39 seconds |
| Started | Aug 06 08:45:56 PM PDT 24 |
| Finished | Aug 06 08:53:33 PM PDT 24 |
| Peak memory | 644420 kb |
| Host | smart-74bfa9db-ca66-4c17-ac71-c1989c559dc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2567348450 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.2567348450 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.779634779 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 5710537065 ps |
| CPU time | 648.1 seconds |
| Started | Aug 06 08:45:47 PM PDT 24 |
| Finished | Aug 06 08:56:36 PM PDT 24 |
| Peak memory | 598600 kb |
| Host | smart-f9715fbb-159a-40ba-9609-b0cccc95b24c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779634779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.779634779 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1113774718 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 30089584739 ps |
| CPU time | 3540.58 seconds |
| Started | Aug 06 08:45:17 PM PDT 24 |
| Finished | Aug 06 09:44:17 PM PDT 24 |
| Peak memory | 592996 kb |
| Host | smart-8e9a4062-fe54-427d-87ce-d8c640550f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113774718 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.1113774718 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1171448554 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 3870832835 ps |
| CPU time | 281.11 seconds |
| Started | Aug 06 08:45:19 PM PDT 24 |
| Finished | Aug 06 08:50:00 PM PDT 24 |
| Peak memory | 598624 kb |
| Host | smart-2010ed8d-1415-4c1a-ac84-98f829d229b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171448554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1171448554 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.1153318905 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 193623067 ps |
| CPU time | 15.31 seconds |
| Started | Aug 06 08:45:36 PM PDT 24 |
| Finished | Aug 06 08:45:51 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-5e48f968-52f8-4c90-bb70-b4424546d0db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153318905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 1153318905 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.2535562325 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 63279018930 ps |
| CPU time | 1073 seconds |
| Started | Aug 06 08:45:35 PM PDT 24 |
| Finished | Aug 06 09:03:28 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-2b13c13a-59e7-44cc-96e5-10f79d91cdc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2535562325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.2535562325 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.3393825113 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 188942767 ps |
| CPU time | 10.69 seconds |
| Started | Aug 06 08:45:40 PM PDT 24 |
| Finished | Aug 06 08:45:51 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-40a053d1-74c6-4c9e-8659-160588bae850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393825113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .3393825113 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.42830329 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 2212451321 ps |
| CPU time | 81.5 seconds |
| Started | Aug 06 08:45:39 PM PDT 24 |
| Finished | Aug 06 08:47:00 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-957d9e2c-3dc0-4e3c-8bd3-2844049aff3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42830329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.42830329 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.3703887684 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 445641615 ps |
| CPU time | 47.93 seconds |
| Started | Aug 06 08:45:33 PM PDT 24 |
| Finished | Aug 06 08:46:22 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-9d37815f-f6c5-4996-b273-24e9f05f81f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703887684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.3703887684 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2566670762 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 19492398504 ps |
| CPU time | 235.03 seconds |
| Started | Aug 06 08:45:42 PM PDT 24 |
| Finished | Aug 06 08:49:37 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-afe541ca-434f-45c7-b685-45c1478e283e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566670762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2566670762 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.3657845860 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 38290486083 ps |
| CPU time | 690.68 seconds |
| Started | Aug 06 08:45:35 PM PDT 24 |
| Finished | Aug 06 08:57:06 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-cc85fedd-d990-49c5-ab16-eaaccd74891a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657845860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.3657845860 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.3944548632 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 553871748 ps |
| CPU time | 66.01 seconds |
| Started | Aug 06 08:45:32 PM PDT 24 |
| Finished | Aug 06 08:46:38 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-02d1574c-94f4-43fa-8cf9-791abc28b15e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944548632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.3944548632 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.2049135483 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 533708237 ps |
| CPU time | 47.54 seconds |
| Started | Aug 06 08:45:32 PM PDT 24 |
| Finished | Aug 06 08:46:19 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-12981553-ea5f-468d-a879-2d627ae4413c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049135483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2049135483 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.3532561526 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 227750939 ps |
| CPU time | 10.71 seconds |
| Started | Aug 06 08:45:15 PM PDT 24 |
| Finished | Aug 06 08:45:26 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-4a1e5a97-e57d-4192-aa78-cdcc24b497a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532561526 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.3532561526 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.185249306 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 8709556823 ps |
| CPU time | 95.7 seconds |
| Started | Aug 06 08:45:25 PM PDT 24 |
| Finished | Aug 06 08:47:01 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-1c7b1fe1-c567-403f-a1be-92778817043c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185249306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.185249306 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.3139273521 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 5923300876 ps |
| CPU time | 103.39 seconds |
| Started | Aug 06 08:45:26 PM PDT 24 |
| Finished | Aug 06 08:47:10 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-8394b37d-44a2-4fe9-a497-8bb09266e535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139273521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3139273521 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1559921582 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 48881517 ps |
| CPU time | 6.98 seconds |
| Started | Aug 06 08:45:18 PM PDT 24 |
| Finished | Aug 06 08:45:25 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-11e98c81-3d80-4c19-a16d-fcbd879af60b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559921582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .1559921582 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.1040553054 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 3863364579 ps |
| CPU time | 413.75 seconds |
| Started | Aug 06 08:45:49 PM PDT 24 |
| Finished | Aug 06 08:52:43 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-3967072b-60f9-4b65-bb3d-62d812564059 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040553054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.1040553054 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.285698236 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 9712700992 ps |
| CPU time | 360.11 seconds |
| Started | Aug 06 08:45:44 PM PDT 24 |
| Finished | Aug 06 08:51:44 PM PDT 24 |
| Peak memory | 576484 kb |
| Host | smart-71650c26-12a3-43e9-b781-f41dd0b3b044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=285698236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.285698236 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.2599196867 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 277461484 ps |
| CPU time | 130.04 seconds |
| Started | Aug 06 08:45:46 PM PDT 24 |
| Finished | Aug 06 08:47:56 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-e886bddd-d6d8-4a82-8d7b-6d9e9a8c6608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599196867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.2599196867 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1563930627 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 434829372 ps |
| CPU time | 166.12 seconds |
| Started | Aug 06 08:46:04 PM PDT 24 |
| Finished | Aug 06 08:48:50 PM PDT 24 |
| Peak memory | 576640 kb |
| Host | smart-96577ccc-8844-4d02-9dc3-da429e6d11ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563930627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.1563930627 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.2192306997 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 21364805 ps |
| CPU time | 6.19 seconds |
| Started | Aug 06 08:45:39 PM PDT 24 |
| Finished | Aug 06 08:45:45 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-146a7200-d712-45d6-a731-c203843043b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192306997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.2192306997 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.2103042469 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 739805209 ps |
| CPU time | 64.05 seconds |
| Started | Aug 06 08:57:54 PM PDT 24 |
| Finished | Aug 06 08:58:58 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-c3309175-321a-416a-a85c-81a99674a51a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103042469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device .2103042469 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2074284828 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 13872331376 ps |
| CPU time | 258.27 seconds |
| Started | Aug 06 08:57:54 PM PDT 24 |
| Finished | Aug 06 09:02:13 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-5c76deba-ea21-422d-8412-c01ff5a825cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074284828 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2074284828 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3615789019 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 271653783 ps |
| CPU time | 14.49 seconds |
| Started | Aug 06 08:57:59 PM PDT 24 |
| Finished | Aug 06 08:58:13 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-82289cf9-25cc-4a24-abf9-b66f3f0e0672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615789019 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.3615789019 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.1701123253 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 586085973 ps |
| CPU time | 47.47 seconds |
| Started | Aug 06 08:57:59 PM PDT 24 |
| Finished | Aug 06 08:58:47 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-2dcc3a18-d320-4e2e-9234-7f4f8f4ff1d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701123253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.1701123253 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.883867169 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 1737330768 ps |
| CPU time | 67.74 seconds |
| Started | Aug 06 08:57:53 PM PDT 24 |
| Finished | Aug 06 08:59:01 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-2d107073-0efa-466a-85e9-16a6c1ae426c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883867169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.883867169 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.3632055923 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 23772753415 ps |
| CPU time | 246.84 seconds |
| Started | Aug 06 08:57:55 PM PDT 24 |
| Finished | Aug 06 09:02:02 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-73321b6a-4249-4d95-bced-34efa884080e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632055923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.3632055923 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.3226917685 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 51846425297 ps |
| CPU time | 891.86 seconds |
| Started | Aug 06 08:57:58 PM PDT 24 |
| Finished | Aug 06 09:12:50 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-a643dcfd-0e9f-4263-b19e-9451fa2519d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226917685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.3226917685 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1702270860 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 71730433 ps |
| CPU time | 10.35 seconds |
| Started | Aug 06 08:57:55 PM PDT 24 |
| Finished | Aug 06 08:58:05 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-b0e53b0b-e7f8-448b-b1a9-2d30530e0e6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702270860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1702270860 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.1444267431 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 222514612 ps |
| CPU time | 18.74 seconds |
| Started | Aug 06 08:58:00 PM PDT 24 |
| Finished | Aug 06 08:58:18 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-61a3fba4-a40c-4628-a03e-6043585f4e6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444267431 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.1444267431 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3424010200 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 167463172 ps |
| CPU time | 8.8 seconds |
| Started | Aug 06 08:57:49 PM PDT 24 |
| Finished | Aug 06 08:57:58 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-124d6412-ffb9-4229-ab17-f55eb5c178a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424010200 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3424010200 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.950448844 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 7609070465 ps |
| CPU time | 76.81 seconds |
| Started | Aug 06 08:57:53 PM PDT 24 |
| Finished | Aug 06 08:59:10 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-978f70d1-ce01-47d1-8146-51736a36ce71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950448844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.950448844 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.1651615856 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 4925136155 ps |
| CPU time | 85.2 seconds |
| Started | Aug 06 08:57:52 PM PDT 24 |
| Finished | Aug 06 08:59:17 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-b6a80376-b82c-4b08-a1fd-a75432e9b464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651615856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.1651615856 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.3799294906 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 56647825 ps |
| CPU time | 6.86 seconds |
| Started | Aug 06 08:57:50 PM PDT 24 |
| Finished | Aug 06 08:57:57 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-79903b0d-eeba-43bc-97ef-1b5f5f0d6054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799294906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.3799294906 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.1733076268 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 1191772676 ps |
| CPU time | 52.43 seconds |
| Started | Aug 06 08:58:01 PM PDT 24 |
| Finished | Aug 06 08:58:53 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-d8b1a57f-36eb-4809-aef3-0c729c9aabd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733076268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.1733076268 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.851737949 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 233964923 ps |
| CPU time | 27.24 seconds |
| Started | Aug 06 08:58:01 PM PDT 24 |
| Finished | Aug 06 08:58:29 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-0ccc1476-7366-4e2d-b320-2f7324cfd807 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851737949 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.851737949 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.1049463969 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 7616424405 ps |
| CPU time | 579.53 seconds |
| Started | Aug 06 08:57:58 PM PDT 24 |
| Finished | Aug 06 09:07:37 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-8795e335-4ce0-4640-a49d-fb026c13d5b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049463969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.1049463969 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.4292643827 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 564778700 ps |
| CPU time | 29.6 seconds |
| Started | Aug 06 08:58:00 PM PDT 24 |
| Finished | Aug 06 08:58:30 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-2ba1497d-9cfa-43e9-9180-00957b68652f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292643827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.4292643827 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.2029273461 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 1028647089 ps |
| CPU time | 47.65 seconds |
| Started | Aug 06 08:58:07 PM PDT 24 |
| Finished | Aug 06 08:58:55 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-aec234bb-7d07-48c5-8e42-e0a3b633332a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029273461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .2029273461 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2456888577 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 97594614553 ps |
| CPU time | 1791.83 seconds |
| Started | Aug 06 08:58:03 PM PDT 24 |
| Finished | Aug 06 09:27:55 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-9c0780d8-e132-49e7-bf01-7feb6c585275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2456888577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.2456888577 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2157752784 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 557904985 ps |
| CPU time | 22.77 seconds |
| Started | Aug 06 08:58:11 PM PDT 24 |
| Finished | Aug 06 08:58:34 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-9ca324c8-f588-4f22-a562-1c4987bf0c61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157752784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.2157752784 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.4109634242 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 475949823 ps |
| CPU time | 23.25 seconds |
| Started | Aug 06 08:58:03 PM PDT 24 |
| Finished | Aug 06 08:58:26 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-5d6039cb-4726-49fa-9e86-987c22015de5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109634242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.4109634242 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.45672835 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2082702529 ps |
| CPU time | 75.03 seconds |
| Started | Aug 06 08:58:02 PM PDT 24 |
| Finished | Aug 06 08:59:17 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-a3f4ab08-5f81-4d43-84f6-6a9e41ca86f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45672835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.45672835 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.4069884299 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 51864276638 ps |
| CPU time | 550.75 seconds |
| Started | Aug 06 08:58:04 PM PDT 24 |
| Finished | Aug 06 09:07:14 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-5d943809-50db-42b9-b749-daf9d4f4f614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069884299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.4069884299 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1521611098 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 6721630480 ps |
| CPU time | 114.35 seconds |
| Started | Aug 06 08:58:03 PM PDT 24 |
| Finished | Aug 06 08:59:58 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-3e6db44b-6447-4bdb-bc33-19b8963102fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1521611098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.1521611098 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.823168696 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 424799157 ps |
| CPU time | 42.51 seconds |
| Started | Aug 06 08:58:03 PM PDT 24 |
| Finished | Aug 06 08:58:45 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-604b7909-23d9-4d54-b3c1-d9674d55877f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823168696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_dela ys.823168696 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.564507192 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 180683997 ps |
| CPU time | 17.14 seconds |
| Started | Aug 06 08:58:02 PM PDT 24 |
| Finished | Aug 06 08:58:19 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-cbd7e9a9-e137-486b-8b3a-bb11150db353 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564507192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.564507192 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.3083782934 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 36248941 ps |
| CPU time | 6.08 seconds |
| Started | Aug 06 08:57:59 PM PDT 24 |
| Finished | Aug 06 08:58:05 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-d995bf9d-9adc-4b99-a083-c20091d6445f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083782934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.3083782934 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.875883441 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 8466427345 ps |
| CPU time | 89.08 seconds |
| Started | Aug 06 08:58:02 PM PDT 24 |
| Finished | Aug 06 08:59:31 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-2b6fb600-1513-4b35-8849-38e887ac5d63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875883441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.875883441 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.2724799885 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 4045741023 ps |
| CPU time | 71.62 seconds |
| Started | Aug 06 08:58:03 PM PDT 24 |
| Finished | Aug 06 08:59:14 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-5f0dcb55-60c6-4117-838e-3da38fd7ffa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724799885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.2724799885 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.1605199456 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 56547095 ps |
| CPU time | 6.57 seconds |
| Started | Aug 06 08:57:56 PM PDT 24 |
| Finished | Aug 06 08:58:03 PM PDT 24 |
| Peak memory | 573120 kb |
| Host | smart-aadf2743-8319-4dee-bede-8bcbdaffc86c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605199456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.1605199456 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1416938150 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 3565667419 ps |
| CPU time | 276.47 seconds |
| Started | Aug 06 08:58:08 PM PDT 24 |
| Finished | Aug 06 09:02:44 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-0da212ad-b1ab-43d9-affd-55dc40ed6485 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416938150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1416938150 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.1269165286 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 305827940 ps |
| CPU time | 107.18 seconds |
| Started | Aug 06 08:58:11 PM PDT 24 |
| Finished | Aug 06 08:59:58 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-6138319f-42b3-40bd-96ec-d7c1fe96757e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269165286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.1269165286 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1659479768 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 319578475 ps |
| CPU time | 91.95 seconds |
| Started | Aug 06 08:58:07 PM PDT 24 |
| Finished | Aug 06 08:59:39 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-2fd8a911-1242-41ae-9424-2fb00ae3e982 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659479768 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1659479768 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.2377229314 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 472604487 ps |
| CPU time | 26.49 seconds |
| Started | Aug 06 08:58:03 PM PDT 24 |
| Finished | Aug 06 08:58:29 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-75fd465c-ab5f-4bf1-b94e-5304f11cb6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377229314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.2377229314 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.3007045805 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 845338577 ps |
| CPU time | 63.46 seconds |
| Started | Aug 06 08:58:13 PM PDT 24 |
| Finished | Aug 06 08:59:16 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-1a4a1cc8-0c61-43de-8b47-adae4bbbfe31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007045805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .3007045805 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.438534924 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 11492243862 ps |
| CPU time | 205.49 seconds |
| Started | Aug 06 08:58:14 PM PDT 24 |
| Finished | Aug 06 09:01:39 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-8f1e7090-d1aa-4457-96b0-a33acfdadbef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438534924 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_d evice_slow_rsp.438534924 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.2587324294 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 704398446 ps |
| CPU time | 32.25 seconds |
| Started | Aug 06 08:58:17 PM PDT 24 |
| Finished | Aug 06 08:58:49 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-115edda3-f54c-44af-8dc4-cb393d81b122 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587324294 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.2587324294 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.3707729861 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2219638998 ps |
| CPU time | 96.09 seconds |
| Started | Aug 06 08:58:18 PM PDT 24 |
| Finished | Aug 06 08:59:54 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-28d055f6-1d00-407c-a259-70439c815e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3707729861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.3707729861 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.1796014908 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 1140931530 ps |
| CPU time | 40.08 seconds |
| Started | Aug 06 08:58:14 PM PDT 24 |
| Finished | Aug 06 08:58:54 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-a77bcfa1-5551-4404-b8e5-de486d36238e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796014908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.1796014908 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.925576213 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 9987458914 ps |
| CPU time | 112.61 seconds |
| Started | Aug 06 08:58:15 PM PDT 24 |
| Finished | Aug 06 09:00:08 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-51e296e9-6d17-4a4c-9e63-f2ed8f1e0a76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=925576213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.925576213 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.542109199 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 12018935972 ps |
| CPU time | 213.88 seconds |
| Started | Aug 06 08:58:14 PM PDT 24 |
| Finished | Aug 06 09:01:48 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-b73c4e23-6ff9-4aab-9562-7d1e78e23ff8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542109199 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.542109199 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1677804907 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 72841222 ps |
| CPU time | 10.08 seconds |
| Started | Aug 06 08:58:14 PM PDT 24 |
| Finished | Aug 06 08:58:24 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-1eefac46-64dd-4d33-92a8-37a6b015cd68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1677804907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_del ays.1677804907 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.866027598 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 1295010888 ps |
| CPU time | 41.53 seconds |
| Started | Aug 06 08:58:14 PM PDT 24 |
| Finished | Aug 06 08:58:56 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-ccdedc1b-2d3c-4c5d-b256-1ecd766099fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866027598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.866027598 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.290351065 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 212626921 ps |
| CPU time | 9.76 seconds |
| Started | Aug 06 08:58:09 PM PDT 24 |
| Finished | Aug 06 08:58:19 PM PDT 24 |
| Peak memory | 573760 kb |
| Host | smart-863901bd-0519-4897-a681-615d70f6d3e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290351065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.290351065 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2177962234 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 4975377455 ps |
| CPU time | 51.19 seconds |
| Started | Aug 06 08:58:09 PM PDT 24 |
| Finished | Aug 06 08:59:01 PM PDT 24 |
| Peak memory | 574516 kb |
| Host | smart-f18b9c39-92cb-4fa7-836f-efa97ffc712c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177962234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.2177962234 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1585512249 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 4380956673 ps |
| CPU time | 78.36 seconds |
| Started | Aug 06 08:58:11 PM PDT 24 |
| Finished | Aug 06 08:59:29 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-5909664e-dff9-4256-897e-4d8a8dacc3c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585512249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1585512249 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.1798152451 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 39172209 ps |
| CPU time | 6.22 seconds |
| Started | Aug 06 08:58:11 PM PDT 24 |
| Finished | Aug 06 08:58:17 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-66225882-548e-48a7-ab25-77153e8ddaeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1798152451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delay s.1798152451 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.3820432325 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 9370404822 ps |
| CPU time | 395.82 seconds |
| Started | Aug 06 08:58:21 PM PDT 24 |
| Finished | Aug 06 09:04:57 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-c3c15d78-3594-4a32-a7eb-920550b7b50a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820432325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.3820432325 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.2632275681 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 11530604830 ps |
| CPU time | 424.95 seconds |
| Started | Aug 06 08:58:18 PM PDT 24 |
| Finished | Aug 06 09:05:23 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-27af96fd-4623-44a5-8da1-94f1cccd640c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632275681 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.2632275681 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.1473678278 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 47889416 ps |
| CPU time | 23.03 seconds |
| Started | Aug 06 08:58:21 PM PDT 24 |
| Finished | Aug 06 08:58:44 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-8fabe5d8-47d6-4989-a66c-34a2871a5e15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473678278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.1473678278 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2418698308 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 240248442 ps |
| CPU time | 33.47 seconds |
| Started | Aug 06 08:58:17 PM PDT 24 |
| Finished | Aug 06 08:58:51 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-be5f9d38-3afa-496b-92d3-c1206862e244 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418698308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2418698308 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3961100715 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 678974510 ps |
| CPU time | 32.86 seconds |
| Started | Aug 06 08:58:27 PM PDT 24 |
| Finished | Aug 06 08:59:00 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-04c7898c-e1ff-4c0e-93a2-7395d99661be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961100715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .3961100715 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.3948145012 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 89191110856 ps |
| CPU time | 1632.98 seconds |
| Started | Aug 06 08:58:29 PM PDT 24 |
| Finished | Aug 06 09:25:42 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-eb5deba3-6e10-45b6-a8d5-62c9676be630 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948145012 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.3948145012 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.1683669089 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 304239353 ps |
| CPU time | 38.51 seconds |
| Started | Aug 06 08:58:28 PM PDT 24 |
| Finished | Aug 06 08:59:07 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-4243f52b-ac3d-4318-bf81-eab40e3e1801 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683669089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_add r.1683669089 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.3174040779 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 1674863720 ps |
| CPU time | 64.71 seconds |
| Started | Aug 06 08:58:28 PM PDT 24 |
| Finished | Aug 06 08:59:33 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-23b7b2bd-2656-4bd7-93ee-16ff522c05ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174040779 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.3174040779 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.389311113 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 108751951 ps |
| CPU time | 13.13 seconds |
| Started | Aug 06 08:58:17 PM PDT 24 |
| Finished | Aug 06 08:58:30 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-c070a018-b0ca-42ed-a0ba-7996c0a7e6a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389311113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.389311113 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.1960327857 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 93325745570 ps |
| CPU time | 1016.09 seconds |
| Started | Aug 06 08:58:28 PM PDT 24 |
| Finished | Aug 06 09:15:24 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-3549eff8-c1fb-4266-af26-f7128d772e15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960327857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.1960327857 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.297350270 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 53688540979 ps |
| CPU time | 921.36 seconds |
| Started | Aug 06 08:58:28 PM PDT 24 |
| Finished | Aug 06 09:13:49 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-37c1e0c6-8a11-492c-b277-fd7c94bb1bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297350270 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.297350270 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2521930824 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 565333118 ps |
| CPU time | 51.18 seconds |
| Started | Aug 06 08:58:28 PM PDT 24 |
| Finished | Aug 06 08:59:19 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-be4cd07b-3aec-4745-954f-df4b43a80946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521930824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.2521930824 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.3023167977 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 1509198026 ps |
| CPU time | 47.91 seconds |
| Started | Aug 06 08:58:27 PM PDT 24 |
| Finished | Aug 06 08:59:15 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-ce5efde5-b8a4-4056-87cc-de3def00c4f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023167977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.3023167977 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.2780200806 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 200214799 ps |
| CPU time | 10.17 seconds |
| Started | Aug 06 08:58:21 PM PDT 24 |
| Finished | Aug 06 08:58:31 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-5e4c10b2-d241-48a5-bb91-99a7cd52f45d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780200806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.2780200806 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.1073914327 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 7261048664 ps |
| CPU time | 83.3 seconds |
| Started | Aug 06 08:58:18 PM PDT 24 |
| Finished | Aug 06 08:59:41 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-bf7a075f-b101-41ac-aa03-355cacf4454e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073914327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.1073914327 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.400840304 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 5819018403 ps |
| CPU time | 101.19 seconds |
| Started | Aug 06 08:58:19 PM PDT 24 |
| Finished | Aug 06 09:00:00 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-2ab41c9e-70d6-451c-8b01-fe5fc1dc57c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400840304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.400840304 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2563967084 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 60102028 ps |
| CPU time | 8.55 seconds |
| Started | Aug 06 08:58:20 PM PDT 24 |
| Finished | Aug 06 08:58:29 PM PDT 24 |
| Peak memory | 574456 kb |
| Host | smart-dcf33ead-3073-4aee-9f1b-0185f1a7c0c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563967084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2563967084 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.1163946561 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 1187827554 ps |
| CPU time | 121 seconds |
| Started | Aug 06 08:58:29 PM PDT 24 |
| Finished | Aug 06 09:00:30 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-d1342ed2-f372-4af0-8dbc-f4aba37d9c3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163946561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.1163946561 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.960817216 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 3397842006 ps |
| CPU time | 294.33 seconds |
| Started | Aug 06 08:58:32 PM PDT 24 |
| Finished | Aug 06 09:03:27 PM PDT 24 |
| Peak memory | 576600 kb |
| Host | smart-35cc9f6d-a9ba-4f6b-8c5f-0177089ef1b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960817216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.960817216 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2704607642 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 520741680 ps |
| CPU time | 155.23 seconds |
| Started | Aug 06 08:58:28 PM PDT 24 |
| Finished | Aug 06 09:01:03 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-3fc2fa1c-8a9a-4128-a9f0-e55668cdf20d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2704607642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.2704607642 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.4147321991 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 4132234776 ps |
| CPU time | 237.65 seconds |
| Started | Aug 06 08:58:34 PM PDT 24 |
| Finished | Aug 06 09:02:32 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-d77d246c-af2e-44f1-a9be-5383508846af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4147321991 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.4147321991 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.2099238855 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 36796912 ps |
| CPU time | 7.22 seconds |
| Started | Aug 06 08:58:29 PM PDT 24 |
| Finished | Aug 06 08:58:36 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-e10437e6-7fe8-47b5-8285-145bc0a5ce88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099238855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.2099238855 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.2108450605 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 1320746325 ps |
| CPU time | 52.8 seconds |
| Started | Aug 06 08:58:32 PM PDT 24 |
| Finished | Aug 06 08:59:25 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-1fbb6972-97cd-4bcc-8180-c54467720b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108450605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .2108450605 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.3092744873 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 49626601122 ps |
| CPU time | 849.9 seconds |
| Started | Aug 06 08:58:34 PM PDT 24 |
| Finished | Aug 06 09:12:44 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-8465fd14-d5fa-44fb-b971-d8e8ea8ebfcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092744873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.3092744873 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.2276387663 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 323172451 ps |
| CPU time | 37.05 seconds |
| Started | Aug 06 08:58:32 PM PDT 24 |
| Finished | Aug 06 08:59:09 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-84fa2bfd-2c06-4507-bc9f-a48ac8c4fc9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276387663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_add r.2276387663 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.4217842035 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 111356695 ps |
| CPU time | 7.57 seconds |
| Started | Aug 06 08:58:50 PM PDT 24 |
| Finished | Aug 06 08:58:57 PM PDT 24 |
| Peak memory | 574340 kb |
| Host | smart-903b3e1f-0f15-4fd8-a5ea-311fb992bcf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217842035 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.4217842035 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.2366809459 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 334996664 ps |
| CPU time | 35.63 seconds |
| Started | Aug 06 08:58:33 PM PDT 24 |
| Finished | Aug 06 08:59:09 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-9fbe1781-434c-4fc8-8356-08e98f342ab4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366809459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.2366809459 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.2702623503 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 113791904834 ps |
| CPU time | 1225.66 seconds |
| Started | Aug 06 08:58:50 PM PDT 24 |
| Finished | Aug 06 09:19:16 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-dd4bd150-47a7-441c-8104-8ae06d884271 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702623503 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.2702623503 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.2650973039 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 28580992782 ps |
| CPU time | 504.81 seconds |
| Started | Aug 06 08:58:49 PM PDT 24 |
| Finished | Aug 06 09:07:14 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-72c15170-3d29-4456-b6fc-f5ba48515ca0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650973039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.2650973039 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.251733533 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 163009218 ps |
| CPU time | 16.26 seconds |
| Started | Aug 06 08:58:49 PM PDT 24 |
| Finished | Aug 06 08:59:05 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-b7028f42-db03-415b-bcfa-7a33101935f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251733533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela ys.251733533 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.1511555307 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 1891155464 ps |
| CPU time | 68.15 seconds |
| Started | Aug 06 08:58:32 PM PDT 24 |
| Finished | Aug 06 08:59:40 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4633465f-3d16-43ea-8056-3a4c6334a4ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511555307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.1511555307 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.2373343258 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 45571289 ps |
| CPU time | 6.33 seconds |
| Started | Aug 06 08:58:34 PM PDT 24 |
| Finished | Aug 06 08:58:41 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-4bcbd891-31f4-4a4d-af3f-1f19bd7fc93a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373343258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.2373343258 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.4293334226 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 10493222524 ps |
| CPU time | 106.14 seconds |
| Started | Aug 06 08:58:32 PM PDT 24 |
| Finished | Aug 06 09:00:19 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-3a6d3e53-16dd-4853-8620-23f371f096f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293334226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.4293334226 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3940333435 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 6325144404 ps |
| CPU time | 112.51 seconds |
| Started | Aug 06 08:58:32 PM PDT 24 |
| Finished | Aug 06 09:00:24 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-c266a92a-841d-4585-83d1-8bdbe6184d00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940333435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.3940333435 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1909054463 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 42467078 ps |
| CPU time | 6.45 seconds |
| Started | Aug 06 08:58:31 PM PDT 24 |
| Finished | Aug 06 08:58:37 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-d448f4d5-7a9f-4db8-9771-780d0d449c2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909054463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1909054463 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.4170479116 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 10925214049 ps |
| CPU time | 439.42 seconds |
| Started | Aug 06 08:58:36 PM PDT 24 |
| Finished | Aug 06 09:05:56 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-f0875d7b-c2f2-4f34-b1b6-bf6ca2db32ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170479116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.4170479116 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.489401326 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 7536403508 ps |
| CPU time | 255.84 seconds |
| Started | Aug 06 08:58:38 PM PDT 24 |
| Finished | Aug 06 09:02:53 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-e706b5e6-32fb-41c6-b849-1e64e7c0d7be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489401326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.489401326 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.568348680 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 708166524 ps |
| CPU time | 232.98 seconds |
| Started | Aug 06 08:58:34 PM PDT 24 |
| Finished | Aug 06 09:02:27 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-0ef8ad07-3908-4156-ad82-63ed3d57d5e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568348680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_ with_rand_reset.568348680 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3889877874 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 7903112118 ps |
| CPU time | 456.75 seconds |
| Started | Aug 06 08:58:39 PM PDT 24 |
| Finished | Aug 06 09:06:16 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-51195542-941e-45b8-a6b4-e24c179c00ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889877874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.3889877874 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.3963455499 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 894596098 ps |
| CPU time | 37.98 seconds |
| Started | Aug 06 08:58:35 PM PDT 24 |
| Finished | Aug 06 08:59:13 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-3451f7f6-c842-49ba-968b-f6bca4534b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963455499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.3963455499 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.4118012860 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 977961217 ps |
| CPU time | 77.45 seconds |
| Started | Aug 06 08:58:41 PM PDT 24 |
| Finished | Aug 06 08:59:58 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-00668aca-2e0b-4cfe-9854-1adfba3538f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118012860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .4118012860 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.4051110645 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 2716738848 ps |
| CPU time | 48.73 seconds |
| Started | Aug 06 08:58:38 PM PDT 24 |
| Finished | Aug 06 08:59:27 PM PDT 24 |
| Peak memory | 573820 kb |
| Host | smart-2aee9483-8a68-4a99-adcd-6f37b88449b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4051110645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_ device_slow_rsp.4051110645 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.878455936 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 1277604676 ps |
| CPU time | 51.38 seconds |
| Started | Aug 06 08:58:43 PM PDT 24 |
| Finished | Aug 06 08:59:35 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-dd461b28-8f67-48cc-bace-d2b619f65f05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878455936 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_addr .878455936 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1359394629 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 341256901 ps |
| CPU time | 30.48 seconds |
| Started | Aug 06 08:58:44 PM PDT 24 |
| Finished | Aug 06 08:59:15 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-46a667cb-3fe7-4b41-a090-90c05c3f0f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359394629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1359394629 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.1228505064 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 408916859 ps |
| CPU time | 38.52 seconds |
| Started | Aug 06 08:58:51 PM PDT 24 |
| Finished | Aug 06 08:59:29 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-5d51917a-895f-4513-9192-a4648a90e7fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228505064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.1228505064 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.1996579745 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 104200769532 ps |
| CPU time | 1059.42 seconds |
| Started | Aug 06 08:58:39 PM PDT 24 |
| Finished | Aug 06 09:16:19 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-3efee70b-8dfd-42a3-80d5-a5a15fbbba95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996579745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.1996579745 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.4222360110 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 61546192280 ps |
| CPU time | 1157.01 seconds |
| Started | Aug 06 08:58:40 PM PDT 24 |
| Finished | Aug 06 09:17:57 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-7516691a-43df-48ad-8bef-dca566513fe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222360110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.4222360110 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.3871296842 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 287124473 ps |
| CPU time | 25.53 seconds |
| Started | Aug 06 08:58:50 PM PDT 24 |
| Finished | Aug 06 08:59:16 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-2d8c0d50-3f2d-49ae-8c64-dfcbc71122c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3871296842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.3871296842 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.3767877645 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2446890388 ps |
| CPU time | 79.43 seconds |
| Started | Aug 06 08:58:44 PM PDT 24 |
| Finished | Aug 06 09:00:04 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-6a886ab2-5f80-4191-a3c3-9dd58f2b005e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767877645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.3767877645 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.4139302523 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 265532694 ps |
| CPU time | 10.74 seconds |
| Started | Aug 06 08:58:37 PM PDT 24 |
| Finished | Aug 06 08:58:47 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-09500a2f-d3f4-48d8-ba94-345a87388348 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139302523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.4139302523 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.3248343983 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 6433211901 ps |
| CPU time | 73.56 seconds |
| Started | Aug 06 08:58:50 PM PDT 24 |
| Finished | Aug 06 09:00:04 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-df3be07a-60e7-4616-973b-d02e22583efe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248343983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.3248343983 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2013792767 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 5372255462 ps |
| CPU time | 96.1 seconds |
| Started | Aug 06 08:58:36 PM PDT 24 |
| Finished | Aug 06 09:00:12 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-e2ca1300-6042-48e5-a3d3-883f2e9e29a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013792767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2013792767 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.2246756983 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 40924317 ps |
| CPU time | 6.2 seconds |
| Started | Aug 06 08:58:49 PM PDT 24 |
| Finished | Aug 06 08:58:56 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-434033a4-a5c4-42f1-bbe2-d12578c14ee8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246756983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delay s.2246756983 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.622083095 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 734523950 ps |
| CPU time | 90.18 seconds |
| Started | Aug 06 08:58:51 PM PDT 24 |
| Finished | Aug 06 09:00:21 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-a5ba7129-3dc4-45d6-8e31-9f9c05487c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622083095 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.622083095 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.4178921316 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 1640997723 ps |
| CPU time | 130.62 seconds |
| Started | Aug 06 08:58:52 PM PDT 24 |
| Finished | Aug 06 09:01:02 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-bc696782-092d-4ebc-863d-88cf7dca0683 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178921316 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.4178921316 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.1451814711 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 11568911079 ps |
| CPU time | 460.23 seconds |
| Started | Aug 06 08:58:45 PM PDT 24 |
| Finished | Aug 06 09:06:26 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-aeee7441-268c-46ac-b1f2-a7b78f1a31ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451814711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.1451814711 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.2633551937 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 592816301 ps |
| CPU time | 120.9 seconds |
| Started | Aug 06 08:58:52 PM PDT 24 |
| Finished | Aug 06 09:00:52 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-0712c125-c67e-460a-992e-05a05e9a8892 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633551937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_al l_with_reset_error.2633551937 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.3824038577 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 213335568 ps |
| CPU time | 12.67 seconds |
| Started | Aug 06 08:58:51 PM PDT 24 |
| Finished | Aug 06 08:59:04 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-f8132f12-0b40-4e60-84e0-e0ad2fff7e95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824038577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.3824038577 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.1289941963 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 355542831 ps |
| CPU time | 38.64 seconds |
| Started | Aug 06 08:58:49 PM PDT 24 |
| Finished | Aug 06 08:59:28 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-941a4c08-55ab-458e-8406-7b80da8ed092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289941963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .1289941963 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.339052853 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 10473143384 ps |
| CPU time | 180.72 seconds |
| Started | Aug 06 08:58:55 PM PDT 24 |
| Finished | Aug 06 09:01:56 PM PDT 24 |
| Peak memory | 573840 kb |
| Host | smart-2d8e88fc-268a-46f2-a35c-42b4daef43d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339052853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_d evice_slow_rsp.339052853 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2357979020 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 1299178048 ps |
| CPU time | 57.79 seconds |
| Started | Aug 06 08:58:58 PM PDT 24 |
| Finished | Aug 06 08:59:56 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-7fd9c78d-a158-4f49-a933-8ef607a85749 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357979020 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.2357979020 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.4141755034 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 524496598 ps |
| CPU time | 45.59 seconds |
| Started | Aug 06 08:58:55 PM PDT 24 |
| Finished | Aug 06 08:59:40 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-ce61d0c8-7453-4493-a25b-55ac95f23b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141755034 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.4141755034 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.3465874920 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 1628549427 ps |
| CPU time | 65.59 seconds |
| Started | Aug 06 08:58:50 PM PDT 24 |
| Finished | Aug 06 08:59:55 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-9615fe98-4b51-42a1-8ef3-7b56e0452153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465874920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.3465874920 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.1684826682 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 98914718199 ps |
| CPU time | 1035.99 seconds |
| Started | Aug 06 08:58:50 PM PDT 24 |
| Finished | Aug 06 09:16:06 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-e134ecca-8bfd-4861-bee5-dada6f1e0b22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684826682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.1684826682 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.1025851919 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 15101258686 ps |
| CPU time | 285.16 seconds |
| Started | Aug 06 08:58:51 PM PDT 24 |
| Finished | Aug 06 09:03:37 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-187b41d1-4134-4f0b-9ed1-6d731cb0f99b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025851919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.1025851919 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.1842386047 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 124468372 ps |
| CPU time | 15.04 seconds |
| Started | Aug 06 08:58:49 PM PDT 24 |
| Finished | Aug 06 08:59:04 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-7b6563ae-f261-467a-b6ec-c8dec515ed64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842386047 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_del ays.1842386047 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.1490208187 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 2720591860 ps |
| CPU time | 85.42 seconds |
| Started | Aug 06 08:58:55 PM PDT 24 |
| Finished | Aug 06 09:00:20 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4c123da6-b0d5-4ceb-9d1d-4ecf665358dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490208187 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.1490208187 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.3206409730 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 178596388 ps |
| CPU time | 9.04 seconds |
| Started | Aug 06 08:58:47 PM PDT 24 |
| Finished | Aug 06 08:58:56 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-73586c01-4a52-4ffd-ab33-be826bd06777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206409730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.3206409730 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.2963354734 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 9096636088 ps |
| CPU time | 94.66 seconds |
| Started | Aug 06 08:58:46 PM PDT 24 |
| Finished | Aug 06 09:00:20 PM PDT 24 |
| Peak memory | 574560 kb |
| Host | smart-70181f73-a4c1-4fd6-9607-b1c9f291d5c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963354734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.2963354734 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.2565342981 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 4869567313 ps |
| CPU time | 87.35 seconds |
| Started | Aug 06 08:58:49 PM PDT 24 |
| Finished | Aug 06 09:00:17 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-2266420b-7d97-4734-923e-3c680674b1e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565342981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.2565342981 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1422005599 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 48685688 ps |
| CPU time | 6.98 seconds |
| Started | Aug 06 08:58:44 PM PDT 24 |
| Finished | Aug 06 08:58:51 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-919a58a6-b8bf-4422-9de8-f048a5d35718 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422005599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.1422005599 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.2146044510 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 6937393051 ps |
| CPU time | 304.28 seconds |
| Started | Aug 06 08:58:57 PM PDT 24 |
| Finished | Aug 06 09:04:01 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-5a81f402-bba0-448e-be7b-1817b7c09229 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146044510 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.2146044510 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.1729264259 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 1109957060 ps |
| CPU time | 83.09 seconds |
| Started | Aug 06 08:58:55 PM PDT 24 |
| Finished | Aug 06 09:00:18 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-d97b3de5-f78b-40af-959e-b6a3e0621401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729264259 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.1729264259 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.4215711222 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 535002150 ps |
| CPU time | 145.09 seconds |
| Started | Aug 06 08:58:54 PM PDT 24 |
| Finished | Aug 06 09:01:19 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-91abf013-7c12-48c4-956f-1fc2f24f6d24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215711222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.4215711222 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.906116630 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 3816619976 ps |
| CPU time | 428.98 seconds |
| Started | Aug 06 08:58:59 PM PDT 24 |
| Finished | Aug 06 09:06:09 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-66de977b-a537-4b2d-8a48-041bb714911b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=906116630 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_reset_error.906116630 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.127685670 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 222822099 ps |
| CPU time | 11.93 seconds |
| Started | Aug 06 08:58:55 PM PDT 24 |
| Finished | Aug 06 08:59:07 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-24b95f66-fba7-416b-8bb2-29bdd35fe41d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127685670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.127685670 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.797641996 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 749969922 ps |
| CPU time | 70.83 seconds |
| Started | Aug 06 08:59:04 PM PDT 24 |
| Finished | Aug 06 09:00:14 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-f5601a6a-31bb-48cf-83a9-361f5d5b6c16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797641996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device. 797641996 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.136993901 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 65024668558 ps |
| CPU time | 1199.27 seconds |
| Started | Aug 06 08:59:00 PM PDT 24 |
| Finished | Aug 06 09:18:59 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-df265d7c-39e6-4ee7-9d0e-26d2e5155ca6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136993901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d evice_slow_rsp.136993901 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1898012077 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 616727439 ps |
| CPU time | 32.37 seconds |
| Started | Aug 06 08:58:58 PM PDT 24 |
| Finished | Aug 06 08:59:31 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-eadc299b-8b61-4884-ab85-e7d921fcf42e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898012077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1898012077 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.3553362718 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 2477497712 ps |
| CPU time | 99.12 seconds |
| Started | Aug 06 08:59:00 PM PDT 24 |
| Finished | Aug 06 09:00:40 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-05dd28fd-0061-4de1-83af-eeb9ff5b5a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553362718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.3553362718 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.1762969782 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 307290419 ps |
| CPU time | 33.19 seconds |
| Started | Aug 06 08:59:05 PM PDT 24 |
| Finished | Aug 06 08:59:39 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f7565f4b-0b06-42bb-9712-1d84cc2c233b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762969782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.1762969782 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.3575891376 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 33505368658 ps |
| CPU time | 341.06 seconds |
| Started | Aug 06 08:59:01 PM PDT 24 |
| Finished | Aug 06 09:04:42 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-c69a498b-e4a5-49a3-850e-e54807ac7be0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575891376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.3575891376 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.3444324050 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 20072631836 ps |
| CPU time | 361.5 seconds |
| Started | Aug 06 08:59:03 PM PDT 24 |
| Finished | Aug 06 09:05:05 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-e3544495-28e0-456f-b06f-cc861dfbc5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444324050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.3444324050 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2691600407 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 437294950 ps |
| CPU time | 46.33 seconds |
| Started | Aug 06 08:59:04 PM PDT 24 |
| Finished | Aug 06 08:59:50 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-03e4a9ac-473d-4bf4-a92e-1e654da57e10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691600407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_del ays.2691600407 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.481414578 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 1171614513 ps |
| CPU time | 36.43 seconds |
| Started | Aug 06 08:59:00 PM PDT 24 |
| Finished | Aug 06 08:59:36 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-45957ad6-d13b-4147-964a-86450b9e8905 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481414578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.481414578 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.3597815084 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 212588828 ps |
| CPU time | 9.79 seconds |
| Started | Aug 06 08:58:55 PM PDT 24 |
| Finished | Aug 06 08:59:05 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-9e65f7a8-659a-47a3-97aa-34c7c3ee24aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597815084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3597815084 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.114202956 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 8181062901 ps |
| CPU time | 82.55 seconds |
| Started | Aug 06 08:59:02 PM PDT 24 |
| Finished | Aug 06 09:00:25 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-74235657-e2cb-4f34-94d9-6f452180b198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114202956 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.114202956 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.4226469647 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 3311909228 ps |
| CPU time | 55.8 seconds |
| Started | Aug 06 08:59:01 PM PDT 24 |
| Finished | Aug 06 08:59:57 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-65482878-6232-4b3d-9b13-10036669a653 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4226469647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.4226469647 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.346018567 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 50422994 ps |
| CPU time | 7.29 seconds |
| Started | Aug 06 08:59:04 PM PDT 24 |
| Finished | Aug 06 08:59:11 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-b2a91745-ef1d-43d6-85a0-4473fe6d531e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346018567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delays .346018567 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.3729244893 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 2406910711 ps |
| CPU time | 178.16 seconds |
| Started | Aug 06 08:59:01 PM PDT 24 |
| Finished | Aug 06 09:01:59 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-3dca1d79-914f-4e36-b2ed-09881205deee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729244893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.3729244893 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.1542600092 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 277957239 ps |
| CPU time | 12.07 seconds |
| Started | Aug 06 08:59:07 PM PDT 24 |
| Finished | Aug 06 08:59:19 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-2c603148-e3ab-46ff-a9fa-d970a525d497 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542600092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.1542600092 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.1338341938 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 716364316 ps |
| CPU time | 314.03 seconds |
| Started | Aug 06 08:59:06 PM PDT 24 |
| Finished | Aug 06 09:04:21 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-9fe81dcb-dac5-43c7-97fe-c3094b599063 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338341938 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.1338341938 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3299860603 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 400260639 ps |
| CPU time | 176.16 seconds |
| Started | Aug 06 08:59:06 PM PDT 24 |
| Finished | Aug 06 09:02:03 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-717277b5-988c-4a15-8359-beb70e8c6850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3299860603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.3299860603 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.2568346307 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 630770236 ps |
| CPU time | 29.58 seconds |
| Started | Aug 06 08:59:02 PM PDT 24 |
| Finished | Aug 06 08:59:32 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-2cbd71a2-a918-48d7-8d3c-e348ef416214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568346307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.2568346307 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.3525950742 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 893296658 ps |
| CPU time | 77.09 seconds |
| Started | Aug 06 08:59:11 PM PDT 24 |
| Finished | Aug 06 09:00:28 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-6636fcd7-f898-4b0a-aca7-844699c39589 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525950742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .3525950742 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.2124204523 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 45556373767 ps |
| CPU time | 830.85 seconds |
| Started | Aug 06 08:59:12 PM PDT 24 |
| Finished | Aug 06 09:13:03 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-7e6de81e-e659-4f34-8b1a-12b34d580fc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124204523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.2124204523 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.1774450668 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 116072279 ps |
| CPU time | 16.4 seconds |
| Started | Aug 06 08:59:16 PM PDT 24 |
| Finished | Aug 06 08:59:32 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-4ec2c0ed-7dbd-4b98-afdf-782df7847902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774450668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.1774450668 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.2425558308 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 1169499299 ps |
| CPU time | 45.64 seconds |
| Started | Aug 06 08:59:12 PM PDT 24 |
| Finished | Aug 06 08:59:58 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-1fd8265f-9b95-4ab7-bf82-fe8473082883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425558308 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.2425558308 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.917509166 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 1416347856 ps |
| CPU time | 58.96 seconds |
| Started | Aug 06 08:59:06 PM PDT 24 |
| Finished | Aug 06 09:00:05 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-9e868abe-f311-431d-ae0d-a07051f34e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=917509166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.917509166 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.4032187136 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 33172631060 ps |
| CPU time | 388.59 seconds |
| Started | Aug 06 08:59:07 PM PDT 24 |
| Finished | Aug 06 09:05:35 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-c0f38dea-7582-4620-803c-7c2ef084c62f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032187136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.4032187136 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.1441624083 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 23817609074 ps |
| CPU time | 406.96 seconds |
| Started | Aug 06 08:59:14 PM PDT 24 |
| Finished | Aug 06 09:06:01 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-fe956dc3-4a97-4bd4-b720-8c41bbdbcec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441624083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.1441624083 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.632331798 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 593422106 ps |
| CPU time | 58.36 seconds |
| Started | Aug 06 08:59:06 PM PDT 24 |
| Finished | Aug 06 09:00:05 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-2279ed49-9db2-4721-881d-c60997766704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632331798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_dela ys.632331798 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.379221605 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 493936543 ps |
| CPU time | 41.02 seconds |
| Started | Aug 06 08:59:13 PM PDT 24 |
| Finished | Aug 06 08:59:54 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-71fb32a2-eb3d-431c-abdd-7691051f4b97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379221605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.379221605 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.484485343 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 42503322 ps |
| CPU time | 6.84 seconds |
| Started | Aug 06 08:59:07 PM PDT 24 |
| Finished | Aug 06 08:59:14 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-fe9978a4-d68e-4cde-892c-d64bbf352f0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484485343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.484485343 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.3980944952 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 7963575862 ps |
| CPU time | 82.94 seconds |
| Started | Aug 06 08:59:05 PM PDT 24 |
| Finished | Aug 06 09:00:28 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-ce915343-c487-43ac-813a-19f7831a95a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980944952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.3980944952 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.459707393 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 4479827035 ps |
| CPU time | 80.83 seconds |
| Started | Aug 06 08:59:06 PM PDT 24 |
| Finished | Aug 06 09:00:27 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-207b254f-89f1-4704-99ac-bc87cea8a431 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459707393 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.459707393 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.1902494723 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 55683071 ps |
| CPU time | 7.49 seconds |
| Started | Aug 06 08:59:04 PM PDT 24 |
| Finished | Aug 06 08:59:12 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-02237239-e575-42c7-88fd-d53b94faa3ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902494723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delay s.1902494723 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.3121483823 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 4108656809 ps |
| CPU time | 407.1 seconds |
| Started | Aug 06 08:59:14 PM PDT 24 |
| Finished | Aug 06 09:06:01 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-3f517e41-32b1-4d1c-b245-7ccdb2b8e5ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121483823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.3121483823 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3863660059 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 1905075093 ps |
| CPU time | 65.91 seconds |
| Started | Aug 06 08:59:19 PM PDT 24 |
| Finished | Aug 06 09:00:25 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-f972e33e-412c-4621-964b-140d0dfc999b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863660059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.3863660059 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3079472895 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 105807465 ps |
| CPU time | 43.89 seconds |
| Started | Aug 06 08:59:17 PM PDT 24 |
| Finished | Aug 06 09:00:01 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-5e6a4021-9f86-4703-90ee-7422d42ef401 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079472895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.3079472895 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.477706381 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 1167960146 ps |
| CPU time | 53.29 seconds |
| Started | Aug 06 08:59:11 PM PDT 24 |
| Finished | Aug 06 09:00:05 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-830c4862-7dd4-494e-94fd-50bcc6793f2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477706381 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.477706381 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.2150270420 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 1789753103 ps |
| CPU time | 81.6 seconds |
| Started | Aug 06 08:59:17 PM PDT 24 |
| Finished | Aug 06 09:00:39 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-4e2850cc-e1f8-4e3b-b748-3eaf6a9fcb22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150270420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device .2150270420 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3514876574 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 86042701512 ps |
| CPU time | 1559.2 seconds |
| Started | Aug 06 08:59:23 PM PDT 24 |
| Finished | Aug 06 09:25:22 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-381b0d8a-a31b-4313-afa7-6662bad8be35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514876574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3514876574 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.1940859417 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 1153376118 ps |
| CPU time | 46.72 seconds |
| Started | Aug 06 08:59:20 PM PDT 24 |
| Finished | Aug 06 09:00:07 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-027fd729-394d-4c59-ad55-bb3a60520e60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940859417 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.1940859417 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.3659786791 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 2515073049 ps |
| CPU time | 91.85 seconds |
| Started | Aug 06 08:59:21 PM PDT 24 |
| Finished | Aug 06 09:00:53 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-8f6d04ef-b2f7-469c-bd75-a471ffed4a28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659786791 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.3659786791 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.1011240767 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 1092695099 ps |
| CPU time | 41.03 seconds |
| Started | Aug 06 08:59:17 PM PDT 24 |
| Finished | Aug 06 08:59:58 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-eeda4316-2f45-4146-b4e5-fed89e896d7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011240767 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.1011240767 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1200194950 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 15017702990 ps |
| CPU time | 158.83 seconds |
| Started | Aug 06 08:59:14 PM PDT 24 |
| Finished | Aug 06 09:01:53 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-1ff8c043-7c4f-4cfd-b760-7bbc49212e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200194950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1200194950 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.2195788723 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 12043928433 ps |
| CPU time | 221.29 seconds |
| Started | Aug 06 08:59:19 PM PDT 24 |
| Finished | Aug 06 09:03:01 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-4c7be1b5-ba8f-43b6-8245-e4b4ca84f383 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195788723 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.2195788723 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.1800554544 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 543001466 ps |
| CPU time | 50.5 seconds |
| Started | Aug 06 08:59:17 PM PDT 24 |
| Finished | Aug 06 09:00:07 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-3aa02041-dc1d-4284-851a-bf55a22895ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800554544 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.1800554544 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.2270358983 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 447103855 ps |
| CPU time | 34.99 seconds |
| Started | Aug 06 08:59:22 PM PDT 24 |
| Finished | Aug 06 08:59:57 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-962a422f-51c3-42b2-abc5-f561701a331b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270358983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.2270358983 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.441592509 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 194836138 ps |
| CPU time | 9 seconds |
| Started | Aug 06 08:59:19 PM PDT 24 |
| Finished | Aug 06 08:59:28 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-337543d7-0038-4e34-8a16-812f14f34ef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441592509 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.441592509 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.1944944019 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 9130560895 ps |
| CPU time | 97.3 seconds |
| Started | Aug 06 08:59:16 PM PDT 24 |
| Finished | Aug 06 09:00:53 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-5e72c18f-73ce-43a9-8ade-b78105246b65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944944019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.1944944019 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3837620633 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 5429308814 ps |
| CPU time | 95.52 seconds |
| Started | Aug 06 08:59:17 PM PDT 24 |
| Finished | Aug 06 09:00:53 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-f8ec5ee2-115f-467d-a32a-a7bcccd8aa0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837620633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3837620633 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.574736177 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 44087206 ps |
| CPU time | 6.73 seconds |
| Started | Aug 06 08:59:15 PM PDT 24 |
| Finished | Aug 06 08:59:22 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-9b531f67-cea3-4fbf-a81c-71b97e8de037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574736177 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delays .574736177 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.1039294602 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 1641544549 ps |
| CPU time | 146.71 seconds |
| Started | Aug 06 08:59:21 PM PDT 24 |
| Finished | Aug 06 09:01:48 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-1f7feb62-ea91-4400-8642-d1b39f562767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039294602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.1039294602 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.4025521943 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 16563612408 ps |
| CPU time | 618.18 seconds |
| Started | Aug 06 08:59:26 PM PDT 24 |
| Finished | Aug 06 09:09:44 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-156f82d6-cb38-4a2e-9df7-20d20750c9c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025521943 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.4025521943 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.488511746 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 7646913445 ps |
| CPU time | 508.98 seconds |
| Started | Aug 06 08:59:25 PM PDT 24 |
| Finished | Aug 06 09:07:54 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-6923a949-17d7-49a3-b1a4-89a93b6ff3e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488511746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_ with_rand_reset.488511746 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3300240204 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 8069457058 ps |
| CPU time | 492.23 seconds |
| Started | Aug 06 08:59:26 PM PDT 24 |
| Finished | Aug 06 09:07:38 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-e443291a-ac0b-403c-b1e9-bbd179e055ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300240204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.3300240204 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.35245314 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 969251378 ps |
| CPU time | 47.41 seconds |
| Started | Aug 06 08:59:21 PM PDT 24 |
| Finished | Aug 06 09:00:08 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-43742610-4e55-483f-bc64-7b74a5604018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35245314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.35245314 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.2267857045 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 6517137500 ps |
| CPU time | 473.72 seconds |
| Started | Aug 06 08:46:22 PM PDT 24 |
| Finished | Aug 06 08:54:16 PM PDT 24 |
| Peak memory | 641540 kb |
| Host | smart-4e4324b0-7e2f-49cc-ba0c-f8bda5400055 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2267857045 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.2267857045 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.3497489852 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 3816925474 ps |
| CPU time | 325.36 seconds |
| Started | Aug 06 08:46:27 PM PDT 24 |
| Finished | Aug 06 08:51:52 PM PDT 24 |
| Peak memory | 598276 kb |
| Host | smart-79b5f28e-3405-477a-a220-543559050864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497489852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.3497489852 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3859795959 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 30953988184 ps |
| CPU time | 4356.42 seconds |
| Started | Aug 06 08:45:52 PM PDT 24 |
| Finished | Aug 06 09:58:29 PM PDT 24 |
| Peak memory | 593692 kb |
| Host | smart-7d968cd6-7679-49fd-94f7-3a82e55b3014 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859795959 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3859795959 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.2060411713 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 4778511727 ps |
| CPU time | 323.04 seconds |
| Started | Aug 06 08:45:51 PM PDT 24 |
| Finished | Aug 06 08:51:14 PM PDT 24 |
| Peak memory | 598640 kb |
| Host | smart-87af0f27-ecfb-497c-9259-110536d9c18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060411713 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2060411713 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.404782584 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 888394554 ps |
| CPU time | 37.82 seconds |
| Started | Aug 06 08:45:58 PM PDT 24 |
| Finished | Aug 06 08:46:36 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-37e01dc6-f38b-4e80-8790-bb1a39bc5251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404782584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device.404782584 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.901127429 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 153282489608 ps |
| CPU time | 2657.15 seconds |
| Started | Aug 06 08:46:07 PM PDT 24 |
| Finished | Aug 06 09:30:24 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-9f0c0251-fa5c-4fbc-8566-28e242de3d8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=901127429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_de vice_slow_rsp.901127429 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.3324157284 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 282244094 ps |
| CPU time | 34.68 seconds |
| Started | Aug 06 08:46:14 PM PDT 24 |
| Finished | Aug 06 08:46:49 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-474d9b7f-0fa6-43ec-a508-6fbdb024570b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324157284 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr .3324157284 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.665215608 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 377221940 ps |
| CPU time | 36.06 seconds |
| Started | Aug 06 08:46:13 PM PDT 24 |
| Finished | Aug 06 08:46:49 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-265e71d3-2987-4830-b9e1-14cb09e784eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665215608 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.665215608 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.1574120489 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 235231611 ps |
| CPU time | 12.06 seconds |
| Started | Aug 06 08:45:51 PM PDT 24 |
| Finished | Aug 06 08:46:03 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-36c366df-a1b6-424c-a381-3cf1a7372a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574120489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.1574120489 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.1888423584 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 74391973154 ps |
| CPU time | 797.16 seconds |
| Started | Aug 06 08:45:58 PM PDT 24 |
| Finished | Aug 06 08:59:15 PM PDT 24 |
| Peak memory | 576656 kb |
| Host | smart-282defd1-749b-4ed2-abc7-ccecdee21269 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888423584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.1888423584 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.3952102248 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 2990016885 ps |
| CPU time | 54.31 seconds |
| Started | Aug 06 08:45:58 PM PDT 24 |
| Finished | Aug 06 08:46:53 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-9444c15a-22e6-4f45-8592-90c0494f55e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952102248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3952102248 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.68253371 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 482815878 ps |
| CPU time | 45.1 seconds |
| Started | Aug 06 08:45:51 PM PDT 24 |
| Finished | Aug 06 08:46:36 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-22f7bffd-fb58-47ff-b335-f9e062d08ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68253371 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_delays .68253371 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.2787179462 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 1201644019 ps |
| CPU time | 40.88 seconds |
| Started | Aug 06 08:46:12 PM PDT 24 |
| Finished | Aug 06 08:46:53 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-38835f2a-a912-4a4a-b293-ceb273808c7a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787179462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.2787179462 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.225913458 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 151626631 ps |
| CPU time | 8.23 seconds |
| Started | Aug 06 08:45:57 PM PDT 24 |
| Finished | Aug 06 08:46:06 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-ca4e17b4-ad17-460a-b9bd-64d82817bdcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225913458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.225913458 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.1904899452 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 5658756859 ps |
| CPU time | 67.04 seconds |
| Started | Aug 06 08:46:14 PM PDT 24 |
| Finished | Aug 06 08:47:21 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-49fa077c-112f-4c13-9452-4a60ea7aa8cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904899452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.1904899452 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1414285860 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 6269971361 ps |
| CPU time | 114.85 seconds |
| Started | Aug 06 08:45:53 PM PDT 24 |
| Finished | Aug 06 08:47:48 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-925cd641-575f-48bb-8c08-a57421952184 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414285860 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.1414285860 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.3181237244 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 44407643 ps |
| CPU time | 6.8 seconds |
| Started | Aug 06 08:45:50 PM PDT 24 |
| Finished | Aug 06 08:45:57 PM PDT 24 |
| Peak memory | 573888 kb |
| Host | smart-afb4a79a-2010-4e69-b220-d4328341eec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181237244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .3181237244 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.3759361709 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 16015451888 ps |
| CPU time | 610.55 seconds |
| Started | Aug 06 08:46:13 PM PDT 24 |
| Finished | Aug 06 08:56:23 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-c9bcebe4-dced-4509-b91b-703452449e20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759361709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.3759361709 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.3075954174 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 7605224479 ps |
| CPU time | 259.21 seconds |
| Started | Aug 06 08:46:17 PM PDT 24 |
| Finished | Aug 06 08:50:36 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-eac54be2-794a-468e-a304-5bbdfad4b5f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075954174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.3075954174 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.1840401973 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 8137624781 ps |
| CPU time | 458.3 seconds |
| Started | Aug 06 08:46:19 PM PDT 24 |
| Finished | Aug 06 08:53:57 PM PDT 24 |
| Peak memory | 576692 kb |
| Host | smart-14ff4fba-c9b6-4ca9-b006-e21c07a6ca58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840401973 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.1840401973 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.3265094397 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 496992448 ps |
| CPU time | 22.86 seconds |
| Started | Aug 06 08:46:15 PM PDT 24 |
| Finished | Aug 06 08:46:38 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-69a4bed9-55ce-4747-acd9-b992ef65f0f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265094397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.3265094397 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.1556651761 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 2945104413 ps |
| CPU time | 118.3 seconds |
| Started | Aug 06 08:59:31 PM PDT 24 |
| Finished | Aug 06 09:01:29 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-f979dc14-3d09-4f9a-867f-9ef700b313c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1556651761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device .1556651761 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.4010772083 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 150943538924 ps |
| CPU time | 2755.66 seconds |
| Started | Aug 06 08:59:31 PM PDT 24 |
| Finished | Aug 06 09:45:27 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-e061ed4e-530c-48f4-a9e2-8682200d03e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010772083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_ device_slow_rsp.4010772083 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.1915728678 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 726025369 ps |
| CPU time | 37.89 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:00:10 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-9ee1a8a7-7638-4077-8649-5d1a48b696b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915728678 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.1915728678 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.3632437780 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 267620160 ps |
| CPU time | 13.43 seconds |
| Started | Aug 06 08:59:31 PM PDT 24 |
| Finished | Aug 06 08:59:45 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-8c302a7d-c014-43ec-b232-81db0e1a08c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632437780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.3632437780 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.1180687539 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 90285744932 ps |
| CPU time | 973.81 seconds |
| Started | Aug 06 08:59:31 PM PDT 24 |
| Finished | Aug 06 09:15:45 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-0388ffd6-2e12-4af9-bddd-b82d1f4b9fbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1180687539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.1180687539 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1175705010 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 47170115742 ps |
| CPU time | 786 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:12:38 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-e8a82759-6708-4ea3-98a6-8b28b71e38b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175705010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1175705010 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.586397447 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 120432030 ps |
| CPU time | 13.85 seconds |
| Started | Aug 06 08:59:29 PM PDT 24 |
| Finished | Aug 06 08:59:43 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-aaabc8a2-83ce-40fb-a3f8-50d474d32aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586397447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_dela ys.586397447 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.474896966 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 2239196018 ps |
| CPU time | 77.61 seconds |
| Started | Aug 06 08:59:34 PM PDT 24 |
| Finished | Aug 06 09:00:52 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-2307e64d-0cd0-4289-aec9-d0585bf06283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474896966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.474896966 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1236996150 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 41499112 ps |
| CPU time | 6.24 seconds |
| Started | Aug 06 08:59:25 PM PDT 24 |
| Finished | Aug 06 08:59:31 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-49c5d91f-0655-435a-9314-f7001b7ded15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236996150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1236996150 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.3401192624 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 9629759045 ps |
| CPU time | 102.02 seconds |
| Started | Aug 06 08:59:26 PM PDT 24 |
| Finished | Aug 06 09:01:08 PM PDT 24 |
| Peak memory | 574512 kb |
| Host | smart-88ca49cd-d8a4-4488-b84f-4eeee95256fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3401192624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.3401192624 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2600644474 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 6177493771 ps |
| CPU time | 106.1 seconds |
| Started | Aug 06 08:59:29 PM PDT 24 |
| Finished | Aug 06 09:01:15 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-3ca8cc63-6911-45b9-9682-fb6a72bfed57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600644474 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.2600644474 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.3714330745 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 38625715 ps |
| CPU time | 6.31 seconds |
| Started | Aug 06 08:59:27 PM PDT 24 |
| Finished | Aug 06 08:59:34 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-b9963934-21ee-4d16-b036-b6d9847472fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714330745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delay s.3714330745 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.2217803714 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 3028833051 ps |
| CPU time | 227.84 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:03:20 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-e0aa1d11-c875-48af-848b-451be5a1d0e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217803714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.2217803714 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.1006173661 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 905913539 ps |
| CPU time | 80.52 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:00:53 PM PDT 24 |
| Peak memory | 575964 kb |
| Host | smart-59fd7fce-6918-4fb7-814f-a71ac332ea90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006173661 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.1006173661 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.235297711 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 12050499390 ps |
| CPU time | 730.29 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:11:43 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-028d3167-5fb5-4d3a-99dd-63eb30e1d995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235297711 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.235297711 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.416670888 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 15012498509 ps |
| CPU time | 804.44 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:12:56 PM PDT 24 |
| Peak memory | 578712 kb |
| Host | smart-f0053267-93e8-4896-a708-1ca1e3b7d8b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416670888 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all _with_reset_error.416670888 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.4010628707 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 1312215760 ps |
| CPU time | 58.48 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:00:31 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-491e91ee-79de-4be6-b6db-cc1a62c9b03e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010628707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.4010628707 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.4195188601 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 381015933 ps |
| CPU time | 29.16 seconds |
| Started | Aug 06 08:59:37 PM PDT 24 |
| Finished | Aug 06 09:00:06 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-2cc16914-6e6f-47b7-aa4b-600e5325e2d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195188601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .4195188601 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2007098483 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 76497023033 ps |
| CPU time | 1288.54 seconds |
| Started | Aug 06 08:59:35 PM PDT 24 |
| Finished | Aug 06 09:21:04 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-11586e69-1178-4e41-a8db-ecc7caf871e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2007098483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.2007098483 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.1844368999 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 187795340 ps |
| CPU time | 11.14 seconds |
| Started | Aug 06 08:59:41 PM PDT 24 |
| Finished | Aug 06 08:59:53 PM PDT 24 |
| Peak memory | 574368 kb |
| Host | smart-00fb4543-546e-4d8b-82e8-28141fae488c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844368999 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.1844368999 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.68285666 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 798425682 ps |
| CPU time | 32.53 seconds |
| Started | Aug 06 08:59:36 PM PDT 24 |
| Finished | Aug 06 09:00:09 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-9857c336-b254-419a-870c-9c1a2ba75a60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68285666 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.68285666 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.383507698 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 312307448 ps |
| CPU time | 15.01 seconds |
| Started | Aug 06 08:59:31 PM PDT 24 |
| Finished | Aug 06 08:59:46 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-aa8f940a-8100-49aa-9a3a-84e7869433fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383507698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.383507698 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.567731858 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 19664876153 ps |
| CPU time | 212.32 seconds |
| Started | Aug 06 08:59:39 PM PDT 24 |
| Finished | Aug 06 09:03:11 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-cafa3218-a02b-4637-b6c5-786e1223e288 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567731858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.567731858 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.1220988394 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 24690603097 ps |
| CPU time | 445.86 seconds |
| Started | Aug 06 08:59:36 PM PDT 24 |
| Finished | Aug 06 09:07:02 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-4bbc2de7-806c-436b-bd73-50a052dbe446 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220988394 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.1220988394 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.3801400320 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 259439730 ps |
| CPU time | 29.04 seconds |
| Started | Aug 06 08:59:33 PM PDT 24 |
| Finished | Aug 06 09:00:03 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-8409bf2e-3968-46c8-aa9a-6817d8e889ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801400320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.3801400320 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.117299066 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 1478088826 ps |
| CPU time | 47.88 seconds |
| Started | Aug 06 08:59:36 PM PDT 24 |
| Finished | Aug 06 09:00:24 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-c2268055-53b8-4842-ac8f-ea62d25435fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117299066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.117299066 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.2746934191 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 199794599 ps |
| CPU time | 9.68 seconds |
| Started | Aug 06 08:59:31 PM PDT 24 |
| Finished | Aug 06 08:59:41 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-a68bd8ec-024e-412f-aefb-28d8a4ede49c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746934191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.2746934191 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.1032379227 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 10162228609 ps |
| CPU time | 105.63 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:01:18 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-7bd4a8b7-bce6-45f9-94c9-cb755564d258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032379227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.1032379227 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.3635915283 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 4719063585 ps |
| CPU time | 85.05 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 09:00:57 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-cf627cff-2139-4fbe-871f-568d15fa2f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635915283 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.3635915283 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.1410335852 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 39245010 ps |
| CPU time | 6.34 seconds |
| Started | Aug 06 08:59:32 PM PDT 24 |
| Finished | Aug 06 08:59:38 PM PDT 24 |
| Peak memory | 573632 kb |
| Host | smart-9ccfa80f-cf37-44cc-ba20-c8d175a01530 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410335852 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.1410335852 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.1932186900 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 9993509107 ps |
| CPU time | 352.75 seconds |
| Started | Aug 06 08:59:41 PM PDT 24 |
| Finished | Aug 06 09:05:33 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-29640e12-c614-4fcf-af0f-5baf0962b2f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932186900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.1932186900 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.3115862257 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 13548544069 ps |
| CPU time | 500.53 seconds |
| Started | Aug 06 08:59:40 PM PDT 24 |
| Finished | Aug 06 09:08:00 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-c62cc0d9-8741-48b8-80ed-62ca88e1e214 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115862257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.3115862257 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3506525508 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 317468123 ps |
| CPU time | 143.69 seconds |
| Started | Aug 06 08:59:41 PM PDT 24 |
| Finished | Aug 06 09:02:05 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-51816521-42d1-4af5-a3bf-a2f09aa0d8e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506525508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.3506525508 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1345529958 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 5701905178 ps |
| CPU time | 252.33 seconds |
| Started | Aug 06 08:59:41 PM PDT 24 |
| Finished | Aug 06 09:03:53 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-01e22299-c965-4998-91f9-5153413a5021 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345529958 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1345529958 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.4272430140 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 116713261 ps |
| CPU time | 16.21 seconds |
| Started | Aug 06 08:59:35 PM PDT 24 |
| Finished | Aug 06 08:59:52 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-8a9fd2e6-4b40-4052-ac42-a90b4f47a077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272430140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.4272430140 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.3031987525 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 1143870256 ps |
| CPU time | 43.47 seconds |
| Started | Aug 06 08:59:50 PM PDT 24 |
| Finished | Aug 06 09:00:33 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-94430d3c-0a65-4c1b-98d8-b952536593b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031987525 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device .3031987525 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.1817477392 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 132225709400 ps |
| CPU time | 2179.76 seconds |
| Started | Aug 06 08:59:45 PM PDT 24 |
| Finished | Aug 06 09:36:05 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-10078142-cce3-40da-8633-a3e33c5a6ca2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817477392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_ device_slow_rsp.1817477392 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.1846640177 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 843403121 ps |
| CPU time | 37.76 seconds |
| Started | Aug 06 08:59:46 PM PDT 24 |
| Finished | Aug 06 09:00:24 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-7a03d349-d4e2-4906-9d27-5bcd18fbd614 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846640177 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_add r.1846640177 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.69690007 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 1388241135 ps |
| CPU time | 51.57 seconds |
| Started | Aug 06 08:59:49 PM PDT 24 |
| Finished | Aug 06 09:00:41 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-f68df28c-9eab-4abc-a26f-935275281aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69690007 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.69690007 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.3693986923 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 343275177 ps |
| CPU time | 35.98 seconds |
| Started | Aug 06 08:59:47 PM PDT 24 |
| Finished | Aug 06 09:00:23 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-3527ce87-efa1-4751-b923-756964a27ec9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693986923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.3693986923 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.1061859999 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 95131842387 ps |
| CPU time | 1030.87 seconds |
| Started | Aug 06 08:59:46 PM PDT 24 |
| Finished | Aug 06 09:16:57 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-9ba9f2fb-ba58-4840-8010-616a225d01cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061859999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.1061859999 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.2802756364 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 23798775369 ps |
| CPU time | 408.38 seconds |
| Started | Aug 06 08:59:50 PM PDT 24 |
| Finished | Aug 06 09:06:38 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-2b37bec6-c875-4df0-bdd6-09a0890c5731 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802756364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.2802756364 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.2429339423 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 595761906 ps |
| CPU time | 54.75 seconds |
| Started | Aug 06 08:59:45 PM PDT 24 |
| Finished | Aug 06 09:00:40 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-ada2f2d2-d107-4cd5-9039-9119bcee3bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429339423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.2429339423 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2573325084 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 514504841 ps |
| CPU time | 43.98 seconds |
| Started | Aug 06 08:59:46 PM PDT 24 |
| Finished | Aug 06 09:00:30 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-8a6dcd84-b801-4434-971b-7af6d200acad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2573325084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2573325084 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.918477029 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 44003020 ps |
| CPU time | 6.49 seconds |
| Started | Aug 06 08:59:40 PM PDT 24 |
| Finished | Aug 06 08:59:47 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-44f3c675-bd90-4745-840e-2deea46ad943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918477029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.918477029 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.1594941613 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 7259604909 ps |
| CPU time | 77.99 seconds |
| Started | Aug 06 08:59:47 PM PDT 24 |
| Finished | Aug 06 09:01:05 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-51f70a4d-1c88-467b-b8d8-022fffd4e102 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594941613 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.1594941613 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1323440720 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 5875789771 ps |
| CPU time | 99.49 seconds |
| Started | Aug 06 08:59:50 PM PDT 24 |
| Finished | Aug 06 09:01:30 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-138f262f-6cbf-4ee0-98ac-8721cc81994b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323440720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1323440720 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.1613544136 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 43177255 ps |
| CPU time | 6.19 seconds |
| Started | Aug 06 08:59:39 PM PDT 24 |
| Finished | Aug 06 08:59:46 PM PDT 24 |
| Peak memory | 574376 kb |
| Host | smart-7151d984-a729-4df1-b94e-dcfe3de9fa0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613544136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.1613544136 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.816724211 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 1118927055 ps |
| CPU time | 98.82 seconds |
| Started | Aug 06 08:59:51 PM PDT 24 |
| Finished | Aug 06 09:01:30 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-dc8c4902-3b67-44ca-bc43-cd56f877fa5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816724211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.816724211 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3628346023 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 8694376154 ps |
| CPU time | 330.45 seconds |
| Started | Aug 06 08:59:51 PM PDT 24 |
| Finished | Aug 06 09:05:22 PM PDT 24 |
| Peak memory | 576136 kb |
| Host | smart-75fec114-fe3a-46be-a4a0-b58f2b987500 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628346023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.3628346023 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.4109873439 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 4576927246 ps |
| CPU time | 745.19 seconds |
| Started | Aug 06 08:59:50 PM PDT 24 |
| Finished | Aug 06 09:12:15 PM PDT 24 |
| Peak memory | 576680 kb |
| Host | smart-2b3f43ce-727c-43bb-a636-a286f61587c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4109873439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.4109873439 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2687245719 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 41750764 ps |
| CPU time | 19.44 seconds |
| Started | Aug 06 08:59:49 PM PDT 24 |
| Finished | Aug 06 09:00:08 PM PDT 24 |
| Peak memory | 573928 kb |
| Host | smart-0949977f-eb3e-4f32-a580-1f2a0ab93eed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687245719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.2687245719 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.938750549 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 53652081 ps |
| CPU time | 9.67 seconds |
| Started | Aug 06 08:59:50 PM PDT 24 |
| Finished | Aug 06 09:00:00 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-573a2a29-c75b-4fde-bea4-f0ca83930fd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938750549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.938750549 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.1308982325 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 1116281530 ps |
| CPU time | 72.29 seconds |
| Started | Aug 06 08:59:56 PM PDT 24 |
| Finished | Aug 06 09:01:08 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-599b8c88-cfc8-44a4-9b1e-132154e3ebe0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308982325 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device .1308982325 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.943111821 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 31115877083 ps |
| CPU time | 549 seconds |
| Started | Aug 06 08:59:56 PM PDT 24 |
| Finished | Aug 06 09:09:05 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-57faede2-d2fa-4b89-a9a5-3617429c22dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943111821 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_d evice_slow_rsp.943111821 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3456656206 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 268152242 ps |
| CPU time | 33.48 seconds |
| Started | Aug 06 08:59:57 PM PDT 24 |
| Finished | Aug 06 09:00:31 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-a54cebd0-0856-47a5-adca-7fda91c7c4aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456656206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3456656206 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.1518084729 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 2586293504 ps |
| CPU time | 94.11 seconds |
| Started | Aug 06 08:59:59 PM PDT 24 |
| Finished | Aug 06 09:01:33 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-c79bba05-e1ce-410b-9e17-9efaee489885 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518084729 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.1518084729 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.2081002926 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 1643815022 ps |
| CPU time | 67 seconds |
| Started | Aug 06 08:59:50 PM PDT 24 |
| Finished | Aug 06 09:00:57 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-33de91d3-a942-419f-83c4-a15cab7b1bc6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081002926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.2081002926 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.3896272472 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 92912228830 ps |
| CPU time | 992.25 seconds |
| Started | Aug 06 08:59:57 PM PDT 24 |
| Finished | Aug 06 09:16:29 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-36d46fee-03da-4ea2-9e7b-2f062591a3f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896272472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.3896272472 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1033818537 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 20431012176 ps |
| CPU time | 383.12 seconds |
| Started | Aug 06 08:59:58 PM PDT 24 |
| Finished | Aug 06 09:06:21 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-988b9b1b-11f0-43dd-98b8-aaef0298d1b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1033818537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.1033818537 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.1370766101 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 92131131 ps |
| CPU time | 12.65 seconds |
| Started | Aug 06 08:59:52 PM PDT 24 |
| Finished | Aug 06 09:00:04 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-84c5a922-e91f-48c3-8813-8f522734a3ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370766101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_del ays.1370766101 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.4032476833 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 206255253 ps |
| CPU time | 9.84 seconds |
| Started | Aug 06 08:59:56 PM PDT 24 |
| Finished | Aug 06 09:00:06 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-b9c6df19-c959-434a-914c-659f75cf99b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032476833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.4032476833 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.4283152326 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 205976232 ps |
| CPU time | 9.16 seconds |
| Started | Aug 06 08:59:54 PM PDT 24 |
| Finished | Aug 06 09:00:03 PM PDT 24 |
| Peak memory | 573784 kb |
| Host | smart-49bc5880-7c16-44bc-a3b5-f488b033b15d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283152326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.4283152326 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.2324591202 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 9318517250 ps |
| CPU time | 99.16 seconds |
| Started | Aug 06 08:59:51 PM PDT 24 |
| Finished | Aug 06 09:01:30 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-8c3e11fe-8bf9-4c20-b8b8-f7c7974ff7b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324591202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.2324591202 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2783882988 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 6707120648 ps |
| CPU time | 123.6 seconds |
| Started | Aug 06 08:59:53 PM PDT 24 |
| Finished | Aug 06 09:01:57 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-b8941d5f-a820-4d3b-bb07-16cbf430e539 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783882988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2783882988 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.845996247 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 44710137 ps |
| CPU time | 6.4 seconds |
| Started | Aug 06 08:59:54 PM PDT 24 |
| Finished | Aug 06 09:00:01 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-1e9e303b-d0e2-4eae-9f09-8856c6ceab25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=845996247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .845996247 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.2594020055 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 2783278075 ps |
| CPU time | 258.63 seconds |
| Started | Aug 06 08:59:56 PM PDT 24 |
| Finished | Aug 06 09:04:15 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-32a5d308-4f2d-43f8-ac96-13ae74fa1311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2594020055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.2594020055 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2892081499 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 968541923 ps |
| CPU time | 66.66 seconds |
| Started | Aug 06 08:59:55 PM PDT 24 |
| Finished | Aug 06 09:01:02 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-52e07714-2c36-4e32-b0c8-c489b1c9ef91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892081499 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2892081499 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.3746903258 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 2565823743 ps |
| CPU time | 261.33 seconds |
| Started | Aug 06 09:00:01 PM PDT 24 |
| Finished | Aug 06 09:04:27 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-0b9b691c-4376-4a8b-ba08-0560459039fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3746903258 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_al l_with_reset_error.3746903258 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.686144643 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 1463141203 ps |
| CPU time | 73.75 seconds |
| Started | Aug 06 08:59:55 PM PDT 24 |
| Finished | Aug 06 09:01:08 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-0e4232ce-d5de-423c-8f84-b57afe8e9479 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686144643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.686144643 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.1065603557 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 2627228180 ps |
| CPU time | 93.3 seconds |
| Started | Aug 06 09:00:04 PM PDT 24 |
| Finished | Aug 06 09:01:39 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-6ea59669-4cc4-4b96-aaf6-806e12589408 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065603557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .1065603557 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.4210860600 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 46528534301 ps |
| CPU time | 800.92 seconds |
| Started | Aug 06 09:00:02 PM PDT 24 |
| Finished | Aug 06 09:13:26 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-e45214e6-0ede-478d-a53e-e431bcc162b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210860600 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_ device_slow_rsp.4210860600 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.1094022062 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 171195231 ps |
| CPU time | 18.18 seconds |
| Started | Aug 06 09:00:09 PM PDT 24 |
| Finished | Aug 06 09:00:27 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-23be2f01-ebcb-4d2c-ae55-bda53798773f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094022062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_add r.1094022062 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.339565132 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 504775046 ps |
| CPU time | 22.6 seconds |
| Started | Aug 06 09:00:06 PM PDT 24 |
| Finished | Aug 06 09:00:29 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-7a8da94b-96cd-4de2-8cb1-104efb15ed3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339565132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.339565132 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.1393740215 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 1971998125 ps |
| CPU time | 81.65 seconds |
| Started | Aug 06 09:00:01 PM PDT 24 |
| Finished | Aug 06 09:01:22 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-e295ab65-2ec0-49e9-8f5c-521543245817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393740215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.1393740215 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.3848118920 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 78901862442 ps |
| CPU time | 787.66 seconds |
| Started | Aug 06 09:00:05 PM PDT 24 |
| Finished | Aug 06 09:13:13 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-4f9b5a8f-24fb-48e3-bd94-f982f9c3fbd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848118920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.3848118920 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.2032323516 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 3565985022 ps |
| CPU time | 65.72 seconds |
| Started | Aug 06 09:00:03 PM PDT 24 |
| Finished | Aug 06 09:01:11 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-522029f8-83ae-4345-82d9-e6faa3e153d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032323516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.2032323516 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.3854318714 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 431630392 ps |
| CPU time | 45.19 seconds |
| Started | Aug 06 09:00:00 PM PDT 24 |
| Finished | Aug 06 09:00:46 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-2ddedc4d-0b78-44b8-a251-1ca14adf0ecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854318714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.3854318714 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.171089957 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 311649087 ps |
| CPU time | 27.75 seconds |
| Started | Aug 06 09:00:01 PM PDT 24 |
| Finished | Aug 06 09:00:28 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-624e4a86-06bd-46ae-a074-3257b7b02b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171089957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.171089957 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.3030865104 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 164555625 ps |
| CPU time | 8.44 seconds |
| Started | Aug 06 09:00:01 PM PDT 24 |
| Finished | Aug 06 09:00:14 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-5df5f159-62ca-477c-a1df-d36c9aabe945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030865104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.3030865104 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.3487907257 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 8011392834 ps |
| CPU time | 84.15 seconds |
| Started | Aug 06 09:00:03 PM PDT 24 |
| Finished | Aug 06 09:01:29 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-4041a575-c293-4743-99a2-1000f0566c94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487907257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.3487907257 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2465556180 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 5483880698 ps |
| CPU time | 90.58 seconds |
| Started | Aug 06 09:00:05 PM PDT 24 |
| Finished | Aug 06 09:01:36 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-83e77e41-7a5d-4106-8635-fe98b4e6f6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465556180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2465556180 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.273840721 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 42582032 ps |
| CPU time | 5.79 seconds |
| Started | Aug 06 09:00:04 PM PDT 24 |
| Finished | Aug 06 09:00:11 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-2235e9db-fc05-4770-9aad-09f6143b6622 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273840721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .273840721 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.3373869502 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 12179284659 ps |
| CPU time | 584.81 seconds |
| Started | Aug 06 09:00:06 PM PDT 24 |
| Finished | Aug 06 09:09:51 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-17b23c8d-de4a-4ee9-a8c1-f0cdd648366d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373869502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.3373869502 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.1661405126 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 6476511639 ps |
| CPU time | 231.35 seconds |
| Started | Aug 06 09:00:08 PM PDT 24 |
| Finished | Aug 06 09:03:59 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-222d6cca-73aa-451b-b0ea-bd38f4637b59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661405126 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.1661405126 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.2089258322 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 698030704 ps |
| CPU time | 257.44 seconds |
| Started | Aug 06 09:00:07 PM PDT 24 |
| Finished | Aug 06 09:04:24 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-b9b0fa33-61cb-4061-870e-6185b4cabcb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089258322 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_rand_reset.2089258322 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.391359444 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 125925269 ps |
| CPU time | 46.21 seconds |
| Started | Aug 06 09:00:07 PM PDT 24 |
| Finished | Aug 06 09:00:53 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-8bc21447-32ad-4f11-939c-342a50227b06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391359444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_reset_error.391359444 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.1194999645 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 513714399 ps |
| CPU time | 26.97 seconds |
| Started | Aug 06 09:00:06 PM PDT 24 |
| Finished | Aug 06 09:00:33 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-046961ca-d416-4f56-ba76-0c0054ce75d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194999645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.1194999645 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.3236952552 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 1845383434 ps |
| CPU time | 93.64 seconds |
| Started | Aug 06 09:00:16 PM PDT 24 |
| Finished | Aug 06 09:01:49 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-4a4d981c-f01c-4544-88c2-47bde7ec14cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236952552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .3236952552 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2817657602 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 48265292962 ps |
| CPU time | 882.44 seconds |
| Started | Aug 06 09:00:14 PM PDT 24 |
| Finished | Aug 06 09:14:57 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-e8653614-0f14-4467-9145-9575cd34a180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817657602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.2817657602 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.314980243 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 102006378 ps |
| CPU time | 12.72 seconds |
| Started | Aug 06 09:00:19 PM PDT 24 |
| Finished | Aug 06 09:00:32 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-9bc8faa1-8160-41b0-bb29-d00ba41009b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314980243 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .314980243 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.2812292003 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 363954666 ps |
| CPU time | 14.94 seconds |
| Started | Aug 06 09:00:14 PM PDT 24 |
| Finished | Aug 06 09:00:29 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-889c1406-d02f-49cc-9f05-fab37c433538 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812292003 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.2812292003 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.2959926533 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 1728849044 ps |
| CPU time | 65.71 seconds |
| Started | Aug 06 09:00:13 PM PDT 24 |
| Finished | Aug 06 09:01:19 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-666e9395-1ee2-4d6f-8fd9-4a010648246e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959926533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.2959926533 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.1780659961 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 4701209931 ps |
| CPU time | 48.73 seconds |
| Started | Aug 06 09:00:14 PM PDT 24 |
| Finished | Aug 06 09:01:03 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-21fa4488-c5c6-4749-bf1c-edfd138f8af7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1780659961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.1780659961 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.722027833 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 65585405401 ps |
| CPU time | 1178.4 seconds |
| Started | Aug 06 09:00:13 PM PDT 24 |
| Finished | Aug 06 09:19:52 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-6546fec7-8458-49f8-820a-000497602874 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722027833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.722027833 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.4056428789 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 243975932 ps |
| CPU time | 23.56 seconds |
| Started | Aug 06 09:00:14 PM PDT 24 |
| Finished | Aug 06 09:00:38 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-391a563a-7683-4978-8aef-95bbae4d6eff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056428789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.4056428789 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.1511412943 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 2127623021 ps |
| CPU time | 59.35 seconds |
| Started | Aug 06 09:00:13 PM PDT 24 |
| Finished | Aug 06 09:01:12 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-26f98b7e-e129-456c-a9b9-1f77753b6316 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511412943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.1511412943 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.1661538546 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 190439823 ps |
| CPU time | 9.52 seconds |
| Started | Aug 06 09:00:12 PM PDT 24 |
| Finished | Aug 06 09:00:21 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-4bf7372e-06a5-45c2-b4b9-523d1cf571c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661538546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.1661538546 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.32165986 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 7991911620 ps |
| CPU time | 83.79 seconds |
| Started | Aug 06 09:00:14 PM PDT 24 |
| Finished | Aug 06 09:01:38 PM PDT 24 |
| Peak memory | 574548 kb |
| Host | smart-88cf13d4-8816-41e9-96f5-9cb20c98ef41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32165986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.32165986 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.2173747675 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 6004229701 ps |
| CPU time | 108.52 seconds |
| Started | Aug 06 09:00:13 PM PDT 24 |
| Finished | Aug 06 09:02:02 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-a5957408-d157-4887-ab51-293104f5c6a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173747675 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.2173747675 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.184491192 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 42354473 ps |
| CPU time | 6.59 seconds |
| Started | Aug 06 09:00:09 PM PDT 24 |
| Finished | Aug 06 09:00:15 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-a7b59e9c-72ba-41ff-a6b2-4973cefe72ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184491192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delays .184491192 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.1893006493 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 11222390650 ps |
| CPU time | 457.69 seconds |
| Started | Aug 06 09:00:19 PM PDT 24 |
| Finished | Aug 06 09:07:57 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-d62579c2-ba6c-4343-a8cc-0fdca8bf0020 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1893006493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.1893006493 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1488502358 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 1990717831 ps |
| CPU time | 84.73 seconds |
| Started | Aug 06 09:00:18 PM PDT 24 |
| Finished | Aug 06 09:01:43 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-fa82e771-4a7e-4743-809a-056ecb969c42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488502358 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1488502358 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.689008420 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 63392400 ps |
| CPU time | 53.89 seconds |
| Started | Aug 06 09:00:19 PM PDT 24 |
| Finished | Aug 06 09:01:13 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-c25f26a4-d4d1-43ae-b1a5-62eb1e481634 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689008420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_ with_rand_reset.689008420 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.628070270 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 8650737 ps |
| CPU time | 4.8 seconds |
| Started | Aug 06 09:00:17 PM PDT 24 |
| Finished | Aug 06 09:00:22 PM PDT 24 |
| Peak memory | 573744 kb |
| Host | smart-69445707-3a1f-4f11-ba59-353b42a40198 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628070270 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_reset_error.628070270 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.119408594 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 180415166 ps |
| CPU time | 24.86 seconds |
| Started | Aug 06 09:00:19 PM PDT 24 |
| Finished | Aug 06 09:00:44 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-c88e2083-23f6-4861-9aff-d64d67e0a920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119408594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.119408594 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2063367692 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 134552543 ps |
| CPU time | 14.01 seconds |
| Started | Aug 06 09:00:27 PM PDT 24 |
| Finished | Aug 06 09:00:41 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-186a09e8-8659-4bdf-9a0f-c7219fc4771b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063367692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2063367692 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.4149652070 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 81834198590 ps |
| CPU time | 1415.43 seconds |
| Started | Aug 06 09:00:25 PM PDT 24 |
| Finished | Aug 06 09:24:01 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-ea4aefe0-aed0-438d-97f3-66a988100454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149652070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.4149652070 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.3239109215 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 63181436 ps |
| CPU time | 8.7 seconds |
| Started | Aug 06 09:00:31 PM PDT 24 |
| Finished | Aug 06 09:00:40 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f9760d0a-0466-4660-8ce3-92ce9caa63e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3239109215 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_add r.3239109215 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.2771500975 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 1264125765 ps |
| CPU time | 47.26 seconds |
| Started | Aug 06 09:00:29 PM PDT 24 |
| Finished | Aug 06 09:01:16 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-7786cc44-096f-4143-b9f8-956f0ecbc7f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771500975 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.2771500975 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.2119387667 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 881583519 ps |
| CPU time | 35.69 seconds |
| Started | Aug 06 09:00:19 PM PDT 24 |
| Finished | Aug 06 09:00:55 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-e172471e-a29a-414f-9a6f-8e423b6facf2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119387667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.2119387667 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.1225577671 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 44781082724 ps |
| CPU time | 461.51 seconds |
| Started | Aug 06 09:00:26 PM PDT 24 |
| Finished | Aug 06 09:08:08 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-79a2e2f1-5be2-4186-8df0-7da586923f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225577671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.1225577671 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.3622599285 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 43352900490 ps |
| CPU time | 843.92 seconds |
| Started | Aug 06 09:00:25 PM PDT 24 |
| Finished | Aug 06 09:14:29 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-e5e5ab29-834e-4d18-a78e-c94070b3aa4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622599285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.3622599285 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.1298208555 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 43048711 ps |
| CPU time | 7.34 seconds |
| Started | Aug 06 09:00:26 PM PDT 24 |
| Finished | Aug 06 09:00:33 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-b4ca3747-2f1d-4bc3-a677-885108eb6278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298208555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.1298208555 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.1558772941 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 1112721070 ps |
| CPU time | 36.07 seconds |
| Started | Aug 06 09:00:28 PM PDT 24 |
| Finished | Aug 06 09:01:04 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-aa69ed7c-93dc-4963-8c3d-28678e0f2df4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558772941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.1558772941 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.4030704185 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 189125856 ps |
| CPU time | 9.06 seconds |
| Started | Aug 06 09:00:19 PM PDT 24 |
| Finished | Aug 06 09:00:28 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-e12c4bf8-53c0-43e0-82a5-7e1e7d7f56b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030704185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.4030704185 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.2374390379 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 8706106861 ps |
| CPU time | 100.36 seconds |
| Started | Aug 06 09:00:18 PM PDT 24 |
| Finished | Aug 06 09:01:59 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-b3471d45-4246-42ab-a827-665559364208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374390379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.2374390379 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1270109694 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 5435564001 ps |
| CPU time | 92.48 seconds |
| Started | Aug 06 09:00:19 PM PDT 24 |
| Finished | Aug 06 09:01:52 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-d64f4dc1-3fbc-4708-9d82-206510befd09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270109694 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1270109694 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3948266609 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 52943922 ps |
| CPU time | 7.03 seconds |
| Started | Aug 06 09:00:20 PM PDT 24 |
| Finished | Aug 06 09:00:27 PM PDT 24 |
| Peak memory | 574372 kb |
| Host | smart-5dd0ee9e-5f25-442a-bf1c-94e7344fbc61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948266609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delay s.3948266609 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.2137271720 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 1580353227 ps |
| CPU time | 105.82 seconds |
| Started | Aug 06 09:00:33 PM PDT 24 |
| Finished | Aug 06 09:02:19 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-938bbd45-e4e6-41e5-ab0f-0da2c793083a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137271720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2137271720 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.3013576744 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 3599438865 ps |
| CPU time | 131.01 seconds |
| Started | Aug 06 09:00:27 PM PDT 24 |
| Finished | Aug 06 09:02:39 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-3f62e693-5fbd-4fc7-883d-dcbd1156f4c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013576744 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.3013576744 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.1952126232 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 1575364866 ps |
| CPU time | 282.21 seconds |
| Started | Aug 06 09:00:28 PM PDT 24 |
| Finished | Aug 06 09:05:10 PM PDT 24 |
| Peak memory | 576632 kb |
| Host | smart-915df5a1-bf71-4230-8a4a-b4beb2530c47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952126232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.1952126232 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.80679280 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 4481559603 ps |
| CPU time | 361.1 seconds |
| Started | Aug 06 09:00:34 PM PDT 24 |
| Finished | Aug 06 09:06:35 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-a79b6420-ce21-4839-859e-f23db70cf449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80679280 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_ with_reset_error.80679280 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3442514465 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 683019662 ps |
| CPU time | 32.78 seconds |
| Started | Aug 06 09:00:29 PM PDT 24 |
| Finished | Aug 06 09:01:02 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-ad72f50d-b250-496b-8ee0-319799bb6f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442514465 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.3442514465 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.2946244833 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 2178597959 ps |
| CPU time | 90.45 seconds |
| Started | Aug 06 09:00:34 PM PDT 24 |
| Finished | Aug 06 09:02:05 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-ab4cf6f9-465d-452c-83b7-1360f352fa8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2946244833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .2946244833 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.4229556450 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 140133429278 ps |
| CPU time | 2296.92 seconds |
| Started | Aug 06 09:00:35 PM PDT 24 |
| Finished | Aug 06 09:38:52 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-fd80b6de-d8af-481a-be3b-5b38cbc90be6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229556450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.4229556450 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.2785452432 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 102205202 ps |
| CPU time | 14.01 seconds |
| Started | Aug 06 09:00:35 PM PDT 24 |
| Finished | Aug 06 09:00:49 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-594dbfe2-b0b0-4031-a1e7-ab3a6dcfd13b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785452432 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.2785452432 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2051228122 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 499347528 ps |
| CPU time | 44.86 seconds |
| Started | Aug 06 09:00:34 PM PDT 24 |
| Finished | Aug 06 09:01:19 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-93867674-6497-4e0a-afaf-711af9ff8cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051228122 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2051228122 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.2953453487 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 444508540 ps |
| CPU time | 41.88 seconds |
| Started | Aug 06 09:00:35 PM PDT 24 |
| Finished | Aug 06 09:01:17 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-1763e204-5093-4d12-9f6b-e418b2e20f50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953453487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.2953453487 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.3364584254 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 87847342637 ps |
| CPU time | 913.87 seconds |
| Started | Aug 06 09:00:33 PM PDT 24 |
| Finished | Aug 06 09:15:47 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-a6ffaf06-8152-4210-aab9-dee44f5fe4b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364584254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.3364584254 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.2728065957 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 63037182108 ps |
| CPU time | 1134.99 seconds |
| Started | Aug 06 09:00:35 PM PDT 24 |
| Finished | Aug 06 09:19:30 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-0a80b6d6-77fe-4834-8753-ccb1298a474c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728065957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.2728065957 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.2469609142 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 103418522 ps |
| CPU time | 10.51 seconds |
| Started | Aug 06 09:00:36 PM PDT 24 |
| Finished | Aug 06 09:00:46 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-527aeec5-17a8-454e-ab00-074a5e455d49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2469609142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_del ays.2469609142 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.2960235834 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 2643882748 ps |
| CPU time | 76.67 seconds |
| Started | Aug 06 09:00:34 PM PDT 24 |
| Finished | Aug 06 09:01:51 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-b9b7495f-ead7-4b38-b59f-311b7c516f57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960235834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.2960235834 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.1213707810 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 161844627 ps |
| CPU time | 7.45 seconds |
| Started | Aug 06 09:00:43 PM PDT 24 |
| Finished | Aug 06 09:00:51 PM PDT 24 |
| Peak memory | 574356 kb |
| Host | smart-de5ad155-0d7d-4fc2-af8b-a57e1e8d0bf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213707810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.1213707810 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.3219497429 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 9697707658 ps |
| CPU time | 101.14 seconds |
| Started | Aug 06 09:00:33 PM PDT 24 |
| Finished | Aug 06 09:02:15 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-6aeba790-aa9a-4c8e-82c7-9c36d63027a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219497429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.3219497429 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.3026186144 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 5140007025 ps |
| CPU time | 85.97 seconds |
| Started | Aug 06 09:00:41 PM PDT 24 |
| Finished | Aug 06 09:02:07 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-908bc6dc-0ec3-4b6d-a207-f18693e22445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026186144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.3026186144 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.169573175 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 41848768 ps |
| CPU time | 6.2 seconds |
| Started | Aug 06 09:00:34 PM PDT 24 |
| Finished | Aug 06 09:00:41 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-fe2624bd-fb4c-4b5b-a056-57c5c398a2b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169573175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delays .169573175 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1805330816 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 9278124176 ps |
| CPU time | 398.75 seconds |
| Started | Aug 06 09:00:38 PM PDT 24 |
| Finished | Aug 06 09:07:17 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-caafb7d7-3f4a-4dfa-9640-05b0674d632f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805330816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1805330816 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1904589222 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 93346496 ps |
| CPU time | 38.35 seconds |
| Started | Aug 06 09:00:40 PM PDT 24 |
| Finished | Aug 06 09:01:19 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-5a8dafac-539b-4a8d-90c8-cedce2a0a704 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904589222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1904589222 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2314490501 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 4730078911 ps |
| CPU time | 413.95 seconds |
| Started | Aug 06 09:00:39 PM PDT 24 |
| Finished | Aug 06 09:07:33 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-e2a03ae1-782c-4a2a-bc9d-1aebc92da78a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314490501 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.2314490501 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3668499358 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 91225268 ps |
| CPU time | 13.32 seconds |
| Started | Aug 06 09:00:34 PM PDT 24 |
| Finished | Aug 06 09:00:48 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-4590e62b-1a04-46f9-83d3-aa50eadb7a9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3668499358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3668499358 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.4011981081 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 579242268 ps |
| CPU time | 59.93 seconds |
| Started | Aug 06 09:00:40 PM PDT 24 |
| Finished | Aug 06 09:01:40 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-0be27938-afc1-40b0-8af2-e9db26510051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011981081 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .4011981081 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1331717782 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 107948338648 ps |
| CPU time | 1831.91 seconds |
| Started | Aug 06 09:00:42 PM PDT 24 |
| Finished | Aug 06 09:31:14 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-d131d954-2db6-4140-a081-f3885d0719bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331717782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1331717782 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.1846038637 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 108607027 ps |
| CPU time | 15.72 seconds |
| Started | Aug 06 09:00:45 PM PDT 24 |
| Finished | Aug 06 09:01:00 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-849ceee4-3958-4ba3-ae21-3b602742eb96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846038637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.1846038637 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2187799724 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 563405183 ps |
| CPU time | 25 seconds |
| Started | Aug 06 09:00:45 PM PDT 24 |
| Finished | Aug 06 09:01:10 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-379336ea-dc91-4792-bca6-71945c703de7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187799724 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2187799724 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1714562605 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 1966133893 ps |
| CPU time | 87.85 seconds |
| Started | Aug 06 09:00:40 PM PDT 24 |
| Finished | Aug 06 09:02:08 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-a8e1100a-2492-4418-9fa5-8219e481b53a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1714562605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1714562605 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2063172809 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 80292713441 ps |
| CPU time | 840.46 seconds |
| Started | Aug 06 09:00:41 PM PDT 24 |
| Finished | Aug 06 09:14:41 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-b68db508-ef9b-4e93-bf50-2e9ed05b0fa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063172809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.2063172809 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.3956133636 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 40218688741 ps |
| CPU time | 684.59 seconds |
| Started | Aug 06 09:00:39 PM PDT 24 |
| Finished | Aug 06 09:12:04 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-a7c4aa82-a699-49e2-8f57-05bdeb087c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956133636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.3956133636 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.3091381386 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 603100609 ps |
| CPU time | 58.52 seconds |
| Started | Aug 06 09:00:41 PM PDT 24 |
| Finished | Aug 06 09:01:39 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-38990597-1764-4f31-9d6d-df671bf58415 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091381386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_del ays.3091381386 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.3642710238 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 2077504904 ps |
| CPU time | 70.03 seconds |
| Started | Aug 06 09:00:47 PM PDT 24 |
| Finished | Aug 06 09:01:58 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-40438cba-e4b9-4d42-bcda-37959976569d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642710238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.3642710238 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.791785870 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 42034425 ps |
| CPU time | 5.91 seconds |
| Started | Aug 06 09:00:41 PM PDT 24 |
| Finished | Aug 06 09:00:47 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-447c518b-f0e9-4220-9bab-437fc36ae191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791785870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.791785870 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.1191029206 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 9706354298 ps |
| CPU time | 95.66 seconds |
| Started | Aug 06 09:00:40 PM PDT 24 |
| Finished | Aug 06 09:02:16 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-11264cb3-fc3f-4548-b80f-4d172f266b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191029206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.1191029206 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.3938592768 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 6068855432 ps |
| CPU time | 103.32 seconds |
| Started | Aug 06 09:00:43 PM PDT 24 |
| Finished | Aug 06 09:02:26 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-2e48ef9a-283b-4451-ba10-ef32ba07977e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938592768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.3938592768 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.1608105043 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 50732138 ps |
| CPU time | 7.26 seconds |
| Started | Aug 06 09:00:40 PM PDT 24 |
| Finished | Aug 06 09:00:47 PM PDT 24 |
| Peak memory | 573628 kb |
| Host | smart-ee3ea77b-f39c-4dc3-a3d7-ce1b8feed2cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608105043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.1608105043 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.3702365468 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 55393747 ps |
| CPU time | 7.17 seconds |
| Started | Aug 06 09:00:46 PM PDT 24 |
| Finished | Aug 06 09:00:53 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-e69cfa25-18e8-4e42-aaff-1a9b56da9f38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702365468 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.3702365468 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.2641546111 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 2552056031 ps |
| CPU time | 91.99 seconds |
| Started | Aug 06 09:00:44 PM PDT 24 |
| Finished | Aug 06 09:02:16 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-d8bbad1f-1933-448c-b41d-fc6a9b00e673 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641546111 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.2641546111 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.34204370 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 40222513 ps |
| CPU time | 22.8 seconds |
| Started | Aug 06 09:00:54 PM PDT 24 |
| Finished | Aug 06 09:01:16 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-ae0e6f7e-b93b-4e21-8b2e-f192d7735847 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34204370 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_w ith_rand_reset.34204370 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.3243786897 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 203598983 ps |
| CPU time | 105.9 seconds |
| Started | Aug 06 09:00:46 PM PDT 24 |
| Finished | Aug 06 09:02:32 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-abf3f2ce-95e5-4f1a-a595-2f831f0f424a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243786897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.3243786897 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.240379915 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 322187621 ps |
| CPU time | 17.31 seconds |
| Started | Aug 06 09:00:44 PM PDT 24 |
| Finished | Aug 06 09:01:01 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f559ca32-5a8c-4b34-a1b4-aa915104b05a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240379915 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.240379915 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.3948977951 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 395647568 ps |
| CPU time | 49.75 seconds |
| Started | Aug 06 09:00:58 PM PDT 24 |
| Finished | Aug 06 09:01:48 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c36912be-8161-4dc0-b863-0c442a94e540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948977951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .3948977951 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.2192974088 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 79418284581 ps |
| CPU time | 1382.4 seconds |
| Started | Aug 06 09:01:00 PM PDT 24 |
| Finished | Aug 06 09:24:02 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-1aff9581-3579-4029-9014-1ba716b92208 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192974088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_ device_slow_rsp.2192974088 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.2529840134 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 968045122 ps |
| CPU time | 42.99 seconds |
| Started | Aug 06 09:00:57 PM PDT 24 |
| Finished | Aug 06 09:01:40 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-819efb2b-2cb6-495d-a88e-5fa7a50435e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529840134 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.2529840134 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1724951519 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 180670797 ps |
| CPU time | 20 seconds |
| Started | Aug 06 09:00:59 PM PDT 24 |
| Finished | Aug 06 09:01:19 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-ce640cd3-b2b4-4d96-973b-aa8b211ad856 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724951519 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1724951519 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2246254105 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 1890366914 ps |
| CPU time | 72.27 seconds |
| Started | Aug 06 09:00:53 PM PDT 24 |
| Finished | Aug 06 09:02:06 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-37544e0f-b7d4-40f6-b8b1-097d78aaea0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246254105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2246254105 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.2441855317 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 101254662167 ps |
| CPU time | 1024.01 seconds |
| Started | Aug 06 09:00:53 PM PDT 24 |
| Finished | Aug 06 09:17:58 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-7ae8acf1-c844-4ecd-9c39-5b485f161322 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441855317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.2441855317 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.3293958578 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 47970324717 ps |
| CPU time | 787.18 seconds |
| Started | Aug 06 09:00:52 PM PDT 24 |
| Finished | Aug 06 09:13:59 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-3d87370f-8730-451a-8fa9-85fc5e718eb6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293958578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.3293958578 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.90591006 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 178212505 ps |
| CPU time | 20.36 seconds |
| Started | Aug 06 09:00:53 PM PDT 24 |
| Finished | Aug 06 09:01:13 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-f60c7a5a-4f18-43c6-8748-e6b3eada11bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90591006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_delay s.90591006 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.2863904236 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 2066741034 ps |
| CPU time | 58.35 seconds |
| Started | Aug 06 09:01:00 PM PDT 24 |
| Finished | Aug 06 09:01:58 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-6fd7b85d-34e5-46c8-957a-0c5ca289286c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863904236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.2863904236 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.1451878676 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 58109222 ps |
| CPU time | 6.96 seconds |
| Started | Aug 06 09:00:47 PM PDT 24 |
| Finished | Aug 06 09:00:54 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-7a785987-4c65-4625-be53-a1cd0c813bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451878676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.1451878676 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.249201683 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 9140853223 ps |
| CPU time | 101.47 seconds |
| Started | Aug 06 09:00:50 PM PDT 24 |
| Finished | Aug 06 09:02:32 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-0bbb400a-a9ef-4272-87fb-7bbab49cdcc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249201683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.249201683 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.4154739297 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 7081185405 ps |
| CPU time | 130.25 seconds |
| Started | Aug 06 09:00:58 PM PDT 24 |
| Finished | Aug 06 09:03:09 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-d70bdba9-a0ba-4236-a8ef-14a3901c4aac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154739297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.4154739297 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1609108103 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 45926399 ps |
| CPU time | 6.34 seconds |
| Started | Aug 06 09:00:51 PM PDT 24 |
| Finished | Aug 06 09:00:57 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-f971c7ba-2adc-486c-9c2f-bcaf089465dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1609108103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.1609108103 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.2591836604 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 1903682757 ps |
| CPU time | 162.68 seconds |
| Started | Aug 06 09:00:59 PM PDT 24 |
| Finished | Aug 06 09:03:41 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-54f739cc-ae3d-4e7c-b109-a5fcd6caa0eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591836604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.2591836604 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.191906879 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 9404121692 ps |
| CPU time | 389.88 seconds |
| Started | Aug 06 09:00:59 PM PDT 24 |
| Finished | Aug 06 09:07:29 PM PDT 24 |
| Peak memory | 576648 kb |
| Host | smart-9a3acd97-b66b-4ea8-b1fd-8d6bee321831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191906879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.191906879 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1762346430 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 2721901520 ps |
| CPU time | 390.04 seconds |
| Started | Aug 06 09:00:58 PM PDT 24 |
| Finished | Aug 06 09:07:28 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-4401dc04-6a30-4cc4-a7d3-4ba105da78f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762346430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.1762346430 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.1146793895 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 3642249592 ps |
| CPU time | 385.39 seconds |
| Started | Aug 06 09:01:06 PM PDT 24 |
| Finished | Aug 06 09:07:32 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-05c1eb83-789d-40cd-bc3e-37ddf51be566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146793895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.1146793895 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3692205103 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 293257125 ps |
| CPU time | 35.59 seconds |
| Started | Aug 06 09:01:06 PM PDT 24 |
| Finished | Aug 06 09:01:41 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-fd0ecb23-4c82-4054-91ac-6ae9ee415374 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692205103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.3692205103 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.2752628929 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 9889243845 ps |
| CPU time | 1049.13 seconds |
| Started | Aug 06 08:46:53 PM PDT 24 |
| Finished | Aug 06 09:04:22 PM PDT 24 |
| Peak memory | 653016 kb |
| Host | smart-46f5a9b0-4c77-4fac-ac0e-c0d197af5496 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752628929 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.2752628929 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.4279113465 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 3774833220 ps |
| CPU time | 400.82 seconds |
| Started | Aug 06 08:46:55 PM PDT 24 |
| Finished | Aug 06 08:53:36 PM PDT 24 |
| Peak memory | 598960 kb |
| Host | smart-03d5bf10-a7c1-4094-a7c9-a886594f7541 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279113465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.4279113465 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2265149996 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 31600662860 ps |
| CPU time | 3709.86 seconds |
| Started | Aug 06 08:46:25 PM PDT 24 |
| Finished | Aug 06 09:48:16 PM PDT 24 |
| Peak memory | 593532 kb |
| Host | smart-c8d9005e-9233-433d-a248-74f3a77a0f9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265149996 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.2265149996 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3879329784 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 3478500656 ps |
| CPU time | 257.61 seconds |
| Started | Aug 06 08:46:22 PM PDT 24 |
| Finished | Aug 06 08:50:40 PM PDT 24 |
| Peak memory | 603624 kb |
| Host | smart-938d8687-4479-4424-b712-12773cf2549c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879329784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3879329784 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.2910723594 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 559712110 ps |
| CPU time | 50.51 seconds |
| Started | Aug 06 08:46:57 PM PDT 24 |
| Finished | Aug 06 08:47:47 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-9265349f-eab1-420a-b852-8abc933a7d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910723594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device. 2910723594 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2662453331 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 24935912688 ps |
| CPU time | 438.95 seconds |
| Started | Aug 06 08:46:47 PM PDT 24 |
| Finished | Aug 06 08:54:06 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-dd0a26cc-0b3a-430f-8464-bb9313c80b93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662453331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2662453331 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.1177037570 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 158350731 ps |
| CPU time | 22.8 seconds |
| Started | Aug 06 08:46:47 PM PDT 24 |
| Finished | Aug 06 08:47:09 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-f75ac2ba-d1b5-43fb-8547-1d34841792fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177037570 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .1177037570 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.240429956 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 1829935726 ps |
| CPU time | 70.81 seconds |
| Started | Aug 06 08:46:49 PM PDT 24 |
| Finished | Aug 06 08:47:59 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-f3ba13c0-6346-47fb-8847-993008719c13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=240429956 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.240429956 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.169636027 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 2091438867 ps |
| CPU time | 82.58 seconds |
| Started | Aug 06 08:46:40 PM PDT 24 |
| Finished | Aug 06 08:48:03 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-bcf2a0f4-bf09-4722-baad-1486076f6695 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169636027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.169636027 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.3569007870 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 61459093611 ps |
| CPU time | 681.58 seconds |
| Started | Aug 06 08:46:39 PM PDT 24 |
| Finished | Aug 06 08:58:01 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-866750de-efa8-49de-a61f-a2e6b2668a48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569007870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.3569007870 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.3175990676 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 26801538117 ps |
| CPU time | 468.96 seconds |
| Started | Aug 06 08:46:39 PM PDT 24 |
| Finished | Aug 06 08:54:28 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-83bff869-77ce-4dc6-a80a-5409abbdbde7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175990676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.3175990676 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.3063011584 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 515660729 ps |
| CPU time | 50.62 seconds |
| Started | Aug 06 08:46:41 PM PDT 24 |
| Finished | Aug 06 08:47:32 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-dfb1ad62-c1ba-429f-aace-5fed5afa47f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063011584 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.3063011584 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.1036898267 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 79999496 ps |
| CPU time | 9.88 seconds |
| Started | Aug 06 08:46:57 PM PDT 24 |
| Finished | Aug 06 08:47:07 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-6c6df16f-f9f9-4378-b369-e6bdf5b75c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036898267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.1036898267 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.2549210356 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 57397119 ps |
| CPU time | 7.09 seconds |
| Started | Aug 06 08:46:30 PM PDT 24 |
| Finished | Aug 06 08:46:37 PM PDT 24 |
| Peak memory | 574272 kb |
| Host | smart-164f0685-07e3-4897-a3db-5b1257ece5b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549210356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.2549210356 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1265217650 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 8981816700 ps |
| CPU time | 95.63 seconds |
| Started | Aug 06 08:46:31 PM PDT 24 |
| Finished | Aug 06 08:48:07 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-b6e65daa-ca2b-46d5-9c2b-63b6b498a8e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265217650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.1265217650 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4232081704 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 3519423114 ps |
| CPU time | 64.76 seconds |
| Started | Aug 06 08:46:29 PM PDT 24 |
| Finished | Aug 06 08:47:34 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-bea3abef-da46-4194-809a-91e79ebfef24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232081704 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.4232081704 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3445816763 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 52292999 ps |
| CPU time | 7.14 seconds |
| Started | Aug 06 08:46:28 PM PDT 24 |
| Finished | Aug 06 08:46:35 PM PDT 24 |
| Peak memory | 574332 kb |
| Host | smart-a5240490-e69a-4129-b516-7046972ea92c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445816763 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3445816763 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.2488402263 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 6278486271 ps |
| CPU time | 259.65 seconds |
| Started | Aug 06 08:46:57 PM PDT 24 |
| Finished | Aug 06 08:51:17 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-85bf8e17-66cb-4353-ae7a-d866999706d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488402263 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.2488402263 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.449498651 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 1102690107 ps |
| CPU time | 94.92 seconds |
| Started | Aug 06 08:46:52 PM PDT 24 |
| Finished | Aug 06 08:48:27 PM PDT 24 |
| Peak memory | 575976 kb |
| Host | smart-1ad898ff-1d47-4438-a9ef-120d6fd061ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449498651 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.449498651 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.3441055291 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 139116521 ps |
| CPU time | 39.52 seconds |
| Started | Aug 06 08:46:58 PM PDT 24 |
| Finished | Aug 06 08:47:37 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-a8bac82d-c2c7-452e-a644-290fb18c85ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441055291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_rand_reset.3441055291 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.854215543 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 9182192798 ps |
| CPU time | 439.82 seconds |
| Started | Aug 06 08:46:53 PM PDT 24 |
| Finished | Aug 06 08:54:13 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-296d1ff9-bca6-4eaf-8417-2dd02a6212ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854215543 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_reset_error.854215543 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.1882398691 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 336543277 ps |
| CPU time | 40.09 seconds |
| Started | Aug 06 08:46:47 PM PDT 24 |
| Finished | Aug 06 08:47:27 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-ae8bd86e-763a-49b5-997e-5e6a65229aa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882398691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.1882398691 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2191441191 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 535192117 ps |
| CPU time | 54.16 seconds |
| Started | Aug 06 09:01:04 PM PDT 24 |
| Finished | Aug 06 09:01:59 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-ec6e97e2-b7a6-4285-b0a8-5590a6fdc7c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191441191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .2191441191 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.1654901441 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 26831373284 ps |
| CPU time | 452.51 seconds |
| Started | Aug 06 09:01:11 PM PDT 24 |
| Finished | Aug 06 09:08:43 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-b7b034a5-e368-43b1-a197-59069b272adc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1654901441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_ device_slow_rsp.1654901441 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.486100321 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 471673798 ps |
| CPU time | 22.7 seconds |
| Started | Aug 06 09:01:06 PM PDT 24 |
| Finished | Aug 06 09:01:28 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-d1118eeb-d382-4a6e-996e-4b5043ce9206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=486100321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_addr .486100321 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.3575828759 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 1574862851 ps |
| CPU time | 57.94 seconds |
| Started | Aug 06 09:01:07 PM PDT 24 |
| Finished | Aug 06 09:02:05 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-58ac0e60-616a-4737-97c3-3db5e4a805de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575828759 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.3575828759 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.3225713854 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 778641346 ps |
| CPU time | 27.41 seconds |
| Started | Aug 06 09:00:58 PM PDT 24 |
| Finished | Aug 06 09:01:25 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-df77ebe7-5c72-4211-9ab4-483d71c2f566 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225713854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.3225713854 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2660554195 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 44516419160 ps |
| CPU time | 454.05 seconds |
| Started | Aug 06 09:01:10 PM PDT 24 |
| Finished | Aug 06 09:08:44 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-ff26c53d-06f7-4538-88fa-9120657e30c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660554195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.2660554195 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.118219029 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 40568279656 ps |
| CPU time | 688.64 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:12:41 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-40d1f053-6350-4b5c-819b-7b7a3afde588 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118219029 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.118219029 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.2245581519 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 595979606 ps |
| CPU time | 59.3 seconds |
| Started | Aug 06 09:01:07 PM PDT 24 |
| Finished | Aug 06 09:02:06 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-4970a004-8abb-43d5-b2a0-2603b7d91043 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245581519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.2245581519 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.2507727164 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 150653492 ps |
| CPU time | 14.68 seconds |
| Started | Aug 06 09:01:10 PM PDT 24 |
| Finished | Aug 06 09:01:24 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-1efd9b8e-4b41-4c29-be1d-a919c61fe32b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2507727164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.2507727164 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.3290831356 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 258461599 ps |
| CPU time | 10.47 seconds |
| Started | Aug 06 09:00:58 PM PDT 24 |
| Finished | Aug 06 09:01:09 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-ef9f4633-326a-4b8d-9243-fe0c838d7136 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290831356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.3290831356 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.2628959955 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 8167982668 ps |
| CPU time | 90.91 seconds |
| Started | Aug 06 09:01:08 PM PDT 24 |
| Finished | Aug 06 09:02:39 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-5794037b-66c1-47a2-abc1-5830a54ec023 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628959955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.2628959955 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3163642343 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 3852145397 ps |
| CPU time | 67.17 seconds |
| Started | Aug 06 09:00:59 PM PDT 24 |
| Finished | Aug 06 09:02:06 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-f68efb44-f9c2-4816-986d-e94acd170a19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163642343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3163642343 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.522994104 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 39171016 ps |
| CPU time | 6.23 seconds |
| Started | Aug 06 09:01:00 PM PDT 24 |
| Finished | Aug 06 09:01:06 PM PDT 24 |
| Peak memory | 573676 kb |
| Host | smart-babfb80d-f7bc-4307-a201-a80728899513 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522994104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays .522994104 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.2625820511 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 4978178383 ps |
| CPU time | 178.16 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:04:10 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-291e3fd9-89c2-4c65-a42c-25696a5f5cfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625820511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.2625820511 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.296394531 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 2985694583 ps |
| CPU time | 100.61 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:02:53 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-adf0ca6f-254f-4509-85e4-540aae0dd124 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296394531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.296394531 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.19475989 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 85573074 ps |
| CPU time | 33.8 seconds |
| Started | Aug 06 09:01:07 PM PDT 24 |
| Finished | Aug 06 09:01:40 PM PDT 24 |
| Peak memory | 573932 kb |
| Host | smart-df27dbd4-9950-4536-b952-89de41450a6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19475989 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_ with_reset_error.19475989 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.2037266365 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 245489302 ps |
| CPU time | 29.83 seconds |
| Started | Aug 06 09:01:05 PM PDT 24 |
| Finished | Aug 06 09:01:35 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-0d7b1669-1a45-4ed5-abcf-3640b3d2ef83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037266365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.2037266365 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.1960649696 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 2374427409 ps |
| CPU time | 104.62 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:02:57 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-5649b573-91bf-404a-9283-c46ea16aa599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960649696 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .1960649696 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.3532059806 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 67078522684 ps |
| CPU time | 1270.54 seconds |
| Started | Aug 06 09:01:10 PM PDT 24 |
| Finished | Aug 06 09:22:21 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-ebbfb5dd-c7d8-44df-985d-9a5e1489f7ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532059806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.3532059806 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.16123730 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 65272471 ps |
| CPU time | 11 seconds |
| Started | Aug 06 09:01:10 PM PDT 24 |
| Finished | Aug 06 09:01:21 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-695d981b-5a1c-48c4-a10e-410c927748a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16123730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_addr.16123730 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.227019980 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 1306491609 ps |
| CPU time | 53.9 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:02:06 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-893d77b5-9f8b-48bf-90f6-b73044b06d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227019980 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.227019980 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.1690281611 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 1142298729 ps |
| CPU time | 40.53 seconds |
| Started | Aug 06 09:01:06 PM PDT 24 |
| Finished | Aug 06 09:01:46 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-c8a77d0c-381d-432b-b834-79da5fa3e553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690281611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.1690281611 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2878354498 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 75242051710 ps |
| CPU time | 776.18 seconds |
| Started | Aug 06 09:01:07 PM PDT 24 |
| Finished | Aug 06 09:14:04 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-cbd75613-c4ff-4bd8-bbc1-1739774f9d99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878354498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2878354498 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.450314417 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 32546607240 ps |
| CPU time | 579.53 seconds |
| Started | Aug 06 09:01:09 PM PDT 24 |
| Finished | Aug 06 09:10:49 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-0b4f3a05-e8d0-473c-9b90-81e8df76ad23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450314417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.450314417 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.1365427017 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 226676130 ps |
| CPU time | 23.51 seconds |
| Started | Aug 06 09:01:05 PM PDT 24 |
| Finished | Aug 06 09:01:28 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-1494c91a-3fe6-4e60-9ef1-a500f82bd65d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365427017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.1365427017 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.4269511379 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 215195901 ps |
| CPU time | 9.88 seconds |
| Started | Aug 06 09:01:09 PM PDT 24 |
| Finished | Aug 06 09:01:19 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-8dd7101d-7e5c-4deb-aa44-4f0697288a07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269511379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.4269511379 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.60891522 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 215825679 ps |
| CPU time | 10.25 seconds |
| Started | Aug 06 09:01:04 PM PDT 24 |
| Finished | Aug 06 09:01:15 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-066669ca-e525-4e8a-ad71-0eea64ac9751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60891522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.60891522 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.3723273505 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 10269585959 ps |
| CPU time | 109.66 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:03:01 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-9976d321-9126-4222-af6c-6a695f8ba35e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723273505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.3723273505 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.339515429 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 4488198848 ps |
| CPU time | 71.51 seconds |
| Started | Aug 06 09:01:11 PM PDT 24 |
| Finished | Aug 06 09:02:23 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-1265af9e-4963-4110-9a7d-7b042e13d858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339515429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.339515429 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1607198999 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 49146082 ps |
| CPU time | 6.96 seconds |
| Started | Aug 06 09:01:05 PM PDT 24 |
| Finished | Aug 06 09:01:12 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-8043f2d3-e083-45dc-b2a3-59657276aaee |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607198999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1607198999 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.4189622335 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 5130917562 ps |
| CPU time | 426.48 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:08:19 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-c2814615-f89b-4f7f-906b-1f9e1df3babb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189622335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.4189622335 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2138060494 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 612518594 ps |
| CPU time | 54.43 seconds |
| Started | Aug 06 09:01:13 PM PDT 24 |
| Finished | Aug 06 09:02:08 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-0442da81-4f5f-4b84-94a1-09f50ee490e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138060494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2138060494 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.1636149049 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 130648504 ps |
| CPU time | 69.44 seconds |
| Started | Aug 06 09:01:12 PM PDT 24 |
| Finished | Aug 06 09:02:21 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-97431c88-4ad5-4e2e-89b7-5838c43dcdde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636149049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.1636149049 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.708155567 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 5735337938 ps |
| CPU time | 299.42 seconds |
| Started | Aug 06 09:01:13 PM PDT 24 |
| Finished | Aug 06 09:06:12 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-7c3f4e02-fadc-45db-9a4f-ff130e7a6fd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708155567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_reset_error.708155567 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3334980756 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 311897230 ps |
| CPU time | 14.84 seconds |
| Started | Aug 06 09:01:11 PM PDT 24 |
| Finished | Aug 06 09:01:26 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-421d1292-b3d3-48f1-a7a4-5801765703fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334980756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3334980756 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.242862448 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 2339505781 ps |
| CPU time | 103.21 seconds |
| Started | Aug 06 09:01:21 PM PDT 24 |
| Finished | Aug 06 09:03:04 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-4cc21ebc-804b-484a-8039-50c80989b69d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242862448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device. 242862448 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.1732130989 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 91806053153 ps |
| CPU time | 1631.91 seconds |
| Started | Aug 06 09:01:21 PM PDT 24 |
| Finished | Aug 06 09:28:33 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-d2ef584d-8bb2-40ae-a713-c83746dc29f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732130989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.1732130989 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.1572264242 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 209813209 ps |
| CPU time | 11.21 seconds |
| Started | Aug 06 09:01:23 PM PDT 24 |
| Finished | Aug 06 09:01:34 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c00d59e7-d1ad-4934-892d-3bbc9922035e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572264242 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.1572264242 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.1265925072 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 284335235 ps |
| CPU time | 12.69 seconds |
| Started | Aug 06 09:01:20 PM PDT 24 |
| Finished | Aug 06 09:01:32 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-612f6876-24c2-4a37-805d-515123f662ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265925072 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.1265925072 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.251708210 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 2227939271 ps |
| CPU time | 91.29 seconds |
| Started | Aug 06 09:01:18 PM PDT 24 |
| Finished | Aug 06 09:02:49 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-e7f79866-85f3-4120-9a62-5a5cefae14e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251708210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.251708210 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.1481964211 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 67766249117 ps |
| CPU time | 657.65 seconds |
| Started | Aug 06 09:01:16 PM PDT 24 |
| Finished | Aug 06 09:12:14 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a03930c9-a5c3-4571-b8a7-3472701317ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1481964211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.1481964211 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.4031518553 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 56756496568 ps |
| CPU time | 986.97 seconds |
| Started | Aug 06 09:01:20 PM PDT 24 |
| Finished | Aug 06 09:17:47 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-498114eb-0aa4-45a4-822b-29dcac061cc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031518553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.4031518553 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.2593795662 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 258243474 ps |
| CPU time | 24.17 seconds |
| Started | Aug 06 09:01:14 PM PDT 24 |
| Finished | Aug 06 09:01:38 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-a5dc6ad0-f23b-4155-ba73-16ef799c1a6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593795662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.2593795662 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.4019664242 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2126339323 ps |
| CPU time | 71.24 seconds |
| Started | Aug 06 09:01:22 PM PDT 24 |
| Finished | Aug 06 09:02:34 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-b12bea6f-31ee-420f-8ac4-ba447ca1043a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019664242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.4019664242 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.2929637255 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 196688029 ps |
| CPU time | 8.86 seconds |
| Started | Aug 06 09:01:14 PM PDT 24 |
| Finished | Aug 06 09:01:23 PM PDT 24 |
| Peak memory | 574488 kb |
| Host | smart-f2f77213-897a-408e-af8b-087e24ffd490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929637255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.2929637255 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.194598829 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 9036395746 ps |
| CPU time | 98.97 seconds |
| Started | Aug 06 09:01:14 PM PDT 24 |
| Finished | Aug 06 09:02:53 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-82179d7a-c91c-4ffd-8303-444cc56e54b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194598829 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.194598829 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3957888979 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 4739903201 ps |
| CPU time | 86.12 seconds |
| Started | Aug 06 09:01:15 PM PDT 24 |
| Finished | Aug 06 09:02:41 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-80a20710-a8dc-4608-998c-dde746f7dcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957888979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.3957888979 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.1924455687 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 46769948 ps |
| CPU time | 6.59 seconds |
| Started | Aug 06 09:01:17 PM PDT 24 |
| Finished | Aug 06 09:01:24 PM PDT 24 |
| Peak memory | 574420 kb |
| Host | smart-de3ac79c-3ea6-4a75-bd44-25bda41dd126 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924455687 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.1924455687 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3603549425 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 607541874 ps |
| CPU time | 29.46 seconds |
| Started | Aug 06 09:01:30 PM PDT 24 |
| Finished | Aug 06 09:01:59 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-65a54b40-b580-4028-8787-8d963448a548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603549425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3603549425 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.2813679028 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 305622997 ps |
| CPU time | 24.97 seconds |
| Started | Aug 06 09:01:26 PM PDT 24 |
| Finished | Aug 06 09:01:51 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-03c0c998-df59-44f7-a039-c87a2076a926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813679028 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.2813679028 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.1398841800 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 271885339 ps |
| CPU time | 161.06 seconds |
| Started | Aug 06 09:01:26 PM PDT 24 |
| Finished | Aug 06 09:04:07 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-be24b649-181d-4b03-9be2-193a5c219ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398841800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.1398841800 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.2829603319 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 96089689 ps |
| CPU time | 42.8 seconds |
| Started | Aug 06 09:01:26 PM PDT 24 |
| Finished | Aug 06 09:02:08 PM PDT 24 |
| Peak memory | 576548 kb |
| Host | smart-3b3ccee6-9c30-483d-97a3-fd3a50cb0f74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829603319 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_al l_with_reset_error.2829603319 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.416188820 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 38478089 ps |
| CPU time | 8.02 seconds |
| Started | Aug 06 09:01:23 PM PDT 24 |
| Finished | Aug 06 09:01:31 PM PDT 24 |
| Peak memory | 574532 kb |
| Host | smart-86b2394b-ef39-4ff7-b6d0-ad2a71e8a156 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416188820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.416188820 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.915009774 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 2549877903 ps |
| CPU time | 108.46 seconds |
| Started | Aug 06 09:01:27 PM PDT 24 |
| Finished | Aug 06 09:03:16 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-e0e3b095-c267-422e-b6cc-d478863711b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915009774 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device. 915009774 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.1908833078 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 161167300094 ps |
| CPU time | 2835.14 seconds |
| Started | Aug 06 09:01:30 PM PDT 24 |
| Finished | Aug 06 09:48:46 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-e2132bf3-6efc-4dc3-a9e3-65aefbc16cd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908833078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.1908833078 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.1647867048 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 230545922 ps |
| CPU time | 26.66 seconds |
| Started | Aug 06 09:01:31 PM PDT 24 |
| Finished | Aug 06 09:01:58 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-1cd4473e-6780-47c8-8a9f-4b0c246f604b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1647867048 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.1647867048 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.1053711981 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 26817949 ps |
| CPU time | 5.73 seconds |
| Started | Aug 06 09:01:39 PM PDT 24 |
| Finished | Aug 06 09:01:45 PM PDT 24 |
| Peak memory | 574316 kb |
| Host | smart-b0660bab-5265-45ef-85f8-910d28565e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053711981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1053711981 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.459826158 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 457950369 ps |
| CPU time | 48.25 seconds |
| Started | Aug 06 09:01:27 PM PDT 24 |
| Finished | Aug 06 09:02:16 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-1c8336a2-2cc1-4100-9469-d482611310c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459826158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.459826158 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1400807417 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 88873709177 ps |
| CPU time | 939.84 seconds |
| Started | Aug 06 09:01:27 PM PDT 24 |
| Finished | Aug 06 09:17:07 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-7cfefce6-ea1a-40ec-865e-d33f4d04e46a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400807417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.1400807417 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.4029279478 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 46705387623 ps |
| CPU time | 822.12 seconds |
| Started | Aug 06 09:01:29 PM PDT 24 |
| Finished | Aug 06 09:15:11 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-456a20e1-c289-4585-9620-ceb1bdf60275 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029279478 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.4029279478 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.2699585502 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 502821857 ps |
| CPU time | 43.33 seconds |
| Started | Aug 06 09:01:28 PM PDT 24 |
| Finished | Aug 06 09:02:12 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-66a9fed7-12dd-46ff-8741-eeb8e15e502d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2699585502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.2699585502 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.2137868303 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 454475057 ps |
| CPU time | 35.29 seconds |
| Started | Aug 06 09:01:30 PM PDT 24 |
| Finished | Aug 06 09:02:06 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-ccf3689f-7c35-4ddc-a081-6400875a7233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137868303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.2137868303 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.231338822 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 47581900 ps |
| CPU time | 6.8 seconds |
| Started | Aug 06 09:01:26 PM PDT 24 |
| Finished | Aug 06 09:01:33 PM PDT 24 |
| Peak memory | 574432 kb |
| Host | smart-2b2e3765-90dc-4449-9185-7f843d3228f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231338822 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.231338822 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.300876748 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 7563218068 ps |
| CPU time | 85.71 seconds |
| Started | Aug 06 09:01:29 PM PDT 24 |
| Finished | Aug 06 09:02:55 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-d0e054d5-eb05-48ac-aa30-f155b82134cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300876748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.300876748 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1203438766 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 6060561180 ps |
| CPU time | 109.18 seconds |
| Started | Aug 06 09:01:26 PM PDT 24 |
| Finished | Aug 06 09:03:15 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-59e6d9e7-d615-48a0-b09d-4e4affc92b87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203438766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1203438766 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1052990292 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 45912890 ps |
| CPU time | 6.95 seconds |
| Started | Aug 06 09:01:27 PM PDT 24 |
| Finished | Aug 06 09:01:34 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-f3c8b74e-b078-465a-beda-9d732346289c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052990292 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.1052990292 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.1364746425 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 4058559956 ps |
| CPU time | 394.54 seconds |
| Started | Aug 06 09:01:38 PM PDT 24 |
| Finished | Aug 06 09:08:13 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-90e39dc3-f270-415a-9d0b-2835f1f14389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364746425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.1364746425 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.3465324268 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 11420003533 ps |
| CPU time | 462.65 seconds |
| Started | Aug 06 09:01:35 PM PDT 24 |
| Finished | Aug 06 09:09:17 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-2f96ee99-f2be-4ea8-8aea-05c8789e39fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465324268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.3465324268 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.14363091 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 425512703 ps |
| CPU time | 150.2 seconds |
| Started | Aug 06 09:01:32 PM PDT 24 |
| Finished | Aug 06 09:04:02 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-80dcf7ca-60da-494a-854d-622c2c49a4ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14363091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_w ith_rand_reset.14363091 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3751155497 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 4880216893 ps |
| CPU time | 513.08 seconds |
| Started | Aug 06 09:01:35 PM PDT 24 |
| Finished | Aug 06 09:10:08 PM PDT 24 |
| Peak memory | 577952 kb |
| Host | smart-5fa603d7-37aa-4e00-a9d5-0c04833b2d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751155497 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3751155497 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.1314261243 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 864905084 ps |
| CPU time | 38.67 seconds |
| Started | Aug 06 09:01:36 PM PDT 24 |
| Finished | Aug 06 09:02:15 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-b7eba9a9-6d29-4a36-9f57-55ca52036012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1314261243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.1314261243 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.2648479808 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 2504857939 ps |
| CPU time | 130.44 seconds |
| Started | Aug 06 09:01:41 PM PDT 24 |
| Finished | Aug 06 09:03:52 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-d132d8a7-e23a-4033-bee7-49c0fb74c38c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648479808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .2648479808 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.808689170 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 100253173525 ps |
| CPU time | 1814.46 seconds |
| Started | Aug 06 09:01:40 PM PDT 24 |
| Finished | Aug 06 09:31:55 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-c85ecd91-3dd2-4c04-b92f-ee3b3d4a8e21 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=808689170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_d evice_slow_rsp.808689170 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.1539444865 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 526626646 ps |
| CPU time | 18.87 seconds |
| Started | Aug 06 09:01:40 PM PDT 24 |
| Finished | Aug 06 09:01:58 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-de2b9871-9f22-4ff2-821e-62cdc95c9dd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539444865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.1539444865 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.2774090524 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 331843469 ps |
| CPU time | 27.5 seconds |
| Started | Aug 06 09:01:42 PM PDT 24 |
| Finished | Aug 06 09:02:09 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-7df4ae7c-2b2d-4f9b-a2c6-4fda2a7ade80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774090524 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.2774090524 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.858306359 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 151639995 ps |
| CPU time | 8.42 seconds |
| Started | Aug 06 09:01:38 PM PDT 24 |
| Finished | Aug 06 09:01:46 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-62c4e312-58dc-4915-b061-418d72502092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858306359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.858306359 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1194484146 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 22829880171 ps |
| CPU time | 257.22 seconds |
| Started | Aug 06 09:01:36 PM PDT 24 |
| Finished | Aug 06 09:05:53 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-566856d1-431d-4bf8-8b59-888ec6820aa3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194484146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.1194484146 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.11379496 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 43736243240 ps |
| CPU time | 727.99 seconds |
| Started | Aug 06 09:01:37 PM PDT 24 |
| Finished | Aug 06 09:13:45 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-f15c25f5-03d0-4040-93fd-89ae717efb71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11379496 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.11379496 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.2941139475 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 34015440 ps |
| CPU time | 7.08 seconds |
| Started | Aug 06 09:01:35 PM PDT 24 |
| Finished | Aug 06 09:01:42 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-a22f3d08-7b24-4d94-a8fd-085ddc848c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941139475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.2941139475 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.1628522768 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 1977816172 ps |
| CPU time | 63.03 seconds |
| Started | Aug 06 09:01:42 PM PDT 24 |
| Finished | Aug 06 09:02:45 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-7076356e-9247-4469-8662-64639e07b7a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628522768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.1628522768 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.1585025046 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 199998479 ps |
| CPU time | 9.56 seconds |
| Started | Aug 06 09:01:31 PM PDT 24 |
| Finished | Aug 06 09:01:41 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-4981fc5d-360b-476a-8c64-5c1a9de76924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585025046 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1585025046 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.3294566073 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 7435893888 ps |
| CPU time | 79.33 seconds |
| Started | Aug 06 09:01:34 PM PDT 24 |
| Finished | Aug 06 09:02:54 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-dd35751c-83fd-447b-9b0b-9fdafc2d74c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294566073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.3294566073 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.2940345949 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 4551529584 ps |
| CPU time | 79.87 seconds |
| Started | Aug 06 09:01:39 PM PDT 24 |
| Finished | Aug 06 09:02:58 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-31a6d844-56cf-47e2-b926-a7d2289e4624 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940345949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.2940345949 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.1224493458 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 42977098 ps |
| CPU time | 6.03 seconds |
| Started | Aug 06 09:01:35 PM PDT 24 |
| Finished | Aug 06 09:01:41 PM PDT 24 |
| Peak memory | 573648 kb |
| Host | smart-fa2ecec0-1523-4df2-94bb-b1d32fd7d13b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224493458 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.1224493458 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.2797544783 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3086474225 ps |
| CPU time | 119.59 seconds |
| Started | Aug 06 09:01:41 PM PDT 24 |
| Finished | Aug 06 09:03:40 PM PDT 24 |
| Peak memory | 576188 kb |
| Host | smart-9ef91c23-9918-4fe9-b4c4-5fc30a7b4575 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2797544783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.2797544783 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.1912471054 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 1292528575 ps |
| CPU time | 49.22 seconds |
| Started | Aug 06 09:01:46 PM PDT 24 |
| Finished | Aug 06 09:02:35 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-08139e5f-4aa0-426b-9ecb-000f26895672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912471054 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.1912471054 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.649287918 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 130462450 ps |
| CPU time | 42.12 seconds |
| Started | Aug 06 09:01:42 PM PDT 24 |
| Finished | Aug 06 09:02:24 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-a508e691-66de-427b-a36e-2b79fe2b7e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649287918 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_ with_rand_reset.649287918 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3126976987 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 400980046 ps |
| CPU time | 135.4 seconds |
| Started | Aug 06 09:01:45 PM PDT 24 |
| Finished | Aug 06 09:04:00 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-1bc28234-d033-49d6-b866-680d3406283a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126976987 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3126976987 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.4135392985 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 1099095998 ps |
| CPU time | 48.21 seconds |
| Started | Aug 06 09:01:42 PM PDT 24 |
| Finished | Aug 06 09:02:30 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-9ae60963-0ad2-47d9-827f-7f2f0cdb3d8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135392985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.4135392985 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.1099467827 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 229669220 ps |
| CPU time | 31.37 seconds |
| Started | Aug 06 09:01:52 PM PDT 24 |
| Finished | Aug 06 09:02:23 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-8bcb5fc8-19e2-4ba7-8ea1-fa575be8a583 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1099467827 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device .1099467827 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.1152288886 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 59513421479 ps |
| CPU time | 952.24 seconds |
| Started | Aug 06 09:01:51 PM PDT 24 |
| Finished | Aug 06 09:17:43 PM PDT 24 |
| Peak memory | 575980 kb |
| Host | smart-5b1355b4-eafe-4cfe-9c1a-1041b30a3ec1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152288886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.1152288886 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.921576745 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 1222010196 ps |
| CPU time | 55.09 seconds |
| Started | Aug 06 09:01:56 PM PDT 24 |
| Finished | Aug 06 09:02:51 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-274591d3-ef9e-45e5-ad8c-c2b57bc6d4b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921576745 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_addr .921576745 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.3995060213 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 228275402 ps |
| CPU time | 21.21 seconds |
| Started | Aug 06 09:01:51 PM PDT 24 |
| Finished | Aug 06 09:02:12 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-22c0e8f5-9da8-45b3-9da1-dc8148969991 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995060213 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.3995060213 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.3983986842 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 456796997 ps |
| CPU time | 46.83 seconds |
| Started | Aug 06 09:01:48 PM PDT 24 |
| Finished | Aug 06 09:02:35 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-bfe09194-7c00-4239-91f5-2d50e45ca997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983986842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.3983986842 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.1008083555 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 29235481894 ps |
| CPU time | 303.04 seconds |
| Started | Aug 06 09:01:46 PM PDT 24 |
| Finished | Aug 06 09:06:50 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-db5759cc-48b8-4538-8ca3-29c14fe03492 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008083555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.1008083555 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.1641485891 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 37848422419 ps |
| CPU time | 652.63 seconds |
| Started | Aug 06 09:01:50 PM PDT 24 |
| Finished | Aug 06 09:12:43 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-6757a45b-d027-48d2-bb4e-432d605cf60f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641485891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.1641485891 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.1342483588 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 561998901 ps |
| CPU time | 54.22 seconds |
| Started | Aug 06 09:01:49 PM PDT 24 |
| Finished | Aug 06 09:02:43 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-40e40cf6-38eb-4fdc-8ed4-926e347f6934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342483588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.1342483588 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.793469147 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 169351869 ps |
| CPU time | 17.31 seconds |
| Started | Aug 06 09:01:55 PM PDT 24 |
| Finished | Aug 06 09:02:13 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-6b065d0f-ba48-4543-80c5-3d55389581a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793469147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.793469147 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.3496845057 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 51808903 ps |
| CPU time | 6.42 seconds |
| Started | Aug 06 09:01:48 PM PDT 24 |
| Finished | Aug 06 09:01:54 PM PDT 24 |
| Peak memory | 574404 kb |
| Host | smart-322b15ed-f701-4864-ac8f-ea4296471f4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496845057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3496845057 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.564870141 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 7653578626 ps |
| CPU time | 81.4 seconds |
| Started | Aug 06 09:01:44 PM PDT 24 |
| Finished | Aug 06 09:03:06 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-ab1a5588-b72a-4643-95de-d65ca322ddb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=564870141 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.564870141 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.1972364 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 6420615243 ps |
| CPU time | 119.81 seconds |
| Started | Aug 06 09:01:46 PM PDT 24 |
| Finished | Aug 06 09:03:46 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-c2f64b0f-4a56-4348-a2d5-154e759ae9b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.1972364 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.2211304511 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 46868838 ps |
| CPU time | 6.61 seconds |
| Started | Aug 06 09:01:48 PM PDT 24 |
| Finished | Aug 06 09:01:55 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-c94f7e3d-1ef7-4388-b0cf-615cb57ac041 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211304511 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.2211304511 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.3016917642 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 8782123108 ps |
| CPU time | 321.19 seconds |
| Started | Aug 06 09:01:51 PM PDT 24 |
| Finished | Aug 06 09:07:12 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-99ef9b0d-fa50-4ea6-b8fb-806ea4a5721f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016917642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.3016917642 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3205788806 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 1077464060 ps |
| CPU time | 29.84 seconds |
| Started | Aug 06 09:01:50 PM PDT 24 |
| Finished | Aug 06 09:02:20 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-9b870cd7-d46c-47b0-ac93-61a9c474a22b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205788806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3205788806 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3835509395 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 1816704378 ps |
| CPU time | 472.99 seconds |
| Started | Aug 06 09:01:52 PM PDT 24 |
| Finished | Aug 06 09:09:45 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-67aab657-e153-4ec7-8d2e-4d22e95f5ff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835509395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.3835509395 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.1874697155 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 10046981714 ps |
| CPU time | 517.51 seconds |
| Started | Aug 06 09:01:51 PM PDT 24 |
| Finished | Aug 06 09:10:28 PM PDT 24 |
| Peak memory | 576748 kb |
| Host | smart-e6d37f5b-8fae-4045-8742-a28d684eec37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1874697155 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.1874697155 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1311013515 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 39904245 ps |
| CPU time | 7.82 seconds |
| Started | Aug 06 09:01:52 PM PDT 24 |
| Finished | Aug 06 09:02:00 PM PDT 24 |
| Peak memory | 574464 kb |
| Host | smart-11370e7f-d5ea-4fa3-9ae4-94bd433bab29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311013515 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1311013515 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.1276682781 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 777825886 ps |
| CPU time | 38.57 seconds |
| Started | Aug 06 09:02:01 PM PDT 24 |
| Finished | Aug 06 09:02:40 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-6dd6ac7a-e7b9-4745-b738-12f1e108164b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276682781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .1276682781 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.3588100960 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 53839937306 ps |
| CPU time | 951.25 seconds |
| Started | Aug 06 09:02:01 PM PDT 24 |
| Finished | Aug 06 09:17:52 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-f77c5440-2707-4459-9b67-14b45fd04e32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3588100960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.3588100960 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.4275406128 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1020960152 ps |
| CPU time | 41.92 seconds |
| Started | Aug 06 09:02:02 PM PDT 24 |
| Finished | Aug 06 09:02:44 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-bed8e0d6-34fb-446b-ba04-efbaa71c11c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275406128 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.4275406128 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.2701700766 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 1870083157 ps |
| CPU time | 70.04 seconds |
| Started | Aug 06 09:02:08 PM PDT 24 |
| Finished | Aug 06 09:03:18 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-b0fa8a0a-5796-4d85-91c4-40307d7e0bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701700766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.2701700766 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.2605805955 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 1925269273 ps |
| CPU time | 67.7 seconds |
| Started | Aug 06 09:01:58 PM PDT 24 |
| Finished | Aug 06 09:03:05 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-e1e529d3-b118-4f0a-b892-435783320985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605805955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.2605805955 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3270920103 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 90885683889 ps |
| CPU time | 960.21 seconds |
| Started | Aug 06 09:01:57 PM PDT 24 |
| Finished | Aug 06 09:17:57 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-8a8a980f-ec06-45ca-b38c-bd1d5fa71486 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270920103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.3270920103 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.488369415 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 50352525578 ps |
| CPU time | 863.39 seconds |
| Started | Aug 06 09:02:02 PM PDT 24 |
| Finished | Aug 06 09:16:26 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-6687febc-c1d7-433d-a817-99cc5225df81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488369415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.488369415 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1487036761 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 163111792 ps |
| CPU time | 19.47 seconds |
| Started | Aug 06 09:01:56 PM PDT 24 |
| Finished | Aug 06 09:02:15 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-b99f4ffe-bfc3-489e-8f00-d8ff28dbc74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487036761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.1487036761 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.2822353238 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 210236988 ps |
| CPU time | 10.09 seconds |
| Started | Aug 06 09:02:01 PM PDT 24 |
| Finished | Aug 06 09:02:12 PM PDT 24 |
| Peak memory | 573728 kb |
| Host | smart-4823b869-9bb9-4056-8b55-0972fc9fadcc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822353238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.2822353238 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.3465743887 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 231936052 ps |
| CPU time | 10.36 seconds |
| Started | Aug 06 09:01:56 PM PDT 24 |
| Finished | Aug 06 09:02:06 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-945bce7d-22d3-494e-aa03-181c07dd62b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465743887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.3465743887 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.322069837 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 9809552070 ps |
| CPU time | 103.11 seconds |
| Started | Aug 06 09:01:58 PM PDT 24 |
| Finished | Aug 06 09:03:41 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-7e41be56-6d93-4f28-8510-1bfc0d6ce037 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322069837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.322069837 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.1102722310 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 5725234640 ps |
| CPU time | 104.78 seconds |
| Started | Aug 06 09:01:56 PM PDT 24 |
| Finished | Aug 06 09:03:41 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-2da64273-e549-4964-b796-b5bc2606d79b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102722310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.1102722310 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1547348164 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 43748359 ps |
| CPU time | 6.83 seconds |
| Started | Aug 06 09:01:57 PM PDT 24 |
| Finished | Aug 06 09:02:04 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-f933598d-cb0e-4ec8-bc21-bf23737d7030 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547348164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.1547348164 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.501499195 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 4993410550 ps |
| CPU time | 185.51 seconds |
| Started | Aug 06 09:02:07 PM PDT 24 |
| Finished | Aug 06 09:05:13 PM PDT 24 |
| Peak memory | 576520 kb |
| Host | smart-9e2bfb2d-5598-4959-8521-e7b80f7ff220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501499195 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.501499195 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1409637917 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 6308644289 ps |
| CPU time | 204.59 seconds |
| Started | Aug 06 09:02:05 PM PDT 24 |
| Finished | Aug 06 09:05:30 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-0c37a6a4-18ca-4c77-96f3-d8f9ff93e767 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409637917 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1409637917 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.2581683487 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 3596021359 ps |
| CPU time | 339.32 seconds |
| Started | Aug 06 09:02:02 PM PDT 24 |
| Finished | Aug 06 09:07:42 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-a6530a64-c9f3-4b26-8bc2-8efef039aa75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581683487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.2581683487 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2417203618 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 5900418325 ps |
| CPU time | 274.59 seconds |
| Started | Aug 06 09:02:10 PM PDT 24 |
| Finished | Aug 06 09:06:44 PM PDT 24 |
| Peak memory | 576676 kb |
| Host | smart-fe623ab8-7500-4fec-b3a4-02f46f1d125e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417203618 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2417203618 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.417781373 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 245428499 ps |
| CPU time | 12.82 seconds |
| Started | Aug 06 09:02:02 PM PDT 24 |
| Finished | Aug 06 09:02:15 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-438e0c57-0a56-4469-afaa-bc4e2d929744 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417781373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.417781373 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.297073871 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 499086238 ps |
| CPU time | 44.37 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:03:04 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-ce51a986-6251-4169-baeb-9a4ce1f4c103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297073871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device. 297073871 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.3820253225 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 137494535182 ps |
| CPU time | 2474.55 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:43:34 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-23abdc60-3b16-4065-a7bc-3ad27449eb1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820253225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.3820253225 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.2156436201 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 269174228 ps |
| CPU time | 34.28 seconds |
| Started | Aug 06 09:02:12 PM PDT 24 |
| Finished | Aug 06 09:02:47 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-f21f3e72-db8d-490b-96ce-7188920ffc41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156436201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.2156436201 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.3298727068 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 408279033 ps |
| CPU time | 38.71 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:02:58 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-63f94bc2-c7de-4e5e-af90-2d380641c5f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298727068 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.3298727068 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1056094989 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 1878732853 ps |
| CPU time | 72.71 seconds |
| Started | Aug 06 09:02:10 PM PDT 24 |
| Finished | Aug 06 09:03:23 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-1db59788-8c5c-4a38-b5c3-6d2d6cb9ed88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056094989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1056094989 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.2885680017 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 53277223113 ps |
| CPU time | 589.89 seconds |
| Started | Aug 06 09:02:07 PM PDT 24 |
| Finished | Aug 06 09:11:57 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-ace1cd9c-f9af-4e5e-b7cf-9a213c29e523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885680017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.2885680017 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.1014448858 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 54252279355 ps |
| CPU time | 1017.73 seconds |
| Started | Aug 06 09:02:06 PM PDT 24 |
| Finished | Aug 06 09:19:04 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-e8aeacf4-255e-453c-8ef8-6c650af87a81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014448858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.1014448858 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.895477157 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 302237874 ps |
| CPU time | 33.44 seconds |
| Started | Aug 06 09:02:05 PM PDT 24 |
| Finished | Aug 06 09:02:38 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-c7cad954-a90a-4da2-bbec-abe0d7e38483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=895477157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_dela ys.895477157 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3498377318 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 1856490977 ps |
| CPU time | 61.14 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:03:21 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-8c2051a4-ee14-4aca-b06a-1aa2af31c490 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498377318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3498377318 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.1384188682 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 220153570 ps |
| CPU time | 10.14 seconds |
| Started | Aug 06 09:02:06 PM PDT 24 |
| Finished | Aug 06 09:02:16 PM PDT 24 |
| Peak memory | 573756 kb |
| Host | smart-005e31db-6198-4223-a315-c98dc0ec3284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384188682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1384188682 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.3350468235 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 8387591020 ps |
| CPU time | 89.75 seconds |
| Started | Aug 06 09:02:06 PM PDT 24 |
| Finished | Aug 06 09:03:36 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-94e81af3-0b53-4611-9732-87683729c85c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350468235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.3350468235 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3638543665 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 6130117066 ps |
| CPU time | 111.89 seconds |
| Started | Aug 06 09:02:07 PM PDT 24 |
| Finished | Aug 06 09:03:59 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-1509e382-eec3-45ec-808d-e9783792f440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638543665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.3638543665 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2844884174 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 44461906 ps |
| CPU time | 6.64 seconds |
| Started | Aug 06 09:02:07 PM PDT 24 |
| Finished | Aug 06 09:02:14 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-091d7919-8b4d-4618-ae86-53ff29ffa2ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844884174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.2844884174 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.1042717055 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 12305198289 ps |
| CPU time | 540.02 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:11:19 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-d2ec0bf6-4a00-497f-8c1c-aa5a8fe8d359 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042717055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.1042717055 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2592460940 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 11598918854 ps |
| CPU time | 421.13 seconds |
| Started | Aug 06 09:02:11 PM PDT 24 |
| Finished | Aug 06 09:09:12 PM PDT 24 |
| Peak memory | 576740 kb |
| Host | smart-2281399f-58ff-4ab3-a34f-9b594601b06e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592460940 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2592460940 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.156097013 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 1543152517 ps |
| CPU time | 159.45 seconds |
| Started | Aug 06 09:02:11 PM PDT 24 |
| Finished | Aug 06 09:04:51 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-5dd31960-5dc0-47e4-a64c-0a2c194e5426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156097013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_ with_rand_reset.156097013 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3850677298 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 390759882 ps |
| CPU time | 112.36 seconds |
| Started | Aug 06 09:02:17 PM PDT 24 |
| Finished | Aug 06 09:04:09 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-93d6569b-8a5d-4a7a-a434-173e0ea2f445 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850677298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.3850677298 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.1287132817 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 796933692 ps |
| CPU time | 37.35 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:02:57 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-930ae19c-8caf-4927-8933-36cb3515607b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287132817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.1287132817 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.816683391 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 1527580984 ps |
| CPU time | 78.15 seconds |
| Started | Aug 06 09:02:17 PM PDT 24 |
| Finished | Aug 06 09:03:35 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-9beef679-5402-499c-b916-3b46e144b5eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816683391 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device. 816683391 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2128195944 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 21767710298 ps |
| CPU time | 372.5 seconds |
| Started | Aug 06 09:02:26 PM PDT 24 |
| Finished | Aug 06 09:08:38 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-16e3d4b4-cee5-4c3a-a61d-ed744806419a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128195944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2128195944 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.3491999884 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 216674118 ps |
| CPU time | 26.96 seconds |
| Started | Aug 06 09:02:21 PM PDT 24 |
| Finished | Aug 06 09:02:48 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-862165a1-3174-4773-a8d3-e030975d1132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491999884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.3491999884 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.53538422 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 240102690 ps |
| CPU time | 11.77 seconds |
| Started | Aug 06 09:02:20 PM PDT 24 |
| Finished | Aug 06 09:02:31 PM PDT 24 |
| Peak memory | 573696 kb |
| Host | smart-8b2f9da6-01bd-4a48-a494-bdac394d9cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53538422 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.53538422 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2031300939 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 1940743639 ps |
| CPU time | 72.8 seconds |
| Started | Aug 06 09:02:18 PM PDT 24 |
| Finished | Aug 06 09:03:31 PM PDT 24 |
| Peak memory | 575720 kb |
| Host | smart-2b47d0cc-9ac4-4907-bf0b-aef4b41a25b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2031300939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2031300939 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3159329751 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 86228202791 ps |
| CPU time | 974.01 seconds |
| Started | Aug 06 09:02:15 PM PDT 24 |
| Finished | Aug 06 09:18:29 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-2cdb482c-6745-4d80-824b-60409c18085e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159329751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3159329751 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.593437582 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 50873723576 ps |
| CPU time | 931.1 seconds |
| Started | Aug 06 09:02:25 PM PDT 24 |
| Finished | Aug 06 09:17:56 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-c4d49595-53e1-4b41-a925-c5db1ae2200c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593437582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.593437582 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.3819096358 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 144455181 ps |
| CPU time | 16.58 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:02:35 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-cac9aaba-fd30-401f-b764-585825fa81ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819096358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.3819096358 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.2252218975 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 2133845179 ps |
| CPU time | 70.5 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:03:29 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-6e8c969c-408e-485f-8598-6a3e7e6e79e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252218975 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.2252218975 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.655206923 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 192986521 ps |
| CPU time | 8.78 seconds |
| Started | Aug 06 09:02:26 PM PDT 24 |
| Finished | Aug 06 09:02:34 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-953351c4-db01-482d-a846-cf9f3e7a64a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655206923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.655206923 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2873596794 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 7646562428 ps |
| CPU time | 78.56 seconds |
| Started | Aug 06 09:02:17 PM PDT 24 |
| Finished | Aug 06 09:03:36 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-e757b9be-1853-4062-b6ff-c1a0d3e70e3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873596794 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.2873596794 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3469702063 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 4015778890 ps |
| CPU time | 75.4 seconds |
| Started | Aug 06 09:02:17 PM PDT 24 |
| Finished | Aug 06 09:03:32 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-a7ebdf6b-058b-4e5e-886b-eac7b71d58dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469702063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3469702063 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.1889676654 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 37586108 ps |
| CPU time | 5.74 seconds |
| Started | Aug 06 09:02:19 PM PDT 24 |
| Finished | Aug 06 09:02:24 PM PDT 24 |
| Peak memory | 573716 kb |
| Host | smart-6639b625-76f9-4027-99eb-a3c5dc6fb2a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889676654 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.1889676654 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.3685248886 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 8806354645 ps |
| CPU time | 352.68 seconds |
| Started | Aug 06 09:02:24 PM PDT 24 |
| Finished | Aug 06 09:08:17 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-f6e59e05-f423-4e69-81f3-50d780c17782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685248886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.3685248886 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.626258622 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 2384635483 ps |
| CPU time | 189.4 seconds |
| Started | Aug 06 09:02:24 PM PDT 24 |
| Finished | Aug 06 09:05:34 PM PDT 24 |
| Peak memory | 575960 kb |
| Host | smart-18a01e11-72c5-428a-afa5-526dac1ec02f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626258622 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.626258622 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.3325848255 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 459426119 ps |
| CPU time | 251.41 seconds |
| Started | Aug 06 09:02:22 PM PDT 24 |
| Finished | Aug 06 09:06:33 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-16668e84-1019-4e9b-8a30-ce22e100a9b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325848255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all _with_rand_reset.3325848255 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.1156407354 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 307481601 ps |
| CPU time | 117.51 seconds |
| Started | Aug 06 09:02:23 PM PDT 24 |
| Finished | Aug 06 09:04:20 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-18607819-9e13-4af3-8517-9a069ec30273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156407354 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.1156407354 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.1299063072 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 568424857 ps |
| CPU time | 27.62 seconds |
| Started | Aug 06 09:02:17 PM PDT 24 |
| Finished | Aug 06 09:02:45 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-b8937433-ea3e-4d93-b041-9f5c8eb07110 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299063072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.1299063072 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2661634028 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 237104589 ps |
| CPU time | 22.39 seconds |
| Started | Aug 06 09:02:30 PM PDT 24 |
| Finished | Aug 06 09:02:52 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-85dbc26d-dd8c-4025-a598-e3ca7a404c08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661634028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .2661634028 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.346751128 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 51788636898 ps |
| CPU time | 897.41 seconds |
| Started | Aug 06 09:02:29 PM PDT 24 |
| Finished | Aug 06 09:17:27 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-a43f6590-feb0-4c22-b254-60aea30df909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346751128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.346751128 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.217402807 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 24211459 ps |
| CPU time | 5.82 seconds |
| Started | Aug 06 09:02:34 PM PDT 24 |
| Finished | Aug 06 09:02:39 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-8e795461-63f9-47da-b06e-99fd660788cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217402807 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_addr .217402807 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3852398315 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 332224378 ps |
| CPU time | 32.36 seconds |
| Started | Aug 06 09:02:27 PM PDT 24 |
| Finished | Aug 06 09:03:00 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-0deef8b8-c74a-4471-b722-7b8364e3c1fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852398315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3852398315 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.3509103650 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 1517203815 ps |
| CPU time | 54.01 seconds |
| Started | Aug 06 09:02:27 PM PDT 24 |
| Finished | Aug 06 09:03:21 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-55431d00-fd63-4811-9c0d-645c9a95f1b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509103650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.3509103650 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.2665193100 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 72714920199 ps |
| CPU time | 796.71 seconds |
| Started | Aug 06 09:02:30 PM PDT 24 |
| Finished | Aug 06 09:15:47 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-a340a24f-b707-44fd-a521-fd94b91023ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665193100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.2665193100 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.263374456 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 42614172688 ps |
| CPU time | 763.68 seconds |
| Started | Aug 06 09:02:30 PM PDT 24 |
| Finished | Aug 06 09:15:14 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-cc3a438d-a3f3-467a-a851-b8244a4cc032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263374456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.263374456 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.1655816533 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 300139617 ps |
| CPU time | 27.44 seconds |
| Started | Aug 06 09:02:31 PM PDT 24 |
| Finished | Aug 06 09:02:58 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-1e37609a-e89b-4d3a-8165-29e903510be8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655816533 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.1655816533 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.817444435 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 2730483309 ps |
| CPU time | 88.66 seconds |
| Started | Aug 06 09:02:27 PM PDT 24 |
| Finished | Aug 06 09:03:56 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-4ea93797-84b5-41d0-96bf-fbfe6f87a243 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817444435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.817444435 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.1258636870 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 207758689 ps |
| CPU time | 8.96 seconds |
| Started | Aug 06 09:02:26 PM PDT 24 |
| Finished | Aug 06 09:02:35 PM PDT 24 |
| Peak memory | 573780 kb |
| Host | smart-113e85e2-1d28-474e-8eba-f7473d8a4733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258636870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.1258636870 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.2587217644 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 10237253017 ps |
| CPU time | 108.55 seconds |
| Started | Aug 06 09:02:29 PM PDT 24 |
| Finished | Aug 06 09:04:18 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-8a4f2098-d6ca-4666-9182-5936e6fd1974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2587217644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.2587217644 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.3181853128 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 6592315388 ps |
| CPU time | 119.46 seconds |
| Started | Aug 06 09:02:29 PM PDT 24 |
| Finished | Aug 06 09:04:28 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-fd1952af-4035-4506-b250-9d1adf30dfdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181853128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.3181853128 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.2583614880 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 39689809 ps |
| CPU time | 6.52 seconds |
| Started | Aug 06 09:02:23 PM PDT 24 |
| Finished | Aug 06 09:02:30 PM PDT 24 |
| Peak memory | 574452 kb |
| Host | smart-0be81ca6-300f-4e27-a870-ea8545f7af0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583614880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.2583614880 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.1957021179 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 10340983715 ps |
| CPU time | 364.76 seconds |
| Started | Aug 06 09:02:36 PM PDT 24 |
| Finished | Aug 06 09:08:41 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-c50d9e1c-6d23-4035-924f-58e1e67da879 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957021179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.1957021179 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.2878222820 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 22829803183 ps |
| CPU time | 1111.76 seconds |
| Started | Aug 06 09:02:34 PM PDT 24 |
| Finished | Aug 06 09:21:06 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-2af9ae79-71c9-43d0-975c-6e79f7b09b2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878222820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.2878222820 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3604557266 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 224870439 ps |
| CPU time | 75.42 seconds |
| Started | Aug 06 09:02:36 PM PDT 24 |
| Finished | Aug 06 09:03:52 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-832eb0f9-1760-40dc-8d79-f06eb594bde9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604557266 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_al l_with_reset_error.3604557266 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3956112980 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 235239969 ps |
| CPU time | 28.99 seconds |
| Started | Aug 06 09:02:28 PM PDT 24 |
| Finished | Aug 06 09:02:57 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-687f3562-5393-4aba-b531-eacf90dee23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956112980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3956112980 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2050514726 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 9337766877 ps |
| CPU time | 734.8 seconds |
| Started | Aug 06 08:47:45 PM PDT 24 |
| Finished | Aug 06 09:00:00 PM PDT 24 |
| Peak memory | 652952 kb |
| Host | smart-3765786f-c8a2-4595-8ed9-dc09a104c33a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050514726 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.2050514726 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.1371068631 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 6151361786 ps |
| CPU time | 596.57 seconds |
| Started | Aug 06 08:47:45 PM PDT 24 |
| Finished | Aug 06 08:57:42 PM PDT 24 |
| Peak memory | 598452 kb |
| Host | smart-5bad382a-db1a-41ed-b1c9-ffa1648d4f6d |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371068631 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.1371068631 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.1758898348 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 14997764473 ps |
| CPU time | 2183.02 seconds |
| Started | Aug 06 08:47:01 PM PDT 24 |
| Finished | Aug 06 09:23:24 PM PDT 24 |
| Peak memory | 592888 kb |
| Host | smart-0c417381-811f-4c42-aae6-3d2e21be1a09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758898348 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.1758898348 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.1428296437 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 4065034184 ps |
| CPU time | 298.55 seconds |
| Started | Aug 06 08:46:59 PM PDT 24 |
| Finished | Aug 06 08:51:58 PM PDT 24 |
| Peak memory | 603684 kb |
| Host | smart-7018344d-2c0c-45f5-a349-7369b38f8e93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428296437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.1428296437 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.501349733 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 2206112899 ps |
| CPU time | 103.28 seconds |
| Started | Aug 06 08:47:13 PM PDT 24 |
| Finished | Aug 06 08:48:56 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-3c077f4e-cd6a-43a4-b2cd-fb681a55720d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501349733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.501349733 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.21062904 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 98658238170 ps |
| CPU time | 1763.43 seconds |
| Started | Aug 06 08:47:18 PM PDT 24 |
| Finished | Aug 06 09:16:42 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4a702853-5ea5-43d3-b62f-b851acb9b1da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21062904 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_dev ice_slow_rsp.21062904 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.3499708710 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 173699252 ps |
| CPU time | 22.11 seconds |
| Started | Aug 06 08:47:23 PM PDT 24 |
| Finished | Aug 06 08:47:45 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-376ecbe9-9145-4bf4-af91-31beaccd9b5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499708710 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr .3499708710 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.3756516675 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 2393910682 ps |
| CPU time | 94.82 seconds |
| Started | Aug 06 08:47:25 PM PDT 24 |
| Finished | Aug 06 08:49:00 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-36df24bc-c16f-40e4-b606-00f272bb426d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756516675 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3756516675 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.3043813305 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 181621106 ps |
| CPU time | 11.99 seconds |
| Started | Aug 06 08:47:14 PM PDT 24 |
| Finished | Aug 06 08:47:26 PM PDT 24 |
| Peak memory | 574424 kb |
| Host | smart-7e20a257-f36c-485d-a934-bd50f9c0bcad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043813305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.3043813305 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.938170982 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 47557533119 ps |
| CPU time | 530.71 seconds |
| Started | Aug 06 08:47:12 PM PDT 24 |
| Finished | Aug 06 08:56:03 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-95716087-129c-41a7-a85f-8d3b33a3198e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938170982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.938170982 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1320085717 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 18775577531 ps |
| CPU time | 332.23 seconds |
| Started | Aug 06 08:47:15 PM PDT 24 |
| Finished | Aug 06 08:52:47 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-08abbc0a-0a0c-4d79-aa72-9287cf1d1407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320085717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.1320085717 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.1074520588 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 156284382 ps |
| CPU time | 17.88 seconds |
| Started | Aug 06 08:47:17 PM PDT 24 |
| Finished | Aug 06 08:47:34 PM PDT 24 |
| Peak memory | 575956 kb |
| Host | smart-bcd353be-07ed-4e8b-9b57-cd985d64cd94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074520588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.1074520588 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.4042453228 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 435252822 ps |
| CPU time | 38.7 seconds |
| Started | Aug 06 08:47:19 PM PDT 24 |
| Finished | Aug 06 08:47:58 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-74c57658-1915-408e-b28e-6ebb02980ec7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042453228 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.4042453228 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.3647742900 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 49239049 ps |
| CPU time | 7.13 seconds |
| Started | Aug 06 08:47:10 PM PDT 24 |
| Finished | Aug 06 08:47:17 PM PDT 24 |
| Peak memory | 573764 kb |
| Host | smart-ef2fb86c-3149-4c05-801b-5df166d7a846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647742900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.3647742900 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.299541682 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 7945599389 ps |
| CPU time | 81.19 seconds |
| Started | Aug 06 08:47:16 PM PDT 24 |
| Finished | Aug 06 08:48:37 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-6f44d33f-5259-43de-b5f5-9c1d09761b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299541682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.299541682 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.69506277 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 5357024533 ps |
| CPU time | 89.35 seconds |
| Started | Aug 06 08:47:14 PM PDT 24 |
| Finished | Aug 06 08:48:44 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-0cc89b1a-78e6-4ffa-a403-dc90d70797d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69506277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.69506277 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.1097962545 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 53935536 ps |
| CPU time | 6.99 seconds |
| Started | Aug 06 08:47:07 PM PDT 24 |
| Finished | Aug 06 08:47:14 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-8cc417df-a633-4488-906b-b2659f0e3d7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097962545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .1097962545 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.3922251633 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 2937209340 ps |
| CPU time | 107.17 seconds |
| Started | Aug 06 08:47:28 PM PDT 24 |
| Finished | Aug 06 08:49:15 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-daa9fe6c-f002-4307-b3d0-829596a63064 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922251633 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.3922251633 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.2445021119 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 1746020296 ps |
| CPU time | 70.3 seconds |
| Started | Aug 06 08:47:31 PM PDT 24 |
| Finished | Aug 06 08:48:41 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-07f02072-c52a-4bb7-8029-11c10a04a483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445021119 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.2445021119 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.2145903065 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 62119710 ps |
| CPU time | 30.95 seconds |
| Started | Aug 06 08:47:25 PM PDT 24 |
| Finished | Aug 06 08:47:56 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-24d5d2d4-94c3-4ade-bcc9-8975e2dc5fee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145903065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.2145903065 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.2223721205 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 892436807 ps |
| CPU time | 197.91 seconds |
| Started | Aug 06 08:47:31 PM PDT 24 |
| Finished | Aug 06 08:50:49 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-7f1552ed-2ea0-471d-bfe6-2e900bf1de82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223721205 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.2223721205 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.66334671 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 1239107406 ps |
| CPU time | 61.3 seconds |
| Started | Aug 06 08:47:22 PM PDT 24 |
| Finished | Aug 06 08:48:24 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-08202bc0-5379-427b-96a1-23c9974c63c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66334671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.66334671 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.1856895775 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 953530553 ps |
| CPU time | 44.15 seconds |
| Started | Aug 06 09:02:44 PM PDT 24 |
| Finished | Aug 06 09:03:29 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-9e2c9af8-52f3-4940-9888-4a35162acabd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856895775 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .1856895775 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.1680795959 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 43813685237 ps |
| CPU time | 753.5 seconds |
| Started | Aug 06 09:02:44 PM PDT 24 |
| Finished | Aug 06 09:15:18 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-8dd1fe43-a562-45e3-93d7-fcc0e77286b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680795959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.1680795959 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.2104041264 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 54929770 ps |
| CPU time | 8.85 seconds |
| Started | Aug 06 09:02:38 PM PDT 24 |
| Finished | Aug 06 09:02:47 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-da78c76e-4bfc-4e7b-98ee-dc41bee64b54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104041264 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_add r.2104041264 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.2675473758 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 116424705 ps |
| CPU time | 11.71 seconds |
| Started | Aug 06 09:02:44 PM PDT 24 |
| Finished | Aug 06 09:02:56 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-6454b91b-1dd0-4905-a549-38cf45182883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2675473758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.2675473758 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.369218438 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 422544056 ps |
| CPU time | 44.15 seconds |
| Started | Aug 06 09:02:38 PM PDT 24 |
| Finished | Aug 06 09:03:22 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-480f59d6-f4c4-4bd7-acd3-00077724d3e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369218438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.369218438 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.2641913006 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 37079368940 ps |
| CPU time | 398.42 seconds |
| Started | Aug 06 09:02:39 PM PDT 24 |
| Finished | Aug 06 09:09:18 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-ccdb741b-a671-4c9b-9836-84e0a21b74c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641913006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.2641913006 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.2788217840 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 16280815893 ps |
| CPU time | 301.47 seconds |
| Started | Aug 06 09:02:43 PM PDT 24 |
| Finished | Aug 06 09:07:45 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-485d48c8-5fe4-4712-b1bf-9412538e3fb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788217840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.2788217840 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.1710626993 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 393009290 ps |
| CPU time | 38.25 seconds |
| Started | Aug 06 09:02:40 PM PDT 24 |
| Finished | Aug 06 09:03:18 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-cde05e21-3537-44f6-9bcf-e0f7dcde139b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1710626993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.1710626993 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.3424270981 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 1021762254 ps |
| CPU time | 30.73 seconds |
| Started | Aug 06 09:02:38 PM PDT 24 |
| Finished | Aug 06 09:03:09 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-27a31b3e-98c0-4c4b-898f-e0895a341044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424270981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.3424270981 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.1005731622 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 45276667 ps |
| CPU time | 6.34 seconds |
| Started | Aug 06 09:02:34 PM PDT 24 |
| Finished | Aug 06 09:02:40 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-02b102fc-24af-401b-933f-d1282f69e64f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005731622 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.1005731622 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.4092130482 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 6607012165 ps |
| CPU time | 71.56 seconds |
| Started | Aug 06 09:02:33 PM PDT 24 |
| Finished | Aug 06 09:03:44 PM PDT 24 |
| Peak memory | 574508 kb |
| Host | smart-2bd22552-2e3b-45c1-b01c-a36446559a51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092130482 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.4092130482 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.1959123374 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 5212742110 ps |
| CPU time | 91.19 seconds |
| Started | Aug 06 09:02:32 PM PDT 24 |
| Finished | Aug 06 09:04:04 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-67c07ab1-0e6c-400e-b22c-a991a08707f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959123374 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.1959123374 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.2472929762 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 45793043 ps |
| CPU time | 6.46 seconds |
| Started | Aug 06 09:02:34 PM PDT 24 |
| Finished | Aug 06 09:02:41 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-b3bda044-775e-4b84-85a6-8e192a9377d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472929762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.2472929762 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.2105543862 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 2149963656 ps |
| CPU time | 215.32 seconds |
| Started | Aug 06 09:02:52 PM PDT 24 |
| Finished | Aug 06 09:06:27 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-c92abe8f-1506-4b51-8821-3d7e6aabe917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105543862 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2105543862 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.4194057702 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 2704583401 ps |
| CPU time | 103.62 seconds |
| Started | Aug 06 09:02:46 PM PDT 24 |
| Finished | Aug 06 09:04:29 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-b0083cd7-82d7-4d08-918a-e02fde1cba97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194057702 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.4194057702 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.261591524 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 4521660207 ps |
| CPU time | 524.73 seconds |
| Started | Aug 06 09:02:45 PM PDT 24 |
| Finished | Aug 06 09:11:30 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-bbfc7be1-6b9a-4f9e-a203-3c5a47dc8313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261591524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_ with_rand_reset.261591524 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.522689646 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 225707694 ps |
| CPU time | 77.49 seconds |
| Started | Aug 06 09:02:46 PM PDT 24 |
| Finished | Aug 06 09:04:04 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-7d2a58dd-1c93-49ff-bf3f-237a87059153 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522689646 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_reset_error.522689646 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.4089147660 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 215920614 ps |
| CPU time | 12.72 seconds |
| Started | Aug 06 09:02:38 PM PDT 24 |
| Finished | Aug 06 09:02:51 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-a2488119-9975-49a4-a7c9-1e89a77c9c11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089147660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.4089147660 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.3823963922 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 796646750 ps |
| CPU time | 69.75 seconds |
| Started | Aug 06 09:02:53 PM PDT 24 |
| Finished | Aug 06 09:04:03 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-c28a40ae-ceaa-403c-9706-87e9da991aa0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823963922 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .3823963922 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.1848463530 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 146410344964 ps |
| CPU time | 2559.73 seconds |
| Started | Aug 06 09:02:49 PM PDT 24 |
| Finished | Aug 06 09:45:29 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-50a5152c-361a-48e5-8463-a7b300fddb89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1848463530 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.1848463530 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.941024505 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 52673037 ps |
| CPU time | 8.68 seconds |
| Started | Aug 06 09:02:51 PM PDT 24 |
| Finished | Aug 06 09:02:59 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-d32e5240-82e8-4c3d-9b45-a169079c41ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941024505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_addr .941024505 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.297601933 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 2097661211 ps |
| CPU time | 68.18 seconds |
| Started | Aug 06 09:02:52 PM PDT 24 |
| Finished | Aug 06 09:04:00 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-a74e9762-a901-46aa-8195-354ecda73540 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297601933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.297601933 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.2257090543 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 1748361128 ps |
| CPU time | 65.58 seconds |
| Started | Aug 06 09:02:53 PM PDT 24 |
| Finished | Aug 06 09:03:59 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-b8253119-9fdb-448c-994b-f3ff71bb1857 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257090543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.2257090543 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2654807401 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 85445011562 ps |
| CPU time | 886.86 seconds |
| Started | Aug 06 09:02:50 PM PDT 24 |
| Finished | Aug 06 09:17:37 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-089d423d-f07b-43ed-8b6b-20fbccdedfbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654807401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.2654807401 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.1675093551 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 4434292553 ps |
| CPU time | 79.98 seconds |
| Started | Aug 06 09:02:53 PM PDT 24 |
| Finished | Aug 06 09:04:13 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-de002af4-f12e-4316-b3bc-0f2066ba6ee4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1675093551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.1675093551 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.2145923802 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 179751288 ps |
| CPU time | 17.94 seconds |
| Started | Aug 06 09:02:51 PM PDT 24 |
| Finished | Aug 06 09:03:09 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-5e315cf1-241a-49b1-a90e-c06b92719e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145923802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.2145923802 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.1170057695 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 2743270042 ps |
| CPU time | 94.97 seconds |
| Started | Aug 06 09:02:53 PM PDT 24 |
| Finished | Aug 06 09:04:28 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-032732e0-0090-4469-a0eb-8cd747f4bef7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170057695 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1170057695 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.186131937 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 191862721 ps |
| CPU time | 9.28 seconds |
| Started | Aug 06 09:02:44 PM PDT 24 |
| Finished | Aug 06 09:02:53 PM PDT 24 |
| Peak memory | 574320 kb |
| Host | smart-46479d4f-d939-4522-a50b-cd8b9821f224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186131937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.186131937 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2554252364 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 8640070523 ps |
| CPU time | 88.6 seconds |
| Started | Aug 06 09:02:43 PM PDT 24 |
| Finished | Aug 06 09:04:12 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-c430e408-3224-44f1-9479-5d66bb5a36e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554252364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2554252364 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2174994730 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 4259973517 ps |
| CPU time | 81.33 seconds |
| Started | Aug 06 09:02:45 PM PDT 24 |
| Finished | Aug 06 09:04:07 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-9f3b198b-6ec8-433b-a2a0-6931162b83e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2174994730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2174994730 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.737364628 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 50298780 ps |
| CPU time | 6.73 seconds |
| Started | Aug 06 09:02:45 PM PDT 24 |
| Finished | Aug 06 09:02:52 PM PDT 24 |
| Peak memory | 573700 kb |
| Host | smart-b5d6ae6a-01a2-4faa-8f82-de6d9abd0a2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737364628 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delays .737364628 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.2163986191 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2616522616 ps |
| CPU time | 221.53 seconds |
| Started | Aug 06 09:02:52 PM PDT 24 |
| Finished | Aug 06 09:06:33 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-c079272b-60d3-4e37-a934-588784337984 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163986191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.2163986191 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.259177238 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 3434182583 ps |
| CPU time | 125.44 seconds |
| Started | Aug 06 09:02:56 PM PDT 24 |
| Finished | Aug 06 09:05:01 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-aef00578-5be7-44d3-a161-f17f3e32b438 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259177238 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.259177238 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.4025682060 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 8757746119 ps |
| CPU time | 423.36 seconds |
| Started | Aug 06 09:02:53 PM PDT 24 |
| Finished | Aug 06 09:09:57 PM PDT 24 |
| Peak memory | 576744 kb |
| Host | smart-b543d8c6-57be-43e8-a627-2f5a484d0a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025682060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.4025682060 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.2401939286 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 4871600557 ps |
| CPU time | 469.05 seconds |
| Started | Aug 06 09:02:58 PM PDT 24 |
| Finished | Aug 06 09:10:47 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-21eaca87-1bbb-4d7c-8cf6-8e4b4fd30f92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401939286 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.2401939286 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.3827114565 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 80434532 ps |
| CPU time | 6.81 seconds |
| Started | Aug 06 09:02:49 PM PDT 24 |
| Finished | Aug 06 09:02:56 PM PDT 24 |
| Peak memory | 573776 kb |
| Host | smart-c8316a6b-03c0-4967-a31d-3484a2d1c85a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827114565 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.3827114565 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.2683167050 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 1291582490 ps |
| CPU time | 102.03 seconds |
| Started | Aug 06 09:03:01 PM PDT 24 |
| Finished | Aug 06 09:04:43 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-0eb72c87-e7ac-4801-925d-4dab81e4e308 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683167050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .2683167050 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.1088285180 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 104571202044 ps |
| CPU time | 1901.47 seconds |
| Started | Aug 06 09:03:01 PM PDT 24 |
| Finished | Aug 06 09:34:42 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-c89dcb0e-dcd0-4265-a4e3-f181fb9216c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088285180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.1088285180 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.1235072506 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 472645103 ps |
| CPU time | 20.46 seconds |
| Started | Aug 06 09:03:00 PM PDT 24 |
| Finished | Aug 06 09:03:20 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-728bb36d-94b4-4d6b-a69c-9a751aebb30c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235072506 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.1235072506 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.3197837277 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 553974970 ps |
| CPU time | 23.97 seconds |
| Started | Aug 06 09:03:00 PM PDT 24 |
| Finished | Aug 06 09:03:24 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-e20bd2c1-f804-4dbe-9b76-4a7110ffa0cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3197837277 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.3197837277 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.1339663620 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 1173991342 ps |
| CPU time | 47.31 seconds |
| Started | Aug 06 09:03:01 PM PDT 24 |
| Finished | Aug 06 09:03:48 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-6bbf83bc-45fa-4005-b9ec-a2c2e422c315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339663620 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.1339663620 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.1643380048 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 81820961412 ps |
| CPU time | 821.62 seconds |
| Started | Aug 06 09:02:54 PM PDT 24 |
| Finished | Aug 06 09:16:36 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-f6c86fdc-b43e-4b68-a0ba-dc656d43ad46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643380048 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.1643380048 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3522007001 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 55809548085 ps |
| CPU time | 911.86 seconds |
| Started | Aug 06 09:03:00 PM PDT 24 |
| Finished | Aug 06 09:18:12 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-83e2b135-6b64-4013-a7e2-e5635ad334a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522007001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.3522007001 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.2668002477 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 167787592 ps |
| CPU time | 15.63 seconds |
| Started | Aug 06 09:03:00 PM PDT 24 |
| Finished | Aug 06 09:03:16 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-d83f7aa6-cc03-4386-a262-1147af78bc05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668002477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.2668002477 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.47480849 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 499219657 ps |
| CPU time | 41.58 seconds |
| Started | Aug 06 09:03:01 PM PDT 24 |
| Finished | Aug 06 09:03:43 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-24b2a495-6e0c-4893-9936-878ae677e44f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47480849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.47480849 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.1290526035 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 44260814 ps |
| CPU time | 7.24 seconds |
| Started | Aug 06 09:02:56 PM PDT 24 |
| Finished | Aug 06 09:03:03 PM PDT 24 |
| Peak memory | 573660 kb |
| Host | smart-e25cad59-87c0-4d0d-873a-d2fa1de16171 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1290526035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.1290526035 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.1669261274 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 7911339289 ps |
| CPU time | 85.21 seconds |
| Started | Aug 06 09:02:56 PM PDT 24 |
| Finished | Aug 06 09:04:21 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-215a13ae-34e1-4211-a995-826e9872bc42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669261274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.1669261274 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2001122273 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 4154886887 ps |
| CPU time | 74.53 seconds |
| Started | Aug 06 09:02:58 PM PDT 24 |
| Finished | Aug 06 09:04:12 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-45a63cb2-82c4-4fcb-a64e-97ebcaaafb6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001122273 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2001122273 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.2764080230 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 54813004 ps |
| CPU time | 6.86 seconds |
| Started | Aug 06 09:02:55 PM PDT 24 |
| Finished | Aug 06 09:03:02 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-f0ba80aa-df62-40dc-aa16-769301f252f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764080230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.2764080230 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.960146724 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 5472850921 ps |
| CPU time | 202.75 seconds |
| Started | Aug 06 09:03:00 PM PDT 24 |
| Finished | Aug 06 09:06:23 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-30a6a5d2-0662-43c2-94a5-f092cf1dcaed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960146724 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.960146724 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1124070291 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 2995893143 ps |
| CPU time | 234.86 seconds |
| Started | Aug 06 09:03:04 PM PDT 24 |
| Finished | Aug 06 09:06:59 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-e70ac3a0-5b68-4c90-9dd5-b2f7905e7846 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124070291 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1124070291 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.2691117528 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 66469301 ps |
| CPU time | 22.47 seconds |
| Started | Aug 06 09:03:00 PM PDT 24 |
| Finished | Aug 06 09:03:23 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-4c95a162-3fe8-4552-9749-93434fc961d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691117528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all _with_rand_reset.2691117528 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1552709002 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 3054988589 ps |
| CPU time | 283.52 seconds |
| Started | Aug 06 09:02:59 PM PDT 24 |
| Finished | Aug 06 09:07:43 PM PDT 24 |
| Peak memory | 576696 kb |
| Host | smart-ece251e1-5499-4e61-80ee-4dd7637a93ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1552709002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.1552709002 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.1426030174 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 222331290 ps |
| CPU time | 28.67 seconds |
| Started | Aug 06 09:02:59 PM PDT 24 |
| Finished | Aug 06 09:03:28 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-1c628ccb-5f2d-45f1-a21c-81bf5fae8796 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426030174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.1426030174 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.1746551764 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 1166621525 ps |
| CPU time | 55.17 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:04:04 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-93a476c0-cd96-42d0-9c8f-074e74fc886f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746551764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device .1746551764 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.1867168392 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 60626858068 ps |
| CPU time | 1066.55 seconds |
| Started | Aug 06 09:03:08 PM PDT 24 |
| Finished | Aug 06 09:20:55 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-0128a38e-c4d6-4c49-acc5-c718dd097c0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867168392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.1867168392 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3565691292 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 116206389 ps |
| CPU time | 14.68 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:03:23 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-9552ba21-7598-4a5e-85b4-2057a80c7e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3565691292 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.3565691292 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.2961706884 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 160515316 ps |
| CPU time | 9.21 seconds |
| Started | Aug 06 09:03:08 PM PDT 24 |
| Finished | Aug 06 09:03:17 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-bdb6a8fc-0d0b-452c-b71b-8436d293d925 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961706884 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.2961706884 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.1946178111 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 138054078 ps |
| CPU time | 8.59 seconds |
| Started | Aug 06 09:03:08 PM PDT 24 |
| Finished | Aug 06 09:03:17 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-e3372e64-c5aa-4153-8c13-6462155342b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946178111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.1946178111 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.3799154834 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 21561921355 ps |
| CPU time | 218.69 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:06:48 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-cf14c734-6f19-43e0-9123-b1d441811150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799154834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.3799154834 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.623846843 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 16636836590 ps |
| CPU time | 290.24 seconds |
| Started | Aug 06 09:03:07 PM PDT 24 |
| Finished | Aug 06 09:07:57 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-c45f0f42-88de-4075-a7ed-758a15557514 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623846843 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.623846843 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.617210234 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 532996200 ps |
| CPU time | 49.51 seconds |
| Started | Aug 06 09:03:07 PM PDT 24 |
| Finished | Aug 06 09:03:57 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-ca110716-c130-4209-87bf-9a2949b85977 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617210234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_dela ys.617210234 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.3313199356 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 315762627 ps |
| CPU time | 21.13 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:03:30 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-fb07f2cb-1c7b-4f8f-9551-dec21619248c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313199356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.3313199356 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.2737587210 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 202204510 ps |
| CPU time | 9.91 seconds |
| Started | Aug 06 09:03:00 PM PDT 24 |
| Finished | Aug 06 09:03:10 PM PDT 24 |
| Peak memory | 574400 kb |
| Host | smart-aacaf37d-1024-4b3b-b2c8-1b17017d2ffa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2737587210 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.2737587210 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.2479650113 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 8372564933 ps |
| CPU time | 87.79 seconds |
| Started | Aug 06 09:03:05 PM PDT 24 |
| Finished | Aug 06 09:04:32 PM PDT 24 |
| Peak memory | 574476 kb |
| Host | smart-beb47603-c40a-4a0d-834a-e9d1f6d222ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479650113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.2479650113 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.651632100 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 3461077864 ps |
| CPU time | 58.02 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:04:07 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-ae55d912-32fc-43e5-8eb8-84057f078282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651632100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.651632100 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.31681864 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 42532663 ps |
| CPU time | 6.64 seconds |
| Started | Aug 06 09:03:01 PM PDT 24 |
| Finished | Aug 06 09:03:08 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-eeb3a30f-8143-43cc-87a7-0efe69eacff6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31681864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delays.31681864 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.1762021206 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 8238998516 ps |
| CPU time | 356.81 seconds |
| Started | Aug 06 09:03:11 PM PDT 24 |
| Finished | Aug 06 09:09:07 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-1a2205f9-dccb-45f0-85d3-54dafdb5b389 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762021206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1762021206 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.250404860 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 7448172326 ps |
| CPU time | 247.8 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:07:17 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-e90e684c-b0e2-4f92-8f2b-4cbc8a027473 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250404860 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.250404860 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.2528298740 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 163890775 ps |
| CPU time | 64.61 seconds |
| Started | Aug 06 09:03:14 PM PDT 24 |
| Finished | Aug 06 09:04:19 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-9b924c3f-b72e-47d2-8f3e-590c48c80c10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528298740 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.2528298740 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.3672406247 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 79023219 ps |
| CPU time | 12.13 seconds |
| Started | Aug 06 09:03:09 PM PDT 24 |
| Finished | Aug 06 09:03:21 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-b6f4adf4-b810-4cb6-853b-640bfc735b42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672406247 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.3672406247 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.99617581 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 982435657 ps |
| CPU time | 45.12 seconds |
| Started | Aug 06 09:03:12 PM PDT 24 |
| Finished | Aug 06 09:03:58 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-0487b59d-5616-4356-8fa1-e9f05f3fe93d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99617581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device.99617581 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1809117515 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 335485095 ps |
| CPU time | 39.71 seconds |
| Started | Aug 06 09:03:13 PM PDT 24 |
| Finished | Aug 06 09:03:53 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-600f5a0c-593d-4deb-841a-7076717d5f35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809117515 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.1809117515 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.3182872005 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 1057492557 ps |
| CPU time | 40.72 seconds |
| Started | Aug 06 09:03:19 PM PDT 24 |
| Finished | Aug 06 09:04:00 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-8d73f529-ef4d-4b0a-aa73-37eccc90a4f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182872005 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.3182872005 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.1085479916 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 1956300160 ps |
| CPU time | 75 seconds |
| Started | Aug 06 09:03:15 PM PDT 24 |
| Finished | Aug 06 09:04:31 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-d7d0b051-74bc-4dea-8436-88634a87cd52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085479916 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.1085479916 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.886487562 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 32228456131 ps |
| CPU time | 353.46 seconds |
| Started | Aug 06 09:03:14 PM PDT 24 |
| Finished | Aug 06 09:09:07 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-bf283877-6ed0-4154-a143-b03250a5c997 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886487562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.886487562 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.1479101234 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 49151537947 ps |
| CPU time | 823.43 seconds |
| Started | Aug 06 09:03:14 PM PDT 24 |
| Finished | Aug 06 09:16:58 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-de1eb7dc-18ae-4188-aa9c-5a8b84273918 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479101234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.1479101234 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.1534015124 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 186099238 ps |
| CPU time | 20.73 seconds |
| Started | Aug 06 09:03:13 PM PDT 24 |
| Finished | Aug 06 09:03:33 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-20599541-b89d-4023-9046-4167332fe97f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534015124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.1534015124 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.2434602640 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 1879861273 ps |
| CPU time | 62.61 seconds |
| Started | Aug 06 09:03:12 PM PDT 24 |
| Finished | Aug 06 09:04:15 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-6ce59cb2-f9bf-4c02-9660-fb84b159376d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434602640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.2434602640 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.1009860662 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 53545065 ps |
| CPU time | 6.81 seconds |
| Started | Aug 06 09:03:14 PM PDT 24 |
| Finished | Aug 06 09:03:21 PM PDT 24 |
| Peak memory | 574460 kb |
| Host | smart-12056764-7e4e-4d9a-a467-170e4544f0ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009860662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.1009860662 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.1773438066 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 5561654349 ps |
| CPU time | 61.56 seconds |
| Started | Aug 06 09:03:13 PM PDT 24 |
| Finished | Aug 06 09:04:14 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-cf3410a6-b223-4dda-b05e-4fd0f8a7ee6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773438066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.1773438066 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.3368983342 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 5654575749 ps |
| CPU time | 94.19 seconds |
| Started | Aug 06 09:03:12 PM PDT 24 |
| Finished | Aug 06 09:04:47 PM PDT 24 |
| Peak memory | 575812 kb |
| Host | smart-d9fb539c-65b2-4e93-ba20-3b09b71b27b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368983342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.3368983342 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.4081922884 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 54550758 ps |
| CPU time | 7.73 seconds |
| Started | Aug 06 09:03:18 PM PDT 24 |
| Finished | Aug 06 09:03:26 PM PDT 24 |
| Peak memory | 574392 kb |
| Host | smart-91797024-beb5-45a7-a41d-010ef9757a05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081922884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.4081922884 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.2184434699 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 9154748849 ps |
| CPU time | 374.58 seconds |
| Started | Aug 06 09:03:14 PM PDT 24 |
| Finished | Aug 06 09:09:29 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-c6dd884e-5f03-4294-90b8-73e8fc5d0606 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184434699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.2184434699 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.2334024062 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 9788965788 ps |
| CPU time | 346.11 seconds |
| Started | Aug 06 09:03:16 PM PDT 24 |
| Finished | Aug 06 09:09:02 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-5cbfbe1d-9577-44d9-858d-c70c5e753aad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334024062 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.2334024062 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.841570129 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3586421677 ps |
| CPU time | 578.9 seconds |
| Started | Aug 06 09:03:14 PM PDT 24 |
| Finished | Aug 06 09:12:53 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-119fd824-104a-45e4-8d5f-dc859caee8e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841570129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_ with_rand_reset.841570129 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.2642366988 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 16446195230 ps |
| CPU time | 679.81 seconds |
| Started | Aug 06 09:03:14 PM PDT 24 |
| Finished | Aug 06 09:14:34 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-eec3b25d-8367-41af-be8e-8d39feaba43f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642366988 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.2642366988 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.2780339399 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 1242492980 ps |
| CPU time | 61.63 seconds |
| Started | Aug 06 09:03:13 PM PDT 24 |
| Finished | Aug 06 09:04:15 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-33726782-7716-440b-94f8-6cb7782dc31a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780339399 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.2780339399 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.1720951148 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 421486437 ps |
| CPU time | 18.69 seconds |
| Started | Aug 06 09:03:23 PM PDT 24 |
| Finished | Aug 06 09:03:42 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-5a6f8e16-64d3-4caa-9933-b32782a3a48d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720951148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device .1720951148 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3231064229 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 57288276461 ps |
| CPU time | 970.14 seconds |
| Started | Aug 06 09:03:23 PM PDT 24 |
| Finished | Aug 06 09:19:34 PM PDT 24 |
| Peak memory | 576628 kb |
| Host | smart-a0913531-fb20-4645-b3ef-2c1940aa93fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231064229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.3231064229 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.1632808301 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 1251708142 ps |
| CPU time | 49.42 seconds |
| Started | Aug 06 09:03:29 PM PDT 24 |
| Finished | Aug 06 09:04:19 PM PDT 24 |
| Peak memory | 576028 kb |
| Host | smart-64e8ce70-4102-4160-8489-9c4b425629c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632808301 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.1632808301 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.1032990052 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 201165139 ps |
| CPU time | 19.02 seconds |
| Started | Aug 06 09:03:25 PM PDT 24 |
| Finished | Aug 06 09:03:44 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-3dba72e0-59dc-4411-8bcc-756df214a296 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032990052 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.1032990052 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.3997967102 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 1935683233 ps |
| CPU time | 75.56 seconds |
| Started | Aug 06 09:03:19 PM PDT 24 |
| Finished | Aug 06 09:04:34 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4f72b0b4-dd10-44e6-86fb-20756036df11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997967102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.3997967102 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.2693654991 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 90288840255 ps |
| CPU time | 953.86 seconds |
| Started | Aug 06 09:03:18 PM PDT 24 |
| Finished | Aug 06 09:19:12 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-ce8f064b-25f9-4499-9b36-663e2759221d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2693654991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.2693654991 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.2071164420 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 50860955468 ps |
| CPU time | 863.93 seconds |
| Started | Aug 06 09:03:19 PM PDT 24 |
| Finished | Aug 06 09:17:43 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-84c6f348-dcb0-4d16-99a7-33825724f0ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2071164420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.2071164420 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.402811483 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 219337972 ps |
| CPU time | 22.02 seconds |
| Started | Aug 06 09:03:18 PM PDT 24 |
| Finished | Aug 06 09:03:40 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-df6bf94a-5435-42ad-ad00-3ace2d8c6230 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=402811483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_dela ys.402811483 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.3757333356 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 160638930 ps |
| CPU time | 14.67 seconds |
| Started | Aug 06 09:03:23 PM PDT 24 |
| Finished | Aug 06 09:03:38 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-22fe6a7e-2540-4125-9156-345a369153f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757333356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.3757333356 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1819996338 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 199448601 ps |
| CPU time | 9.24 seconds |
| Started | Aug 06 09:03:18 PM PDT 24 |
| Finished | Aug 06 09:03:27 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-5d7ca5a7-c2a1-4da0-ae61-0e21b29faaed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819996338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1819996338 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2669767804 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 9645353005 ps |
| CPU time | 100.85 seconds |
| Started | Aug 06 09:03:22 PM PDT 24 |
| Finished | Aug 06 09:05:03 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-c9031633-88d0-4f9f-b1d3-374c5ea24901 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669767804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2669767804 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.2663026314 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 5163966429 ps |
| CPU time | 95.52 seconds |
| Started | Aug 06 09:03:21 PM PDT 24 |
| Finished | Aug 06 09:04:57 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-2e3292c0-97af-4309-8878-f1d26646d5de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663026314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.2663026314 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1114412731 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 52263792 ps |
| CPU time | 7.3 seconds |
| Started | Aug 06 09:03:18 PM PDT 24 |
| Finished | Aug 06 09:03:25 PM PDT 24 |
| Peak memory | 574364 kb |
| Host | smart-8d5bdde3-06c2-476e-aeac-18f59604082f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114412731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.1114412731 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.1768625369 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 4289742435 ps |
| CPU time | 183.29 seconds |
| Started | Aug 06 09:03:23 PM PDT 24 |
| Finished | Aug 06 09:06:26 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-5e4837d3-1079-47c8-912e-62465317dd28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768625369 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.1768625369 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.579521163 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 7509131400 ps |
| CPU time | 283.48 seconds |
| Started | Aug 06 09:03:28 PM PDT 24 |
| Finished | Aug 06 09:08:12 PM PDT 24 |
| Peak memory | 576036 kb |
| Host | smart-4dab47ea-da98-4b0b-b455-fd60b4053b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579521163 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.579521163 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.4074450899 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 1141190347 ps |
| CPU time | 177.18 seconds |
| Started | Aug 06 09:03:26 PM PDT 24 |
| Finished | Aug 06 09:06:23 PM PDT 24 |
| Peak memory | 576572 kb |
| Host | smart-c46a3289-9ef1-44f1-b2c8-2a292648f93f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074450899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.4074450899 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.1985309088 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 3048735370 ps |
| CPU time | 255.13 seconds |
| Started | Aug 06 09:03:27 PM PDT 24 |
| Finished | Aug 06 09:07:43 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-06ac983f-dacb-4d39-b5ab-ea23e456648a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985309088 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_al l_with_reset_error.1985309088 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.2751969229 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 1259627730 ps |
| CPU time | 55.17 seconds |
| Started | Aug 06 09:03:23 PM PDT 24 |
| Finished | Aug 06 09:04:18 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-63df48c9-cc8c-4ec3-ace7-4bd917a54dcd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751969229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.2751969229 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2004215254 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 671140537 ps |
| CPU time | 31.38 seconds |
| Started | Aug 06 09:03:34 PM PDT 24 |
| Finished | Aug 06 09:04:06 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-3f4f05fd-79e3-4383-b14e-46e9f78ae56c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004215254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2004215254 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.3179508596 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 57903914830 ps |
| CPU time | 1067.13 seconds |
| Started | Aug 06 09:03:35 PM PDT 24 |
| Finished | Aug 06 09:21:22 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-f4320820-1871-4ec7-8fcb-a5a065ba9ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179508596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_ device_slow_rsp.3179508596 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.2039642268 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 911757857 ps |
| CPU time | 37.83 seconds |
| Started | Aug 06 09:03:37 PM PDT 24 |
| Finished | Aug 06 09:04:15 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-f79ab08d-d6af-4c75-b592-2b83b597268d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039642268 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.2039642268 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.1398539695 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 2162720278 ps |
| CPU time | 72.47 seconds |
| Started | Aug 06 09:03:34 PM PDT 24 |
| Finished | Aug 06 09:04:47 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-3dfc19a2-a57c-4c5f-8187-0551253af5fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398539695 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.1398539695 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.4179386473 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 2194095176 ps |
| CPU time | 87.93 seconds |
| Started | Aug 06 09:03:39 PM PDT 24 |
| Finished | Aug 06 09:05:07 PM PDT 24 |
| Peak memory | 575888 kb |
| Host | smart-ff3984c8-0638-4939-a4c3-81a8884e6f11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179386473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.4179386473 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4237640258 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 48562227458 ps |
| CPU time | 520.06 seconds |
| Started | Aug 06 09:03:35 PM PDT 24 |
| Finished | Aug 06 09:12:15 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-878ba9ed-9b29-4d02-9ce9-901a43b816e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4237640258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.4237640258 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.488305397 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 45166518068 ps |
| CPU time | 790.45 seconds |
| Started | Aug 06 09:03:36 PM PDT 24 |
| Finished | Aug 06 09:16:46 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-20b8159c-a3e1-463b-81cb-6ad330812ca5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488305397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.488305397 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.1630694170 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 73899945 ps |
| CPU time | 8.96 seconds |
| Started | Aug 06 09:03:34 PM PDT 24 |
| Finished | Aug 06 09:03:44 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-4d026010-c4d4-41d1-805b-b5d8720b8b98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630694170 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.1630694170 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1595163301 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 346612236 ps |
| CPU time | 27.77 seconds |
| Started | Aug 06 09:03:37 PM PDT 24 |
| Finished | Aug 06 09:04:04 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-fbe9512f-725a-42ca-9ac8-4ff414567706 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595163301 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1595163301 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.3469439889 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 251968153 ps |
| CPU time | 11.13 seconds |
| Started | Aug 06 09:03:30 PM PDT 24 |
| Finished | Aug 06 09:03:41 PM PDT 24 |
| Peak memory | 574408 kb |
| Host | smart-0edc8107-4647-4a29-9fc0-451fdaeb5bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469439889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.3469439889 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2059456539 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 8625539538 ps |
| CPU time | 98.75 seconds |
| Started | Aug 06 09:03:30 PM PDT 24 |
| Finished | Aug 06 09:05:09 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-7da28f7e-f4ed-49ff-9c98-8a82b95e4a35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059456539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.2059456539 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.1305188625 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 3807875546 ps |
| CPU time | 67 seconds |
| Started | Aug 06 09:03:29 PM PDT 24 |
| Finished | Aug 06 09:04:36 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-db3b948e-b40a-49a9-81e8-f571b3982a7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305188625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.1305188625 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.996873429 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 48196648 ps |
| CPU time | 6.71 seconds |
| Started | Aug 06 09:03:29 PM PDT 24 |
| Finished | Aug 06 09:03:35 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-4c3351c1-0d87-4476-9ade-0f2dcb8004e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=996873429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delays .996873429 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.4173614899 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 14098967630 ps |
| CPU time | 499.59 seconds |
| Started | Aug 06 09:03:35 PM PDT 24 |
| Finished | Aug 06 09:11:54 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-78bc4828-dc6c-4c8b-9ded-5e50baa9a516 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173614899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.4173614899 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3237032500 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 3556809709 ps |
| CPU time | 146.39 seconds |
| Started | Aug 06 09:03:39 PM PDT 24 |
| Finished | Aug 06 09:06:05 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-ad956828-d674-490b-8fa7-f333fe278dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237032500 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3237032500 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.108251492 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 3860683615 ps |
| CPU time | 428.17 seconds |
| Started | Aug 06 09:03:35 PM PDT 24 |
| Finished | Aug 06 09:10:44 PM PDT 24 |
| Peak memory | 576672 kb |
| Host | smart-cea20e9b-c5ef-4dbe-b1cf-d65ec2600511 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108251492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_ with_rand_reset.108251492 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.382502337 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 1602633285 ps |
| CPU time | 223.03 seconds |
| Started | Aug 06 09:03:40 PM PDT 24 |
| Finished | Aug 06 09:07:23 PM PDT 24 |
| Peak memory | 576580 kb |
| Host | smart-e381bfcc-6d21-49af-9d72-395529fbcd1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382502337 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_reset_error.382502337 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.3843919005 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 73187454 ps |
| CPU time | 11.55 seconds |
| Started | Aug 06 09:03:39 PM PDT 24 |
| Finished | Aug 06 09:03:50 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-9e5d23b1-6e39-4c5e-9012-3e8bd31cca12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843919005 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.3843919005 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1371364677 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 589491038 ps |
| CPU time | 28.7 seconds |
| Started | Aug 06 09:03:43 PM PDT 24 |
| Finished | Aug 06 09:04:11 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-9100a3ab-1b1f-4660-a3fc-f52fdb6eaee3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371364677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .1371364677 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.796557980 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 50950932984 ps |
| CPU time | 923.85 seconds |
| Started | Aug 06 09:03:41 PM PDT 24 |
| Finished | Aug 06 09:19:05 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-904950d0-ed4b-4f54-9ca6-ab6cfa874f1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796557980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_d evice_slow_rsp.796557980 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.3365614402 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 137046352 ps |
| CPU time | 9.51 seconds |
| Started | Aug 06 09:03:46 PM PDT 24 |
| Finished | Aug 06 09:03:56 PM PDT 24 |
| Peak memory | 574584 kb |
| Host | smart-8c52b215-937a-46fa-925f-794210d86f38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3365614402 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.3365614402 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.2294882798 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 305829468 ps |
| CPU time | 31.11 seconds |
| Started | Aug 06 09:03:46 PM PDT 24 |
| Finished | Aug 06 09:04:17 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-3d136327-ed03-439a-bc60-1b82f3f37311 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294882798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.2294882798 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.2052834461 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 953384729 ps |
| CPU time | 35.62 seconds |
| Started | Aug 06 09:03:41 PM PDT 24 |
| Finished | Aug 06 09:04:17 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-a6256529-936f-486c-86aa-c8eb357ce51c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052834461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.2052834461 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3369033856 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 57672521020 ps |
| CPU time | 594.34 seconds |
| Started | Aug 06 09:03:42 PM PDT 24 |
| Finished | Aug 06 09:13:36 PM PDT 24 |
| Peak memory | 575992 kb |
| Host | smart-786bb602-3280-49ef-bf68-3962ebf1db25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369033856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3369033856 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.2982097430 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 42042593471 ps |
| CPU time | 699.63 seconds |
| Started | Aug 06 09:03:42 PM PDT 24 |
| Finished | Aug 06 09:15:22 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-b08ef47f-5e33-4486-bfae-0249d06ffcca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982097430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.2982097430 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.1554036320 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 533852338 ps |
| CPU time | 51.35 seconds |
| Started | Aug 06 09:03:38 PM PDT 24 |
| Finished | Aug 06 09:04:30 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-3a81e198-881c-4878-af71-009b5b69a0a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554036320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_del ays.1554036320 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.3399085521 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 461885101 ps |
| CPU time | 15.74 seconds |
| Started | Aug 06 09:03:42 PM PDT 24 |
| Finished | Aug 06 09:03:58 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-8a2921d5-71a6-4c29-9540-dde5cd4fe599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399085521 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.3399085521 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.3999796236 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 54600867 ps |
| CPU time | 6.96 seconds |
| Started | Aug 06 09:03:42 PM PDT 24 |
| Finished | Aug 06 09:03:49 PM PDT 24 |
| Peak memory | 573768 kb |
| Host | smart-df9f6547-f315-4ceb-80e3-ea9cf45c451b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999796236 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.3999796236 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.497793863 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 8517040761 ps |
| CPU time | 86.88 seconds |
| Started | Aug 06 09:03:40 PM PDT 24 |
| Finished | Aug 06 09:05:07 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-ee2cd8b1-b792-4ec9-ac36-92abf18932b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497793863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.497793863 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.3093330293 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 4932901019 ps |
| CPU time | 86.22 seconds |
| Started | Aug 06 09:03:39 PM PDT 24 |
| Finished | Aug 06 09:05:05 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-d5fd1d3b-6bf3-4c3c-9e85-0bd8fa03d47d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093330293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.3093330293 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.2663609710 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 49036198 ps |
| CPU time | 6.9 seconds |
| Started | Aug 06 09:03:42 PM PDT 24 |
| Finished | Aug 06 09:03:48 PM PDT 24 |
| Peak memory | 574436 kb |
| Host | smart-efd16afe-44d2-4526-8f31-1cfc642b7f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2663609710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.2663609710 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.561867466 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 1189208267 ps |
| CPU time | 109.08 seconds |
| Started | Aug 06 09:03:45 PM PDT 24 |
| Finished | Aug 06 09:05:34 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-a600cd0f-0153-4870-9743-52f4cd34d2d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561867466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.561867466 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.4120769106 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 1961438353 ps |
| CPU time | 183.67 seconds |
| Started | Aug 06 09:03:47 PM PDT 24 |
| Finished | Aug 06 09:06:51 PM PDT 24 |
| Peak memory | 576592 kb |
| Host | smart-891affcb-dd45-4600-931a-e41c2260129a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120769106 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.4120769106 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.2284908109 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 303750643 ps |
| CPU time | 165.27 seconds |
| Started | Aug 06 09:03:45 PM PDT 24 |
| Finished | Aug 06 09:06:30 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-4c439888-11c6-45f6-8392-2e7dd9b89734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284908109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.2284908109 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3194211877 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 446277637 ps |
| CPU time | 116.29 seconds |
| Started | Aug 06 09:03:47 PM PDT 24 |
| Finished | Aug 06 09:05:44 PM PDT 24 |
| Peak memory | 576608 kb |
| Host | smart-3a6e923b-765d-42f3-963c-af902af48a1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3194211877 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_al l_with_reset_error.3194211877 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2879804050 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 144045542 ps |
| CPU time | 19.82 seconds |
| Started | Aug 06 09:03:46 PM PDT 24 |
| Finished | Aug 06 09:04:06 PM PDT 24 |
| Peak memory | 575916 kb |
| Host | smart-d7336eb6-7054-4a77-a7ad-bc603c2d92e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879804050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.2879804050 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2729845285 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 552512298 ps |
| CPU time | 48.98 seconds |
| Started | Aug 06 09:03:52 PM PDT 24 |
| Finished | Aug 06 09:04:41 PM PDT 24 |
| Peak memory | 575716 kb |
| Host | smart-d53d58a1-8b22-4443-a9a8-a8544fc892db |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729845285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2729845285 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.748329537 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 54202451444 ps |
| CPU time | 967.27 seconds |
| Started | Aug 06 09:03:51 PM PDT 24 |
| Finished | Aug 06 09:19:59 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-cd8ad02c-40d7-4372-b6da-fa92e393ebfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748329537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_d evice_slow_rsp.748329537 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.1088781330 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 164833268 ps |
| CPU time | 19.37 seconds |
| Started | Aug 06 09:03:57 PM PDT 24 |
| Finished | Aug 06 09:04:17 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-576338c2-1bef-4bea-9ebe-4066ccbd73e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1088781330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_add r.1088781330 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.1472108621 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 1437227394 ps |
| CPU time | 55.05 seconds |
| Started | Aug 06 09:03:53 PM PDT 24 |
| Finished | Aug 06 09:04:49 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-90179344-ce4a-4bb5-8ce2-8154c9e01fff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472108621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.1472108621 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.1148062977 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 2102605906 ps |
| CPU time | 90.18 seconds |
| Started | Aug 06 09:03:53 PM PDT 24 |
| Finished | Aug 06 09:05:23 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-7f01ff05-09d5-4fb1-b797-01cf96e516d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148062977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.1148062977 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.417247452 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 43805310162 ps |
| CPU time | 494.91 seconds |
| Started | Aug 06 09:03:52 PM PDT 24 |
| Finished | Aug 06 09:12:07 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-9f8bf10c-3c58-4ee7-9602-602658ca6f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417247452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.417247452 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.2119739592 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 9584690602 ps |
| CPU time | 172.27 seconds |
| Started | Aug 06 09:03:53 PM PDT 24 |
| Finished | Aug 06 09:06:45 PM PDT 24 |
| Peak memory | 576644 kb |
| Host | smart-8216e6fa-b9e2-4099-942e-ff7aa71f4612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119739592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.2119739592 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.1277508604 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 183462461 ps |
| CPU time | 21.09 seconds |
| Started | Aug 06 09:03:53 PM PDT 24 |
| Finished | Aug 06 09:04:14 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-24439f5b-5785-49e7-9171-0ff7737fd970 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277508604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_del ays.1277508604 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.3907856071 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 536040946 ps |
| CPU time | 42 seconds |
| Started | Aug 06 09:03:52 PM PDT 24 |
| Finished | Aug 06 09:04:34 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-68eb94fb-051b-4071-abb9-9b0dfd4d49ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907856071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.3907856071 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.131652148 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 225643046 ps |
| CPU time | 9.87 seconds |
| Started | Aug 06 09:03:46 PM PDT 24 |
| Finished | Aug 06 09:03:56 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-6dd40cab-9049-442d-986d-f9b6497b5b26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131652148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.131652148 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.871166110 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 7839816674 ps |
| CPU time | 87.11 seconds |
| Started | Aug 06 09:03:51 PM PDT 24 |
| Finished | Aug 06 09:05:19 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-bd0e9dd0-5b33-4954-8fa9-a087067d1f60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871166110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.871166110 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3478837992 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 4842462039 ps |
| CPU time | 89.78 seconds |
| Started | Aug 06 09:03:53 PM PDT 24 |
| Finished | Aug 06 09:05:23 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-d9353df1-2d17-40ec-9adc-4a188830553c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478837992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3478837992 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.3519494277 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 48929209 ps |
| CPU time | 6.23 seconds |
| Started | Aug 06 09:03:53 PM PDT 24 |
| Finished | Aug 06 09:03:59 PM PDT 24 |
| Peak memory | 573656 kb |
| Host | smart-ab20a42a-667b-4e33-9c8a-85dd087a53f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519494277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.3519494277 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.3270396044 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 1250439838 ps |
| CPU time | 98.02 seconds |
| Started | Aug 06 09:03:55 PM PDT 24 |
| Finished | Aug 06 09:05:33 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-7632c301-5f8e-4ccb-9dd0-6432d6f93ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270396044 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.3270396044 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.588287664 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 3166117372 ps |
| CPU time | 260.16 seconds |
| Started | Aug 06 09:03:58 PM PDT 24 |
| Finished | Aug 06 09:08:18 PM PDT 24 |
| Peak memory | 576684 kb |
| Host | smart-a3f0ddc8-14d8-4560-a156-2de4873131b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588287664 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.588287664 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1408107801 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1303848874 ps |
| CPU time | 309.56 seconds |
| Started | Aug 06 09:03:57 PM PDT 24 |
| Finished | Aug 06 09:09:06 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-eabc8e52-0942-4c87-b053-ea23af11cc4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408107801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all _with_rand_reset.1408107801 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3020884555 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 819478444 ps |
| CPU time | 279.7 seconds |
| Started | Aug 06 09:04:00 PM PDT 24 |
| Finished | Aug 06 09:08:40 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-c792cf15-8f4c-4dd0-82b9-e037f5fed154 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020884555 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.3020884555 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.3437630188 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 774984399 ps |
| CPU time | 34.66 seconds |
| Started | Aug 06 09:03:58 PM PDT 24 |
| Finished | Aug 06 09:04:32 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-ff9579b2-5a43-4b9d-adad-16422eb1cf83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3437630188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.3437630188 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.556870959 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 3719609623 ps |
| CPU time | 172.62 seconds |
| Started | Aug 06 09:04:01 PM PDT 24 |
| Finished | Aug 06 09:06:54 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-7a5d7447-e762-49cb-80e1-c4a568249e40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556870959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device. 556870959 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.618162129 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 10717873795 ps |
| CPU time | 189.54 seconds |
| Started | Aug 06 09:04:07 PM PDT 24 |
| Finished | Aug 06 09:07:16 PM PDT 24 |
| Peak memory | 573796 kb |
| Host | smart-e50d2460-d07a-4751-ac8e-180e5abde713 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618162129 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_d evice_slow_rsp.618162129 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.2344536306 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 817920334 ps |
| CPU time | 33.45 seconds |
| Started | Aug 06 09:04:03 PM PDT 24 |
| Finished | Aug 06 09:04:36 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-e9dbef1c-c3d2-4568-b3d7-e1676b3d0e90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344536306 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.2344536306 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.3334714314 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 65312237 ps |
| CPU time | 8.73 seconds |
| Started | Aug 06 09:04:03 PM PDT 24 |
| Finished | Aug 06 09:04:11 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-d3fdd810-6ba6-4103-98d5-6fb9ff30567e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334714314 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.3334714314 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1052615621 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 149026218 ps |
| CPU time | 14.6 seconds |
| Started | Aug 06 09:04:00 PM PDT 24 |
| Finished | Aug 06 09:04:15 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-636d3789-f24a-4657-afca-35c755ec995c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052615621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1052615621 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.3749757802 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 21654323034 ps |
| CPU time | 246.32 seconds |
| Started | Aug 06 09:04:02 PM PDT 24 |
| Finished | Aug 06 09:08:08 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-2dd2007d-f0d3-4772-b444-9483419443ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749757802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.3749757802 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.1942915603 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 38722238036 ps |
| CPU time | 629.54 seconds |
| Started | Aug 06 09:03:58 PM PDT 24 |
| Finished | Aug 06 09:14:27 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-ef98d0cd-41a6-4871-a551-ac246cea74ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942915603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.1942915603 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3026353049 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 420879704 ps |
| CPU time | 40.04 seconds |
| Started | Aug 06 09:03:57 PM PDT 24 |
| Finished | Aug 06 09:04:37 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-3b851335-14c3-4ce6-bf9a-a2f169348cb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3026353049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_del ays.3026353049 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.2641619543 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 1105473305 ps |
| CPU time | 30.71 seconds |
| Started | Aug 06 09:04:06 PM PDT 24 |
| Finished | Aug 06 09:04:37 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-91e4af49-4750-4082-8d3b-b94973ade133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641619543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.2641619543 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.3078516266 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 46417448 ps |
| CPU time | 7.07 seconds |
| Started | Aug 06 09:03:59 PM PDT 24 |
| Finished | Aug 06 09:04:06 PM PDT 24 |
| Peak memory | 573732 kb |
| Host | smart-4427f807-aad1-4a6b-a51e-dfff7f5fad14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078516266 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.3078516266 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.4061720823 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 9595592540 ps |
| CPU time | 102.62 seconds |
| Started | Aug 06 09:03:58 PM PDT 24 |
| Finished | Aug 06 09:05:40 PM PDT 24 |
| Peak memory | 575876 kb |
| Host | smart-3dd03ff2-8479-458b-8e76-363d15fd132b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061720823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.4061720823 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.2080978469 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 4461034270 ps |
| CPU time | 78.84 seconds |
| Started | Aug 06 09:03:59 PM PDT 24 |
| Finished | Aug 06 09:05:17 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-6ad82426-8bdd-47f0-9e61-611ef7200a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080978469 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.2080978469 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.836881120 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 50404797 ps |
| CPU time | 7.33 seconds |
| Started | Aug 06 09:03:58 PM PDT 24 |
| Finished | Aug 06 09:04:06 PM PDT 24 |
| Peak memory | 574448 kb |
| Host | smart-0439f6b2-ae73-4c1d-8ee3-47ce38ac4fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836881120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays .836881120 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.376451055 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 1455509072 ps |
| CPU time | 59.18 seconds |
| Started | Aug 06 09:04:05 PM PDT 24 |
| Finished | Aug 06 09:05:04 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-e94678a1-60d8-487f-94f8-d37a1475b8d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376451055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.376451055 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.4287860557 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 3917446619 ps |
| CPU time | 344.47 seconds |
| Started | Aug 06 09:04:06 PM PDT 24 |
| Finished | Aug 06 09:09:51 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-19953b14-4d43-4358-bea3-9186cc41bfdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287860557 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.4287860557 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.2986898815 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 2210704872 ps |
| CPU time | 307.81 seconds |
| Started | Aug 06 09:04:03 PM PDT 24 |
| Finished | Aug 06 09:09:11 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-a4b29132-db06-4dad-9578-ed730e5d2ad1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986898815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.2986898815 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3225178183 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 7085978466 ps |
| CPU time | 285.99 seconds |
| Started | Aug 06 09:04:06 PM PDT 24 |
| Finished | Aug 06 09:08:52 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-2ea7c3aa-d4f7-4704-b5a9-523bbc0e68e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225178183 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.3225178183 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.4144408662 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 596169711 ps |
| CPU time | 29.36 seconds |
| Started | Aug 06 09:04:05 PM PDT 24 |
| Finished | Aug 06 09:04:34 PM PDT 24 |
| Peak memory | 575912 kb |
| Host | smart-df853392-1a03-43df-a49d-c38a97cbd412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144408662 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.4144408662 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.642141565 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 7464693675 ps |
| CPU time | 490.98 seconds |
| Started | Aug 06 08:48:06 PM PDT 24 |
| Finished | Aug 06 08:56:17 PM PDT 24 |
| Peak memory | 640640 kb |
| Host | smart-6407baf0-8107-4212-89f5-f9e03b73cdd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=642141565 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.642141565 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.1104616019 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5822142315 ps |
| CPU time | 601.88 seconds |
| Started | Aug 06 08:48:03 PM PDT 24 |
| Finished | Aug 06 08:58:05 PM PDT 24 |
| Peak memory | 599056 kb |
| Host | smart-b4bd7227-b628-4bbf-ad30-c206c43e88d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104616019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.1104616019 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.3348461520 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 17261669963 ps |
| CPU time | 1721.27 seconds |
| Started | Aug 06 08:47:44 PM PDT 24 |
| Finished | Aug 06 09:16:25 PM PDT 24 |
| Peak memory | 593164 kb |
| Host | smart-41a031f9-8d11-4f2d-9d9a-c8fd99b28a03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348461520 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.3348461520 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.317592722 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3828620408 ps |
| CPU time | 349.12 seconds |
| Started | Aug 06 08:47:35 PM PDT 24 |
| Finished | Aug 06 08:53:24 PM PDT 24 |
| Peak memory | 598624 kb |
| Host | smart-907d9e10-a1ae-40c1-8629-d8eba2502260 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317592722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.317592722 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.2945939858 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 2863199250 ps |
| CPU time | 142.74 seconds |
| Started | Aug 06 08:47:54 PM PDT 24 |
| Finished | Aug 06 08:50:17 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-d7b37be2-0ee0-4607-addd-1135c0162448 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945939858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 2945939858 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.4038222211 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 71314380487 ps |
| CPU time | 1294.56 seconds |
| Started | Aug 06 08:47:52 PM PDT 24 |
| Finished | Aug 06 09:09:26 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-b9063dd5-4e91-4300-b486-2c0b5c9ee5f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038222211 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.4038222211 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.1297972505 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 538923243 ps |
| CPU time | 24.68 seconds |
| Started | Aug 06 08:48:01 PM PDT 24 |
| Finished | Aug 06 08:48:25 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-000531e1-6a9e-4339-a4f3-970f7ecfe0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297972505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr .1297972505 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.1939120605 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 1311802575 ps |
| CPU time | 50.4 seconds |
| Started | Aug 06 08:47:55 PM PDT 24 |
| Finished | Aug 06 08:48:45 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-4c86224a-3a28-439c-8256-5f7c8d38e80d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939120605 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.1939120605 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.2517985349 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 1499856588 ps |
| CPU time | 53.83 seconds |
| Started | Aug 06 08:47:47 PM PDT 24 |
| Finished | Aug 06 08:48:40 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-0ee9eb8d-b675-4c3f-b889-ed0b0182b3be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517985349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.2517985349 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.484537410 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 96619824654 ps |
| CPU time | 995.82 seconds |
| Started | Aug 06 08:47:52 PM PDT 24 |
| Finished | Aug 06 09:04:28 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-ed29136f-4895-4cd6-bebc-f5dadb725e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484537410 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.484537410 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.750023176 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 34092960191 ps |
| CPU time | 610.42 seconds |
| Started | Aug 06 08:47:54 PM PDT 24 |
| Finished | Aug 06 08:58:05 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-b55e690f-4a35-4bc4-94d0-04c5c4e788eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750023176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.750023176 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2196415632 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 373305778 ps |
| CPU time | 37.63 seconds |
| Started | Aug 06 08:47:54 PM PDT 24 |
| Finished | Aug 06 08:48:32 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-577304d7-d85a-4b37-b7a7-45f1e1c29203 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2196415632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2196415632 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.1863098108 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 1226638881 ps |
| CPU time | 38.14 seconds |
| Started | Aug 06 08:47:58 PM PDT 24 |
| Finished | Aug 06 08:48:36 PM PDT 24 |
| Peak memory | 575756 kb |
| Host | smart-3aeff56d-a784-4c71-ab6c-61f004c856a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863098108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.1863098108 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.1439547955 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 211416344 ps |
| CPU time | 8.83 seconds |
| Started | Aug 06 08:47:45 PM PDT 24 |
| Finished | Aug 06 08:47:54 PM PDT 24 |
| Peak memory | 574352 kb |
| Host | smart-b6089c19-0f18-42ab-9257-1ff64f1c593e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439547955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.1439547955 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.768176424 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 7772078438 ps |
| CPU time | 86.08 seconds |
| Started | Aug 06 08:47:40 PM PDT 24 |
| Finished | Aug 06 08:49:07 PM PDT 24 |
| Peak memory | 574536 kb |
| Host | smart-04495ad3-4bb1-4ab0-b1c4-a1f3814436aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768176424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.768176424 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3710391841 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 6486237559 ps |
| CPU time | 102.61 seconds |
| Started | Aug 06 08:47:40 PM PDT 24 |
| Finished | Aug 06 08:49:23 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-7073423d-29cf-434f-b97d-01d1a1dec850 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710391841 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.3710391841 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2590701954 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 44101429 ps |
| CPU time | 6.6 seconds |
| Started | Aug 06 08:47:42 PM PDT 24 |
| Finished | Aug 06 08:47:49 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-d4b1b077-b098-4029-b4a9-b2b6e3144aa4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590701954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2590701954 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.4186913035 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 15787817586 ps |
| CPU time | 716.13 seconds |
| Started | Aug 06 08:48:03 PM PDT 24 |
| Finished | Aug 06 08:59:59 PM PDT 24 |
| Peak memory | 576700 kb |
| Host | smart-22b77ba2-5d69-4648-a7a6-343d878afc9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186913035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4186913035 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.941447323 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 3220195236 ps |
| CPU time | 262.01 seconds |
| Started | Aug 06 08:48:01 PM PDT 24 |
| Finished | Aug 06 08:52:23 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-73efea39-9ae8-434b-92f5-6f22c306b7b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941447323 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.941447323 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2561513952 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 352821961 ps |
| CPU time | 164.37 seconds |
| Started | Aug 06 08:48:05 PM PDT 24 |
| Finished | Aug 06 08:50:49 PM PDT 24 |
| Peak memory | 576604 kb |
| Host | smart-1f5de0b2-02cd-4afd-921e-b990bc30ae30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561513952 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.2561513952 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1855831129 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 5187749327 ps |
| CPU time | 648.55 seconds |
| Started | Aug 06 08:48:04 PM PDT 24 |
| Finished | Aug 06 08:58:53 PM PDT 24 |
| Peak memory | 582692 kb |
| Host | smart-60dbd48a-aaff-4187-a635-65954afba618 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855831129 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.1855831129 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.1013103402 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 258182758 ps |
| CPU time | 35.56 seconds |
| Started | Aug 06 08:47:56 PM PDT 24 |
| Finished | Aug 06 08:48:31 PM PDT 24 |
| Peak memory | 575832 kb |
| Host | smart-d7f10cbd-680e-4190-a2fd-1ecd4513f696 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1013103402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.1013103402 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.2098634772 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 987820377 ps |
| CPU time | 40.02 seconds |
| Started | Aug 06 09:04:12 PM PDT 24 |
| Finished | Aug 06 09:04:53 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-92551918-8132-48fe-8311-d3b00c941b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098634772 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device .2098634772 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.515992991 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 72374534127 ps |
| CPU time | 1267.99 seconds |
| Started | Aug 06 09:04:12 PM PDT 24 |
| Finished | Aug 06 09:25:20 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-d2f1a11d-5a68-4253-83d5-3d740d1a122b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515992991 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.515992991 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2836991161 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 294645544 ps |
| CPU time | 13.99 seconds |
| Started | Aug 06 09:04:17 PM PDT 24 |
| Finished | Aug 06 09:04:31 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-e5003184-311d-4a83-b3db-9c281402b274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836991161 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.2836991161 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.3196198204 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 258317642 ps |
| CPU time | 25.63 seconds |
| Started | Aug 06 09:04:16 PM PDT 24 |
| Finished | Aug 06 09:04:41 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-31146f6f-eabf-4f87-97c3-86259c51f5da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196198204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.3196198204 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.3504181606 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 68656116 ps |
| CPU time | 10.44 seconds |
| Started | Aug 06 09:04:07 PM PDT 24 |
| Finished | Aug 06 09:04:17 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-707b0167-9f64-4ea4-ad98-528ffa7d31ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504181606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.3504181606 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.3853341015 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 23122973006 ps |
| CPU time | 238.28 seconds |
| Started | Aug 06 09:04:13 PM PDT 24 |
| Finished | Aug 06 09:08:11 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-a6b09d8c-b1cd-45f9-897f-6c002a2ec344 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853341015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.3853341015 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.2479697599 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 33445606928 ps |
| CPU time | 576.5 seconds |
| Started | Aug 06 09:04:12 PM PDT 24 |
| Finished | Aug 06 09:13:49 PM PDT 24 |
| Peak memory | 576616 kb |
| Host | smart-ac8e38c0-7939-4f88-84f2-439406e6797f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479697599 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.2479697599 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1303726277 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 328928747 ps |
| CPU time | 33.97 seconds |
| Started | Aug 06 09:04:11 PM PDT 24 |
| Finished | Aug 06 09:04:45 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-61225bc2-4be7-4cff-8233-693a1ddefbdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303726277 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1303726277 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.2524366557 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 500174059 ps |
| CPU time | 18.37 seconds |
| Started | Aug 06 09:04:17 PM PDT 24 |
| Finished | Aug 06 09:04:35 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-886d7b51-0aab-4805-95b3-b6ae421424bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524366557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.2524366557 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.3157923445 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 171364158 ps |
| CPU time | 8.96 seconds |
| Started | Aug 06 09:04:08 PM PDT 24 |
| Finished | Aug 06 09:04:17 PM PDT 24 |
| Peak memory | 574396 kb |
| Host | smart-e4721aa3-c89c-4753-9182-3eebe1c8e044 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157923445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.3157923445 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2939100427 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 6215570788 ps |
| CPU time | 66.53 seconds |
| Started | Aug 06 09:04:08 PM PDT 24 |
| Finished | Aug 06 09:05:15 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-f78114ef-146b-474f-aec5-a840e49d296e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939100427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2939100427 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.2979434241 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 6505495314 ps |
| CPU time | 118.6 seconds |
| Started | Aug 06 09:04:10 PM PDT 24 |
| Finished | Aug 06 09:06:09 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-ca22785e-bb70-4d5f-97d3-adf2600504a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979434241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.2979434241 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.1697075939 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 48248957 ps |
| CPU time | 6.96 seconds |
| Started | Aug 06 09:04:09 PM PDT 24 |
| Finished | Aug 06 09:04:16 PM PDT 24 |
| Peak memory | 573652 kb |
| Host | smart-5e8cb3c3-650a-4e25-8e4a-d69fbf9a1907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697075939 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.1697075939 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2795139743 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 17037251142 ps |
| CPU time | 629.97 seconds |
| Started | Aug 06 09:04:17 PM PDT 24 |
| Finished | Aug 06 09:14:47 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-98a54277-cbc9-4df3-aa88-3bc7a30f704f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2795139743 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2795139743 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.2107513865 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 1513191912 ps |
| CPU time | 132.8 seconds |
| Started | Aug 06 09:04:24 PM PDT 24 |
| Finished | Aug 06 09:06:37 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-91a9fc8b-c18f-41f9-b419-24d06b93c74d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107513865 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.2107513865 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.429512609 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 222231029 ps |
| CPU time | 59.13 seconds |
| Started | Aug 06 09:04:21 PM PDT 24 |
| Finished | Aug 06 09:05:20 PM PDT 24 |
| Peak memory | 576584 kb |
| Host | smart-65b5d9ad-d474-441d-975a-01d035be6053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429512609 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_ with_rand_reset.429512609 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.296123613 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 17669608441 ps |
| CPU time | 792.74 seconds |
| Started | Aug 06 09:04:20 PM PDT 24 |
| Finished | Aug 06 09:17:33 PM PDT 24 |
| Peak memory | 576716 kb |
| Host | smart-a7d537b3-6445-4fb9-99cd-b59cb6c49a77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296123613 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_reset_error.296123613 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.3884572839 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 319527240 ps |
| CPU time | 38.64 seconds |
| Started | Aug 06 09:04:16 PM PDT 24 |
| Finished | Aug 06 09:04:55 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-d85321d3-a5e5-4aeb-83ef-65d6fb719247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3884572839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.3884572839 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.4238642688 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 63716010 ps |
| CPU time | 7.47 seconds |
| Started | Aug 06 09:04:28 PM PDT 24 |
| Finished | Aug 06 09:04:35 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-9781804f-8957-45a3-b48b-29918026088d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238642688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .4238642688 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.149387986 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 108167256976 ps |
| CPU time | 1857.32 seconds |
| Started | Aug 06 09:04:28 PM PDT 24 |
| Finished | Aug 06 09:35:26 PM PDT 24 |
| Peak memory | 575972 kb |
| Host | smart-aa260c49-c49f-41b3-8fb2-fe6cbcce8855 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=149387986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_d evice_slow_rsp.149387986 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.412366603 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 104744415 ps |
| CPU time | 13.33 seconds |
| Started | Aug 06 09:04:23 PM PDT 24 |
| Finished | Aug 06 09:04:37 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-41233c08-b2bc-4727-9635-14f02577b17b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412366603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_addr .412366603 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.605897081 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 439646391 ps |
| CPU time | 33.9 seconds |
| Started | Aug 06 09:04:23 PM PDT 24 |
| Finished | Aug 06 09:04:57 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-78a49446-4ac9-4282-88d1-3df0ca6e2940 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605897081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.605897081 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.2037363244 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2452509553 ps |
| CPU time | 86.52 seconds |
| Started | Aug 06 09:04:23 PM PDT 24 |
| Finished | Aug 06 09:05:50 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-15f98871-85cf-4f6d-b6a3-4ef3cc076164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037363244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.2037363244 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.511274720 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 79523747731 ps |
| CPU time | 815.13 seconds |
| Started | Aug 06 09:04:24 PM PDT 24 |
| Finished | Aug 06 09:17:59 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-cfd13819-40bd-4260-a818-d5144c7029e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511274720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.511274720 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.4191113450 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 8579018951 ps |
| CPU time | 145.01 seconds |
| Started | Aug 06 09:04:25 PM PDT 24 |
| Finished | Aug 06 09:06:50 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-0598baf5-da21-49fc-90fa-7aaccb91467f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191113450 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.4191113450 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.162773783 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 171415562 ps |
| CPU time | 17.64 seconds |
| Started | Aug 06 09:04:25 PM PDT 24 |
| Finished | Aug 06 09:04:43 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-60bc5c80-e9ea-4334-92ed-038d7a5e94f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162773783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_dela ys.162773783 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3878219492 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 461538683 ps |
| CPU time | 38.05 seconds |
| Started | Aug 06 09:04:25 PM PDT 24 |
| Finished | Aug 06 09:05:03 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-43c908c7-ccb6-4f09-be42-02c6ccf44f6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3878219492 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3878219492 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.459055664 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 202687279 ps |
| CPU time | 9.73 seconds |
| Started | Aug 06 09:04:21 PM PDT 24 |
| Finished | Aug 06 09:04:31 PM PDT 24 |
| Peak memory | 573740 kb |
| Host | smart-909da6b1-45b0-43cc-9d0e-e5acb1c188d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459055664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.459055664 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.2157883618 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 5990729282 ps |
| CPU time | 63.05 seconds |
| Started | Aug 06 09:04:26 PM PDT 24 |
| Finished | Aug 06 09:05:29 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-77312140-8f86-4cc7-a0bc-869bb7b47d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157883618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.2157883618 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.4018235001 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 4155803996 ps |
| CPU time | 71.6 seconds |
| Started | Aug 06 09:04:17 PM PDT 24 |
| Finished | Aug 06 09:05:28 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-902dfd1c-2fb3-4fae-847d-c6e351445faa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018235001 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.4018235001 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.1617188866 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 49587483 ps |
| CPU time | 6.87 seconds |
| Started | Aug 06 09:04:26 PM PDT 24 |
| Finished | Aug 06 09:04:33 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-45544c31-e9a2-4693-ac4f-4fcecb6ac69d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617188866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delay s.1617188866 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1275294007 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 2505104193 ps |
| CPU time | 94.38 seconds |
| Started | Aug 06 09:04:28 PM PDT 24 |
| Finished | Aug 06 09:06:02 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-4e8fe344-9064-474e-8eaa-eded1e6f1a27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275294007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1275294007 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.954369407 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 4847600936 ps |
| CPU time | 193.84 seconds |
| Started | Aug 06 09:04:22 PM PDT 24 |
| Finished | Aug 06 09:07:36 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-0c3f3991-fb87-4477-a17a-1d4782d7f8b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954369407 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.954369407 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.700397055 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 530211951 ps |
| CPU time | 207.39 seconds |
| Started | Aug 06 09:04:30 PM PDT 24 |
| Finished | Aug 06 09:07:57 PM PDT 24 |
| Peak memory | 576660 kb |
| Host | smart-3fdbe9c9-1117-45dc-bf4e-c1c743f143c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700397055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_ with_rand_reset.700397055 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.559397965 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 8596245 ps |
| CPU time | 10.37 seconds |
| Started | Aug 06 09:04:31 PM PDT 24 |
| Finished | Aug 06 09:04:42 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-7e1cc279-13e6-4ec6-a0a0-24e65230fea3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559397965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_reset_error.559397965 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.2500652098 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 212783210 ps |
| CPU time | 25.71 seconds |
| Started | Aug 06 09:04:23 PM PDT 24 |
| Finished | Aug 06 09:04:49 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-8426194b-46f6-4639-9a06-2118eb1291fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500652098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.2500652098 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.1776846856 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 658132372 ps |
| CPU time | 28.33 seconds |
| Started | Aug 06 09:04:27 PM PDT 24 |
| Finished | Aug 06 09:04:56 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-6ca1c04f-e4ea-47cb-a431-b12c63765e28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776846856 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .1776846856 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.979094710 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 39942644525 ps |
| CPU time | 710.86 seconds |
| Started | Aug 06 09:04:32 PM PDT 24 |
| Finished | Aug 06 09:16:23 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-524c96d9-5f72-4971-a7a2-dae3c54d9c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979094710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_d evice_slow_rsp.979094710 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.34180305 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 629375749 ps |
| CPU time | 26.31 seconds |
| Started | Aug 06 09:04:31 PM PDT 24 |
| Finished | Aug 06 09:04:58 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-48d9dbd6-9f29-4400-b15a-55576be2af57 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34180305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_addr.34180305 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.2450173639 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 341149813 ps |
| CPU time | 31.21 seconds |
| Started | Aug 06 09:04:32 PM PDT 24 |
| Finished | Aug 06 09:05:03 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-2317a83f-7e29-4db7-ab79-e1da294225c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450173639 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.2450173639 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.2539000078 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 846541881 ps |
| CPU time | 33.88 seconds |
| Started | Aug 06 09:04:28 PM PDT 24 |
| Finished | Aug 06 09:05:02 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-b9b28193-1308-4b57-b6b7-0caa8bb1bf14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539000078 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2539000078 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.580879505 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 51878506429 ps |
| CPU time | 540.44 seconds |
| Started | Aug 06 09:04:29 PM PDT 24 |
| Finished | Aug 06 09:13:30 PM PDT 24 |
| Peak memory | 575948 kb |
| Host | smart-74bddf0f-d9c7-47f1-a49a-8f16af7fda2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580879505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.580879505 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.381265940 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 61445719710 ps |
| CPU time | 1025.03 seconds |
| Started | Aug 06 09:04:25 PM PDT 24 |
| Finished | Aug 06 09:21:30 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-0a2e5a8d-6e23-4e47-9c1e-0c12eb4d9a11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381265940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.381265940 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.3624077432 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 211820128 ps |
| CPU time | 22.09 seconds |
| Started | Aug 06 09:04:31 PM PDT 24 |
| Finished | Aug 06 09:04:54 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-c01fe612-7666-4e8b-be2e-9dd6dff3eb4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624077432 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.3624077432 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.1345549094 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 2218147145 ps |
| CPU time | 75.02 seconds |
| Started | Aug 06 09:04:26 PM PDT 24 |
| Finished | Aug 06 09:05:41 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-f0b847be-cc21-4967-81f5-889f1af95d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345549094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.1345549094 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.2235485089 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 51361750 ps |
| CPU time | 6.76 seconds |
| Started | Aug 06 09:04:26 PM PDT 24 |
| Finished | Aug 06 09:04:33 PM PDT 24 |
| Peak memory | 573736 kb |
| Host | smart-8b9b808c-72af-44e9-9804-a65f61f82b56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235485089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.2235485089 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.3196227745 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 10064151896 ps |
| CPU time | 106.03 seconds |
| Started | Aug 06 09:04:27 PM PDT 24 |
| Finished | Aug 06 09:06:13 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-6dc707e0-3662-4c85-a804-23672dc70c83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3196227745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.3196227745 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.3067180420 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 4661426529 ps |
| CPU time | 81.02 seconds |
| Started | Aug 06 09:04:26 PM PDT 24 |
| Finished | Aug 06 09:05:47 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-6959349e-86d6-450d-9ab0-bc5b3fa845c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067180420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.3067180420 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2348335839 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 51691255 ps |
| CPU time | 7.65 seconds |
| Started | Aug 06 09:04:25 PM PDT 24 |
| Finished | Aug 06 09:04:33 PM PDT 24 |
| Peak memory | 573712 kb |
| Host | smart-51277cf3-4816-4ccc-9551-1e76631b3757 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348335839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.2348335839 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.2222379030 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 8220895792 ps |
| CPU time | 342.06 seconds |
| Started | Aug 06 09:04:33 PM PDT 24 |
| Finished | Aug 06 09:10:16 PM PDT 24 |
| Peak memory | 576704 kb |
| Host | smart-a4739fba-c2c4-4059-a906-5ee09afb6299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222379030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.2222379030 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.369050414 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 57795021 ps |
| CPU time | 6.64 seconds |
| Started | Aug 06 09:04:38 PM PDT 24 |
| Finished | Aug 06 09:04:45 PM PDT 24 |
| Peak memory | 573792 kb |
| Host | smart-fcf74606-3063-4378-bf79-f788080e8d2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369050414 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.369050414 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.438943267 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 62267306 ps |
| CPU time | 23.94 seconds |
| Started | Aug 06 09:04:35 PM PDT 24 |
| Finished | Aug 06 09:04:59 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-768ca499-ac81-4dc1-8b2e-876440b6e7f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438943267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_ with_rand_reset.438943267 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.587897150 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 391917053 ps |
| CPU time | 165.82 seconds |
| Started | Aug 06 09:04:37 PM PDT 24 |
| Finished | Aug 06 09:07:23 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-7d3e9c0a-0848-4d00-ae3c-da6f20e98423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587897150 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all _with_reset_error.587897150 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.1608803486 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 698055545 ps |
| CPU time | 33.22 seconds |
| Started | Aug 06 09:04:34 PM PDT 24 |
| Finished | Aug 06 09:05:07 PM PDT 24 |
| Peak memory | 575884 kb |
| Host | smart-73497aa1-5179-4687-b266-5f0408a31687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608803486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.1608803486 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3128647439 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 132854198 ps |
| CPU time | 14.94 seconds |
| Started | Aug 06 09:04:43 PM PDT 24 |
| Finished | Aug 06 09:04:58 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-77a53414-2f5d-4f99-8224-7b79588b986c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128647439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3128647439 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.3389213397 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 134713141775 ps |
| CPU time | 2330.33 seconds |
| Started | Aug 06 09:04:42 PM PDT 24 |
| Finished | Aug 06 09:43:33 PM PDT 24 |
| Peak memory | 575836 kb |
| Host | smart-0d372b6a-b1da-4adf-8ce8-ab97b5bf1599 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389213397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.3389213397 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.4254104872 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 182206046 ps |
| CPU time | 20.65 seconds |
| Started | Aug 06 09:04:45 PM PDT 24 |
| Finished | Aug 06 09:05:06 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-89b0fd90-4a7a-4d87-b45e-40c69423ab54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254104872 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.4254104872 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.896661419 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 34349958 ps |
| CPU time | 6.66 seconds |
| Started | Aug 06 09:04:43 PM PDT 24 |
| Finished | Aug 06 09:04:50 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-75dcf158-e9a7-4c16-82cf-577d3f3c6fa8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896661419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.896661419 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.2434415929 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 195605491 ps |
| CPU time | 20.26 seconds |
| Started | Aug 06 09:04:49 PM PDT 24 |
| Finished | Aug 06 09:05:09 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-764aa695-133f-4517-9a40-0014914440a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434415929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.2434415929 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.1118074114 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 19203989365 ps |
| CPU time | 194.97 seconds |
| Started | Aug 06 09:04:51 PM PDT 24 |
| Finished | Aug 06 09:08:06 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-e1297925-6770-48f9-9405-2577f480a686 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118074114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.1118074114 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.280218925 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 49923014549 ps |
| CPU time | 839.6 seconds |
| Started | Aug 06 09:04:43 PM PDT 24 |
| Finished | Aug 06 09:18:43 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-b7efb6e6-7833-4b5b-a193-5731148db2cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280218925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.280218925 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.2447976100 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 563236306 ps |
| CPU time | 50.1 seconds |
| Started | Aug 06 09:04:41 PM PDT 24 |
| Finished | Aug 06 09:05:31 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-586f1841-5872-411a-9468-3bbf7169c992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447976100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_del ays.2447976100 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.2398760548 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 350125535 ps |
| CPU time | 24.4 seconds |
| Started | Aug 06 09:04:51 PM PDT 24 |
| Finished | Aug 06 09:05:15 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-1618cad2-2ac6-4dbd-b696-de4ce393bc8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398760548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.2398760548 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.614532573 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 54258677 ps |
| CPU time | 6.86 seconds |
| Started | Aug 06 09:04:49 PM PDT 24 |
| Finished | Aug 06 09:04:56 PM PDT 24 |
| Peak memory | 573688 kb |
| Host | smart-6bad9ab9-c13a-41de-9c67-dad771225642 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614532573 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.614532573 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.1114824350 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 9131588783 ps |
| CPU time | 106.53 seconds |
| Started | Aug 06 09:04:37 PM PDT 24 |
| Finished | Aug 06 09:06:24 PM PDT 24 |
| Peak memory | 575860 kb |
| Host | smart-85da8fed-cfd3-49c9-a56f-ad3dc188eeeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114824350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.1114824350 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.3277076782 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 6410633408 ps |
| CPU time | 113.8 seconds |
| Started | Aug 06 09:04:40 PM PDT 24 |
| Finished | Aug 06 09:06:34 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-82322426-2ff7-4a7c-a386-c4432944362c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277076782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.3277076782 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.1936687125 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 46386302 ps |
| CPU time | 5.7 seconds |
| Started | Aug 06 09:04:38 PM PDT 24 |
| Finished | Aug 06 09:04:43 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-310fa338-c3b8-461c-8dc4-7e90d611ebc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936687125 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.1936687125 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.2668531853 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 498108605 ps |
| CPU time | 45.11 seconds |
| Started | Aug 06 09:04:43 PM PDT 24 |
| Finished | Aug 06 09:05:28 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-35bb8684-1257-4114-9ef2-3ac68100f58c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668531853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2668531853 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.644081766 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 2548394907 ps |
| CPU time | 156.03 seconds |
| Started | Aug 06 09:04:45 PM PDT 24 |
| Finished | Aug 06 09:07:21 PM PDT 24 |
| Peak memory | 576128 kb |
| Host | smart-b8b2096e-4125-4fb3-8850-4007c8d28a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644081766 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.644081766 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.1170204546 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 237280506 ps |
| CPU time | 98.2 seconds |
| Started | Aug 06 09:04:42 PM PDT 24 |
| Finished | Aug 06 09:06:20 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-597db98e-be3a-4934-85c1-bf16d64a8fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1170204546 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.1170204546 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.1321656352 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 504940285 ps |
| CPU time | 133.36 seconds |
| Started | Aug 06 09:04:41 PM PDT 24 |
| Finished | Aug 06 09:06:55 PM PDT 24 |
| Peak memory | 576624 kb |
| Host | smart-b537676c-fe37-4c4d-aff3-e10f05427b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321656352 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.1321656352 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.2884306214 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 35745995 ps |
| CPU time | 7.76 seconds |
| Started | Aug 06 09:04:44 PM PDT 24 |
| Finished | Aug 06 09:04:52 PM PDT 24 |
| Peak memory | 573804 kb |
| Host | smart-b0b8d8b7-7b39-44a7-b1ad-3ef47a8f487e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884306214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.2884306214 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.3337542770 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 2423031820 ps |
| CPU time | 123.85 seconds |
| Started | Aug 06 09:04:51 PM PDT 24 |
| Finished | Aug 06 09:06:55 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-955bca4c-116f-4ef7-8d9f-a1e8e70bae53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337542770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device .3337542770 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.4185206536 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 54075909940 ps |
| CPU time | 886.42 seconds |
| Started | Aug 06 09:04:52 PM PDT 24 |
| Finished | Aug 06 09:19:39 PM PDT 24 |
| Peak memory | 575920 kb |
| Host | smart-e3e91d8a-dd16-4212-b019-64470a0cf29c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185206536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.4185206536 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.3314650329 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 1215202315 ps |
| CPU time | 47.57 seconds |
| Started | Aug 06 09:04:52 PM PDT 24 |
| Finished | Aug 06 09:05:40 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-3742550c-7c7e-4543-b453-481d0b1af56c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314650329 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_add r.3314650329 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.470312758 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 983705876 ps |
| CPU time | 35.35 seconds |
| Started | Aug 06 09:04:51 PM PDT 24 |
| Finished | Aug 06 09:05:26 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-86d785e9-2566-45b8-a20c-d55655998eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470312758 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.470312758 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2036089976 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 545373437 ps |
| CPU time | 50.71 seconds |
| Started | Aug 06 09:04:48 PM PDT 24 |
| Finished | Aug 06 09:05:39 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-aaf56078-bbbd-4f80-922a-fc44c32fe5e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036089976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2036089976 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.3947368776 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 9312834999 ps |
| CPU time | 96.96 seconds |
| Started | Aug 06 09:04:50 PM PDT 24 |
| Finished | Aug 06 09:06:27 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-1fc9f3e9-0823-446b-b069-b5872b1bab30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947368776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.3947368776 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.2749664359 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 13491363067 ps |
| CPU time | 238.42 seconds |
| Started | Aug 06 09:04:47 PM PDT 24 |
| Finished | Aug 06 09:08:46 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-7ec19c08-25d4-4f5e-8a7e-a64321edc6c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749664359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.2749664359 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3065848437 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 65290076 ps |
| CPU time | 9.74 seconds |
| Started | Aug 06 09:04:47 PM PDT 24 |
| Finished | Aug 06 09:04:57 PM PDT 24 |
| Peak memory | 575724 kb |
| Host | smart-251e7276-ed8a-4eb9-b5b1-9f0a1a019258 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065848437 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.3065848437 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.589445425 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 447682143 ps |
| CPU time | 32.08 seconds |
| Started | Aug 06 09:04:52 PM PDT 24 |
| Finished | Aug 06 09:05:24 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-6ac2b02c-fb50-4e23-a975-52f6be24a710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589445425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.589445425 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.4287916181 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 207853411 ps |
| CPU time | 9.68 seconds |
| Started | Aug 06 09:04:41 PM PDT 24 |
| Finished | Aug 06 09:04:51 PM PDT 24 |
| Peak memory | 573692 kb |
| Host | smart-873ae08f-4dae-46c3-9bff-a9e95497c2f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287916181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.4287916181 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.2479735412 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 9154463564 ps |
| CPU time | 92.25 seconds |
| Started | Aug 06 09:04:51 PM PDT 24 |
| Finished | Aug 06 09:06:23 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-d173f57a-70c4-4a77-b9c4-b2506709306b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479735412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.2479735412 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.593082592 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 6492473388 ps |
| CPU time | 111.02 seconds |
| Started | Aug 06 09:04:48 PM PDT 24 |
| Finished | Aug 06 09:06:39 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-823db39c-79f7-42c6-a7e4-921ba805cf1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593082592 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.593082592 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.920940497 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 60331340 ps |
| CPU time | 7.46 seconds |
| Started | Aug 06 09:04:43 PM PDT 24 |
| Finished | Aug 06 09:04:51 PM PDT 24 |
| Peak memory | 573704 kb |
| Host | smart-1a8c80d0-309d-44e6-a1e8-274d069fe4e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920940497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delays .920940497 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.1801002690 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 2146262445 ps |
| CPU time | 173.89 seconds |
| Started | Aug 06 09:04:58 PM PDT 24 |
| Finished | Aug 06 09:07:52 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-c398e926-8465-4662-8239-6f9f75d45988 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801002690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.1801002690 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2659403195 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 2201756375 ps |
| CPU time | 182.5 seconds |
| Started | Aug 06 09:04:56 PM PDT 24 |
| Finished | Aug 06 09:07:59 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-1e60dadf-937f-4ab2-90b1-8f4dce20e506 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659403195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.2659403195 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.3736932810 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 2667377889 ps |
| CPU time | 473.12 seconds |
| Started | Aug 06 09:05:00 PM PDT 24 |
| Finished | Aug 06 09:12:53 PM PDT 24 |
| Peak memory | 576708 kb |
| Host | smart-5f519c82-579d-46d8-ac92-9c16a6cc2bd7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736932810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_rand_reset.3736932810 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.429853077 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 577386443 ps |
| CPU time | 174.02 seconds |
| Started | Aug 06 09:04:55 PM PDT 24 |
| Finished | Aug 06 09:07:49 PM PDT 24 |
| Peak memory | 576620 kb |
| Host | smart-d1ce524c-243d-4984-9258-0b25a7f2dc4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429853077 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all _with_reset_error.429853077 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1971929647 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 668326238 ps |
| CPU time | 31.4 seconds |
| Started | Aug 06 09:04:53 PM PDT 24 |
| Finished | Aug 06 09:05:25 PM PDT 24 |
| Peak memory | 575936 kb |
| Host | smart-d696bb01-738f-413c-b001-6f8f493dda24 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971929647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1971929647 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2390829845 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 2072957390 ps |
| CPU time | 75.07 seconds |
| Started | Aug 06 09:05:04 PM PDT 24 |
| Finished | Aug 06 09:06:19 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-6df24a6e-390b-4d49-9c14-c597dc3cd2be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2390829845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device .2390829845 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.533001471 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 42680533216 ps |
| CPU time | 697.81 seconds |
| Started | Aug 06 09:05:05 PM PDT 24 |
| Finished | Aug 06 09:16:43 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-ce4d1fec-6104-410c-bab6-e09d45827419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533001471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_d evice_slow_rsp.533001471 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.2450385852 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 319867554 ps |
| CPU time | 36.35 seconds |
| Started | Aug 06 09:05:04 PM PDT 24 |
| Finished | Aug 06 09:05:40 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-2687ab79-b872-48dc-bf1d-f32d564798e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450385852 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.2450385852 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1310586806 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 236641266 ps |
| CPU time | 22.8 seconds |
| Started | Aug 06 09:05:04 PM PDT 24 |
| Finished | Aug 06 09:05:27 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-f0f5e2e7-c6fe-481b-851d-96536754851d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310586806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1310586806 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.803261646 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 178225906 ps |
| CPU time | 9.98 seconds |
| Started | Aug 06 09:04:58 PM PDT 24 |
| Finished | Aug 06 09:05:08 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-7e6a0eb3-2133-489b-8e9e-8d5005d22d7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803261646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.803261646 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.1122774624 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 95754277479 ps |
| CPU time | 1081.49 seconds |
| Started | Aug 06 09:04:57 PM PDT 24 |
| Finished | Aug 06 09:22:59 PM PDT 24 |
| Peak memory | 575904 kb |
| Host | smart-44f07154-d363-418a-9031-b36a5a06b63d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122774624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.1122774624 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1282060124 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 45738090276 ps |
| CPU time | 781.91 seconds |
| Started | Aug 06 09:05:03 PM PDT 24 |
| Finished | Aug 06 09:18:05 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-6bc6ed4a-3445-44dc-94c7-75ecea8305cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282060124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.1282060124 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.2200646889 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 305960313 ps |
| CPU time | 27.66 seconds |
| Started | Aug 06 09:04:57 PM PDT 24 |
| Finished | Aug 06 09:05:25 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-cd6dbff1-0eba-4bdb-9e4a-90b93d79c268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200646889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_del ays.2200646889 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.1127004304 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 536574403 ps |
| CPU time | 40.69 seconds |
| Started | Aug 06 09:05:05 PM PDT 24 |
| Finished | Aug 06 09:05:46 PM PDT 24 |
| Peak memory | 575800 kb |
| Host | smart-a2d01fe8-d1f8-4343-bf5e-12a959aa6045 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127004304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.1127004304 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.2004953167 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 182186625 ps |
| CPU time | 9.18 seconds |
| Started | Aug 06 09:04:57 PM PDT 24 |
| Finished | Aug 06 09:05:06 PM PDT 24 |
| Peak memory | 573724 kb |
| Host | smart-6a1bf7c6-3fb9-468d-b0a4-478a2041797a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004953167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.2004953167 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.2434697415 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 6145798713 ps |
| CPU time | 67.37 seconds |
| Started | Aug 06 09:04:58 PM PDT 24 |
| Finished | Aug 06 09:06:06 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-726e00a0-7e45-4a1f-9c0a-2e0e6746bfd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434697415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.2434697415 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.4042712988 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 4618256022 ps |
| CPU time | 79.47 seconds |
| Started | Aug 06 09:05:00 PM PDT 24 |
| Finished | Aug 06 09:06:19 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-8b1916c8-52b2-4ef5-a61b-2cbf9978c23c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042712988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.4042712988 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2302514255 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 56059003 ps |
| CPU time | 6.85 seconds |
| Started | Aug 06 09:04:57 PM PDT 24 |
| Finished | Aug 06 09:05:04 PM PDT 24 |
| Peak memory | 574552 kb |
| Host | smart-906e6b53-aabe-47d5-aba3-6a158082de1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302514255 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.2302514255 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.1957849691 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 2860168467 ps |
| CPU time | 232.13 seconds |
| Started | Aug 06 09:05:08 PM PDT 24 |
| Finished | Aug 06 09:09:00 PM PDT 24 |
| Peak memory | 576728 kb |
| Host | smart-f2ecef60-9c4d-4e2b-9f61-b5684a92adef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957849691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.1957849691 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.3125960361 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 9871162207 ps |
| CPU time | 342.01 seconds |
| Started | Aug 06 09:05:03 PM PDT 24 |
| Finished | Aug 06 09:10:46 PM PDT 24 |
| Peak memory | 575828 kb |
| Host | smart-bbdb83c4-70ed-4aac-b1e8-269ce43ccc7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125960361 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.3125960361 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3443059777 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 1023382381 ps |
| CPU time | 296.75 seconds |
| Started | Aug 06 09:05:05 PM PDT 24 |
| Finished | Aug 06 09:10:02 PM PDT 24 |
| Peak memory | 576664 kb |
| Host | smart-8b1d4a99-387e-4ab8-9f91-4657e49425ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443059777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3443059777 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2575341981 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 1837811003 ps |
| CPU time | 259.42 seconds |
| Started | Aug 06 09:05:04 PM PDT 24 |
| Finished | Aug 06 09:09:24 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-7571c690-3b05-4dc6-b5cd-c31432aceef5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575341981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.2575341981 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.924790282 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1290468988 ps |
| CPU time | 50.68 seconds |
| Started | Aug 06 09:05:05 PM PDT 24 |
| Finished | Aug 06 09:05:56 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-8f890546-ce9f-49ed-b42e-2337755e4b29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924790282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.924790282 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.2450037781 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 1307544177 ps |
| CPU time | 66.1 seconds |
| Started | Aug 06 09:05:08 PM PDT 24 |
| Finished | Aug 06 09:06:15 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-648226e2-5684-4843-84ba-11067f879865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450037781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .2450037781 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.1786351883 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 246283817 ps |
| CPU time | 26.64 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:05:48 PM PDT 24 |
| Peak memory | 575780 kb |
| Host | smart-1b23e3c3-c18c-450d-bfda-a6f144bd6bb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786351883 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.1786351883 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.3067494858 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 589321450 ps |
| CPU time | 21.83 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:05:43 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-f9425f3a-79c9-43da-a905-fc9195d1fe5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067494858 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.3067494858 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.3502678569 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 2235657356 ps |
| CPU time | 73.17 seconds |
| Started | Aug 06 09:05:08 PM PDT 24 |
| Finished | Aug 06 09:06:22 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-e42f2d14-4d9f-4be3-beb7-b8d470553df8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502678569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.3502678569 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.3996385634 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 65541097148 ps |
| CPU time | 673.52 seconds |
| Started | Aug 06 09:05:10 PM PDT 24 |
| Finished | Aug 06 09:16:24 PM PDT 24 |
| Peak memory | 576652 kb |
| Host | smart-972fc639-9b1d-4deb-b1db-8d9e2f38b02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996385634 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.3996385634 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2923825088 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 27876854361 ps |
| CPU time | 501.94 seconds |
| Started | Aug 06 09:05:09 PM PDT 24 |
| Finished | Aug 06 09:13:31 PM PDT 24 |
| Peak memory | 575932 kb |
| Host | smart-0c5f308f-d000-4cc6-bf84-260b20a6b37e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923825088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.2923825088 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.1572401730 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 302482973 ps |
| CPU time | 30.61 seconds |
| Started | Aug 06 09:05:07 PM PDT 24 |
| Finished | Aug 06 09:05:38 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-d4495415-3d1f-4153-b406-7fc040d97bbe |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572401730 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_del ays.1572401730 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.133061484 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 319316854 ps |
| CPU time | 27.33 seconds |
| Started | Aug 06 09:05:08 PM PDT 24 |
| Finished | Aug 06 09:05:35 PM PDT 24 |
| Peak memory | 575776 kb |
| Host | smart-d11d4db7-e27b-4e75-ab54-9a483ef299e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133061484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.133061484 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.2562108839 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 49591074 ps |
| CPU time | 6.51 seconds |
| Started | Aug 06 09:05:03 PM PDT 24 |
| Finished | Aug 06 09:05:10 PM PDT 24 |
| Peak memory | 573748 kb |
| Host | smart-10bcfe8b-40b4-4605-b981-31bcee1c135d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562108839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.2562108839 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.2018799179 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 8436069153 ps |
| CPU time | 87.57 seconds |
| Started | Aug 06 09:05:07 PM PDT 24 |
| Finished | Aug 06 09:06:35 PM PDT 24 |
| Peak memory | 574568 kb |
| Host | smart-b643b6a7-755f-4f70-81a6-79a3513f54eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018799179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.2018799179 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.2578030059 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 4778042868 ps |
| CPU time | 85.25 seconds |
| Started | Aug 06 09:05:08 PM PDT 24 |
| Finished | Aug 06 09:06:33 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-97f77219-a456-4a6c-845d-79316b2a6143 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578030059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.2578030059 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3526917319 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 50955159 ps |
| CPU time | 7.27 seconds |
| Started | Aug 06 09:05:07 PM PDT 24 |
| Finished | Aug 06 09:05:14 PM PDT 24 |
| Peak memory | 574360 kb |
| Host | smart-b0a7b14e-6ba6-458e-b8de-66a3c43e0255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526917319 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3526917319 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.300320240 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 6449860405 ps |
| CPU time | 245.76 seconds |
| Started | Aug 06 09:05:16 PM PDT 24 |
| Finished | Aug 06 09:09:22 PM PDT 24 |
| Peak memory | 576496 kb |
| Host | smart-4e853f64-2611-4f5e-90b3-007917e56d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300320240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.300320240 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3304432925 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 9526940003 ps |
| CPU time | 318.64 seconds |
| Started | Aug 06 09:05:22 PM PDT 24 |
| Finished | Aug 06 09:10:40 PM PDT 24 |
| Peak memory | 576668 kb |
| Host | smart-4e57742a-d95c-48bb-aea1-2d80c40851b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304432925 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3304432925 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.2941994598 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 4277463637 ps |
| CPU time | 607.24 seconds |
| Started | Aug 06 09:05:15 PM PDT 24 |
| Finished | Aug 06 09:15:22 PM PDT 24 |
| Peak memory | 576724 kb |
| Host | smart-15831c52-17b6-4b44-bb50-164dd604c568 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2941994598 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.2941994598 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2028509780 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 1422724882 ps |
| CPU time | 62.14 seconds |
| Started | Aug 06 09:05:14 PM PDT 24 |
| Finished | Aug 06 09:06:16 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-e2aa6a68-367b-4e02-b097-580c5627ee70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028509780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2028509780 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.465288423 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 547421758 ps |
| CPU time | 32.31 seconds |
| Started | Aug 06 09:05:22 PM PDT 24 |
| Finished | Aug 06 09:05:55 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-55dc757a-be3d-4d7b-9dcf-5eb9941131da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=465288423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 465288423 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1519937397 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 95024428036 ps |
| CPU time | 1523.78 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:30:45 PM PDT 24 |
| Peak memory | 576008 kb |
| Host | smart-c0e9df68-b35b-456b-aa36-3c8ce7807172 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519937397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1519937397 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3552516192 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 1449531227 ps |
| CPU time | 58.98 seconds |
| Started | Aug 06 09:05:22 PM PDT 24 |
| Finished | Aug 06 09:06:21 PM PDT 24 |
| Peak memory | 575880 kb |
| Host | smart-c8b6db60-b222-4796-af18-b0cea15af0d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552516192 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3552516192 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.246464315 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 404054807 ps |
| CPU time | 36.96 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:05:58 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-23c52834-0503-4179-98fe-567a5682a51d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246464315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.246464315 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.2809265429 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 516459758 ps |
| CPU time | 46.89 seconds |
| Started | Aug 06 09:05:15 PM PDT 24 |
| Finished | Aug 06 09:06:02 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-bb431479-58f0-4bc6-ad09-d0fe3f733b6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2809265429 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.2809265429 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.3593462021 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 46315319001 ps |
| CPU time | 469.71 seconds |
| Started | Aug 06 09:05:15 PM PDT 24 |
| Finished | Aug 06 09:13:05 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-4369ac17-3810-4562-827b-eeaf014bdd0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593462021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.3593462021 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.4128339151 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 60780023873 ps |
| CPU time | 994.82 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:21:56 PM PDT 24 |
| Peak memory | 575952 kb |
| Host | smart-cd3744ca-42f4-40b3-8b86-0c3b1ec2a30f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128339151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.4128339151 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.2623688092 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 624921641 ps |
| CPU time | 58.34 seconds |
| Started | Aug 06 09:05:13 PM PDT 24 |
| Finished | Aug 06 09:06:12 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-6cec2cfa-d08d-4866-912b-06a3d874a2e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623688092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.2623688092 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.1719458409 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 606255095 ps |
| CPU time | 21.72 seconds |
| Started | Aug 06 09:05:20 PM PDT 24 |
| Finished | Aug 06 09:05:42 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-8b89dccb-2d37-4db7-ab2e-bb4b76abcdd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719458409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.1719458409 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.2420086809 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 187147477 ps |
| CPU time | 8.45 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:05:30 PM PDT 24 |
| Peak memory | 573720 kb |
| Host | smart-f11c2203-cc90-4ecd-b355-997f7f7f3c71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420086809 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.2420086809 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.1964853423 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 8514732289 ps |
| CPU time | 89.62 seconds |
| Started | Aug 06 09:05:16 PM PDT 24 |
| Finished | Aug 06 09:06:46 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-4cd672f4-0a4d-4992-9968-9ebf3f905df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964853423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.1964853423 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.3861526316 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 5143674190 ps |
| CPU time | 88.45 seconds |
| Started | Aug 06 09:05:15 PM PDT 24 |
| Finished | Aug 06 09:06:43 PM PDT 24 |
| Peak memory | 575824 kb |
| Host | smart-4599376c-0d04-42ae-b282-a944f6da821e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861526316 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.3861526316 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.2821962539 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 43636680 ps |
| CPU time | 5.99 seconds |
| Started | Aug 06 09:05:13 PM PDT 24 |
| Finished | Aug 06 09:05:19 PM PDT 24 |
| Peak memory | 573708 kb |
| Host | smart-0ac8606f-b604-472c-806c-9befc5f4d5dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2821962539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delay s.2821962539 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.3271440905 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 2457979964 ps |
| CPU time | 102.99 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:07:04 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-5945f47b-1a22-4aa4-b895-e79a7d126327 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271440905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.3271440905 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.874867625 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 1597254362 ps |
| CPU time | 128.52 seconds |
| Started | Aug 06 09:05:24 PM PDT 24 |
| Finished | Aug 06 09:07:32 PM PDT 24 |
| Peak memory | 575896 kb |
| Host | smart-51f6bbfc-2cb2-472b-b4ca-854139fa270a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874867625 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.874867625 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.2762193179 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 423836663 ps |
| CPU time | 212.09 seconds |
| Started | Aug 06 09:05:20 PM PDT 24 |
| Finished | Aug 06 09:08:52 PM PDT 24 |
| Peak memory | 576780 kb |
| Host | smart-3e7afe7f-a10a-4166-9f78-32949d4f4b93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762193179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.2762193179 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.625555518 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 12900092897 ps |
| CPU time | 544.68 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:14:26 PM PDT 24 |
| Peak memory | 576712 kb |
| Host | smart-d9be565a-9b69-4abe-a094-23acd564e46d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625555518 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_reset_error.625555518 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.1865488324 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 203627668 ps |
| CPU time | 11.82 seconds |
| Started | Aug 06 09:05:22 PM PDT 24 |
| Finished | Aug 06 09:05:34 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-96d82901-f366-4669-aae2-0d2760589b73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865488324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.1865488324 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.18884464 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 449228422 ps |
| CPU time | 35.48 seconds |
| Started | Aug 06 09:05:25 PM PDT 24 |
| Finished | Aug 06 09:06:00 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-9692a99c-850e-4f14-96e4-cad263d7407c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18884464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device.18884464 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.124768859 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 18776473654 ps |
| CPU time | 352.6 seconds |
| Started | Aug 06 09:05:33 PM PDT 24 |
| Finished | Aug 06 09:11:26 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-9ca2ba27-c4db-4ce3-ada9-4156937c8cc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124768859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_d evice_slow_rsp.124768859 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.2460660283 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 205401592 ps |
| CPU time | 23.84 seconds |
| Started | Aug 06 09:05:30 PM PDT 24 |
| Finished | Aug 06 09:05:54 PM PDT 24 |
| Peak memory | 575856 kb |
| Host | smart-e247f5b5-aa63-40f2-a1f1-c17c1fb49c2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460660283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_add r.2460660283 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.3066718328 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 119537963 ps |
| CPU time | 14.95 seconds |
| Started | Aug 06 09:05:30 PM PDT 24 |
| Finished | Aug 06 09:05:45 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-9386afd7-ecc9-4846-88d3-0116b9af195e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066718328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.3066718328 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.1161025935 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 2322067865 ps |
| CPU time | 83.28 seconds |
| Started | Aug 06 09:05:24 PM PDT 24 |
| Finished | Aug 06 09:06:47 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-9e658bc5-cdb1-4105-8973-d8f1fb3f1d80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161025935 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.1161025935 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2497594310 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 5157203426 ps |
| CPU time | 54.84 seconds |
| Started | Aug 06 09:05:25 PM PDT 24 |
| Finished | Aug 06 09:06:20 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-14630116-ad19-4521-a77d-bcb437bd6c48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497594310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.2497594310 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.3155701963 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 57951836129 ps |
| CPU time | 928.83 seconds |
| Started | Aug 06 09:05:26 PM PDT 24 |
| Finished | Aug 06 09:20:55 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-90d7e381-94cb-4aab-84d1-330d2cd8500c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155701963 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.3155701963 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.596695285 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 371504908 ps |
| CPU time | 29.49 seconds |
| Started | Aug 06 09:05:26 PM PDT 24 |
| Finished | Aug 06 09:05:55 PM PDT 24 |
| Peak memory | 575796 kb |
| Host | smart-0f77064b-8162-45d7-8a1d-aafb1a200ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596695285 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_dela ys.596695285 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.3604937674 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 2179706854 ps |
| CPU time | 67.47 seconds |
| Started | Aug 06 09:05:31 PM PDT 24 |
| Finished | Aug 06 09:06:39 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-bcefdd13-3dbb-4e3a-9956-17074cfc3bc4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604937674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.3604937674 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.2509598030 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 195509042 ps |
| CPU time | 9.76 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:05:31 PM PDT 24 |
| Peak memory | 574388 kb |
| Host | smart-600b944b-ec97-404b-8f62-739c0965389b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509598030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.2509598030 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.1799528215 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 6972455428 ps |
| CPU time | 71.54 seconds |
| Started | Aug 06 09:05:21 PM PDT 24 |
| Finished | Aug 06 09:06:33 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-903953be-1579-4e67-9253-57a16e29a095 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799528215 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.1799528215 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.3527882388 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 3540537843 ps |
| CPU time | 60.42 seconds |
| Started | Aug 06 09:05:24 PM PDT 24 |
| Finished | Aug 06 09:06:25 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-e30d6110-ded0-43c4-8f99-b0cfef938ff0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527882388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.3527882388 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.127394308 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 50075369 ps |
| CPU time | 6.75 seconds |
| Started | Aug 06 09:05:24 PM PDT 24 |
| Finished | Aug 06 09:05:31 PM PDT 24 |
| Peak memory | 574300 kb |
| Host | smart-153bf9a8-c281-4d99-aeaa-730bd9110802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=127394308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delays .127394308 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.4070679198 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 3258303373 ps |
| CPU time | 117.95 seconds |
| Started | Aug 06 09:05:33 PM PDT 24 |
| Finished | Aug 06 09:07:31 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-8aeaabbe-2aa6-4cd5-86b5-5b3ed087650a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070679198 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.4070679198 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.2954032469 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 14590581806 ps |
| CPU time | 544.28 seconds |
| Started | Aug 06 09:05:31 PM PDT 24 |
| Finished | Aug 06 09:14:35 PM PDT 24 |
| Peak memory | 575892 kb |
| Host | smart-70615067-03de-47c2-8b92-ee7e7d45a697 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954032469 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2954032469 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.3456459032 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 137276977 ps |
| CPU time | 67.34 seconds |
| Started | Aug 06 09:05:30 PM PDT 24 |
| Finished | Aug 06 09:06:38 PM PDT 24 |
| Peak memory | 575772 kb |
| Host | smart-51316ea9-ed37-4028-ae94-dfad18556af5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456459032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.3456459032 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.1708196629 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 679579200 ps |
| CPU time | 154.83 seconds |
| Started | Aug 06 09:05:33 PM PDT 24 |
| Finished | Aug 06 09:08:08 PM PDT 24 |
| Peak memory | 576612 kb |
| Host | smart-f95165c4-52ed-47c5-bcf9-91b5762af61f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708196629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_al l_with_reset_error.1708196629 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1959013618 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 290628115 ps |
| CPU time | 31.76 seconds |
| Started | Aug 06 09:05:28 PM PDT 24 |
| Finished | Aug 06 09:06:00 PM PDT 24 |
| Peak memory | 575924 kb |
| Host | smart-4f285344-9ac4-41a4-946a-a2ae39d5348e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959013618 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.1959013618 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.3031629350 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 641476570 ps |
| CPU time | 33.4 seconds |
| Started | Aug 06 09:05:36 PM PDT 24 |
| Finished | Aug 06 09:06:09 PM PDT 24 |
| Peak memory | 575784 kb |
| Host | smart-2577a2e7-29a4-4963-94b3-42ddcb5b56d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3031629350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device .3031629350 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.179569440 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 77914841504 ps |
| CPU time | 1300.01 seconds |
| Started | Aug 06 09:05:34 PM PDT 24 |
| Finished | Aug 06 09:27:14 PM PDT 24 |
| Peak memory | 575804 kb |
| Host | smart-27004bb8-6f88-4d30-9695-f8a8581b7f64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179569440 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_d evice_slow_rsp.179569440 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.1946368981 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 645130274 ps |
| CPU time | 27.6 seconds |
| Started | Aug 06 09:05:39 PM PDT 24 |
| Finished | Aug 06 09:06:07 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-d1e12393-7c16-4043-8169-da504b9f0a75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946368981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.1946368981 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.3368534558 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 1027154826 ps |
| CPU time | 37.72 seconds |
| Started | Aug 06 09:05:38 PM PDT 24 |
| Finished | Aug 06 09:06:16 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-f9a0dedb-5d69-49b0-be2e-dcbf5454d782 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368534558 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.3368534558 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.1790052192 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 817783891 ps |
| CPU time | 34.25 seconds |
| Started | Aug 06 09:05:35 PM PDT 24 |
| Finished | Aug 06 09:06:10 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-ee60ff0c-a39c-4809-8fd1-0c22d86ce3d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790052192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.1790052192 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.1621824879 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 104574954763 ps |
| CPU time | 1098.92 seconds |
| Started | Aug 06 09:05:35 PM PDT 24 |
| Finished | Aug 06 09:23:54 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-f2ec148e-cf41-4b4c-8a04-b744f8101a8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621824879 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.1621824879 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.3057392274 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 50751625185 ps |
| CPU time | 880.99 seconds |
| Started | Aug 06 09:05:37 PM PDT 24 |
| Finished | Aug 06 09:20:18 PM PDT 24 |
| Peak memory | 575908 kb |
| Host | smart-08e36221-f69e-46f3-b130-edc94bf8f50f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057392274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.3057392274 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.1664079346 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 43927179 ps |
| CPU time | 6.78 seconds |
| Started | Aug 06 09:05:38 PM PDT 24 |
| Finished | Aug 06 09:05:45 PM PDT 24 |
| Peak memory | 573684 kb |
| Host | smart-7adfbd2a-b63b-4138-9b36-1d9c5bd212c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664079346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.1664079346 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.407247303 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 1761948556 ps |
| CPU time | 55.1 seconds |
| Started | Aug 06 09:05:38 PM PDT 24 |
| Finished | Aug 06 09:06:33 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-ef1b8710-5f1f-4d12-b6fc-4da8d1d7b0ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=407247303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.407247303 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.1005128427 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 49433484 ps |
| CPU time | 6.53 seconds |
| Started | Aug 06 09:05:31 PM PDT 24 |
| Finished | Aug 06 09:05:38 PM PDT 24 |
| Peak memory | 574416 kb |
| Host | smart-2b1ea570-9105-4fa3-8305-d8b8641ff5bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005128427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.1005128427 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.1295145107 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 5901674182 ps |
| CPU time | 62.24 seconds |
| Started | Aug 06 09:05:36 PM PDT 24 |
| Finished | Aug 06 09:06:38 PM PDT 24 |
| Peak memory | 575788 kb |
| Host | smart-194471e5-2bc6-4123-8642-130991057e3f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295145107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.1295145107 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.805763660 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 5003949526 ps |
| CPU time | 85.24 seconds |
| Started | Aug 06 09:05:35 PM PDT 24 |
| Finished | Aug 06 09:07:00 PM PDT 24 |
| Peak memory | 575816 kb |
| Host | smart-70feaa6d-98e2-4be2-b3a4-b7e9070bb90a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805763660 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.805763660 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.2943411288 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 47020748 ps |
| CPU time | 6.72 seconds |
| Started | Aug 06 09:05:35 PM PDT 24 |
| Finished | Aug 06 09:05:41 PM PDT 24 |
| Peak memory | 573828 kb |
| Host | smart-9b5d7b40-16a5-48bc-8e33-18f367eb9974 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2943411288 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delay s.2943411288 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.1653675412 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 9148905319 ps |
| CPU time | 311.75 seconds |
| Started | Aug 06 09:05:41 PM PDT 24 |
| Finished | Aug 06 09:10:53 PM PDT 24 |
| Peak memory | 575872 kb |
| Host | smart-a8967163-ee9f-41d4-a386-87f4eac8b612 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1653675412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.1653675412 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.686911061 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 6674581640 ps |
| CPU time | 225.12 seconds |
| Started | Aug 06 09:05:38 PM PDT 24 |
| Finished | Aug 06 09:09:23 PM PDT 24 |
| Peak memory | 575944 kb |
| Host | smart-b1ff6f91-6f86-4f7f-a911-120416d4b8a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686911061 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.686911061 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.175460091 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 6120344619 ps |
| CPU time | 423.09 seconds |
| Started | Aug 06 09:05:41 PM PDT 24 |
| Finished | Aug 06 09:12:44 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-f9cc9c98-c31e-424c-846e-4dbd9c6b0b7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175460091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_ with_rand_reset.175460091 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3931820364 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 410465699 ps |
| CPU time | 141.54 seconds |
| Started | Aug 06 09:05:41 PM PDT 24 |
| Finished | Aug 06 09:08:02 PM PDT 24 |
| Peak memory | 576636 kb |
| Host | smart-0fb5dac9-b363-4cfb-b692-bb64b0d0a4c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931820364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_al l_with_reset_error.3931820364 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.4235941260 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 322561608 ps |
| CPU time | 40.06 seconds |
| Started | Aug 06 09:05:41 PM PDT 24 |
| Finished | Aug 06 09:06:21 PM PDT 24 |
| Peak memory | 575844 kb |
| Host | smart-fd611219-f152-4f45-8fe1-794c8609fc04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235941260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.4235941260 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.2115244555 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 13665686604 ps |
| CPU time | 1310.13 seconds |
| Started | Aug 06 08:10:29 PM PDT 24 |
| Finished | Aug 06 08:32:20 PM PDT 24 |
| Peak memory | 607952 kb |
| Host | smart-c2789996-c624-4f72-9568-4b0c27c3b97f |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115244555 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.2 115244555 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.1039651912 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 2864311960 ps |
| CPU time | 328.62 seconds |
| Started | Aug 06 08:21:31 PM PDT 24 |
| Finished | Aug 06 08:27:00 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-73d51017-ae85-4e2a-b45c-6e6a941e3f9e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1039651912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.1039651912 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.2233511012 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 2395087834 ps |
| CPU time | 320.82 seconds |
| Started | Aug 06 08:26:28 PM PDT 24 |
| Finished | Aug 06 08:31:50 PM PDT 24 |
| Peak memory | 609588 kb |
| Host | smart-b44c5712-e2d9-48d0-8fdc-d9a21e90ed3c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233511012 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.2233511012 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2859943426 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 2666969264 ps |
| CPU time | 317.58 seconds |
| Started | Aug 06 08:22:36 PM PDT 24 |
| Finished | Aug 06 08:27:55 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-950445e9-5825-43e9-b44f-93a027360c83 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859 943426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2859943426 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.523689812 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 2678658836 ps |
| CPU time | 253.54 seconds |
| Started | Aug 06 08:22:42 PM PDT 24 |
| Finished | Aug 06 08:26:56 PM PDT 24 |
| Peak memory | 608500 kb |
| Host | smart-13f42fe7-2c71-42cf-bbe2-80f6f1b9459a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=523689812 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.523689812 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.3090768908 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 2697291056 ps |
| CPU time | 298.6 seconds |
| Started | Aug 06 08:26:20 PM PDT 24 |
| Finished | Aug 06 08:31:19 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-5c37ff82-95cd-4d4e-aeea-c1876085b175 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090768908 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.3090768908 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.2880542850 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 2576658912 ps |
| CPU time | 201.82 seconds |
| Started | Aug 06 08:20:38 PM PDT 24 |
| Finished | Aug 06 08:24:00 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-b3e825f7-dfce-45a5-a43e-7e7ea6a21533 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880542850 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.2880542850 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.1193982600 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 3129506590 ps |
| CPU time | 307.37 seconds |
| Started | Aug 06 08:20:47 PM PDT 24 |
| Finished | Aug 06 08:25:55 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-a8e1393e-da52-4182-a7c6-1a42ed8a283a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193982600 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.1193982600 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.195831627 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 2476006468 ps |
| CPU time | 256.76 seconds |
| Started | Aug 06 08:27:32 PM PDT 24 |
| Finished | Aug 06 08:31:49 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-d2048a9c-0c0c-466c-922f-99f286136ab4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195831627 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.195831627 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.62052455 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 3462847241 ps |
| CPU time | 314.56 seconds |
| Started | Aug 06 08:20:25 PM PDT 24 |
| Finished | Aug 06 08:25:40 PM PDT 24 |
| Peak memory | 609508 kb |
| Host | smart-13a3f85c-7cd1-4277-9ab3-46a8979b4db5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=62052455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.62052455 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.903458363 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 4344569692 ps |
| CPU time | 596.89 seconds |
| Started | Aug 06 08:26:40 PM PDT 24 |
| Finished | Aug 06 08:36:38 PM PDT 24 |
| Peak memory | 619696 kb |
| Host | smart-410374f8-c80d-4716-9b09-42bb3970870a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=903458363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.903458363 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.253427027 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 6035008052 ps |
| CPU time | 1245.33 seconds |
| Started | Aug 06 08:21:32 PM PDT 24 |
| Finished | Aug 06 08:42:18 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-c46127de-6963-4c02-8225-b0c956c58809 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=253427027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.253427027 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3999240746 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 7550269200 ps |
| CPU time | 1964.82 seconds |
| Started | Aug 06 08:24:40 PM PDT 24 |
| Finished | Aug 06 08:57:25 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-f4d6d90e-35a9-4c7b-8392-29bb75003590 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999240746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.3999240746 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.2993077938 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 7938747000 ps |
| CPU time | 1390.44 seconds |
| Started | Aug 06 08:24:15 PM PDT 24 |
| Finished | Aug 06 08:47:26 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-9985a9a8-978d-4269-bac4-b7aab241e883 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2993077938 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.2993077938 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.433889154 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 3583525982 ps |
| CPU time | 459.18 seconds |
| Started | Aug 06 08:26:57 PM PDT 24 |
| Finished | Aug 06 08:34:36 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-6281139d-b3b2-4bb5-b1fc-f708ccf7e420 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=433889154 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.433889154 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.976664697 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 6151195552 ps |
| CPU time | 457.66 seconds |
| Started | Aug 06 08:21:34 PM PDT 24 |
| Finished | Aug 06 08:29:12 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-36bd517b-0c66-4542-9ba9-592518351872 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=976664697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.976664697 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2081275045 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 3139966150 ps |
| CPU time | 276.79 seconds |
| Started | Aug 06 08:22:53 PM PDT 24 |
| Finished | Aug 06 08:27:31 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-fffd3973-dec1-4385-a56c-3e4e8e51175c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081275045 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_aon_timer_smoketest.2081275045 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3458887638 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 6940672792 ps |
| CPU time | 734.25 seconds |
| Started | Aug 06 08:24:40 PM PDT 24 |
| Finished | Aug 06 08:36:55 PM PDT 24 |
| Peak memory | 610252 kb |
| Host | smart-6f0d2654-3bb4-400b-9cd4-6cd22526bff0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3458887638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.3458887638 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4020731795 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 4351480890 ps |
| CPU time | 496.14 seconds |
| Started | Aug 06 08:21:44 PM PDT 24 |
| Finished | Aug 06 08:30:01 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-7d7fab10-5e0f-411d-b2cc-e6f8c43ae7a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =4020731795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.4020731795 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2277377900 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 8354820050 ps |
| CPU time | 917.93 seconds |
| Started | Aug 06 08:25:22 PM PDT 24 |
| Finished | Aug 06 08:40:40 PM PDT 24 |
| Peak memory | 617108 kb |
| Host | smart-ff6645d2-65e3-453c-a394-1206b035c263 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277377900 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2277377900 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4204899308 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 4441478824 ps |
| CPU time | 588.47 seconds |
| Started | Aug 06 08:23:06 PM PDT 24 |
| Finished | Aug 06 08:32:55 PM PDT 24 |
| Peak memory | 612216 kb |
| Host | smart-42e407b1-82d9-4409-a17e-3fedd04b2889 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204899308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.4204899308 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2593208143 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4435013360 ps |
| CPU time | 772.06 seconds |
| Started | Aug 06 08:23:51 PM PDT 24 |
| Finished | Aug 06 08:36:43 PM PDT 24 |
| Peak memory | 612188 kb |
| Host | smart-d2e4322a-a535-4f85-9471-9d04e6d155c6 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593208143 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2593208143 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3539777108 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 5095616664 ps |
| CPU time | 734.75 seconds |
| Started | Aug 06 08:23:04 PM PDT 24 |
| Finished | Aug 06 08:35:19 PM PDT 24 |
| Peak memory | 612140 kb |
| Host | smart-086433e4-55ce-4cc5-9d57-1c1152088698 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539777108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.3539777108 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2677596201 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 4976048320 ps |
| CPU time | 724.31 seconds |
| Started | Aug 06 08:26:22 PM PDT 24 |
| Finished | Aug 06 08:38:27 PM PDT 24 |
| Peak memory | 612936 kb |
| Host | smart-ce11be36-2eb7-49d9-9cc4-58c1a228e436 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677596201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2677596201 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3076761129 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 5525433486 ps |
| CPU time | 652.42 seconds |
| Started | Aug 06 08:22:30 PM PDT 24 |
| Finished | Aug 06 08:33:23 PM PDT 24 |
| Peak memory | 612968 kb |
| Host | smart-c6e73098-73cf-41a4-be51-2fe2f17aaaab |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076761129 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.3076761129 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.867558130 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 3416181611 ps |
| CPU time | 275.28 seconds |
| Started | Aug 06 08:27:21 PM PDT 24 |
| Finished | Aug 06 08:31:57 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-5413f53e-6eb1-43f6-9a9d-3efc52e92d6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867558130 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_clkmgr_jitter.867558130 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2841255789 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 3302490340 ps |
| CPU time | 343.7 seconds |
| Started | Aug 06 08:20:25 PM PDT 24 |
| Finished | Aug 06 08:26:09 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-6f2e9ddb-16ef-47a7-9400-3585406dbf46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841255789 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2841255789 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2484759570 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 3355306992 ps |
| CPU time | 241.64 seconds |
| Started | Aug 06 08:22:05 PM PDT 24 |
| Finished | Aug 06 08:26:07 PM PDT 24 |
| Peak memory | 609304 kb |
| Host | smart-a957944e-38e3-4a3e-9158-81176de330b9 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484759570 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.2484759570 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1532244275 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 5314949880 ps |
| CPU time | 485.81 seconds |
| Started | Aug 06 08:26:14 PM PDT 24 |
| Finished | Aug 06 08:34:20 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-731e4ea2-9645-4fe9-9f2a-7515ce13bca9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532244275 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.1532244275 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3038599218 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 5352153640 ps |
| CPU time | 386.6 seconds |
| Started | Aug 06 08:20:23 PM PDT 24 |
| Finished | Aug 06 08:26:50 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-e5459165-ecc2-40c1-b85b-5dfecb7f19c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038599218 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.3038599218 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.1840355669 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 4801431024 ps |
| CPU time | 407.61 seconds |
| Started | Aug 06 08:26:24 PM PDT 24 |
| Finished | Aug 06 08:33:12 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-3756dae6-6c6f-4747-85a0-779378d3be16 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840355669 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.1840355669 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.2386498721 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 11265581664 ps |
| CPU time | 1825.71 seconds |
| Started | Aug 06 08:21:23 PM PDT 24 |
| Finished | Aug 06 08:51:49 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-274fd713-9f14-419f-8b91-3ccee6c4df66 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386498721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.2386498721 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1024481944 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 3395068160 ps |
| CPU time | 444.96 seconds |
| Started | Aug 06 08:23:36 PM PDT 24 |
| Finished | Aug 06 08:31:02 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-8c84cc95-f7c2-4626-b218-8f4ea9cdab0b |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024481944 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.1024481944 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2600066730 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 4473020220 ps |
| CPU time | 648.77 seconds |
| Started | Aug 06 08:25:34 PM PDT 24 |
| Finished | Aug 06 08:36:23 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-aaa3a0f2-b1bc-4a35-862a-be151fd26199 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600066730 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.2600066730 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4016162892 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 2924393140 ps |
| CPU time | 290.27 seconds |
| Started | Aug 06 08:27:27 PM PDT 24 |
| Finished | Aug 06 08:32:17 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-cf154376-8344-45b5-9053-9f753d4e3d20 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016162892 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.4016162892 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.3614474491 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 72034697560 ps |
| CPU time | 13808.1 seconds |
| Started | Aug 06 08:26:39 PM PDT 24 |
| Finished | Aug 07 12:16:50 AM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-370f413d-b41a-48c2-b54e-43f76c249aa5 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3614474491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.3614474491 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1386988661 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 9465718300 ps |
| CPU time | 2680.81 seconds |
| Started | Aug 06 08:24:50 PM PDT 24 |
| Finished | Aug 06 09:09:31 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-2f1df5c1-f200-461b-b6d6-3df0a7a38d81 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386988661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.1386988661 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2933768564 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 9288049859 ps |
| CPU time | 2112.85 seconds |
| Started | Aug 06 08:22:18 PM PDT 24 |
| Finished | Aug 06 08:57:31 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-ebeeb767-d530-4be5-a7de-cdd7b62cb71d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2933768564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.2933768564 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2013440347 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 3436481856 ps |
| CPU time | 336.81 seconds |
| Started | Aug 06 08:23:56 PM PDT 24 |
| Finished | Aug 06 08:29:33 PM PDT 24 |
| Peak memory | 610528 kb |
| Host | smart-c5473355-180a-4c41-a8c4-cafd83837fb1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20134 40347 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.2013440347 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.317297 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 2909831368 ps |
| CPU time | 219.94 seconds |
| Started | Aug 06 08:24:10 PM PDT 24 |
| Finished | Aug 06 08:27:50 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-c78e7c43-5227-4711-b541-71c64440fdff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317297 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.317297 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.997338354 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 5609369264 ps |
| CPU time | 632.48 seconds |
| Started | Aug 06 08:21:14 PM PDT 24 |
| Finished | Aug 06 08:31:47 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-174d006e-51b6-48ec-abd1-e399e3e8d196 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=997338354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_l c_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrn g_lc_hw_debug_en_test.997338354 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.1334157983 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2457430296 ps |
| CPU time | 287.83 seconds |
| Started | Aug 06 08:27:06 PM PDT 24 |
| Finished | Aug 06 08:31:55 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-5a9f54ed-d634-4375-88ae-be6766f99c81 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334157983 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_csrng_smoketest.1334157983 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.618778118 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 5801888202 ps |
| CPU time | 660.72 seconds |
| Started | Aug 06 08:23:45 PM PDT 24 |
| Finished | Aug 06 08:34:47 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-8d74e660-f6c0-4433-b459-647e2052780d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=618778118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.618778118 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3840396290 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 6393249734 ps |
| CPU time | 1272.41 seconds |
| Started | Aug 06 08:21:59 PM PDT 24 |
| Finished | Aug 06 08:43:12 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-2c1104ba-adb6-430e-893c-5f96457c7d0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3840396290 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.3840396290 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3845682283 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 7865048011 ps |
| CPU time | 1504.59 seconds |
| Started | Aug 06 08:21:59 PM PDT 24 |
| Finished | Aug 06 08:47:04 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-5c789cff-36dd-40f7-8467-e1b89b2ec601 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845682283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.3845682283 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.2539763920 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3855069908 ps |
| CPU time | 683.7 seconds |
| Started | Aug 06 08:23:48 PM PDT 24 |
| Finished | Aug 06 08:35:12 PM PDT 24 |
| Peak memory | 615584 kb |
| Host | smart-2879e15f-ce50-4d0d-9429-c4deeb3b5f19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539763920 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.2539763920 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.449163252 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 9732941788 ps |
| CPU time | 2128.37 seconds |
| Started | Aug 06 08:24:26 PM PDT 24 |
| Finished | Aug 06 08:59:55 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-560a3526-d37c-42c9-95f0-b6a1a0183b58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449163252 -assert n opostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.449163252 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.173273080 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 2410259792 ps |
| CPU time | 218.1 seconds |
| Started | Aug 06 08:24:20 PM PDT 24 |
| Finished | Aug 06 08:27:58 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-60a68195-7ffa-450a-bd4d-f3a945938ce7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17 3273080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.173273080 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2485016673 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 2576406120 ps |
| CPU time | 259.77 seconds |
| Started | Aug 06 08:23:53 PM PDT 24 |
| Finished | Aug 06 08:28:13 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-beaed2c2-ba58-404f-a1cd-5b6be894c89e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485016673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.2485016673 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3625137282 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 4369721992 ps |
| CPU time | 649.04 seconds |
| Started | Aug 06 08:24:20 PM PDT 24 |
| Finished | Aug 06 08:35:09 PM PDT 24 |
| Peak memory | 610016 kb |
| Host | smart-38bfb84f-5cf6-47f1-9d69-e89c7a156c87 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3625137282 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3625137282 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.4002771857 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 3011895500 ps |
| CPU time | 315.68 seconds |
| Started | Aug 06 08:22:20 PM PDT 24 |
| Finished | Aug 06 08:27:37 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-6f7d4e6f-3af3-4645-9b76-6b2014861ea6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002771857 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.4002771857 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.3491623069 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 2424125064 ps |
| CPU time | 264.3 seconds |
| Started | Aug 06 08:21:49 PM PDT 24 |
| Finished | Aug 06 08:26:15 PM PDT 24 |
| Peak memory | 608476 kb |
| Host | smart-fad6474f-d179-44a9-b17e-f3d0a3319b3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491623069 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.3491623069 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2554017496 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 2211917410 ps |
| CPU time | 233.45 seconds |
| Started | Aug 06 08:23:41 PM PDT 24 |
| Finished | Aug 06 08:27:34 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-70d6e4db-6f4a-497d-ac80-8970550800f3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554017496 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2554017496 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.2622455928 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 2677862224 ps |
| CPU time | 143.86 seconds |
| Started | Aug 06 08:20:01 PM PDT 24 |
| Finished | Aug 06 08:22:25 PM PDT 24 |
| Peak memory | 607916 kb |
| Host | smart-99365ac8-997e-422f-8340-68c7583b35fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2622455928 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.2622455928 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3869783342 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 58995231309 ps |
| CPU time | 11894.9 seconds |
| Started | Aug 06 08:23:54 PM PDT 24 |
| Finished | Aug 06 11:42:11 PM PDT 24 |
| Peak memory | 624812 kb |
| Host | smart-8fa524b3-2196-4f7c-8894-34ee76be7d47 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3869783342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3869783342 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.492653977 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 5417883480 ps |
| CPU time | 768.45 seconds |
| Started | Aug 06 08:21:03 PM PDT 24 |
| Finished | Aug 06 08:33:53 PM PDT 24 |
| Peak memory | 611012 kb |
| Host | smart-417a8239-cabc-48df-baf0-6e5ffc1b3614 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=492653977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.492653977 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1202528114 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 5831540444 ps |
| CPU time | 1067.58 seconds |
| Started | Aug 06 08:23:20 PM PDT 24 |
| Finished | Aug 06 08:41:09 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-f594e582-9c1d-49ce-bc51-df056b9e4890 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202528114 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.1202528114 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3756265819 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 6200980016 ps |
| CPU time | 1245.48 seconds |
| Started | Aug 06 08:24:53 PM PDT 24 |
| Finished | Aug 06 08:45:40 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-ca4ce13b-9884-4da0-8601-be091187b315 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756265819 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.3756265819 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2322060018 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 7610759917 ps |
| CPU time | 1169.74 seconds |
| Started | Aug 06 08:22:58 PM PDT 24 |
| Finished | Aug 06 08:42:28 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-790b0886-7478-4027-8807-f9bee600a580 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322060018 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2322060018 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.607508589 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 6046139594 ps |
| CPU time | 989.47 seconds |
| Started | Aug 06 08:19:46 PM PDT 24 |
| Finished | Aug 06 08:36:16 PM PDT 24 |
| Peak memory | 609428 kb |
| Host | smart-dc75d010-db38-40f0-a542-7d34158c66e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607508589 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.607508589 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3546172112 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 3905625780 ps |
| CPU time | 388.89 seconds |
| Started | Aug 06 08:26:00 PM PDT 24 |
| Finished | Aug 06 08:32:29 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-8e419621-f4bd-4baf-ac89-e73078ecec6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546172112 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.3546172112 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2405005252 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 5903252236 ps |
| CPU time | 1175.24 seconds |
| Started | Aug 06 08:20:51 PM PDT 24 |
| Finished | Aug 06 08:40:27 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-3784e614-de9b-41a8-8f62-0be29fd46457 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405005252 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.2405005252 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.468312667 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4489474196 ps |
| CPU time | 709.42 seconds |
| Started | Aug 06 08:23:25 PM PDT 24 |
| Finished | Aug 06 08:35:15 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-c03d8fbc-a3d4-42c6-88bc-51797faa5ca5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468312667 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.468312667 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2315659900 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4869218272 ps |
| CPU time | 739.09 seconds |
| Started | Aug 06 08:25:01 PM PDT 24 |
| Finished | Aug 06 08:37:20 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-dd9ac81b-b06c-4956-82e5-99fab9a3ebc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2315659900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.2315659900 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.394391547 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 2429746574 ps |
| CPU time | 354.12 seconds |
| Started | Aug 06 08:22:22 PM PDT 24 |
| Finished | Aug 06 08:28:18 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-07aef04d-0f61-44d0-88ce-cab1c44a5624 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943915 47 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.394391547 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.490742604 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 19890007496 ps |
| CPU time | 2430.53 seconds |
| Started | Aug 06 08:18:28 PM PDT 24 |
| Finished | Aug 06 08:59:00 PM PDT 24 |
| Peak memory | 612696 kb |
| Host | smart-4f473858-8877-4554-bb18-be7c9126c22a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490742604 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.490742604 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.304858293 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 17524755022 ps |
| CPU time | 2373.72 seconds |
| Started | Aug 06 08:25:55 PM PDT 24 |
| Finished | Aug 06 09:05:29 PM PDT 24 |
| Peak memory | 613732 kb |
| Host | smart-0a1e5e0d-a9b9-498a-abae-2cd4d96b31a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=304858293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.304858293 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.821209467 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 3172156116 ps |
| CPU time | 221.59 seconds |
| Started | Aug 06 08:26:52 PM PDT 24 |
| Finished | Aug 06 08:30:33 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-abc7aec6-0879-46a8-99c8-0e442a5b860d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=821209467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.821209467 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.2867460019 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 3149828840 ps |
| CPU time | 508.1 seconds |
| Started | Aug 06 08:24:26 PM PDT 24 |
| Finished | Aug 06 08:32:55 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-a2a10409-9785-4932-87be-592fcc776f29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867460019 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_gpio.2867460019 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.1911841253 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 2746173560 ps |
| CPU time | 247.25 seconds |
| Started | Aug 06 08:26:13 PM PDT 24 |
| Finished | Aug 06 08:30:21 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-e109f004-089d-4bdb-82d5-8cf997b1f3ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911841253 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.1911841253 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.3049959548 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 3534867232 ps |
| CPU time | 391.71 seconds |
| Started | Aug 06 08:22:21 PM PDT 24 |
| Finished | Aug 06 08:28:53 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-4af34a98-d9c3-4cd8-ae8b-1b039b36490d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3049959548 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.3049959548 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.3773391207 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3079691608 ps |
| CPU time | 320.6 seconds |
| Started | Aug 06 08:24:42 PM PDT 24 |
| Finished | Aug 06 08:30:03 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-4945bf09-b8c2-46dc-8e1a-ae477eb5c328 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773391207 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_hmac_enc_idle.3773391207 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2209607252 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3294288428 ps |
| CPU time | 255.64 seconds |
| Started | Aug 06 08:25:33 PM PDT 24 |
| Finished | Aug 06 08:29:50 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-1c2bc59a-3f74-4aef-ad9c-bd836d74d80c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2209607252 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.2209607252 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.1727133838 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 8313866996 ps |
| CPU time | 1932.72 seconds |
| Started | Aug 06 08:26:01 PM PDT 24 |
| Finished | Aug 06 08:58:15 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-529dec9d-5b8f-44e6-8d95-56b6ff596d78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727133838 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.1727133838 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.1772225753 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 2803519902 ps |
| CPU time | 383.71 seconds |
| Started | Aug 06 08:25:44 PM PDT 24 |
| Finished | Aug 06 08:32:10 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-eba5e251-564d-470d-91e1-6c13a1be590e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772225753 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.1772225753 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.2935772697 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 3465041168 ps |
| CPU time | 397.07 seconds |
| Started | Aug 06 08:26:23 PM PDT 24 |
| Finished | Aug 06 08:33:01 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-6377ff84-8e95-41f7-a719-026ceb87882a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935772697 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.2935772697 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1224760714 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 5342855010 ps |
| CPU time | 922.01 seconds |
| Started | Aug 06 08:25:32 PM PDT 24 |
| Finished | Aug 06 08:40:55 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-7ce69ea3-53cf-4512-934f-b36cb072753e |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224760714 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.1224760714 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.3431279186 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 63618006282 ps |
| CPU time | 11835.3 seconds |
| Started | Aug 06 08:25:02 PM PDT 24 |
| Finished | Aug 06 11:42:18 PM PDT 24 |
| Peak memory | 624792 kb |
| Host | smart-d26f68c1-bd2b-400d-8bed-486f5cf8d56f |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3431279186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.3431279186 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1863726421 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 11519923732 ps |
| CPU time | 2287.34 seconds |
| Started | Aug 06 08:26:00 PM PDT 24 |
| Finished | Aug 06 09:04:09 PM PDT 24 |
| Peak memory | 617140 kb |
| Host | smart-19e4c3be-b307-4b83-bd76-4c4ed1258bbf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1863726421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.1863726421 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1945788573 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 12754460033 ps |
| CPU time | 2202.23 seconds |
| Started | Aug 06 08:25:16 PM PDT 24 |
| Finished | Aug 06 09:01:59 PM PDT 24 |
| Peak memory | 617120 kb |
| Host | smart-966b0034-1193-4ac6-a21d-e9ac6ed507c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1945788573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1945788573 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3874485644 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 8497800280 ps |
| CPU time | 1994.99 seconds |
| Started | Aug 06 08:25:28 PM PDT 24 |
| Finished | Aug 06 08:58:44 PM PDT 24 |
| Peak memory | 617852 kb |
| Host | smart-8045b74b-ab5f-450a-9308-205ffc91636e |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3874485644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3874485644 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1441137757 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 7904392710 ps |
| CPU time | 1423.69 seconds |
| Started | Aug 06 08:19:18 PM PDT 24 |
| Finished | Aug 06 08:43:03 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-05751c34-ea8d-4716-b91e-14784f6999cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14411 37757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1441137757 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.3765869275 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 3138820750 ps |
| CPU time | 293.38 seconds |
| Started | Aug 06 08:24:31 PM PDT 24 |
| Finished | Aug 06 08:29:25 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-a354caf7-9a7f-42d5-b943-8dc0531c46a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765869275 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.3765869275 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.3939475746 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 2853371000 ps |
| CPU time | 282.64 seconds |
| Started | Aug 06 08:24:01 PM PDT 24 |
| Finished | Aug 06 08:28:44 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-9fafe779-5987-4630-9f98-b0420df18d7b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939475746 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_entropy.3939475746 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.1697477724 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 2565325082 ps |
| CPU time | 232.83 seconds |
| Started | Aug 06 08:25:18 PM PDT 24 |
| Finished | Aug 06 08:29:13 PM PDT 24 |
| Peak memory | 609288 kb |
| Host | smart-ef1a3cfc-dcd8-4bca-a984-1d79d8adf7b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697477724 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.1697477724 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3771614721 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 3279790890 ps |
| CPU time | 239.92 seconds |
| Started | Aug 06 08:20:50 PM PDT 24 |
| Finished | Aug 06 08:24:50 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-cc424445-9a24-46fa-93e1-d92d49edf668 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771614721 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3771614721 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1273988497 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 3209455632 ps |
| CPU time | 261.16 seconds |
| Started | Aug 06 08:24:47 PM PDT 24 |
| Finished | Aug 06 08:29:10 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-c12cca5d-e801-4a41-a4fd-03f76cd3f360 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273988497 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1273988497 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1917438234 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 2964506681 ps |
| CPU time | 353.84 seconds |
| Started | Aug 06 08:20:48 PM PDT 24 |
| Finished | Aug 06 08:26:42 PM PDT 24 |
| Peak memory | 609324 kb |
| Host | smart-38c7627e-2e91-4e3a-94ac-81a4be85e605 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917438234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.1917438234 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2089565978 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 3396347902 ps |
| CPU time | 302.28 seconds |
| Started | Aug 06 08:19:51 PM PDT 24 |
| Finished | Aug 06 08:24:53 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-8f7f6831-5e69-49bb-b0ae-de298eff11eb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20895659 78 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2089565978 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.1495816831 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 3047477832 ps |
| CPU time | 292.15 seconds |
| Started | Aug 06 08:24:48 PM PDT 24 |
| Finished | Aug 06 08:29:40 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-493a7c2b-5b63-4338-816b-6f451d3839a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495816831 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.1495816831 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1316135202 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 3755849700 ps |
| CPU time | 345.01 seconds |
| Started | Aug 06 08:21:10 PM PDT 24 |
| Finished | Aug 06 08:26:56 PM PDT 24 |
| Peak memory | 609464 kb |
| Host | smart-42c9fd08-9727-410f-a68f-30505bf3d635 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316135202 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1316135202 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.887997156 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 2956837078 ps |
| CPU time | 157.99 seconds |
| Started | Aug 06 08:24:40 PM PDT 24 |
| Finished | Aug 06 08:27:19 PM PDT 24 |
| Peak memory | 620108 kb |
| Host | smart-2c0f91de-b7d0-4fa4-ae27-ed5c8c36e289 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887997156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.887997156 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2318452653 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 3513540413 ps |
| CPU time | 193.33 seconds |
| Started | Aug 06 08:22:33 PM PDT 24 |
| Finished | Aug 06 08:25:47 PM PDT 24 |
| Peak memory | 621772 kb |
| Host | smart-b8381767-b90c-488e-9e64-87cee3f1af39 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318452653 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.2318452653 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1596317779 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 3358300630 ps |
| CPU time | 171.84 seconds |
| Started | Aug 06 08:21:40 PM PDT 24 |
| Finished | Aug 06 08:24:33 PM PDT 24 |
| Peak memory | 620152 kb |
| Host | smart-c46e5efa-e59c-4e4d-b7e6-eb6506a86067 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1596317779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.1596317779 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3855799051 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 6690335753 ps |
| CPU time | 710.39 seconds |
| Started | Aug 06 08:24:04 PM PDT 24 |
| Finished | Aug 06 08:35:55 PM PDT 24 |
| Peak memory | 621476 kb |
| Host | smart-8e46c455-cb09-4af0-ade8-e10192c55390 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855799051 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.3855799051 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2285985251 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 3217185618 ps |
| CPU time | 114.87 seconds |
| Started | Aug 06 08:21:46 PM PDT 24 |
| Finished | Aug 06 08:23:42 PM PDT 24 |
| Peak memory | 617068 kb |
| Host | smart-582b1e72-2c88-454b-9524-275187fdb416 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2285985251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2285985251 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1121760850 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 2177591825 ps |
| CPU time | 125.24 seconds |
| Started | Aug 06 08:25:21 PM PDT 24 |
| Finished | Aug 06 08:27:28 PM PDT 24 |
| Peak memory | 617748 kb |
| Host | smart-9de07bdb-a8c3-4a7d-a426-3ef4e152c48e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121760850 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1121760850 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3259146194 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 50137326536 ps |
| CPU time | 5778.37 seconds |
| Started | Aug 06 08:22:54 PM PDT 24 |
| Finished | Aug 06 09:59:13 PM PDT 24 |
| Peak memory | 620840 kb |
| Host | smart-68fac78c-129b-41a7-ab3a-c349c3667523 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259146194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chi p_sw_lc_walkthrough_prod.3259146194 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.372196735 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 11233046580 ps |
| CPU time | 1285.79 seconds |
| Started | Aug 06 08:25:03 PM PDT 24 |
| Finished | Aug 06 08:46:29 PM PDT 24 |
| Peak memory | 619128 kb |
| Host | smart-dfebaf08-0601-4447-b7d6-abc2eac39844 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=372196735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.372196735 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3912384991 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 49508322869 ps |
| CPU time | 6318.94 seconds |
| Started | Aug 06 08:24:17 PM PDT 24 |
| Finished | Aug 06 10:09:38 PM PDT 24 |
| Peak memory | 619404 kb |
| Host | smart-3a0cdaac-c0d0-4a95-b904-7588aca391a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912384991 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.3912384991 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.4125987856 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 26859051182 ps |
| CPU time | 2322.12 seconds |
| Started | Aug 06 08:25:01 PM PDT 24 |
| Finished | Aug 06 09:03:45 PM PDT 24 |
| Peak memory | 621492 kb |
| Host | smart-943d9478-39fe-47d7-a54d-2972ab55e278 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=4125987856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.4125987856 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2070913860 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 17129556550 ps |
| CPU time | 4198.81 seconds |
| Started | Aug 06 08:25:22 PM PDT 24 |
| Finished | Aug 06 09:35:22 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-f5cc2fc3-6ec1-41b2-902d-3c3ceed04beb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2070913860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.2070913860 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1609945948 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 18061536640 ps |
| CPU time | 4005.1 seconds |
| Started | Aug 06 08:28:49 PM PDT 24 |
| Finished | Aug 06 09:35:35 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-bcd0666d-9aca-4cbc-9183-d89e37d7c814 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1609945948 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1609945948 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3204402219 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 3771019992 ps |
| CPU time | 603.27 seconds |
| Started | Aug 06 08:21:03 PM PDT 24 |
| Finished | Aug 06 08:31:07 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-334a9f26-1f32-40e3-b132-d6a14bc8e24c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204402219 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.3204402219 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.3074636011 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 5510010700 ps |
| CPU time | 1133.49 seconds |
| Started | Aug 06 08:24:57 PM PDT 24 |
| Finished | Aug 06 08:43:51 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-be937a44-bf24-41b7-8764-5113dec427c9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3074636011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.3074636011 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.1797465559 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 4973335604 ps |
| CPU time | 1262.73 seconds |
| Started | Aug 06 08:22:02 PM PDT 24 |
| Finished | Aug 06 08:43:05 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-dc51e46a-fe91-4aee-91bd-3c539aa3b630 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797465559 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.1797465559 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1174353351 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 28481979642 ps |
| CPU time | 5582.44 seconds |
| Started | Aug 06 08:24:56 PM PDT 24 |
| Finished | Aug 06 09:58:00 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-1b108f83-7a58-4f3f-bafd-33c8a80b8e43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117435 3351 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1174353351 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1416956997 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 3713755273 ps |
| CPU time | 363.1 seconds |
| Started | Aug 06 08:19:27 PM PDT 24 |
| Finished | Aug 06 08:25:32 PM PDT 24 |
| Peak memory | 609096 kb |
| Host | smart-4959ac36-1208-4d6d-8a79-961ead840eae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416956997 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.1416956997 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.114428673 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 9092644262 ps |
| CPU time | 1702.11 seconds |
| Started | Aug 06 08:26:21 PM PDT 24 |
| Finished | Aug 06 08:54:44 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-cd245d20-5bf9-4c55-9001-0db99d8e2c7c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=114428673 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.114428673 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3631416057 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 9483047070 ps |
| CPU time | 1292.04 seconds |
| Started | Aug 06 08:23:34 PM PDT 24 |
| Finished | Aug 06 08:45:06 PM PDT 24 |
| Peak memory | 610432 kb |
| Host | smart-593bb7f9-d9f5-4820-ab98-67225077f43e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3631416057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.3631416057 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1952645318 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 7595779212 ps |
| CPU time | 1402.65 seconds |
| Started | Aug 06 08:25:43 PM PDT 24 |
| Finished | Aug 06 08:49:06 PM PDT 24 |
| Peak memory | 610728 kb |
| Host | smart-d4b1dd43-5400-4c83-8b3a-e9eaecaf1838 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1952645318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.1952645318 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1306212062 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4437717940 ps |
| CPU time | 518.01 seconds |
| Started | Aug 06 08:21:30 PM PDT 24 |
| Finished | Aug 06 08:30:09 PM PDT 24 |
| Peak memory | 609048 kb |
| Host | smart-359253c2-69ef-4273-a822-09138f6058a0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1306212062 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1306212062 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.306716716 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 2561539980 ps |
| CPU time | 325.88 seconds |
| Started | Aug 06 08:25:37 PM PDT 24 |
| Finished | Aug 06 08:31:03 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-48716cf4-62f7-4d53-afe3-0649f8ab52d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306716716 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_otp_ctrl_smoketest.306716716 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.1885898054 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 3255923926 ps |
| CPU time | 281.29 seconds |
| Started | Aug 06 08:22:37 PM PDT 24 |
| Finished | Aug 06 08:27:20 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-405faf9b-6ca1-4d1c-bac3-ac450268cce5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885898054 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.1885898054 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.4238222032 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 4010946332 ps |
| CPU time | 773.67 seconds |
| Started | Aug 06 08:28:59 PM PDT 24 |
| Finished | Aug 06 08:41:54 PM PDT 24 |
| Peak memory | 609412 kb |
| Host | smart-2f28228e-e996-4d1f-a194-a3d8b5c1032e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238222032 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.4238222032 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.737927868 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 9965885000 ps |
| CPU time | 403.88 seconds |
| Started | Aug 06 08:25:00 PM PDT 24 |
| Finished | Aug 06 08:31:44 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-bae21a88-0b38-409e-880a-5c94a301a402 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737927868 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.737927868 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2883525180 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 9616935571 ps |
| CPU time | 1779.75 seconds |
| Started | Aug 06 08:22:39 PM PDT 24 |
| Finished | Aug 06 08:52:19 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-2967c878-bb21-4fde-aab5-acf776e8bd29 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883 525180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.2883525180 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.3513046040 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 24055147600 ps |
| CPU time | 2667.91 seconds |
| Started | Aug 06 08:21:00 PM PDT 24 |
| Finished | Aug 06 09:05:29 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-2fd8ff07-e55d-423e-9ba8-455546b24453 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351 3046040 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.3513046040 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2581035721 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 15937787367 ps |
| CPU time | 1842.81 seconds |
| Started | Aug 06 08:22:22 PM PDT 24 |
| Finished | Aug 06 08:53:06 PM PDT 24 |
| Peak memory | 611304 kb |
| Host | smart-fdc0699c-7624-42a6-8a3f-a0a7541732a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2581035721 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2581035721 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.456230457 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 24136533356 ps |
| CPU time | 1710 seconds |
| Started | Aug 06 08:25:39 PM PDT 24 |
| Finished | Aug 06 08:54:09 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-bbffc37a-1a8d-491e-9eb6-90f2f72a69ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 456230457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.456230457 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.2589086128 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 9938365650 ps |
| CPU time | 869.1 seconds |
| Started | Aug 06 08:21:10 PM PDT 24 |
| Finished | Aug 06 08:35:41 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-e1064831-6afe-4084-bed8-0dc1f10ee318 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589086128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.2589086128 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2227303714 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 6218739090 ps |
| CPU time | 433.59 seconds |
| Started | Aug 06 08:19:52 PM PDT 24 |
| Finished | Aug 06 08:27:06 PM PDT 24 |
| Peak memory | 616536 kb |
| Host | smart-8d112d9e-cc63-4cee-8890-3b141d6998da |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2227303714 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2227303714 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3525958576 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 4478785420 ps |
| CPU time | 336.04 seconds |
| Started | Aug 06 08:22:28 PM PDT 24 |
| Finished | Aug 06 08:28:05 PM PDT 24 |
| Peak memory | 616040 kb |
| Host | smart-9f0527fb-08cf-41e3-9dc8-9f53293c897b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3525958576 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.3525958576 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.334810377 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 12840974736 ps |
| CPU time | 1622.43 seconds |
| Started | Aug 06 08:22:57 PM PDT 24 |
| Finished | Aug 06 08:50:01 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-4bfd0f19-5392-434f-bc29-cdbcd3157160 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334810377 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.334810377 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4176588808 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 7475549680 ps |
| CPU time | 543.04 seconds |
| Started | Aug 06 08:26:17 PM PDT 24 |
| Finished | Aug 06 08:35:22 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-053f1496-06b4-4a66-a289-13603a460c60 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176588808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4176588808 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4197899473 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 29134900709 ps |
| CPU time | 3301.49 seconds |
| Started | Aug 06 08:19:54 PM PDT 24 |
| Finished | Aug 06 09:14:56 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-8a9f43c7-e229-42bb-a2fa-38a5347ca5fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4197899473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4197899473 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1038880742 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 21346112840 ps |
| CPU time | 2062.51 seconds |
| Started | Aug 06 08:21:33 PM PDT 24 |
| Finished | Aug 06 08:55:56 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-33cefa68-6635-434e-938c-4098c0e2cd15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1038880742 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1038880742 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2909561761 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 36518847629 ps |
| CPU time | 2677.03 seconds |
| Started | Aug 06 08:25:04 PM PDT 24 |
| Finished | Aug 06 09:09:42 PM PDT 24 |
| Peak memory | 612480 kb |
| Host | smart-8f8a051d-2b12-4b71-854b-19c6ab161abf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909561761 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2909561761 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.574356107 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 3628776680 ps |
| CPU time | 361.02 seconds |
| Started | Aug 06 08:23:08 PM PDT 24 |
| Finished | Aug 06 08:29:09 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-6f1ed245-52f4-4677-b5f0-f5ee4902b1ca |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574356107 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.574356107 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3671978585 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 5036519472 ps |
| CPU time | 459.8 seconds |
| Started | Aug 06 08:21:57 PM PDT 24 |
| Finished | Aug 06 08:29:37 PM PDT 24 |
| Peak memory | 616276 kb |
| Host | smart-d62b54ee-3b57-4fa8-a783-72fd3fa0dbc4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3671978585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_power_glitch_reset.3671978585 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1797707820 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 6043594440 ps |
| CPU time | 549.46 seconds |
| Started | Aug 06 08:25:19 PM PDT 24 |
| Finished | Aug 06 08:34:29 PM PDT 24 |
| Peak memory | 610832 kb |
| Host | smart-15fc3db4-f12b-4731-bba2-f1bc1070dbb5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1797707820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.1797707820 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3934432561 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 6673147384 ps |
| CPU time | 566.39 seconds |
| Started | Aug 06 08:28:06 PM PDT 24 |
| Finished | Aug 06 08:37:33 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-f63409ee-d736-4b7e-a34a-f654a665b4e4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934432561 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.3934432561 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.2723771857 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 8293365160 ps |
| CPU time | 1039.45 seconds |
| Started | Aug 06 08:25:08 PM PDT 24 |
| Finished | Aug 06 08:42:28 PM PDT 24 |
| Peak memory | 610952 kb |
| Host | smart-c56e9fd0-1a93-4060-8b48-4c1075710b95 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723771857 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.2723771857 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1395784388 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 4533184520 ps |
| CPU time | 443.56 seconds |
| Started | Aug 06 08:22:00 PM PDT 24 |
| Finished | Aug 06 08:29:23 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-1a3d10e2-a05a-4e49-9c38-de47a151337f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395784388 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1395784388 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3334755246 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 6115422886 ps |
| CPU time | 436.74 seconds |
| Started | Aug 06 08:26:48 PM PDT 24 |
| Finished | Aug 06 08:34:05 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-86e1cfe1-74cb-45c5-b81f-e0043357a5b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3334755246 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3334755246 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2362536013 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 4093593256 ps |
| CPU time | 451.19 seconds |
| Started | Aug 06 08:22:34 PM PDT 24 |
| Finished | Aug 06 08:30:06 PM PDT 24 |
| Peak memory | 609120 kb |
| Host | smart-cba21b98-42fd-4550-8bc0-b9ebc79489ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236 2536013 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.2362536013 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2494517803 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 9190747507 ps |
| CPU time | 627.11 seconds |
| Started | Aug 06 08:25:08 PM PDT 24 |
| Finished | Aug 06 08:35:36 PM PDT 24 |
| Peak memory | 624728 kb |
| Host | smart-bc06020f-dbf6-42b6-b0c1-24c1aefca3f4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494517803 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.2494517803 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2585311960 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 11781366072 ps |
| CPU time | 2119.63 seconds |
| Started | Aug 06 08:23:50 PM PDT 24 |
| Finished | Aug 06 08:59:10 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-1d0a0092-5360-45f6-a8db-a76e2b1a18d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2585311960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.2585311960 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.4188235422 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 5471792870 ps |
| CPU time | 721.08 seconds |
| Started | Aug 06 08:25:39 PM PDT 24 |
| Finished | Aug 06 08:37:42 PM PDT 24 |
| Peak memory | 609220 kb |
| Host | smart-151ef0c9-ff1a-4e51-b1c3-343a3a2eb0ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188235422 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.4188235422 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2656002266 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 5857225022 ps |
| CPU time | 789.01 seconds |
| Started | Aug 06 08:23:45 PM PDT 24 |
| Finished | Aug 06 08:36:55 PM PDT 24 |
| Peak memory | 641516 kb |
| Host | smart-6bf3aaf3-8cc7-46f2-9284-7007ddb13a3a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2656002266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.2656002266 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2982759469 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 2254392882 ps |
| CPU time | 229.18 seconds |
| Started | Aug 06 08:22:17 PM PDT 24 |
| Finished | Aug 06 08:26:06 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-b18f60d4-af51-4dee-aafb-12902c9a56d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2982759469 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2982759469 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1768687853 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 5001018760 ps |
| CPU time | 527.51 seconds |
| Started | Aug 06 08:23:35 PM PDT 24 |
| Finished | Aug 06 08:32:25 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-860ab12d-6a4b-4347-a067-cab5db95e124 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768687853 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.1768687853 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.638080353 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2415760264 ps |
| CPU time | 227.58 seconds |
| Started | Aug 06 08:21:00 PM PDT 24 |
| Finished | Aug 06 08:24:48 PM PDT 24 |
| Peak memory | 608556 kb |
| Host | smart-09e7e567-f78f-40d6-8019-28639b974169 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638080353 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.638080353 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.85769741 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 3265753634 ps |
| CPU time | 322.3 seconds |
| Started | Aug 06 08:27:02 PM PDT 24 |
| Finished | Aug 06 08:32:25 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-55485122-afdc-4f4f-8949-bb6dc691e354 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85769741 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.85769741 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2570325751 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 3480400664 ps |
| CPU time | 287.39 seconds |
| Started | Aug 06 08:19:57 PM PDT 24 |
| Finished | Aug 06 08:24:45 PM PDT 24 |
| Peak memory | 647308 kb |
| Host | smart-6e322810-4343-401b-91a5-5037a92d5aa1 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570325751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.2570325751 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3508054895 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 5262403370 ps |
| CPU time | 1066.22 seconds |
| Started | Aug 06 08:20:54 PM PDT 24 |
| Finished | Aug 06 08:38:41 PM PDT 24 |
| Peak memory | 608872 kb |
| Host | smart-de80fd79-64cc-4907-acac-b4f893989e51 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=3508054895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.3508054895 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1739492040 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4644005580 ps |
| CPU time | 491.36 seconds |
| Started | Aug 06 08:26:15 PM PDT 24 |
| Finished | Aug 06 08:34:26 PM PDT 24 |
| Peak memory | 624408 kb |
| Host | smart-1bb20b5e-69b8-4d45-acff-873dd4b3ee8c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739492040 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.1739492040 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.3630292990 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 5405646800 ps |
| CPU time | 605.79 seconds |
| Started | Aug 06 08:27:45 PM PDT 24 |
| Finished | Aug 06 08:37:51 PM PDT 24 |
| Peak memory | 619280 kb |
| Host | smart-93eeb08c-868b-4a83-b1d4-6ee2bb0c8ba1 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630292990 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.3630292990 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1575820156 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 2825260592 ps |
| CPU time | 228.13 seconds |
| Started | Aug 06 08:27:04 PM PDT 24 |
| Finished | Aug 06 08:30:52 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-ff243849-afbf-4a29-a255-d55fc8e088eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575820156 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.1575820156 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.1344412847 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 3307173952 ps |
| CPU time | 393.62 seconds |
| Started | Aug 06 08:26:34 PM PDT 24 |
| Finished | Aug 06 08:33:08 PM PDT 24 |
| Peak memory | 609540 kb |
| Host | smart-34cedb61-a75b-4ddb-8393-8b1e414fe578 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344412847 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.1344412847 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.623749274 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 3233345116 ps |
| CPU time | 210.19 seconds |
| Started | Aug 06 08:19:40 PM PDT 24 |
| Finished | Aug 06 08:23:11 PM PDT 24 |
| Peak memory | 608540 kb |
| Host | smart-14123d86-6a44-4b45-9463-973348cd33d7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623749274 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_timer_smoketest.623749274 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2125323840 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 2386073292 ps |
| CPU time | 255.25 seconds |
| Started | Aug 06 08:26:38 PM PDT 24 |
| Finished | Aug 06 08:30:55 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-b1a5b024-ae3b-4b1d-b650-eb8745e034f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125323 840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.2125323840 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1151649071 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 9459647944 ps |
| CPU time | 1270.88 seconds |
| Started | Aug 06 08:25:47 PM PDT 24 |
| Finished | Aug 06 08:46:59 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-627f554c-f003-48fd-ad2e-e2e554c4a515 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151649071 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.1151649071 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1963226066 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 6868623000 ps |
| CPU time | 802.48 seconds |
| Started | Aug 06 08:23:23 PM PDT 24 |
| Finished | Aug 06 08:36:46 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-c730228f-1d38-41f1-a6ba-ca671c323ee1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963226066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sl eep_sram_ret_contents_no_scramble.1963226066 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.25646277 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 9299579626 ps |
| CPU time | 851.83 seconds |
| Started | Aug 06 08:22:49 PM PDT 24 |
| Finished | Aug 06 08:37:01 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-d6e14f96-ce3f-4bfe-ab7c-58250b428b60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25646277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_s ram_ret_contents_scramble.25646277 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.1936104385 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 6653804849 ps |
| CPU time | 616.88 seconds |
| Started | Aug 06 08:24:47 PM PDT 24 |
| Finished | Aug 06 08:35:05 PM PDT 24 |
| Peak memory | 624840 kb |
| Host | smart-8ae35da3-7204-4c81-af82-4c22d900cd4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936104385 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.1936104385 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1149927519 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 4429246426 ps |
| CPU time | 548.62 seconds |
| Started | Aug 06 08:22:45 PM PDT 24 |
| Finished | Aug 06 08:31:55 PM PDT 24 |
| Peak memory | 624704 kb |
| Host | smart-e1f19cd5-b2ba-4bbd-b1cd-0cf96123041c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149927519 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.1149927519 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2599111504 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 3883884127 ps |
| CPU time | 326.7 seconds |
| Started | Aug 06 08:22:45 PM PDT 24 |
| Finished | Aug 06 08:28:12 PM PDT 24 |
| Peak memory | 618928 kb |
| Host | smart-71a0651e-6ee8-4626-bafc-60036f7eebf1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599111504 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.2599111504 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.747898680 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3912116464 ps |
| CPU time | 355.91 seconds |
| Started | Aug 06 08:25:40 PM PDT 24 |
| Finished | Aug 06 08:31:37 PM PDT 24 |
| Peak memory | 618564 kb |
| Host | smart-7d6ccf95-eb75-484f-b0fb-da06676334ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747898680 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.747898680 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2893779472 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 3067706856 ps |
| CPU time | 361.23 seconds |
| Started | Aug 06 08:21:27 PM PDT 24 |
| Finished | Aug 06 08:27:30 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-1c54cb4a-bf9e-41c9-95d9-2ce444f7d5e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893779472 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2893779472 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2147489603 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 4907655480 ps |
| CPU time | 596.08 seconds |
| Started | Aug 06 08:22:31 PM PDT 24 |
| Finished | Aug 06 08:32:28 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-09fe194a-44a5-4178-b903-52a4d9f5f397 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147489603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2147489603 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2971996887 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 5606856925 ps |
| CPU time | 673.58 seconds |
| Started | Aug 06 08:25:33 PM PDT 24 |
| Finished | Aug 06 08:36:47 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-bdd7aef4-1737-4b94-bc34-4e6447893fdb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971996887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2971996887 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3470974172 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 4135566905 ps |
| CPU time | 590.1 seconds |
| Started | Aug 06 08:25:59 PM PDT 24 |
| Finished | Aug 06 08:35:50 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-49dbe524-1f99-4c77-b363-42740861bb83 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470974172 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3470974172 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.643533569 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 3671338450 ps |
| CPU time | 379.38 seconds |
| Started | Aug 06 08:24:15 PM PDT 24 |
| Finished | Aug 06 08:30:35 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-baf3314f-2159-4812-bf0a-a6b6e49a6b56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=643533569 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_sram_ctrl_smoketest.643533569 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3600893200 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 20366892525 ps |
| CPU time | 3560.53 seconds |
| Started | Aug 06 08:19:48 PM PDT 24 |
| Finished | Aug 06 09:19:09 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-254e5f63-44ab-4065-bfdc-c00dfda427e7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600893200 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3600893200 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2111956 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 4237852128 ps |
| CPU time | 582.11 seconds |
| Started | Aug 06 08:23:05 PM PDT 24 |
| Finished | Aug 06 08:32:49 PM PDT 24 |
| Peak memory | 613392 kb |
| Host | smart-784c166d-2202-441d-85a5-4fefaf28f27b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111956 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.2111956 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2967858146 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 4409641536 ps |
| CPU time | 454.58 seconds |
| Started | Aug 06 08:22:20 PM PDT 24 |
| Finished | Aug 06 08:29:55 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-621072f4-7eac-434e-aec4-254e3f622266 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967858146 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.2967858146 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.2290465052 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 24745890248 ps |
| CPU time | 1924.12 seconds |
| Started | Aug 06 08:24:24 PM PDT 24 |
| Finished | Aug 06 08:56:30 PM PDT 24 |
| Peak memory | 615196 kb |
| Host | smart-3d5f069e-1b8c-4133-97bc-9b3a939865bb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22904650 52 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.2290465052 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3515521960 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 6588262096 ps |
| CPU time | 437.43 seconds |
| Started | Aug 06 08:23:05 PM PDT 24 |
| Finished | Aug 06 08:30:23 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-9ea7c19f-981e-4168-8505-42acdc6d1fbb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515521960 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3515521960 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.3269341144 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 3440825048 ps |
| CPU time | 227.25 seconds |
| Started | Aug 06 08:26:10 PM PDT 24 |
| Finished | Aug 06 08:29:58 PM PDT 24 |
| Peak memory | 615072 kb |
| Host | smart-75c8b6dc-e4bc-44fd-960b-0a558ecab5df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269341144 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.3269341144 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2458476426 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 4246713370 ps |
| CPU time | 629.21 seconds |
| Started | Aug 06 08:22:25 PM PDT 24 |
| Finished | Aug 06 08:32:56 PM PDT 24 |
| Peak memory | 619008 kb |
| Host | smart-19b3852d-f1f5-43bb-a5f0-4e47c886055f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458476426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.2458476426 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3881482916 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 5223834941 ps |
| CPU time | 616.8 seconds |
| Started | Aug 06 08:23:03 PM PDT 24 |
| Finished | Aug 06 08:33:20 PM PDT 24 |
| Peak memory | 623632 kb |
| Host | smart-3268e84a-fe9c-4785-bdfb-875ef92c57ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881482916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3881482916 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2050076421 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 78869753000 ps |
| CPU time | 15643.4 seconds |
| Started | Aug 06 08:23:14 PM PDT 24 |
| Finished | Aug 07 12:43:59 AM PDT 24 |
| Peak memory | 634036 kb |
| Host | smart-0ec83440-60d3-4325-a1c1-2ae1cd5a993e |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2050076421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.2050076421 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.670766918 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 5027212908 ps |
| CPU time | 708.94 seconds |
| Started | Aug 06 08:22:26 PM PDT 24 |
| Finished | Aug 06 08:34:16 PM PDT 24 |
| Peak memory | 623960 kb |
| Host | smart-1f8a25c5-d7da-41b9-b50b-d5b24c802cc7 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670766918 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.670766918 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2046048143 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 4561117572 ps |
| CPU time | 756.97 seconds |
| Started | Aug 06 08:24:55 PM PDT 24 |
| Finished | Aug 06 08:37:33 PM PDT 24 |
| Peak memory | 624212 kb |
| Host | smart-fac6e145-4677-413d-b300-33dbe8aaee0c |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046048143 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2046048143 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2501688197 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 3105812754 ps |
| CPU time | 307.59 seconds |
| Started | Aug 06 08:21:28 PM PDT 24 |
| Finished | Aug 06 08:26:37 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-4be58397-271a-465b-9cb8-a31173b46a5a |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501688197 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.2501688197 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3470541442 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7960463504 ps |
| CPU time | 2193.6 seconds |
| Started | Aug 06 08:22:54 PM PDT 24 |
| Finished | Aug 06 08:59:29 PM PDT 24 |
| Peak memory | 608948 kb |
| Host | smart-916fd022-8312-40e5-8d23-98cd4ca7ae27 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34705 41442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3470541442 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.2331091656 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 12054993792 ps |
| CPU time | 2886.9 seconds |
| Started | Aug 06 08:24:08 PM PDT 24 |
| Finished | Aug 06 09:12:16 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-f917d66c-867b-43e0-9c0c-23a22f4c0a68 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2331091656 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.2331091656 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.3849914776 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 3061210610 ps |
| CPU time | 262.61 seconds |
| Started | Aug 06 08:20:25 PM PDT 24 |
| Finished | Aug 06 08:24:49 PM PDT 24 |
| Peak memory | 608560 kb |
| Host | smart-cc96c335-8f34-49b0-97de-00afdf2872d8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3849914776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.3849914776 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3043422617 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 3860483928 ps |
| CPU time | 567.05 seconds |
| Started | Aug 06 08:21:37 PM PDT 24 |
| Finished | Aug 06 08:31:04 PM PDT 24 |
| Peak memory | 609844 kb |
| Host | smart-3c3ce56f-09c5-4c06-a1c6-d389f0601455 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304342261 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.3043422617 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.716754599 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 18541590096 ps |
| CPU time | 4614.05 seconds |
| Started | Aug 06 08:21:59 PM PDT 24 |
| Finished | Aug 06 09:38:54 PM PDT 24 |
| Peak memory | 609268 kb |
| Host | smart-25b460ff-a649-4ebc-a02f-5a669bad3d14 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=716754599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.716754599 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.3385038820 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 2533058934 ps |
| CPU time | 205.29 seconds |
| Started | Aug 06 08:24:21 PM PDT 24 |
| Finished | Aug 06 08:27:47 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-101250da-5c09-44e2-92cf-14e138f95478 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385038820 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.3385038820 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.2812718466 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 7219964589 ps |
| CPU time | 709.13 seconds |
| Started | Aug 06 08:24:29 PM PDT 24 |
| Finished | Aug 06 08:36:19 PM PDT 24 |
| Peak memory | 621016 kb |
| Host | smart-1a915265-b0ee-4612-9036-5c82b7f3e653 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812718466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2812718466 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.3279787525 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 5416301094 ps |
| CPU time | 474.25 seconds |
| Started | Aug 06 08:20:58 PM PDT 24 |
| Finished | Aug 06 08:28:53 PM PDT 24 |
| Peak memory | 624656 kb |
| Host | smart-ac267b70-2fea-4514-ae46-83e4e9558ba8 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3279787525 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.3279787525 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.1375927191 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 14899349440 ps |
| CPU time | 4433.35 seconds |
| Started | Aug 06 08:31:51 PM PDT 24 |
| Finished | Aug 06 09:45:45 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-b6c2fee9-2135-43f5-8d78-4d84dde29cb7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375927191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.1375927191 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.470100320 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 14871804957 ps |
| CPU time | 4477.21 seconds |
| Started | Aug 06 08:28:59 PM PDT 24 |
| Finished | Aug 06 09:43:37 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-07a987bc-d22f-477c-b63a-8600c102fad7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470100320 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.470100320 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3005532903 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 15641630478 ps |
| CPU time | 4538.23 seconds |
| Started | Aug 06 08:31:15 PM PDT 24 |
| Finished | Aug 06 09:46:54 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-34241c1a-4623-4a4c-b64a-ab6e93235bde |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005532903 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3005532903 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.583466395 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 15285759283 ps |
| CPU time | 3862.75 seconds |
| Started | Aug 06 08:28:52 PM PDT 24 |
| Finished | Aug 06 09:33:16 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-fb9b5780-c0c5-41a6-bf9f-ab3147ae7fb5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583466395 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .rom_e2e_asm_init_rma.583466395 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3451257898 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 10693144152 ps |
| CPU time | 3335.78 seconds |
| Started | Aug 06 08:28:10 PM PDT 24 |
| Finished | Aug 06 09:23:47 PM PDT 24 |
| Peak memory | 610548 kb |
| Host | smart-2d93a4bc-79c4-4f21-a337-812578a9b785 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451257898 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.rom_e2e_asm_init_test_unlocked0.3451257898 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4056928394 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 24484244072 ps |
| CPU time | 6372.46 seconds |
| Started | Aug 06 08:33:26 PM PDT 24 |
| Finished | Aug 06 10:19:40 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-bccad3f5-6698-4c2c-9adb-d9409dca32f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4056928394 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4056928394 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1548176664 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 24560839704 ps |
| CPU time | 7099.88 seconds |
| Started | Aug 06 08:33:06 PM PDT 24 |
| Finished | Aug 06 10:31:27 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-f52eb313-f3e8-4d32-aaf9-143ba0488e15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1548176664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.1548176664 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1572857627 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 22911036020 ps |
| CPU time | 6575.68 seconds |
| Started | Aug 06 08:35:58 PM PDT 24 |
| Finished | Aug 06 10:25:35 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-567f3fab-219d-4488-b501-cbfaaeaa5b6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1572857627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.1572857627 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1762418439 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 18408272392 ps |
| CPU time | 4758.85 seconds |
| Started | Aug 06 08:35:30 PM PDT 24 |
| Finished | Aug 06 09:54:50 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-e1b3b902-85ad-45ae-a0bb-b3b4b5839ca6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762418439 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1762418439 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3406844342 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 15210583840 ps |
| CPU time | 3877.47 seconds |
| Started | Aug 06 08:35:09 PM PDT 24 |
| Finished | Aug 06 09:39:47 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-8add640c-cebf-424c-859e-8b99271d9450 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3406844342 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3406844342 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3863060368 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 15065340574 ps |
| CPU time | 3909 seconds |
| Started | Aug 06 08:32:53 PM PDT 24 |
| Finished | Aug 06 09:38:02 PM PDT 24 |
| Peak memory | 609124 kb |
| Host | smart-08c23d02-5b93-4351-8ba1-18cfa21db070 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3863060368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3863060368 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1922510437 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 14782571544 ps |
| CPU time | 4883.77 seconds |
| Started | Aug 06 08:35:09 PM PDT 24 |
| Finished | Aug 06 09:56:34 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-aff63e56-04b3-46b4-a59f-7be69a10a8a2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1922510437 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1922510437 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1431080186 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 15096036622 ps |
| CPU time | 4163.18 seconds |
| Started | Aug 06 08:32:11 PM PDT 24 |
| Finished | Aug 06 09:41:34 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-1b20f612-47c5-4184-a2e7-735da85ddad4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1431080186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1431080186 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.270465390 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 12016977200 ps |
| CPU time | 3112.85 seconds |
| Started | Aug 06 08:26:52 PM PDT 24 |
| Finished | Aug 06 09:18:45 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-523a4430-625e-4451-8b2a-db5f751d4775 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270465390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.270465390 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2685128735 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 15327559410 ps |
| CPU time | 3720.57 seconds |
| Started | Aug 06 08:30:11 PM PDT 24 |
| Finished | Aug 06 09:32:12 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-0a23716f-310a-4d96-8ed9-1560a5fc6f3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685128735 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2685128735 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1865142969 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 15604336808 ps |
| CPU time | 4120 seconds |
| Started | Aug 06 08:33:57 PM PDT 24 |
| Finished | Aug 06 09:42:37 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-47af42a7-3135-4e66-b693-5bcbeb416d16 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865142969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1865142969 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3692835690 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 14817217320 ps |
| CPU time | 4142.38 seconds |
| Started | Aug 06 08:25:41 PM PDT 24 |
| Finished | Aug 06 09:34:43 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-eb121fcd-1019-4531-8337-46f93051d0df |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369283 5690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.3692835690 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2350391045 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 14724663982 ps |
| CPU time | 5051.05 seconds |
| Started | Aug 06 08:35:53 PM PDT 24 |
| Finished | Aug 06 10:00:04 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-cc61432b-7e47-4592-9fc7-b1ef3e0df291 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350391045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2350391045 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3666619136 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 11337972238 ps |
| CPU time | 2842.18 seconds |
| Started | Aug 06 08:27:56 PM PDT 24 |
| Finished | Aug 06 09:15:18 PM PDT 24 |
| Peak memory | 610216 kb |
| Host | smart-03b5ff31-44b9-4b1d-a422-97972e5c13dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3666619136 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3666619136 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.367073059 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 11143616620 ps |
| CPU time | 2024.69 seconds |
| Started | Aug 06 08:24:07 PM PDT 24 |
| Finished | Aug 06 08:57:52 PM PDT 24 |
| Peak memory | 624388 kb |
| Host | smart-293267b4-53c6-41a8-9036-e335823496cb |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36707 3059 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.367073059 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.874111874 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 11002265047 ps |
| CPU time | 2016.76 seconds |
| Started | Aug 06 08:23:22 PM PDT 24 |
| Finished | Aug 06 08:57:01 PM PDT 24 |
| Peak memory | 624428 kb |
| Host | smart-8b245bb8-91b9-4009-b316-3fce29fbfa10 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87411 1874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.874111874 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1381967447 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 11495159951 ps |
| CPU time | 2165.31 seconds |
| Started | Aug 06 08:23:11 PM PDT 24 |
| Finished | Aug 06 08:59:19 PM PDT 24 |
| Peak memory | 624432 kb |
| Host | smart-21ae1cf3-4f33-43e3-95d1-b9ab15876553 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1381967447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.1381967447 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4269959473 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 25868861092 ps |
| CPU time | 1770.47 seconds |
| Started | Aug 06 08:22:14 PM PDT 24 |
| Finished | Aug 06 08:51:45 PM PDT 24 |
| Peak memory | 623720 kb |
| Host | smart-61bc6795-cb64-4724-a47d-9fc740b26dae |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=4269959473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.4269959473 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.663487828 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 29858212003 ps |
| CPU time | 3298.74 seconds |
| Started | Aug 06 08:21:13 PM PDT 24 |
| Finished | Aug 06 09:16:13 PM PDT 24 |
| Peak memory | 623708 kb |
| Host | smart-a9a3c838-23ec-4150-b11d-a637819a84d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=663487828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.663487828 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.139270652 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 31970370255 ps |
| CPU time | 2860.8 seconds |
| Started | Aug 06 08:25:42 PM PDT 24 |
| Finished | Aug 06 09:13:24 PM PDT 24 |
| Peak memory | 621020 kb |
| Host | smart-a3003305-9ebc-4017-aba2-52c89db4fc75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139270652 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_i nject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_ test_unlocked0.139270652 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2020630982 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15054195858 ps |
| CPU time | 3756.77 seconds |
| Started | Aug 06 08:26:27 PM PDT 24 |
| Finished | Aug 06 09:29:04 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-f55463fe-44d8-478c-b13b-8cfc5073181e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020630982 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2020630982 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.4261996107 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 14824797208 ps |
| CPU time | 4241.84 seconds |
| Started | Aug 06 08:27:08 PM PDT 24 |
| Finished | Aug 06 09:37:50 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-0ae5bf05-2f4a-4a0a-b5c7-7d56e0142296 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261996107 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.4261996107 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3366664842 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 15525469456 ps |
| CPU time | 4099.1 seconds |
| Started | Aug 06 08:29:48 PM PDT 24 |
| Finished | Aug 06 09:38:07 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-e63ee8e0-0047-471c-8f06-23e1e1f917f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366664842 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.3366664842 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.2751530542 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 26593213276 ps |
| CPU time | 6113.42 seconds |
| Started | Aug 06 08:31:43 PM PDT 24 |
| Finished | Aug 06 10:13:37 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-432ccb6c-2770-46f5-bb3d-821066cc9748 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751530542 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.2751530542 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1869862670 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 15008586077 ps |
| CPU time | 3790.2 seconds |
| Started | Aug 06 08:29:36 PM PDT 24 |
| Finished | Aug 06 09:32:47 PM PDT 24 |
| Peak memory | 611396 kb |
| Host | smart-7eab90f0-1678-4ca0-95ff-9b52cc078659 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869862670 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.1869862670 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.1208048618 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 25585794092 ps |
| CPU time | 3966.31 seconds |
| Started | Aug 06 08:31:18 PM PDT 24 |
| Finished | Aug 06 09:37:25 PM PDT 24 |
| Peak memory | 611752 kb |
| Host | smart-bd3528d2-a1f8-4dd3-ab1b-e623a417bedd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208048618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.1208048618 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3721938234 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 23047411937 ps |
| CPU time | 7098.09 seconds |
| Started | Aug 06 08:30:02 PM PDT 24 |
| Finished | Aug 06 10:28:21 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-65bb085b-61b3-414f-8a26-2bdcfaf5facb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3721938234 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_b ad_dev.3721938234 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.970922359 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 23916351736 ps |
| CPU time | 6797.41 seconds |
| Started | Aug 06 08:27:34 PM PDT 24 |
| Finished | Aug 06 10:20:53 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-0ccd023b-1abf-4031-a3f1-aed027838800 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=970922359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_b ad_b_bad_prod_end.970922359 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.484982288 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 21971882210 ps |
| CPU time | 7327.42 seconds |
| Started | Aug 06 08:34:58 PM PDT 24 |
| Finished | Aug 06 10:37:07 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-ffabdcbe-250d-428e-8a3c-487ae0f0bd44 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=484982288 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_ bad_rma.484982288 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2490667686 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 17954339592 ps |
| CPU time | 4496.28 seconds |
| Started | Aug 06 08:31:45 PM PDT 24 |
| Finished | Aug 06 09:46:42 PM PDT 24 |
| Peak memory | 610324 kb |
| Host | smart-b2951a05-46fb-4d23-a610-03a07676a87f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2490667686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.2490667686 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.708421464 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 14849806750 ps |
| CPU time | 3457.05 seconds |
| Started | Aug 06 08:27:54 PM PDT 24 |
| Finished | Aug 06 09:25:31 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-0e7c0ace-6f96-4dd2-a7b6-b7252df2917d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708421464 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.708421464 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1553528824 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 14891202620 ps |
| CPU time | 3508.6 seconds |
| Started | Aug 06 08:30:07 PM PDT 24 |
| Finished | Aug 06 09:28:36 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-b78596b7-017e-40c5-bd04-8f27bf267385 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553528824 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1553528824 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.743032643 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 14270437784 ps |
| CPU time | 3156.9 seconds |
| Started | Aug 06 08:26:53 PM PDT 24 |
| Finished | Aug 06 09:19:31 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-1ae7bb08-e60d-4fd4-a711-71495b64b416 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743032643 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.743032643 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4016552241 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 14188946375 ps |
| CPU time | 3618.58 seconds |
| Started | Aug 06 08:30:44 PM PDT 24 |
| Finished | Aug 06 09:31:03 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-dd7381ef-d018-46b9-b07f-f17abfa1edb9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016552241 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4016552241 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2461850853 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 11273135240 ps |
| CPU time | 2903.71 seconds |
| Started | Aug 06 08:25:37 PM PDT 24 |
| Finished | Aug 06 09:14:02 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-68dd32c8-3b6f-495b-85e6-5edc6480c7e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461850853 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2461850853 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4008002514 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 14104478860 ps |
| CPU time | 3873.2 seconds |
| Started | Aug 06 08:28:37 PM PDT 24 |
| Finished | Aug 06 09:33:11 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-76b0f522-ba0b-483c-a800-77654f8d1c05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008002514 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.4008002514 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1814491430 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 14855750950 ps |
| CPU time | 4109.02 seconds |
| Started | Aug 06 08:27:43 PM PDT 24 |
| Finished | Aug 06 09:36:13 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-99a1294c-3c10-4e6e-8c0f-f3669e2f263e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814491430 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1814491430 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.606294261 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 14317654003 ps |
| CPU time | 3572.57 seconds |
| Started | Aug 06 08:28:35 PM PDT 24 |
| Finished | Aug 06 09:28:08 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-983722f0-7d31-4aec-829e-510e2b7229a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606294261 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.606294261 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.847283575 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 14067543698 ps |
| CPU time | 3593.1 seconds |
| Started | Aug 06 08:26:37 PM PDT 24 |
| Finished | Aug 06 09:26:30 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-654e9a8f-d883-4805-a17e-dc796ad761a9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847283575 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.847283575 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3005037923 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 11523033756 ps |
| CPU time | 2983.14 seconds |
| Started | Aug 06 08:29:16 PM PDT 24 |
| Finished | Aug 06 09:19:00 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-5e2b079a-6cfb-4fa1-bb77-83f6c9ffd5a5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005037923 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3005037923 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.2556241995 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 15547870600 ps |
| CPU time | 3689.74 seconds |
| Started | Aug 06 08:28:19 PM PDT 24 |
| Finished | Aug 06 09:29:49 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-a82f99f9-112f-43e2-af4a-24e95aa11180 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2556241995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2556241995 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.3696992605 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 17057703804 ps |
| CPU time | 4342.88 seconds |
| Started | Aug 06 08:31:41 PM PDT 24 |
| Finished | Aug 06 09:44:04 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-914619a1-df90-40d1-be66-fb6eca17242b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696992605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.3696992605 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.1656454323 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 4475459990 ps |
| CPU time | 579.21 seconds |
| Started | Aug 06 08:23:46 PM PDT 24 |
| Finished | Aug 06 08:33:26 PM PDT 24 |
| Peak memory | 610552 kb |
| Host | smart-ffd47c3f-1194-46c6-aaf1-714aa4775c5c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656454323 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.1656454323 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.3745846969 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 5716309926 ps |
| CPU time | 293.83 seconds |
| Started | Aug 06 08:22:22 PM PDT 24 |
| Finished | Aug 06 08:27:16 PM PDT 24 |
| Peak memory | 619832 kb |
| Host | smart-fe265853-603f-4dca-99c9-71714f4ba847 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3745846969 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.3745846969 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.3639024571 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 2739827076 ps |
| CPU time | 115.94 seconds |
| Started | Aug 06 08:27:01 PM PDT 24 |
| Finished | Aug 06 08:28:57 PM PDT 24 |
| Peak memory | 617680 kb |
| Host | smart-47895186-a6cf-46f5-b327-de184bb92d98 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639024571 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.3639024571 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.2461295649 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 13768783253 ps |
| CPU time | 1611.88 seconds |
| Started | Aug 06 08:10:39 PM PDT 24 |
| Finished | Aug 06 08:37:31 PM PDT 24 |
| Peak memory | 603836 kb |
| Host | smart-6f2a6714-c925-4fc0-9e09-a954247ef3a5 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461295649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.2 461295649 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2395170943 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 3908965432 ps |
| CPU time | 507.43 seconds |
| Started | Aug 06 08:25:41 PM PDT 24 |
| Finished | Aug 06 08:34:09 PM PDT 24 |
| Peak memory | 621000 kb |
| Host | smart-b92f52ea-5eba-408d-bd53-5e62501f40ff |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 395170943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2395170943 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.1431277278 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3636065342 ps |
| CPU time | 351.17 seconds |
| Started | Aug 06 08:22:49 PM PDT 24 |
| Finished | Aug 06 08:28:40 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-f4ba4c6b-5b53-408b-9ae3-2fb74033a389 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1431277278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.1431277278 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2663206732 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 17803938600 ps |
| CPU time | 693.73 seconds |
| Started | Aug 06 08:27:23 PM PDT 24 |
| Finished | Aug 06 08:38:57 PM PDT 24 |
| Peak memory | 619484 kb |
| Host | smart-685f22d5-14ec-4f44-832b-86e848229fbc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2663206732 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2663206732 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.345854451 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3164597232 ps |
| CPU time | 338.74 seconds |
| Started | Aug 06 08:25:39 PM PDT 24 |
| Finished | Aug 06 08:31:17 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-c23a551b-3cbb-430d-8807-658b29895fa1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345854451 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.345854451 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1233874303 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 3390335384 ps |
| CPU time | 258.41 seconds |
| Started | Aug 06 08:23:32 PM PDT 24 |
| Finished | Aug 06 08:27:51 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-2c66a55e-30c5-4e1e-a24b-337a69b639ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233 874303 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1233874303 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2621755100 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 2988457008 ps |
| CPU time | 222.54 seconds |
| Started | Aug 06 08:24:38 PM PDT 24 |
| Finished | Aug 06 08:28:20 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-d371243f-6600-4a04-b398-720037b559e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2621755100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.2621755100 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.2959550291 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 3230225030 ps |
| CPU time | 249.31 seconds |
| Started | Aug 06 08:23:30 PM PDT 24 |
| Finished | Aug 06 08:27:40 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-e093b051-3640-4a64-83ad-7815f957264b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959550291 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.2959550291 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.1155758124 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 2798908340 ps |
| CPU time | 205.22 seconds |
| Started | Aug 06 08:19:42 PM PDT 24 |
| Finished | Aug 06 08:23:08 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-509291af-17ec-4a56-996c-6216275746b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155758124 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1155758124 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.459644510 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 3403126246 ps |
| CPU time | 392.23 seconds |
| Started | Aug 06 08:24:47 PM PDT 24 |
| Finished | Aug 06 08:31:20 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-5308238e-6015-461f-96c5-9520937463fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459644510 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.459644510 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.568103243 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 2936494040 ps |
| CPU time | 231.97 seconds |
| Started | Aug 06 08:25:22 PM PDT 24 |
| Finished | Aug 06 08:29:15 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-81f431a2-7ff8-4248-8ef8-5b1034e408a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568103243 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.568103243 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3699063096 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2584511540 ps |
| CPU time | 372.9 seconds |
| Started | Aug 06 08:30:24 PM PDT 24 |
| Finished | Aug 06 08:36:39 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-7a15bfcc-5d59-46ae-8973-54497acef2ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3699063096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.3699063096 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.380100646 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4866194130 ps |
| CPU time | 485.38 seconds |
| Started | Aug 06 08:27:06 PM PDT 24 |
| Finished | Aug 06 08:35:12 PM PDT 24 |
| Peak memory | 619452 kb |
| Host | smart-b9fe6c71-0768-4499-83ea-be342d039a43 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=380100646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+cond +fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.380100646 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3680239396 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 8053601168 ps |
| CPU time | 1710 seconds |
| Started | Aug 06 08:23:43 PM PDT 24 |
| Finished | Aug 06 08:52:13 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-7dca482a-266f-4929-ae57-1bd7b7febcc2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3680239396 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3680239396 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.4130472292 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 6045304246 ps |
| CPU time | 1234.59 seconds |
| Started | Aug 06 08:28:04 PM PDT 24 |
| Finished | Aug 06 08:48:38 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-5d0b533b-3662-41fb-a0cc-04d862f83fb3 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130472292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_togg le.4130472292 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.79128939 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 11477564184 ps |
| CPU time | 1375.31 seconds |
| Started | Aug 06 08:24:08 PM PDT 24 |
| Finished | Aug 06 08:47:04 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-529cc801-be33-4c48-b5d7-ac20e050c737 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79128939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handl er_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_alert_handler_lpg_sleep_mode_pings.79128939 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.504355369 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 8221887998 ps |
| CPU time | 1456.34 seconds |
| Started | Aug 06 08:24:04 PM PDT 24 |
| Finished | Aug 06 08:48:20 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-8d568a8a-bcc4-473d-bf05-36ecbc178a68 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=504355369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.504355369 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4280527675 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3490789440 ps |
| CPU time | 274.31 seconds |
| Started | Aug 06 08:21:20 PM PDT 24 |
| Finished | Aug 06 08:25:55 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-12acc067-b198-4d8c-8bf3-1defee30f4dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4280527675 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.4280527675 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2047958516 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 255175618616 ps |
| CPU time | 13181 seconds |
| Started | Aug 06 08:28:05 PM PDT 24 |
| Finished | Aug 07 12:07:48 AM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-d7cef406-558b-46c7-9f98-d7d19b1cee42 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2047958516 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2047958516 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.1504347549 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 3448054648 ps |
| CPU time | 365.7 seconds |
| Started | Aug 06 08:28:07 PM PDT 24 |
| Finished | Aug 06 08:34:13 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-544aeb1a-e033-4e60-9bbb-be81ae53fbba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504347549 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 1.chip_sw_alert_test.1504347549 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.1083504231 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3760363580 ps |
| CPU time | 466.61 seconds |
| Started | Aug 06 08:24:47 PM PDT 24 |
| Finished | Aug 06 08:32:34 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-9e553a48-8ac8-4a0c-a186-484175caded8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083504231 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.1083504231 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.287733577 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 7907310672 ps |
| CPU time | 415.23 seconds |
| Started | Aug 06 08:26:40 PM PDT 24 |
| Finished | Aug 06 08:33:36 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-e5c5648c-611c-4321-a2d3-9382c672c756 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=287733577 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.287733577 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.4233832817 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 3030034008 ps |
| CPU time | 249.46 seconds |
| Started | Aug 06 08:29:36 PM PDT 24 |
| Finished | Aug 06 08:33:46 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-f4170de9-c091-425a-b3f5-89ec42c3e34b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233832817 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.4233832817 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2314087998 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 9777525560 ps |
| CPU time | 966.31 seconds |
| Started | Aug 06 08:26:27 PM PDT 24 |
| Finished | Aug 06 08:42:34 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-669b0821-6417-406b-8c07-67fa3deebf58 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2314087998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.2314087998 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3253419450 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 5204525598 ps |
| CPU time | 593.35 seconds |
| Started | Aug 06 08:22:52 PM PDT 24 |
| Finished | Aug 06 08:32:45 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-76b50cac-1f9f-46b7-abe9-298cd34ad492 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =3253419450 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.3253419450 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.792284439 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 7246213160 ps |
| CPU time | 1118 seconds |
| Started | Aug 06 08:27:32 PM PDT 24 |
| Finished | Aug 06 08:46:10 PM PDT 24 |
| Peak memory | 617032 kb |
| Host | smart-9fa15fa8-2e48-4c38-a914-082c79fbaa45 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792284439 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.792284439 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.1273847338 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 18624039991 ps |
| CPU time | 3149.61 seconds |
| Started | Aug 06 08:31:20 PM PDT 24 |
| Finished | Aug 06 09:23:54 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-41fe62c4-b6ff-4cbf-affb-4d2ee40bd566 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273847338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.1273847338 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1710264314 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 6178511049 ps |
| CPU time | 420.3 seconds |
| Started | Aug 06 08:26:09 PM PDT 24 |
| Finished | Aug 06 08:33:10 PM PDT 24 |
| Peak memory | 620528 kb |
| Host | smart-8d1d9eb5-a659-4d82-b0c8-19ca9a9d56c9 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1710264314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.1710264314 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.4164563841 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 4022184694 ps |
| CPU time | 723.34 seconds |
| Started | Aug 06 08:22:16 PM PDT 24 |
| Finished | Aug 06 08:34:20 PM PDT 24 |
| Peak memory | 612916 kb |
| Host | smart-b4ea3e49-0f29-425f-9ac5-52b86ec6df8a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164563841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.4164563841 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.790415201 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 4166138108 ps |
| CPU time | 581.74 seconds |
| Started | Aug 06 08:24:07 PM PDT 24 |
| Finished | Aug 06 08:33:49 PM PDT 24 |
| Peak memory | 612176 kb |
| Host | smart-4724103f-852b-4d70-8c64-f3aeccc2e077 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790415201 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_cl kmgr_external_clk_src_for_sw_fast_rma.790415201 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492834055 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 4471907320 ps |
| CPU time | 707.01 seconds |
| Started | Aug 06 08:24:31 PM PDT 24 |
| Finished | Aug 06 08:36:18 PM PDT 24 |
| Peak memory | 612236 kb |
| Host | smart-ef715b5c-8a70-41aa-9fd3-e7c8c72bd549 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492834055 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492834055 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.41133650 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 4778991058 ps |
| CPU time | 472.81 seconds |
| Started | Aug 06 08:23:17 PM PDT 24 |
| Finished | Aug 06 08:31:10 PM PDT 24 |
| Peak memory | 612164 kb |
| Host | smart-7956e096-f9ee-47e9-aefe-53fe2e86b0cb |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41133650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clk mgr_external_clk_src_for_sw_slow_dev.41133650 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3933207364 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 4409813066 ps |
| CPU time | 784.3 seconds |
| Started | Aug 06 08:25:42 PM PDT 24 |
| Finished | Aug 06 08:38:46 PM PDT 24 |
| Peak memory | 612176 kb |
| Host | smart-c7bf72d0-9ab6-473e-94b9-4aceb9e35b3a |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933207364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.3933207364 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.789853697 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 4536380470 ps |
| CPU time | 597.75 seconds |
| Started | Aug 06 08:25:31 PM PDT 24 |
| Finished | Aug 06 08:35:28 PM PDT 24 |
| Peak memory | 612268 kb |
| Host | smart-a42bf4d1-6e3b-4364-8c7b-db7cfa37d171 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789853697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.789853697 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.650063468 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2630394724 ps |
| CPU time | 231.5 seconds |
| Started | Aug 06 08:28:26 PM PDT 24 |
| Finished | Aug 06 08:32:17 PM PDT 24 |
| Peak memory | 609284 kb |
| Host | smart-91342c79-9370-4e47-8e23-d7624d24d639 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650063468 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_clkmgr_jitter.650063468 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.1398478488 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 2567529454 ps |
| CPU time | 388.45 seconds |
| Started | Aug 06 08:23:19 PM PDT 24 |
| Finished | Aug 06 08:29:48 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-a2100597-71c1-4fff-8c52-ca943439fada |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398478488 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.1398478488 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2222951458 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 2338799141 ps |
| CPU time | 220.62 seconds |
| Started | Aug 06 08:25:11 PM PDT 24 |
| Finished | Aug 06 08:28:52 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-2066db29-038b-451f-bb03-e82cfb98bdba |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222951458 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2222951458 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3293898717 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 5683485416 ps |
| CPU time | 676.28 seconds |
| Started | Aug 06 08:23:24 PM PDT 24 |
| Finished | Aug 06 08:34:41 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-f244bbca-07a6-4ecf-914d-94c85d06ddf8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293898717 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.3293898717 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.3525281537 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 4875261560 ps |
| CPU time | 457.48 seconds |
| Started | Aug 06 08:23:52 PM PDT 24 |
| Finished | Aug 06 08:31:30 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-2e931a39-4a1a-4120-82a5-18f1c4e841e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525281537 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.3525281537 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2781707624 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 5821063744 ps |
| CPU time | 533.99 seconds |
| Started | Aug 06 08:23:29 PM PDT 24 |
| Finished | Aug 06 08:32:24 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-ea5ae339-b918-47b4-a928-233cc379f61b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781707624 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.2781707624 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3714991840 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 4296877000 ps |
| CPU time | 495.78 seconds |
| Started | Aug 06 08:27:22 PM PDT 24 |
| Finished | Aug 06 08:35:40 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-c6491cd4-df34-4059-84fb-f83edb804899 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714991840 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.3714991840 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2373725765 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 12312961912 ps |
| CPU time | 1601.06 seconds |
| Started | Aug 06 08:23:24 PM PDT 24 |
| Finished | Aug 06 08:50:06 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-22b7c744-e475-49cd-bda2-cda76d0d95d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373725765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.2373725765 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2947526880 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 3587369256 ps |
| CPU time | 356.79 seconds |
| Started | Aug 06 08:22:57 PM PDT 24 |
| Finished | Aug 06 08:28:53 PM PDT 24 |
| Peak memory | 608636 kb |
| Host | smart-4167c3bd-2b0b-4c90-9eea-0aa112de83f3 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947526880 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.2947526880 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2677202043 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 4375027368 ps |
| CPU time | 715.13 seconds |
| Started | Aug 06 08:28:29 PM PDT 24 |
| Finished | Aug 06 08:40:24 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-3609325a-7b86-45aa-b9b9-a63650339c8a |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677202043 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.2677202043 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1889223318 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 3119760042 ps |
| CPU time | 286.78 seconds |
| Started | Aug 06 08:24:46 PM PDT 24 |
| Finished | Aug 06 08:29:32 PM PDT 24 |
| Peak memory | 609644 kb |
| Host | smart-fecf93f4-4d94-46a6-acf1-ad3c53796981 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889223318 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1889223318 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2942785353 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 15560661188 ps |
| CPU time | 3605.02 seconds |
| Started | Aug 06 08:29:06 PM PDT 24 |
| Finished | Aug 06 09:29:11 PM PDT 24 |
| Peak memory | 610420 kb |
| Host | smart-04300743-0fe4-4b02-a532-88d7ae823f71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942785353 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.2942785353 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1439597087 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 89967814749 ps |
| CPU time | 12936.2 seconds |
| Started | Aug 06 08:28:41 PM PDT 24 |
| Finished | Aug 07 12:04:18 AM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-b9b7eb66-8439-464e-a973-72e132faafa9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1439597087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.1439597087 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1225722118 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 5530425160 ps |
| CPU time | 612.96 seconds |
| Started | Aug 06 08:26:56 PM PDT 24 |
| Finished | Aug 06 08:37:09 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-09001acf-2904-44f2-a1a5-e534c71306b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12257 22118 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1225722118 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.4283071958 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 3147515100 ps |
| CPU time | 314.23 seconds |
| Started | Aug 06 08:24:45 PM PDT 24 |
| Finished | Aug 06 08:30:00 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-16905e24-b264-4d89-ad44-26925ded16f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283071958 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.4283071958 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.1612646051 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 6864477376 ps |
| CPU time | 534.47 seconds |
| Started | Aug 06 08:26:04 PM PDT 24 |
| Finished | Aug 06 08:34:59 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-dea75127-5fa3-4fff-9050-65c29aac0e32 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612646051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.1612646051 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2592399970 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 2291579272 ps |
| CPU time | 218.09 seconds |
| Started | Aug 06 08:28:01 PM PDT 24 |
| Finished | Aug 06 08:31:39 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-bd1202de-0866-4fdf-a5e5-9a6d465136f0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592399970 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2592399970 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.3206451745 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6460582424 ps |
| CPU time | 691.85 seconds |
| Started | Aug 06 08:27:09 PM PDT 24 |
| Finished | Aug 06 08:38:41 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-f65d9bec-cc45-4b03-87e4-1bbdcdfe61e1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3206451745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.3206451745 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.1388490831 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 5135445060 ps |
| CPU time | 1259.91 seconds |
| Started | Aug 06 08:23:10 PM PDT 24 |
| Finished | Aug 06 08:44:10 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-f332745d-174a-4e0d-8dbc-37c8b8140516 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388490831 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.1388490831 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.2197208913 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 3155065444 ps |
| CPU time | 595.8 seconds |
| Started | Aug 06 08:27:17 PM PDT 24 |
| Finished | Aug 06 08:37:14 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-baee97e8-3bce-42b4-aeed-303e872e2d96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197208913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.2197208913 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1179495053 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 7496074440 ps |
| CPU time | 1336.71 seconds |
| Started | Aug 06 08:27:47 PM PDT 24 |
| Finished | Aug 06 08:50:04 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-df0177f7-d5e6-4d9b-af45-dfcb87147183 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1179495053 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.1179495053 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.11306690 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 7555415769 ps |
| CPU time | 1462.89 seconds |
| Started | Aug 06 08:24:29 PM PDT 24 |
| Finished | Aug 06 08:48:52 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-b131b109-2f46-4dd3-a636-086010ff1126 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11306690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.11306690 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.297222710 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3045480860 ps |
| CPU time | 755.74 seconds |
| Started | Aug 06 08:27:51 PM PDT 24 |
| Finished | Aug 06 08:40:27 PM PDT 24 |
| Peak memory | 616612 kb |
| Host | smart-4ce75360-9e89-4b45-8d4e-09091d45268c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=297222710 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_edn_kat.297222710 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.2489807156 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 8305608692 ps |
| CPU time | 1991.44 seconds |
| Started | Aug 06 08:24:14 PM PDT 24 |
| Finished | Aug 06 08:57:27 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-6d623a5b-8797-41a2-846d-d7c87b310c80 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489807156 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.2489807156 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3247211089 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 3053903780 ps |
| CPU time | 195.79 seconds |
| Started | Aug 06 08:25:29 PM PDT 24 |
| Finished | Aug 06 08:28:45 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-08eb98d9-32ed-4a34-9cd9-991750b5e78c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32 47211089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.3247211089 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.3871411591 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 6739972000 ps |
| CPU time | 1779.66 seconds |
| Started | Aug 06 08:28:20 PM PDT 24 |
| Finished | Aug 06 08:58:01 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-2147a95a-4594-400f-b4b6-88fb04442dad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=3871411591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.3871411591 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2296129112 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 2734877320 ps |
| CPU time | 207.96 seconds |
| Started | Aug 06 08:22:48 PM PDT 24 |
| Finished | Aug 06 08:26:16 PM PDT 24 |
| Peak memory | 608524 kb |
| Host | smart-a9ff817f-7ce8-4621-b5f0-f20cacdd961a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296129112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.2296129112 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2087058628 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 3886573336 ps |
| CPU time | 565.58 seconds |
| Started | Aug 06 08:25:54 PM PDT 24 |
| Finished | Aug 06 08:35:20 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-7056c43e-6dd5-43a0-8222-72a4247e12e6 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2087058628 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.2087058628 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.76820688 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 2822048164 ps |
| CPU time | 201.04 seconds |
| Started | Aug 06 08:29:03 PM PDT 24 |
| Finished | Aug 06 08:32:25 PM PDT 24 |
| Peak memory | 609660 kb |
| Host | smart-9eb609ab-fa4e-41de-852e-f522166b9781 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76820688 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_concurrency.76820688 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.3386520035 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 3132749560 ps |
| CPU time | 259.36 seconds |
| Started | Aug 06 08:26:53 PM PDT 24 |
| Finished | Aug 06 08:31:13 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-fd1c7a11-5a18-48ad-b28d-52a514182ddf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386520035 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3386520035 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.2554457788 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 3171944280 ps |
| CPU time | 181.38 seconds |
| Started | Aug 06 08:27:11 PM PDT 24 |
| Finished | Aug 06 08:30:13 PM PDT 24 |
| Peak memory | 609708 kb |
| Host | smart-ec88cbb4-a825-4936-86f8-b5c6591f674e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554457788 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.2554457788 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.4227894235 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 2365592512 ps |
| CPU time | 122.42 seconds |
| Started | Aug 06 08:25:18 PM PDT 24 |
| Finished | Aug 06 08:27:22 PM PDT 24 |
| Peak memory | 608916 kb |
| Host | smart-9aa60e2a-2403-4d27-a9bb-34f84f1ba84e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227894235 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.4227894235 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.2159200328 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 4254338008 ps |
| CPU time | 661.89 seconds |
| Started | Aug 06 08:25:18 PM PDT 24 |
| Finished | Aug 06 08:36:21 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-1bbd4f5a-e3af-4771-9270-402da8677768 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2159200328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.2159200328 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2616366146 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 6150487812 ps |
| CPU time | 845.11 seconds |
| Started | Aug 06 08:19:55 PM PDT 24 |
| Finished | Aug 06 08:34:01 PM PDT 24 |
| Peak memory | 607276 kb |
| Host | smart-fa1e04bb-c681-4c5d-90c2-3774696ab978 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616366146 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.2616366146 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.930255530 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 6362067104 ps |
| CPU time | 1135.07 seconds |
| Started | Aug 06 08:25:42 PM PDT 24 |
| Finished | Aug 06 08:44:39 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-21c2c906-66f8-45fd-a3df-f9337f52f10e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930255530 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.930255530 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3816881948 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 7650095724 ps |
| CPU time | 1324 seconds |
| Started | Aug 06 08:31:10 PM PDT 24 |
| Finished | Aug 06 08:53:14 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-ffded92f-4745-434d-aa05-6e0e0560a63d |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816881948 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3816881948 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3817897422 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 5766086690 ps |
| CPU time | 1324.71 seconds |
| Started | Aug 06 08:25:48 PM PDT 24 |
| Finished | Aug 06 08:47:54 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-74951fa3-e696-4518-9055-698759a19de1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817897422 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.3817897422 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2826566630 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 3318667056 ps |
| CPU time | 350.8 seconds |
| Started | Aug 06 08:26:42 PM PDT 24 |
| Finished | Aug 06 08:32:34 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-934dd14c-2fcb-4154-a8d6-0d119527e2d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826566630 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.2826566630 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.998155161 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4376944530 ps |
| CPU time | 348 seconds |
| Started | Aug 06 08:23:28 PM PDT 24 |
| Finished | Aug 06 08:29:16 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-441d37dd-fe19-4b93-9f9c-282995bc1b0a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99 8155161 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.998155161 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.904143306 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 5510807160 ps |
| CPU time | 1081.04 seconds |
| Started | Aug 06 08:25:56 PM PDT 24 |
| Finished | Aug 06 08:43:57 PM PDT 24 |
| Peak memory | 609484 kb |
| Host | smart-d1807fdb-dbe5-4168-9ab2-e5f4edbcad2e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904143306 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.904143306 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1861567344 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4719147988 ps |
| CPU time | 585.5 seconds |
| Started | Aug 06 08:27:09 PM PDT 24 |
| Finished | Aug 06 08:36:55 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-bf539172-a015-4f2a-83eb-8d3561caa6cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861567344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.1861567344 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3476054966 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 4143811954 ps |
| CPU time | 714.17 seconds |
| Started | Aug 06 08:26:44 PM PDT 24 |
| Finished | Aug 06 08:38:38 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-38ba7dc9-5bfc-4e52-8a6d-e11394cad0be |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=3476054966 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.3476054966 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3321010375 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 4982089402 ps |
| CPU time | 744.07 seconds |
| Started | Aug 06 08:22:40 PM PDT 24 |
| Finished | Aug 06 08:35:05 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-1099d918-f2c2-4807-b4ce-04a67e5a4794 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=3321010375 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3321010375 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.2411034672 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 2854264664 ps |
| CPU time | 354.07 seconds |
| Started | Aug 06 08:26:36 PM PDT 24 |
| Finished | Aug 06 08:32:30 PM PDT 24 |
| Peak memory | 608612 kb |
| Host | smart-89ca4e72-9fa1-48b7-82f4-4b551b24af05 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411034 672 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.2411034672 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.2281905008 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 24263674325 ps |
| CPU time | 2124.53 seconds |
| Started | Aug 06 08:24:37 PM PDT 24 |
| Finished | Aug 06 09:00:03 PM PDT 24 |
| Peak memory | 612416 kb |
| Host | smart-44de0d1c-6782-4532-ac46-966cd6a94276 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281905008 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.2281905008 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.486625958 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 25528410371 ps |
| CPU time | 2024.65 seconds |
| Started | Aug 06 08:23:34 PM PDT 24 |
| Finished | Aug 06 08:57:19 PM PDT 24 |
| Peak memory | 614568 kb |
| Host | smart-21bda9fa-70c0-432c-9842-5e5ecca3227c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=486625958 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.486625958 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.242115456 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 2221153168 ps |
| CPU time | 225.29 seconds |
| Started | Aug 06 08:30:22 PM PDT 24 |
| Finished | Aug 06 08:34:08 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-2f6eb4d2-fa26-4d5c-8ee4-20d318a8e1fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=242115456 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.242115456 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.379472207 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 3161429194 ps |
| CPU time | 240.2 seconds |
| Started | Aug 06 08:26:41 PM PDT 24 |
| Finished | Aug 06 08:30:41 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-8af6984a-266f-4028-a9ac-c7f2b90eaab6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379472207 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_gpio_smoketest.379472207 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.3493862637 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3190891420 ps |
| CPU time | 338.85 seconds |
| Started | Aug 06 08:27:41 PM PDT 24 |
| Finished | Aug 06 08:33:20 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-f8597ff0-72bc-45f8-b455-a3a15ea512aa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493862637 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.3493862637 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3234567369 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 2587493480 ps |
| CPU time | 245.26 seconds |
| Started | Aug 06 08:22:16 PM PDT 24 |
| Finished | Aug 06 08:26:22 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-eae19c3e-9f43-41ae-86ec-e82bd77affa0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234567369 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.3234567369 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3594972084 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 2942947661 ps |
| CPU time | 316.79 seconds |
| Started | Aug 06 08:26:14 PM PDT 24 |
| Finished | Aug 06 08:31:33 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-e0364933-05cb-4006-bd78-18accb521a68 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594972084 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.3594972084 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2475065037 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3412434374 ps |
| CPU time | 274.78 seconds |
| Started | Aug 06 08:24:20 PM PDT 24 |
| Finished | Aug 06 08:28:55 PM PDT 24 |
| Peak memory | 608484 kb |
| Host | smart-69397582-d7d6-44fb-b00a-397d68f104bb |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475065037 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2475065037 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.1863751096 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 7950264858 ps |
| CPU time | 1898.7 seconds |
| Started | Aug 06 08:27:34 PM PDT 24 |
| Finished | Aug 06 08:59:14 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-527e5382-a56b-402d-b72c-ec98b95032d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863751096 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_multistream.1863751096 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.2877219491 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 3009513628 ps |
| CPU time | 375.38 seconds |
| Started | Aug 06 08:24:08 PM PDT 24 |
| Finished | Aug 06 08:30:24 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-b430bc9e-2117-4832-885a-bd1b584fbc3c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877219491 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.2877219491 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.1309624258 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 3160618300 ps |
| CPU time | 305.05 seconds |
| Started | Aug 06 08:27:42 PM PDT 24 |
| Finished | Aug 06 08:32:48 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-3ec3c7d2-d58f-4c8e-8779-14e073e33146 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309624258 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.1309624258 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1734280478 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 4299501230 ps |
| CPU time | 716.99 seconds |
| Started | Aug 06 08:31:08 PM PDT 24 |
| Finished | Aug 06 08:43:06 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-138fddcb-3bd9-47dd-93ca-e8807e4674b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734280478 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.1734280478 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1262025278 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 4938129704 ps |
| CPU time | 557.01 seconds |
| Started | Aug 06 08:20:04 PM PDT 24 |
| Finished | Aug 06 08:29:22 PM PDT 24 |
| Peak memory | 608424 kb |
| Host | smart-e08314d3-52cd-4d97-abd9-cf025ccae0e2 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262025278 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1262025278 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.4074973427 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 5003580088 ps |
| CPU time | 933.36 seconds |
| Started | Aug 06 08:27:12 PM PDT 24 |
| Finished | Aug 06 08:42:46 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-732f49ff-a043-4f14-ac80-a103996b52c9 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074973427 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.4074973427 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.865427196 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 5368038160 ps |
| CPU time | 931.34 seconds |
| Started | Aug 06 08:24:55 PM PDT 24 |
| Finished | Aug 06 08:40:26 PM PDT 24 |
| Peak memory | 610056 kb |
| Host | smart-e86604b6-7be2-4f04-a049-7c0f17ffb17d |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=865427196 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.865427196 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.4023906956 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 64083529187 ps |
| CPU time | 11908.2 seconds |
| Started | Aug 06 08:24:29 PM PDT 24 |
| Finished | Aug 06 11:42:58 PM PDT 24 |
| Peak memory | 624792 kb |
| Host | smart-d98f58f2-a90e-4740-9b46-82c42c3445d1 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4023906956 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.4023906956 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3661368915 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 7853076612 ps |
| CPU time | 1536.85 seconds |
| Started | Aug 06 08:26:26 PM PDT 24 |
| Finished | Aug 06 08:52:05 PM PDT 24 |
| Peak memory | 616844 kb |
| Host | smart-16aefafe-d7e9-4b63-ac7d-84f7c37a5606 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661 368915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.3661368915 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3595142534 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 11772326625 ps |
| CPU time | 2494.78 seconds |
| Started | Aug 06 08:27:21 PM PDT 24 |
| Finished | Aug 06 09:08:56 PM PDT 24 |
| Peak memory | 618252 kb |
| Host | smart-48bd35d2-0074-42c7-a70b-fa2208cfdbcc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3595142534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.3595142534 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.962485920 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 9983429920 ps |
| CPU time | 2108.86 seconds |
| Started | Aug 06 08:27:09 PM PDT 24 |
| Finished | Aug 06 09:02:19 PM PDT 24 |
| Peak memory | 616792 kb |
| Host | smart-d5f400c5-f822-4efd-9232-af4a764b77c2 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=962485920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.962485920 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2608721908 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 7652826398 ps |
| CPU time | 1594.98 seconds |
| Started | Aug 06 08:25:59 PM PDT 24 |
| Finished | Aug 06 08:52:34 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-e8b1dd51-b745-420d-a6b6-3697320e017b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260872 1908 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.2608721908 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.235116520 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 15674580488 ps |
| CPU time | 4608.22 seconds |
| Started | Aug 06 08:25:34 PM PDT 24 |
| Finished | Aug 06 09:42:23 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-44902f9e-2827-4e7a-b92f-d4160852103f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23511 6520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.235116520 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.2002794364 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 3393472882 ps |
| CPU time | 276.93 seconds |
| Started | Aug 06 08:26:28 PM PDT 24 |
| Finished | Aug 06 08:31:05 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-59eb873b-7eeb-40a2-955d-b6689ec4ee70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002794364 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.2002794364 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.1506740365 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 2628306968 ps |
| CPU time | 247.28 seconds |
| Started | Aug 06 08:22:51 PM PDT 24 |
| Finished | Aug 06 08:26:58 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-885ee880-5a3e-482b-9047-e4fcf8427628 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506740365 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.1506740365 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.3181601636 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 2802057816 ps |
| CPU time | 247.22 seconds |
| Started | Aug 06 08:25:22 PM PDT 24 |
| Finished | Aug 06 08:29:29 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-58c3110c-2323-4f6a-91e3-5eaf4597b29d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181601636 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.3181601636 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2153792280 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 3130204808 ps |
| CPU time | 212.55 seconds |
| Started | Aug 06 08:20:21 PM PDT 24 |
| Finished | Aug 06 08:23:54 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-a4e67cd4-feb1-421e-8b11-c841eb6740d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153792280 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.2153792280 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1066912234 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 3451718368 ps |
| CPU time | 335.12 seconds |
| Started | Aug 06 08:24:37 PM PDT 24 |
| Finished | Aug 06 08:30:12 PM PDT 24 |
| Peak memory | 609688 kb |
| Host | smart-6d6fd991-afc8-404d-bcfa-98a6dbf9fdec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1066912234 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_kmac_mode_kmac.1066912234 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3808917641 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 2469188270 ps |
| CPU time | 309.08 seconds |
| Started | Aug 06 08:27:24 PM PDT 24 |
| Finished | Aug 06 08:32:34 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-9f054cc5-5145-456e-bf0d-18eaad78a287 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808917641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.3808917641 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4049469298 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 3172352319 ps |
| CPU time | 271.29 seconds |
| Started | Aug 06 08:27:39 PM PDT 24 |
| Finished | Aug 06 08:32:11 PM PDT 24 |
| Peak memory | 608532 kb |
| Host | smart-708f709f-cd68-4c8d-a60c-675f852e58dc |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40494692 98 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4049469298 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.3176884496 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 3325428530 ps |
| CPU time | 413.05 seconds |
| Started | Aug 06 08:25:04 PM PDT 24 |
| Finished | Aug 06 08:31:57 PM PDT 24 |
| Peak memory | 609632 kb |
| Host | smart-906ddffa-d707-4ba2-9457-55ed648bead9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176884496 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.3176884496 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3261812877 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 3439710040 ps |
| CPU time | 266.75 seconds |
| Started | Aug 06 08:27:06 PM PDT 24 |
| Finished | Aug 06 08:31:33 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-bbb6c99f-40b4-4309-870c-f842fece5fd3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261812877 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.3261812877 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.4269079737 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4630038894 ps |
| CPU time | 495.01 seconds |
| Started | Aug 06 08:26:59 PM PDT 24 |
| Finished | Aug 06 08:35:14 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-0d396416-a36c-4d1a-951b-cbbc97ab9c3e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4269079737 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.4269079737 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4134241356 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 2789417131 ps |
| CPU time | 147.4 seconds |
| Started | Aug 06 08:22:07 PM PDT 24 |
| Finished | Aug 06 08:24:35 PM PDT 24 |
| Peak memory | 620696 kb |
| Host | smart-ecbe8136-8895-4844-8da5-0b549eda9fe0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41342413 56 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.4134241356 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1313374118 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 10336647563 ps |
| CPU time | 783.95 seconds |
| Started | Aug 06 08:26:00 PM PDT 24 |
| Finished | Aug 06 08:39:06 PM PDT 24 |
| Peak memory | 621168 kb |
| Host | smart-103cbf56-7d31-4800-8e7e-46c138e8ae2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313374118 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1313374118 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2674923521 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 2488080398 ps |
| CPU time | 119.66 seconds |
| Started | Aug 06 08:24:02 PM PDT 24 |
| Finished | Aug 06 08:26:01 PM PDT 24 |
| Peak memory | 617964 kb |
| Host | smart-327d911e-858c-47a2-879b-efa97e0104d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2674923521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.2674923521 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.843929731 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 2224250170 ps |
| CPU time | 92.18 seconds |
| Started | Aug 06 08:28:34 PM PDT 24 |
| Finished | Aug 06 08:30:07 PM PDT 24 |
| Peak memory | 617400 kb |
| Host | smart-8c915626-12ab-4087-8195-9d7757b01de2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843929731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.843929731 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.546570932 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 48189077830 ps |
| CPU time | 5705.29 seconds |
| Started | Aug 06 08:26:41 PM PDT 24 |
| Finished | Aug 06 10:01:49 PM PDT 24 |
| Peak memory | 620696 kb |
| Host | smart-ac531b62-b8e5-47f7-b189-12f4b4a26ca0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546570932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_dev.546570932 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.346589283 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 8649965921 ps |
| CPU time | 1027.91 seconds |
| Started | Aug 06 08:27:13 PM PDT 24 |
| Finished | Aug 06 08:44:23 PM PDT 24 |
| Peak memory | 618484 kb |
| Host | smart-79c35266-04db-4304-92e6-a5ff71977ed4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=346589283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.346589283 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1763713973 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 45908930520 ps |
| CPU time | 5860.03 seconds |
| Started | Aug 06 08:27:46 PM PDT 24 |
| Finished | Aug 06 10:05:29 PM PDT 24 |
| Peak memory | 619676 kb |
| Host | smart-8480e124-697d-4d12-a769-57f373054b46 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763713973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_rma.1763713973 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3686110133 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 28284953933 ps |
| CPU time | 1912.94 seconds |
| Started | Aug 06 08:28:44 PM PDT 24 |
| Finished | Aug 06 09:00:38 PM PDT 24 |
| Peak memory | 619920 kb |
| Host | smart-ab86fb68-379c-4649-a9eb-ef674e88593c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3686110133 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testun locks.3686110133 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1645146997 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 16934077400 ps |
| CPU time | 3701.72 seconds |
| Started | Aug 06 08:24:08 PM PDT 24 |
| Finished | Aug 06 09:25:50 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-768e5c13-3d4b-480a-8d15-cca9ce4ebf96 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1645146997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.1645146997 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1247999791 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 18323417022 ps |
| CPU time | 4250.18 seconds |
| Started | Aug 06 08:20:00 PM PDT 24 |
| Finished | Aug 06 09:30:51 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-b0c96129-06a9-465a-969c-2eacd76a7f8f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1247999791 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1247999791 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1229515251 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 24277567724 ps |
| CPU time | 4512.89 seconds |
| Started | Aug 06 08:22:21 PM PDT 24 |
| Finished | Aug 06 09:37:35 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-379c55ef-2b91-4d6d-97e8-dd2dbe145360 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229515251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1229515251 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1901065557 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 3676449176 ps |
| CPU time | 552.28 seconds |
| Started | Aug 06 08:28:01 PM PDT 24 |
| Finished | Aug 06 08:37:14 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-934b438e-0316-4266-b21e-8b4b4ffea742 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901065557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.1901065557 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2546090536 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 5552715134 ps |
| CPU time | 1040.95 seconds |
| Started | Aug 06 08:27:37 PM PDT 24 |
| Finished | Aug 06 08:44:58 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-a186823a-0209-4703-8da2-462ac2d80c78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2546090536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2546090536 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.1268774689 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 7847346026 ps |
| CPU time | 1765.36 seconds |
| Started | Aug 06 08:32:16 PM PDT 24 |
| Finished | Aug 06 09:01:42 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-11ce1941-e796-412e-9feb-b3695fc856d6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268774689 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.1268774689 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.587847254 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 3096572213 ps |
| CPU time | 327.84 seconds |
| Started | Aug 06 08:23:22 PM PDT 24 |
| Finished | Aug 06 08:28:51 PM PDT 24 |
| Peak memory | 610068 kb |
| Host | smart-18b948f2-d5f0-411b-8ae4-5cfaea9d5c32 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587847254 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.587847254 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3626108821 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 9541772558 ps |
| CPU time | 1346.11 seconds |
| Started | Aug 06 08:29:08 PM PDT 24 |
| Finished | Aug 06 08:51:35 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-cbc42b11-9e1d-4111-beb4-b25098d04616 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3626108821 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3626108821 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1816062365 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 9255427400 ps |
| CPU time | 1426.58 seconds |
| Started | Aug 06 08:27:22 PM PDT 24 |
| Finished | Aug 06 08:51:09 PM PDT 24 |
| Peak memory | 610328 kb |
| Host | smart-4aca4e03-dc6e-4ef2-b0ef-f91975c589a6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1816062365 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.1816062365 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3185218996 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 7082631992 ps |
| CPU time | 1254.23 seconds |
| Started | Aug 06 08:26:36 PM PDT 24 |
| Finished | Aug 06 08:47:30 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-6ff42c3e-52b3-4315-82a4-ea21de70f826 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3185218996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.3185218996 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.407222359 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 4682415324 ps |
| CPU time | 751.88 seconds |
| Started | Aug 06 08:27:59 PM PDT 24 |
| Finished | Aug 06 08:40:31 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-2b33b1c3-e4f5-472d-8bfb-2e0fbee02357 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=407222359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.407222359 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3782290049 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 3411606810 ps |
| CPU time | 347.55 seconds |
| Started | Aug 06 08:24:36 PM PDT 24 |
| Finished | Aug 06 08:30:24 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-f6007498-fc2f-4831-9964-e1f4929f3e67 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782290049 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.3782290049 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.4252089037 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 2901973550 ps |
| CPU time | 289.49 seconds |
| Started | Aug 06 08:27:09 PM PDT 24 |
| Finished | Aug 06 08:31:59 PM PDT 24 |
| Peak memory | 612416 kb |
| Host | smart-2fc844e2-54e7-4cc5-bd12-75475da5a488 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252089037 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.4252089037 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.3690730138 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 3522218374 ps |
| CPU time | 329.02 seconds |
| Started | Aug 06 08:26:20 PM PDT 24 |
| Finished | Aug 06 08:31:49 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-21407720-6919-4858-93b1-674971026b4a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690730138 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_plic_sw_irq.3690730138 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.3240759128 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 5102236328 ps |
| CPU time | 671.31 seconds |
| Started | Aug 06 08:28:28 PM PDT 24 |
| Finished | Aug 06 08:39:40 PM PDT 24 |
| Peak memory | 609500 kb |
| Host | smart-389cae94-12ca-4f52-96f5-78e3a862b6b6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240759128 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.3240759128 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.255429711 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 4609119496 ps |
| CPU time | 440.6 seconds |
| Started | Aug 06 08:26:54 PM PDT 24 |
| Finished | Aug 06 08:34:14 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-385e7374-793a-401b-bc13-4d268ee087af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255429711 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.255429711 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.3950448717 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 6031697376 ps |
| CPU time | 1906.01 seconds |
| Started | Aug 06 08:35:45 PM PDT 24 |
| Finished | Aug 06 09:07:32 PM PDT 24 |
| Peak memory | 624984 kb |
| Host | smart-06b8cbbb-aa97-42d8-8486-c3e631ca60a4 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3950448717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.3950448717 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.467794710 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 7198857025 ps |
| CPU time | 1181.38 seconds |
| Started | Aug 06 08:28:32 PM PDT 24 |
| Finished | Aug 06 08:48:14 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-bb678439-c8ed-41c0-b4e9-e101f2cfc022 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4677 94710 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.467794710 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1150718080 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 27466910171 ps |
| CPU time | 2843.44 seconds |
| Started | Aug 06 08:22:44 PM PDT 24 |
| Finished | Aug 06 09:10:08 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-6f889199-73c1-4da8-8df7-acf1d4eab117 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115 0718080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.1150718080 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1472067923 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 13901624325 ps |
| CPU time | 1478.21 seconds |
| Started | Aug 06 08:23:53 PM PDT 24 |
| Finished | Aug 06 08:48:32 PM PDT 24 |
| Peak memory | 611540 kb |
| Host | smart-b4b16105-8f12-4be1-b45b-02221fcdc3c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1472067923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1472067923 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.232957865 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 26512468174 ps |
| CPU time | 2103.73 seconds |
| Started | Aug 06 08:28:21 PM PDT 24 |
| Finished | Aug 06 09:03:26 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-8a10e9ac-5c2b-4b0b-94d8-429d55f635b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 232957865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.232957865 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2282475686 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 8659207994 ps |
| CPU time | 1043.35 seconds |
| Started | Aug 06 08:25:15 PM PDT 24 |
| Finished | Aug 06 08:42:39 PM PDT 24 |
| Peak memory | 610844 kb |
| Host | smart-6c5e07ff-d214-462e-9dd3-ac986efe5500 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282475686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2282475686 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1288545793 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 7672524108 ps |
| CPU time | 560.56 seconds |
| Started | Aug 06 08:28:35 PM PDT 24 |
| Finished | Aug 06 08:37:57 PM PDT 24 |
| Peak memory | 616368 kb |
| Host | smart-d45e9395-4efd-4f2b-b49e-43179a277d08 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1288545793 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1288545793 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.989468244 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 9590908042 ps |
| CPU time | 674.89 seconds |
| Started | Aug 06 08:26:20 PM PDT 24 |
| Finished | Aug 06 08:37:35 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-f08bcde3-94ca-47ab-ba4d-f6cead563893 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989468244 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.989468244 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2099800485 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 4007310502 ps |
| CPU time | 699.04 seconds |
| Started | Aug 06 08:21:44 PM PDT 24 |
| Finished | Aug 06 08:33:24 PM PDT 24 |
| Peak memory | 616372 kb |
| Host | smart-f76746d2-8958-48a3-9c10-87c5644225e7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2099800485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.2099800485 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1040707395 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 9010776348 ps |
| CPU time | 1360.22 seconds |
| Started | Aug 06 08:28:39 PM PDT 24 |
| Finished | Aug 06 08:51:20 PM PDT 24 |
| Peak memory | 611128 kb |
| Host | smart-696d0996-287f-4a46-b00c-5a2675c09556 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040707395 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1040707395 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.414121661 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 7618079768 ps |
| CPU time | 374.18 seconds |
| Started | Aug 06 08:24:11 PM PDT 24 |
| Finished | Aug 06 08:30:25 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-34596917-0e16-4862-9dc8-175af71ca131 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414121661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.414121661 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.607257449 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 5295324900 ps |
| CPU time | 412.91 seconds |
| Started | Aug 06 08:26:04 PM PDT 24 |
| Finished | Aug 06 08:32:57 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-fc609678-a8fc-4e75-8674-0bee780f6572 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607257449 -assert nopostpro c +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.607257449 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2809232052 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 25992598494 ps |
| CPU time | 2190.94 seconds |
| Started | Aug 06 08:29:12 PM PDT 24 |
| Finished | Aug 06 09:05:43 PM PDT 24 |
| Peak memory | 611224 kb |
| Host | smart-04440efd-4102-4580-b4c3-872d72a95e02 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2809232052 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2809232052 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.241935106 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 23514501880 ps |
| CPU time | 1537.49 seconds |
| Started | Aug 06 08:21:51 PM PDT 24 |
| Finished | Aug 06 08:47:29 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-f0a481e3-cb11-4fdc-bdcc-57bf5d90bae9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=241935106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.241935106 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1773416057 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4813975760 ps |
| CPU time | 412.31 seconds |
| Started | Aug 06 08:22:19 PM PDT 24 |
| Finished | Aug 06 08:29:12 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-8dd74716-0292-4b93-af04-a46f657c2a39 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=1773416057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.1773416057 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2824984536 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3798039172 ps |
| CPU time | 351.72 seconds |
| Started | Aug 06 08:25:35 PM PDT 24 |
| Finished | Aug 06 08:31:28 PM PDT 24 |
| Peak memory | 609592 kb |
| Host | smart-72891b1d-3c37-416e-b26e-44b3b8b9ea61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824984536 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.2824984536 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.957610917 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5242430822 ps |
| CPU time | 574.48 seconds |
| Started | Aug 06 08:27:00 PM PDT 24 |
| Finished | Aug 06 08:36:36 PM PDT 24 |
| Peak memory | 616848 kb |
| Host | smart-4c522ee5-a300-4033-a404-ce9c5b9b4aff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=957610917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_power_glitch_reset.957610917 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.238117649 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 5364143416 ps |
| CPU time | 527.47 seconds |
| Started | Aug 06 08:24:27 PM PDT 24 |
| Finished | Aug 06 08:33:15 PM PDT 24 |
| Peak memory | 608996 kb |
| Host | smart-017ef7b4-9f94-4c2b-a60a-3d7ab3e4cac3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23811764 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.238117649 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2867945797 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 6649723470 ps |
| CPU time | 495.12 seconds |
| Started | Aug 06 08:23:24 PM PDT 24 |
| Finished | Aug 06 08:31:39 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-5154ce9e-70c5-447f-8312-0b29a0a87d09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2867945797 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2867945797 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2619889714 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 6348691176 ps |
| CPU time | 511.89 seconds |
| Started | Aug 06 08:26:42 PM PDT 24 |
| Finished | Aug 06 08:35:14 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-e48987e5-62bf-4059-b2b6-ffd6204d82b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619889714 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.2619889714 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.2120095933 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 8347143060 ps |
| CPU time | 1392.43 seconds |
| Started | Aug 06 08:28:37 PM PDT 24 |
| Finished | Aug 06 08:51:51 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-5ffe825f-c77f-44cc-b76a-3a07586d29e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120095933 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.2120095933 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1715222778 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 4531717764 ps |
| CPU time | 423.77 seconds |
| Started | Aug 06 08:28:30 PM PDT 24 |
| Finished | Aug 06 08:35:34 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-0bf51707-6e7b-4fce-9781-b4a70eb058df |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715222778 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1715222778 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.700892667 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 5193606888 ps |
| CPU time | 296.72 seconds |
| Started | Aug 06 08:21:54 PM PDT 24 |
| Finished | Aug 06 08:26:51 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-cfd2e3b5-d631-4e87-9ab3-7d1b017944cd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700892667 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.700892667 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.3507867449 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 5089917922 ps |
| CPU time | 698.39 seconds |
| Started | Aug 06 08:26:47 PM PDT 24 |
| Finished | Aug 06 08:38:26 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-6c34695e-3314-4f58-9dcc-31553fc49e0a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350 7867449 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.3507867449 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2782115361 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 8725640128 ps |
| CPU time | 583.27 seconds |
| Started | Aug 06 08:25:49 PM PDT 24 |
| Finished | Aug 06 08:35:32 PM PDT 24 |
| Peak memory | 624772 kb |
| Host | smart-88eb0bf8-3065-41eb-b727-ab225b373ad4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782115361 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.2782115361 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1484427886 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 4943012348 ps |
| CPU time | 501.43 seconds |
| Started | Aug 06 08:27:38 PM PDT 24 |
| Finished | Aug 06 08:36:00 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-0238411c-430f-49e9-ab8b-5f7445113f12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484427886 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_rstmgr_cpu_info.1484427886 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.2913982902 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 6352046608 ps |
| CPU time | 776.76 seconds |
| Started | Aug 06 08:23:29 PM PDT 24 |
| Finished | Aug 06 08:36:26 PM PDT 24 |
| Peak memory | 641484 kb |
| Host | smart-70de5a6d-967f-409f-99f3-5efb038e1a47 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2913982902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.2913982902 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2823968762 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 2686223334 ps |
| CPU time | 299.81 seconds |
| Started | Aug 06 08:31:39 PM PDT 24 |
| Finished | Aug 06 08:36:40 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-ff40cc1d-2102-4f78-bc68-d084fef2870e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823968762 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_rstmgr_smoketest.2823968762 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.3774226183 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3176958248 ps |
| CPU time | 295.64 seconds |
| Started | Aug 06 08:24:47 PM PDT 24 |
| Finished | Aug 06 08:29:43 PM PDT 24 |
| Peak memory | 610136 kb |
| Host | smart-63878179-ede3-4043-ab58-ee70c04e587a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774226183 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rstmgr_sw_req.3774226183 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3478457666 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 3557429160 ps |
| CPU time | 291.16 seconds |
| Started | Aug 06 08:29:18 PM PDT 24 |
| Finished | Aug 06 08:34:09 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-db538746-6ff2-4f16-8a83-414408b5c2c9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478457666 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.3478457666 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1439427261 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3575520968 ps |
| CPU time | 363.76 seconds |
| Started | Aug 06 08:27:17 PM PDT 24 |
| Finished | Aug 06 08:33:22 PM PDT 24 |
| Peak memory | 608472 kb |
| Host | smart-a1ae8ff3-6b87-40f6-b0ce-2685b08eafea |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1439427261 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.1439427261 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1636447865 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 2634824095 ps |
| CPU time | 305.48 seconds |
| Started | Aug 06 08:24:30 PM PDT 24 |
| Finished | Aug 06 08:29:36 PM PDT 24 |
| Peak memory | 608704 kb |
| Host | smart-84bb45a4-8136-4e40-8b0a-a0591a286e35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636447865 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.1636447865 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2089877238 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 5362244080 ps |
| CPU time | 1040.11 seconds |
| Started | Aug 06 08:23:50 PM PDT 24 |
| Finished | Aug 06 08:41:12 PM PDT 24 |
| Peak memory | 610176 kb |
| Host | smart-e3fb41c1-548f-4638-ae21-c177dad03527 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20898 77238 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2089877238 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.230417878 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 5242843240 ps |
| CPU time | 1083.72 seconds |
| Started | Aug 06 08:27:16 PM PDT 24 |
| Finished | Aug 06 08:45:20 PM PDT 24 |
| Peak memory | 608836 kb |
| Host | smart-d69172a5-942b-4b82-b8e1-efa219886b71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=230417878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.230417878 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.947615486 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 5201846962 ps |
| CPU time | 462.93 seconds |
| Started | Aug 06 08:23:44 PM PDT 24 |
| Finished | Aug 06 08:31:27 PM PDT 24 |
| Peak memory | 624260 kb |
| Host | smart-24d224ad-19bc-4496-a44f-2376ba62fd99 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947615486 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.947615486 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.453119099 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4487051356 ps |
| CPU time | 463.82 seconds |
| Started | Aug 06 08:24:19 PM PDT 24 |
| Finished | Aug 06 08:32:03 PM PDT 24 |
| Peak memory | 621016 kb |
| Host | smart-0af9c640-f761-4e1f-98f8-3c26114d306d |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453119 099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.453119099 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2107747215 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 2246873208 ps |
| CPU time | 202.09 seconds |
| Started | Aug 06 08:24:58 PM PDT 24 |
| Finished | Aug 06 08:28:21 PM PDT 24 |
| Peak memory | 608496 kb |
| Host | smart-85ac755d-4f12-40a6-bd73-6fc3d3be8de8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107747215 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2107747215 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.1405028905 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3224034644 ps |
| CPU time | 262.8 seconds |
| Started | Aug 06 08:22:54 PM PDT 24 |
| Finished | Aug 06 08:27:17 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-7de31bab-9517-438b-bd80-92c62672715f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405028905 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.1405028905 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1503106294 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 3459692586 ps |
| CPU time | 268.24 seconds |
| Started | Aug 06 08:28:43 PM PDT 24 |
| Finished | Aug 06 08:33:12 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-2fb725fe-58e6-48a8-83ff-faf501392787 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503106294 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_smoketest.1503106294 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1251759807 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 3084369770 ps |
| CPU time | 253.99 seconds |
| Started | Aug 06 08:21:44 PM PDT 24 |
| Finished | Aug 06 08:25:58 PM PDT 24 |
| Peak memory | 610768 kb |
| Host | smart-bff26c07-6e62-40fb-978f-c2f000ad7df9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251759 807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1251759807 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.3514296685 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 4107163682 ps |
| CPU time | 399.77 seconds |
| Started | Aug 06 08:25:01 PM PDT 24 |
| Finished | Aug 06 08:31:41 PM PDT 24 |
| Peak memory | 610204 kb |
| Host | smart-e6e3912c-0559-43b9-a8a2-e62f259f8212 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514296685 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.3514296685 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2017314981 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 9402051928 ps |
| CPU time | 883.43 seconds |
| Started | Aug 06 08:19:26 PM PDT 24 |
| Finished | Aug 06 08:34:09 PM PDT 24 |
| Peak memory | 605308 kb |
| Host | smart-58ac390c-1858-4535-bd18-d924ca2e206b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2017314981 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.2017314981 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2901135229 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 7288667762 ps |
| CPU time | 645.4 seconds |
| Started | Aug 06 08:23:27 PM PDT 24 |
| Finished | Aug 06 08:34:14 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-a33cd8cb-eee4-486a-a5fe-bbcaaf10de50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901135229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.2901135229 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2186763006 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 6428345636 ps |
| CPU time | 728.35 seconds |
| Started | Aug 06 08:23:44 PM PDT 24 |
| Finished | Aug 06 08:35:53 PM PDT 24 |
| Peak memory | 624856 kb |
| Host | smart-6b043f58-a210-4b82-9d44-440b74f13969 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186763006 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.2186763006 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1765944596 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 5078623964 ps |
| CPU time | 572.82 seconds |
| Started | Aug 06 08:24:07 PM PDT 24 |
| Finished | Aug 06 08:33:40 PM PDT 24 |
| Peak memory | 624840 kb |
| Host | smart-00c428dc-aae0-408d-87b1-45798e9efd5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1765944596 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.1765944596 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3971934626 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 3561316053 ps |
| CPU time | 419.78 seconds |
| Started | Aug 06 08:25:01 PM PDT 24 |
| Finished | Aug 06 08:32:01 PM PDT 24 |
| Peak memory | 619072 kb |
| Host | smart-1cad9b57-9140-46c5-b8cf-fd30ecad63d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971934626 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.3971934626 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.1903500590 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2768785644 ps |
| CPU time | 318.43 seconds |
| Started | Aug 06 08:27:22 PM PDT 24 |
| Finished | Aug 06 08:32:42 PM PDT 24 |
| Peak memory | 618012 kb |
| Host | smart-6271544c-9ad2-46eb-810a-4b17fe3e116b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1903500590 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.1903500590 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2496459659 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3563269336 ps |
| CPU time | 338 seconds |
| Started | Aug 06 08:27:16 PM PDT 24 |
| Finished | Aug 06 08:32:55 PM PDT 24 |
| Peak memory | 609012 kb |
| Host | smart-9bfcfac6-2bdb-4399-953a-8e22187b749b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496459659 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.2496459659 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2603205200 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 10667360556 ps |
| CPU time | 1278.84 seconds |
| Started | Aug 06 08:25:41 PM PDT 24 |
| Finished | Aug 06 08:47:00 PM PDT 24 |
| Peak memory | 610712 kb |
| Host | smart-63c12950-f744-44fc-81d1-a73320994d78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603205200 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.2603205200 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1334001824 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 6103064428 ps |
| CPU time | 850.61 seconds |
| Started | Aug 06 08:24:44 PM PDT 24 |
| Finished | Aug 06 08:38:55 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-d1c43292-7efb-48ab-8dad-7e2f89163c37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1334001824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.1334001824 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2435345995 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 4650478336 ps |
| CPU time | 620.66 seconds |
| Started | Aug 06 08:23:59 PM PDT 24 |
| Finished | Aug 06 08:34:20 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-579fdaca-20d9-4a82-a482-1ad243c5bfcb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2435345995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2435345995 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.484702674 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 5228841318 ps |
| CPU time | 501.11 seconds |
| Started | Aug 06 08:24:07 PM PDT 24 |
| Finished | Aug 06 08:32:28 PM PDT 24 |
| Peak memory | 610796 kb |
| Host | smart-454c90c7-6e59-44e6-8180-b53ecd702cc0 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484702674 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.484702674 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1115908195 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 2707820634 ps |
| CPU time | 247.42 seconds |
| Started | Aug 06 08:28:49 PM PDT 24 |
| Finished | Aug 06 08:32:57 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-7b249369-435c-4b13-81d2-e0a689acc499 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115908195 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.1115908195 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.3915438369 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 21101850156 ps |
| CPU time | 3363.21 seconds |
| Started | Aug 06 08:25:20 PM PDT 24 |
| Finished | Aug 06 09:21:24 PM PDT 24 |
| Peak memory | 609856 kb |
| Host | smart-0d8c922f-7e5e-4154-860d-243a6fbec066 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915438369 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.3915438369 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.191782904 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4012137244 ps |
| CPU time | 596.82 seconds |
| Started | Aug 06 08:25:51 PM PDT 24 |
| Finished | Aug 06 08:35:50 PM PDT 24 |
| Peak memory | 613472 kb |
| Host | smart-a534bb55-f7da-4b14-b7d9-4e86bc5b1c61 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191782904 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.191782904 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.745072922 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 4012733720 ps |
| CPU time | 451.08 seconds |
| Started | Aug 06 08:28:37 PM PDT 24 |
| Finished | Aug 06 08:36:09 PM PDT 24 |
| Peak memory | 613096 kb |
| Host | smart-38d194a2-449c-475e-b1a9-75eeb811577b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745072922 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.745072922 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2782897302 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3189478472 ps |
| CPU time | 383.11 seconds |
| Started | Aug 06 08:27:19 PM PDT 24 |
| Finished | Aug 06 08:33:43 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-bb4ebe21-ef17-4e84-92b3-dc5b27eb3c38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782897302 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.2782897302 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3548882454 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 24502581976 ps |
| CPU time | 1683.86 seconds |
| Started | Aug 06 08:27:20 PM PDT 24 |
| Finished | Aug 06 08:55:25 PM PDT 24 |
| Peak memory | 614316 kb |
| Host | smart-c36f33b7-c4c5-4fce-8462-ded7f2b1408a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35488824 54 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.3548882454 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.756556135 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 13481909000 ps |
| CPU time | 2904.03 seconds |
| Started | Aug 06 08:25:07 PM PDT 24 |
| Finished | Aug 06 09:13:32 PM PDT 24 |
| Peak memory | 624464 kb |
| Host | smart-875ad5dc-6a21-4679-bc5c-7280a5524389 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=756556135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.756556135 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.1475699981 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 2840572840 ps |
| CPU time | 252.31 seconds |
| Started | Aug 06 08:23:04 PM PDT 24 |
| Finished | Aug 06 08:27:16 PM PDT 24 |
| Peak memory | 614848 kb |
| Host | smart-c7713fdd-38ca-42ab-a718-4ebc26f482d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475699981 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_uart_smoketest.1475699981 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.4223362603 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 4155728888 ps |
| CPU time | 665.26 seconds |
| Started | Aug 06 08:24:14 PM PDT 24 |
| Finished | Aug 06 08:35:20 PM PDT 24 |
| Peak memory | 623932 kb |
| Host | smart-ffc944da-b738-440a-a479-c0d166a87114 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223362603 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.4223362603 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.1484785251 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 4992542285 ps |
| CPU time | 749.95 seconds |
| Started | Aug 06 08:26:20 PM PDT 24 |
| Finished | Aug 06 08:38:51 PM PDT 24 |
| Peak memory | 623516 kb |
| Host | smart-73d865aa-1244-4d51-9d6b-2969ec81ad71 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484785251 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.1484785251 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3127129744 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 3660539999 ps |
| CPU time | 644.37 seconds |
| Started | Aug 06 08:22:37 PM PDT 24 |
| Finished | Aug 06 08:33:23 PM PDT 24 |
| Peak memory | 623588 kb |
| Host | smart-dd8d2351-6906-4339-96dd-2fbaf4f1aa37 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127129744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3127129744 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.2315177189 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 78427930368 ps |
| CPU time | 14193 seconds |
| Started | Aug 06 08:26:01 PM PDT 24 |
| Finished | Aug 07 12:22:36 AM PDT 24 |
| Peak memory | 636056 kb |
| Host | smart-53bf0daf-8ee6-4233-8291-f12eef4e1794 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=2315177189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.2315177189 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1147798458 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3778649054 ps |
| CPU time | 606.91 seconds |
| Started | Aug 06 08:22:29 PM PDT 24 |
| Finished | Aug 06 08:32:37 PM PDT 24 |
| Peak memory | 623896 kb |
| Host | smart-26e515ad-90a6-40f2-a7d4-a996b2c1237a |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147798458 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.1147798458 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2027617051 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4109534412 ps |
| CPU time | 522.91 seconds |
| Started | Aug 06 08:23:49 PM PDT 24 |
| Finished | Aug 06 08:32:33 PM PDT 24 |
| Peak memory | 623948 kb |
| Host | smart-8956a726-759e-4aae-84d0-122088f8888c |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027617051 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2027617051 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.734607216 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 4501348828 ps |
| CPU time | 652.65 seconds |
| Started | Aug 06 08:20:47 PM PDT 24 |
| Finished | Aug 06 08:31:40 PM PDT 24 |
| Peak memory | 624280 kb |
| Host | smart-bc7a0146-fa06-4d10-a9a5-671b7c154934 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734607216 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.734607216 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.3101134989 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 3038561838 ps |
| CPU time | 202.31 seconds |
| Started | Aug 06 08:24:14 PM PDT 24 |
| Finished | Aug 06 08:27:36 PM PDT 24 |
| Peak memory | 621436 kb |
| Host | smart-79a3e342-3d75-43c9-a450-5424269ea05a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3101134989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.3101134989 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.3587455685 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 2739308354 ps |
| CPU time | 125.25 seconds |
| Started | Aug 06 08:22:53 PM PDT 24 |
| Finished | Aug 06 08:24:58 PM PDT 24 |
| Peak memory | 623344 kb |
| Host | smart-e80fa5be-6491-4b1a-84eb-50545f37e0d1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587455685 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.3587455685 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.2749370407 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 5674946404 ps |
| CPU time | 467.61 seconds |
| Started | Aug 06 08:21:30 PM PDT 24 |
| Finished | Aug 06 08:29:18 PM PDT 24 |
| Peak memory | 633204 kb |
| Host | smart-05030cd2-4bc8-46bf-a93b-0c8d9b939495 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2749370407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.2749370407 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.278487551 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 16181406176 ps |
| CPU time | 4447.46 seconds |
| Started | Aug 06 08:35:22 PM PDT 24 |
| Finished | Aug 06 09:49:31 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-0b50bedc-ce87-4744-b366-fb1f51291fd2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278487551 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_dev.278487551 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.3620519839 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 15314435861 ps |
| CPU time | 4037.57 seconds |
| Started | Aug 06 08:27:11 PM PDT 24 |
| Finished | Aug 06 09:34:30 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-26cedcc7-3dd0-4088-be6b-2ceae2aa618f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620519839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3620519839 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3489196363 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 15395397410 ps |
| CPU time | 4432.61 seconds |
| Started | Aug 06 08:25:02 PM PDT 24 |
| Finished | Aug 06 09:38:55 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-e39639b0-27ff-432e-b99b-47068ff82fcb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489196363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.3489196363 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1065179034 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 15154060132 ps |
| CPU time | 4666.85 seconds |
| Started | Aug 06 08:31:50 PM PDT 24 |
| Finished | Aug 06 09:49:37 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-6f1f728a-7f58-4346-8244-423832542671 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1065179034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1065179034 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.420476509 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 10912994655 ps |
| CPU time | 3309.1 seconds |
| Started | Aug 06 08:35:26 PM PDT 24 |
| Finished | Aug 06 09:30:36 PM PDT 24 |
| Peak memory | 610576 kb |
| Host | smart-aa5e16f5-26e1-45be-823e-08e0f630ee30 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420476509 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.rom_e2e_asm_init_test_unlocked0.420476509 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.1374496367 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 15284414520 ps |
| CPU time | 3900.9 seconds |
| Started | Aug 06 08:34:47 PM PDT 24 |
| Finished | Aug 06 09:39:49 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-ba62ef6a-0a68-45e3-8e54-7e8a090aea59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374496367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1374496367 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1122072911 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 15560992344 ps |
| CPU time | 4852.41 seconds |
| Started | Aug 06 08:28:35 PM PDT 24 |
| Finished | Aug 06 09:49:28 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-3bbf2cf5-99f2-417d-a31e-8b0c1bbc2413 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122072911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.1122072911 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3178642894 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 14929973320 ps |
| CPU time | 4273.69 seconds |
| Started | Aug 06 08:30:01 PM PDT 24 |
| Finished | Aug 06 09:41:15 PM PDT 24 |
| Peak memory | 609868 kb |
| Host | smart-931eef8a-c19e-46bc-be51-31ea82af0da2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178642894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.3178642894 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3856578078 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 14721445970 ps |
| CPU time | 3858.06 seconds |
| Started | Aug 06 08:35:11 PM PDT 24 |
| Finished | Aug 06 09:39:30 PM PDT 24 |
| Peak memory | 611244 kb |
| Host | smart-5173167e-1874-4f65-a4b4-d78d3b9d3f93 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856578078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.3856578078 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.211892744 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 25894440990 ps |
| CPU time | 4286.65 seconds |
| Started | Aug 06 08:31:03 PM PDT 24 |
| Finished | Aug 06 09:42:30 PM PDT 24 |
| Peak memory | 611788 kb |
| Host | smart-9ef82151-ee5a-46bc-b876-ed30b0ddd14f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211892744 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.211892744 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.3778472843 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 14695043150 ps |
| CPU time | 3896.19 seconds |
| Started | Aug 06 08:29:55 PM PDT 24 |
| Finished | Aug 06 09:34:52 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-ac39d0f2-4e3e-4363-abd5-0772a22d059c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=3778472843 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.3778472843 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.3150859882 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 16828380100 ps |
| CPU time | 4518.03 seconds |
| Started | Aug 06 08:30:47 PM PDT 24 |
| Finished | Aug 06 09:46:06 PM PDT 24 |
| Peak memory | 610152 kb |
| Host | smart-e796be3d-da8e-4ce1-9f35-4e6748663ac9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150859882 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.3150859882 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2973209165 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 4388490190 ps |
| CPU time | 752.61 seconds |
| Started | Aug 06 08:26:50 PM PDT 24 |
| Finished | Aug 06 08:39:23 PM PDT 24 |
| Peak memory | 610560 kb |
| Host | smart-dea9e0f8-3735-4195-a027-26618793739b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973209165 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2973209165 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.179361774 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 5279764784 ps |
| CPU time | 244.38 seconds |
| Started | Aug 06 08:23:19 PM PDT 24 |
| Finished | Aug 06 08:27:24 PM PDT 24 |
| Peak memory | 619804 kb |
| Host | smart-8cb06832-e8ad-4a1a-8e15-b0f36b3c5972 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=179361774 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.179361774 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.207685113 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 2356123655 ps |
| CPU time | 130.13 seconds |
| Started | Aug 06 08:24:04 PM PDT 24 |
| Finished | Aug 06 08:26:15 PM PDT 24 |
| Peak memory | 617056 kb |
| Host | smart-42cac04f-dd45-4266-a77e-734c6e5c024d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207685113 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.207685113 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.923891213 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 5460272161 ps |
| CPU time | 560.31 seconds |
| Started | Aug 06 08:41:37 PM PDT 24 |
| Finished | Aug 06 08:50:58 PM PDT 24 |
| Peak memory | 621440 kb |
| Host | smart-8110f127-caa2-4f9c-a501-ee56a11d2d35 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=923891213 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.923891213 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3901533674 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 5018413008 ps |
| CPU time | 630.42 seconds |
| Started | Aug 06 08:43:29 PM PDT 24 |
| Finished | Aug 06 08:54:00 PM PDT 24 |
| Peak memory | 623280 kb |
| Host | smart-752c108c-4e7a-423a-a93f-7c2990f09e63 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3901533674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.3901533674 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1841295717 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 11379952491 ps |
| CPU time | 887.8 seconds |
| Started | Aug 06 08:41:47 PM PDT 24 |
| Finished | Aug 06 08:56:36 PM PDT 24 |
| Peak memory | 621120 kb |
| Host | smart-2e845a0c-61a4-4d56-8839-de6079aad65a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841295717 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1841295717 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3081965505 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 4014302920 ps |
| CPU time | 724.62 seconds |
| Started | Aug 06 08:41:35 PM PDT 24 |
| Finished | Aug 06 08:53:41 PM PDT 24 |
| Peak memory | 623232 kb |
| Host | smart-9d6e852d-2a82-4b2e-b205-5c7faf3eaa82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3081965505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.3081965505 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.2371887682 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 3606899174 ps |
| CPU time | 421.17 seconds |
| Started | Aug 06 08:41:59 PM PDT 24 |
| Finished | Aug 06 08:49:00 PM PDT 24 |
| Peak memory | 649116 kb |
| Host | smart-156c0759-6cf8-46eb-8058-3f453aa625a6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371887682 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2371887682 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1102851706 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 12112807669 ps |
| CPU time | 1019.49 seconds |
| Started | Aug 06 08:43:10 PM PDT 24 |
| Finished | Aug 06 09:00:11 PM PDT 24 |
| Peak memory | 621216 kb |
| Host | smart-e80673cf-9f6e-4e3a-acbf-d28f76d0baaf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102851706 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.1102851706 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1030327940 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 8501275774 ps |
| CPU time | 1504.36 seconds |
| Started | Aug 06 08:43:23 PM PDT 24 |
| Finished | Aug 06 09:08:28 PM PDT 24 |
| Peak memory | 623320 kb |
| Host | smart-81aa0d97-89be-4638-a429-6cf9d3d6f21f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1030327940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.1030327940 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3904596659 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 4087065600 ps |
| CPU time | 442.13 seconds |
| Started | Aug 06 08:41:59 PM PDT 24 |
| Finished | Aug 06 08:49:22 PM PDT 24 |
| Peak memory | 649032 kb |
| Host | smart-f38f1710-52a4-41a2-ba66-0932fc61e44e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904596659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3904596659 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1098614272 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 7410973351 ps |
| CPU time | 719.12 seconds |
| Started | Aug 06 08:42:41 PM PDT 24 |
| Finished | Aug 06 08:54:40 PM PDT 24 |
| Peak memory | 622500 kb |
| Host | smart-888bebc7-9da7-48d8-9e52-f1d54786d9ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098614272 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.1098614272 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.926989633 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 4105299800 ps |
| CPU time | 734.48 seconds |
| Started | Aug 06 08:41:53 PM PDT 24 |
| Finished | Aug 06 08:54:07 PM PDT 24 |
| Peak memory | 623456 kb |
| Host | smart-6d642829-54d6-4d9a-9153-8cf6cb5f3f0d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=926989633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.926989633 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2058109746 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 10004457235 ps |
| CPU time | 1095.56 seconds |
| Started | Aug 06 08:43:54 PM PDT 24 |
| Finished | Aug 06 09:02:09 PM PDT 24 |
| Peak memory | 621188 kb |
| Host | smart-08724feb-a871-42cd-88e5-9286720c86c2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2058109746 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2058109746 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2102874690 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 8035672592 ps |
| CPU time | 1620.3 seconds |
| Started | Aug 06 08:42:26 PM PDT 24 |
| Finished | Aug 06 09:09:27 PM PDT 24 |
| Peak memory | 624532 kb |
| Host | smart-4c4e4ddd-056f-44e1-b4bf-f401cedb2120 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2102874690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.2102874690 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1136061597 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8385118616 ps |
| CPU time | 1451.03 seconds |
| Started | Aug 06 08:41:46 PM PDT 24 |
| Finished | Aug 06 09:05:58 PM PDT 24 |
| Peak memory | 623240 kb |
| Host | smart-bba09545-aaec-422d-9646-a3ba09eca1fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1136061597 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.1136061597 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1836709637 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 13281249644 ps |
| CPU time | 2455.57 seconds |
| Started | Aug 06 08:42:42 PM PDT 24 |
| Finished | Aug 06 09:23:38 PM PDT 24 |
| Peak memory | 624616 kb |
| Host | smart-ff77d02b-1e16-4dde-b1c8-77e94fb0c654 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1836709637 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.1836709637 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3203396307 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 12877203214 ps |
| CPU time | 2521.85 seconds |
| Started | Aug 06 08:43:00 PM PDT 24 |
| Finished | Aug 06 09:25:02 PM PDT 24 |
| Peak memory | 624544 kb |
| Host | smart-7237f868-1e4a-49b7-8de4-b6eb4faee7d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3203396307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3203396307 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3462608706 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 4281922296 ps |
| CPU time | 578.54 seconds |
| Started | Aug 06 08:43:48 PM PDT 24 |
| Finished | Aug 06 08:53:27 PM PDT 24 |
| Peak memory | 624484 kb |
| Host | smart-434b4eed-9803-4324-9fe1-125770249b7a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3462608706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.3462608706 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.1948588996 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 5530535748 ps |
| CPU time | 624.32 seconds |
| Started | Aug 06 08:42:27 PM PDT 24 |
| Finished | Aug 06 08:52:52 PM PDT 24 |
| Peak memory | 649912 kb |
| Host | smart-dde730e2-eb0f-4445-98b6-f738fcf3a817 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1948588996 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.1948588996 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.4172470495 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 9034384880 ps |
| CPU time | 2172.8 seconds |
| Started | Aug 06 08:42:32 PM PDT 24 |
| Finished | Aug 06 09:18:46 PM PDT 24 |
| Peak memory | 624448 kb |
| Host | smart-e2f8518b-f7f2-4dbd-93d0-65438e0461f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4172470495 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.4172470495 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.1790879889 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 4415348988 ps |
| CPU time | 327.39 seconds |
| Started | Aug 06 08:30:09 PM PDT 24 |
| Finished | Aug 06 08:35:36 PM PDT 24 |
| Peak memory | 603012 kb |
| Host | smart-cdaa822a-644f-40b4-be23-9054bc4364ba |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790879889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1790879889 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.3642900169 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 13737361598 ps |
| CPU time | 1504.17 seconds |
| Started | Aug 06 08:30:10 PM PDT 24 |
| Finished | Aug 06 08:55:15 PM PDT 24 |
| Peak memory | 607988 kb |
| Host | smart-501f2e95-0fad-4871-8ff4-98d19e7831fc |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642900169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.3 642900169 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3216974581 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 3856163260 ps |
| CPU time | 371.53 seconds |
| Started | Aug 06 08:37:48 PM PDT 24 |
| Finished | Aug 06 08:43:59 PM PDT 24 |
| Peak memory | 619720 kb |
| Host | smart-8018f0b9-1b22-49b7-83d5-02360cb80eea |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3 216974581 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.3216974581 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.3084534322 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3255367082 ps |
| CPU time | 326.25 seconds |
| Started | Aug 06 08:29:50 PM PDT 24 |
| Finished | Aug 06 08:35:16 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-38da6df4-b875-4fa8-bfe3-859f10ac78fc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3084534322 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.3084534322 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.691049104 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 18440315720 ps |
| CPU time | 637.42 seconds |
| Started | Aug 06 08:31:41 PM PDT 24 |
| Finished | Aug 06 08:42:19 PM PDT 24 |
| Peak memory | 619388 kb |
| Host | smart-1d81c625-811d-4a14-ab0e-5a4a5d4df529 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=691049104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.691049104 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.3559482715 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 3438775528 ps |
| CPU time | 331.89 seconds |
| Started | Aug 06 08:34:00 PM PDT 24 |
| Finished | Aug 06 08:39:33 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-99988fd7-12c3-4b6a-9f68-44742f70672d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3559482715 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.3559482715 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4035666571 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 2917224165 ps |
| CPU time | 289.86 seconds |
| Started | Aug 06 08:32:39 PM PDT 24 |
| Finished | Aug 06 08:37:29 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-b50bc2b8-95d1-4c45-bf39-6006c9b6c7ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035 666571 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.4035666571 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3855693159 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 3437471493 ps |
| CPU time | 305.53 seconds |
| Started | Aug 06 08:38:07 PM PDT 24 |
| Finished | Aug 06 08:43:13 PM PDT 24 |
| Peak memory | 608736 kb |
| Host | smart-9f96df78-6722-43f2-b024-aa4b6d501fe6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3855693159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.3855693159 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.75176511 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 2390589944 ps |
| CPU time | 249.35 seconds |
| Started | Aug 06 08:33:37 PM PDT 24 |
| Finished | Aug 06 08:37:46 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-bd456e13-8294-41ca-9995-464f3917337e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75176511 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.75176511 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.3094966105 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 3090820466 ps |
| CPU time | 371 seconds |
| Started | Aug 06 08:34:51 PM PDT 24 |
| Finished | Aug 06 08:41:04 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-acbcda39-f0fa-42eb-a3cd-6dd3fd77be0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094966105 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.3094966105 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.3262209161 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 2357198106 ps |
| CPU time | 290.84 seconds |
| Started | Aug 06 08:32:51 PM PDT 24 |
| Finished | Aug 06 08:37:42 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-f4f8056b-23ce-440b-b479-9467b922136f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262209161 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.3262209161 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.3735528113 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3042442808 ps |
| CPU time | 400.01 seconds |
| Started | Aug 06 08:38:52 PM PDT 24 |
| Finished | Aug 06 08:45:32 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-fc9788cf-d29e-49c6-9dc1-ee8679407588 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735528113 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.3735528113 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.408593689 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 4136223551 ps |
| CPU time | 472.15 seconds |
| Started | Aug 06 08:34:30 PM PDT 24 |
| Finished | Aug 06 08:42:23 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-55b63fea-c04a-4f60-a828-aa66c618af70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=408593689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.408593689 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2118718178 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 6030935144 ps |
| CPU time | 628.8 seconds |
| Started | Aug 06 08:33:06 PM PDT 24 |
| Finished | Aug 06 08:43:35 PM PDT 24 |
| Peak memory | 619444 kb |
| Host | smart-7f52e6ea-9cea-49ef-ae0d-532e25fc4125 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2118718178 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.2118718178 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3457929558 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 6803603478 ps |
| CPU time | 1651.98 seconds |
| Started | Aug 06 08:36:01 PM PDT 24 |
| Finished | Aug 06 09:03:34 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-36e145ad-7e7e-400f-afb4-7da8b8598949 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3457929558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.3457929558 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2138208865 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 8365515668 ps |
| CPU time | 1886.81 seconds |
| Started | Aug 06 08:34:11 PM PDT 24 |
| Finished | Aug 06 09:05:38 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-c6be8f5d-1aca-4646-b7c8-1953034e49de |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138208865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.2138208865 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.760524196 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 10867798008 ps |
| CPU time | 1252.15 seconds |
| Started | Aug 06 08:34:31 PM PDT 24 |
| Finished | Aug 06 08:55:23 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-7e431efb-6bf6-4286-8a2a-de63d82ae4e7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=760524196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_hand ler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.760524196 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.50919112 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 7730940894 ps |
| CPU time | 1462.5 seconds |
| Started | Aug 06 08:34:37 PM PDT 24 |
| Finished | Aug 06 08:58:59 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-2d30d5e5-9177-4311-a272-f29006f46b81 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=50919112 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.50919112 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1520802644 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 3411103404 ps |
| CPU time | 375.93 seconds |
| Started | Aug 06 08:34:37 PM PDT 24 |
| Finished | Aug 06 08:40:53 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-a19a8a13-302d-4313-a9b9-4c300b6604e1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1520802644 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.1520802644 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.2100437861 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 2819685752 ps |
| CPU time | 323.96 seconds |
| Started | Aug 06 08:33:16 PM PDT 24 |
| Finished | Aug 06 08:38:40 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-91b6796b-a24d-4c18-847a-c48d24d768d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100437861 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.2100437861 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.3188464772 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 4134191696 ps |
| CPU time | 369.09 seconds |
| Started | Aug 06 08:32:27 PM PDT 24 |
| Finished | Aug 06 08:38:36 PM PDT 24 |
| Peak memory | 609700 kb |
| Host | smart-d7226c09-4261-4882-a84e-d5b794798849 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3188464772 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.3188464772 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1678286915 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 6287259724 ps |
| CPU time | 417.08 seconds |
| Started | Aug 06 08:31:51 PM PDT 24 |
| Finished | Aug 06 08:38:49 PM PDT 24 |
| Peak memory | 609192 kb |
| Host | smart-d2ccede8-05a7-403e-8eb8-01baa34ebea0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1678286915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1678286915 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2674288542 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 3735577200 ps |
| CPU time | 273.3 seconds |
| Started | Aug 06 08:39:09 PM PDT 24 |
| Finished | Aug 06 08:43:43 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-78ddbf82-3300-4cbb-b66e-6bf2feaf688e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674288542 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.2674288542 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1217227325 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 7898619260 ps |
| CPU time | 716.97 seconds |
| Started | Aug 06 08:30:33 PM PDT 24 |
| Finished | Aug 06 08:42:30 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-f7fcaccc-7e96-4122-99ac-e3c9e97ba7e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1217227325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.1217227325 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2801926845 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 6140909120 ps |
| CPU time | 636.36 seconds |
| Started | Aug 06 08:32:37 PM PDT 24 |
| Finished | Aug 06 08:43:14 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-dd4b9d37-11b3-4d27-824d-1f2b5cf6afec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2801926845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2801926845 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2030695266 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 6624078328 ps |
| CPU time | 835.46 seconds |
| Started | Aug 06 08:37:13 PM PDT 24 |
| Finished | Aug 06 08:51:09 PM PDT 24 |
| Peak memory | 616408 kb |
| Host | smart-1e1c5ece-fa29-498f-beec-2042101d86b7 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030695266 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.2030695266 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3684450800 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 20477894059 ps |
| CPU time | 3183.29 seconds |
| Started | Aug 06 08:38:07 PM PDT 24 |
| Finished | Aug 06 09:31:11 PM PDT 24 |
| Peak memory | 610932 kb |
| Host | smart-00a15268-623f-4055-b9ee-54d7be779507 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3684450800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.3684450800 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.969981071 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 6431381052 ps |
| CPU time | 638.27 seconds |
| Started | Aug 06 08:37:57 PM PDT 24 |
| Finished | Aug 06 08:48:36 PM PDT 24 |
| Peak memory | 620472 kb |
| Host | smart-550ad86e-388b-4ecf-a6d6-7c399ca23390 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=969981071 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.969981071 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2512231345 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 4376492390 ps |
| CPU time | 725.43 seconds |
| Started | Aug 06 08:36:56 PM PDT 24 |
| Finished | Aug 06 08:49:01 PM PDT 24 |
| Peak memory | 612104 kb |
| Host | smart-1bf73283-2035-40e6-8ed3-8c8479b93685 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512231345 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.2512231345 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2603346537 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 4321337728 ps |
| CPU time | 699.56 seconds |
| Started | Aug 06 08:38:26 PM PDT 24 |
| Finished | Aug 06 08:50:06 PM PDT 24 |
| Peak memory | 612900 kb |
| Host | smart-3bec25ba-3b98-4b89-9be6-5d1c69946e04 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603346537 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.2603346537 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2302845681 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 3814922630 ps |
| CPU time | 700.48 seconds |
| Started | Aug 06 08:36:29 PM PDT 24 |
| Finished | Aug 06 08:48:09 PM PDT 24 |
| Peak memory | 612216 kb |
| Host | smart-75053b5e-351d-48d0-be2d-2f1effe8a943 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302845681 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2302845681 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.234492751 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 5250703336 ps |
| CPU time | 583.05 seconds |
| Started | Aug 06 08:38:17 PM PDT 24 |
| Finished | Aug 06 08:48:00 PM PDT 24 |
| Peak memory | 612180 kb |
| Host | smart-34f2d52d-6fe5-4c2f-bf65-18ec5a362370 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234492751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.234492751 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.860964711 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 4841495886 ps |
| CPU time | 597.37 seconds |
| Started | Aug 06 08:37:18 PM PDT 24 |
| Finished | Aug 06 08:47:16 PM PDT 24 |
| Peak memory | 612164 kb |
| Host | smart-14fb36e6-e421-4e7b-b2d3-2170e5ce962e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860964711 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_rma.860964711 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1257096919 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 4213743178 ps |
| CPU time | 596.47 seconds |
| Started | Aug 06 08:36:59 PM PDT 24 |
| Finished | Aug 06 08:46:56 PM PDT 24 |
| Peak memory | 612188 kb |
| Host | smart-511720fd-5866-4a58-a993-dad22dd9752e |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257096919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1257096919 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.387214042 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 1998103926 ps |
| CPU time | 178.65 seconds |
| Started | Aug 06 08:39:32 PM PDT 24 |
| Finished | Aug 06 08:42:30 PM PDT 24 |
| Peak memory | 609252 kb |
| Host | smart-4465de3d-cfe7-4beb-9024-c3bf7776a90c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387214042 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_clkmgr_jitter.387214042 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1485276783 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 2766678852 ps |
| CPU time | 473.17 seconds |
| Started | Aug 06 08:37:58 PM PDT 24 |
| Finished | Aug 06 08:45:52 PM PDT 24 |
| Peak memory | 609512 kb |
| Host | smart-46409daf-ba88-48da-a4b8-cd35aa1951b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485276783 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.1485276783 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.692572180 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 2228229072 ps |
| CPU time | 200.52 seconds |
| Started | Aug 06 08:40:04 PM PDT 24 |
| Finished | Aug 06 08:43:25 PM PDT 24 |
| Peak memory | 609276 kb |
| Host | smart-9f7cd74b-bb37-4e77-8a74-dbdb599ef20f |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692572180 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.692572180 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1350047036 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 5186862748 ps |
| CPU time | 457.27 seconds |
| Started | Aug 06 08:36:32 PM PDT 24 |
| Finished | Aug 06 08:44:09 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-eef8e156-5fa4-4999-b2df-cb38977fa7b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350047036 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.1350047036 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1921384899 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 6007324240 ps |
| CPU time | 673.46 seconds |
| Started | Aug 06 08:37:42 PM PDT 24 |
| Finished | Aug 06 08:48:55 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-be703d55-322d-4a7c-b998-174989b07a4b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921384899 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.1921384899 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.112407920 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 4720860422 ps |
| CPU time | 640.3 seconds |
| Started | Aug 06 08:38:03 PM PDT 24 |
| Finished | Aug 06 08:48:43 PM PDT 24 |
| Peak memory | 610180 kb |
| Host | smart-b73b4db3-5511-4a2b-b3b7-f12dc1a1c815 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112407920 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.112407920 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.609834265 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4401118814 ps |
| CPU time | 461.28 seconds |
| Started | Aug 06 08:37:01 PM PDT 24 |
| Finished | Aug 06 08:44:43 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-99a839ca-6173-4668-a2f6-97f1d2fe114f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609834265 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.609834265 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.742570616 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 10386924160 ps |
| CPU time | 1832.14 seconds |
| Started | Aug 06 08:36:47 PM PDT 24 |
| Finished | Aug 06 09:07:20 PM PDT 24 |
| Peak memory | 610344 kb |
| Host | smart-36d6c74c-7886-494e-9354-1963b5b0967b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742570616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.742570616 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1119538264 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 3731557021 ps |
| CPU time | 515.21 seconds |
| Started | Aug 06 08:37:55 PM PDT 24 |
| Finished | Aug 06 08:46:31 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-e59777e9-55a3-4aec-b33f-6f7a72145ee3 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119538264 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.1119538264 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2261297133 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 4539548248 ps |
| CPU time | 707.89 seconds |
| Started | Aug 06 08:36:47 PM PDT 24 |
| Finished | Aug 06 08:48:35 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-8037ac4f-1cbf-4b73-8269-b769f42bd3f2 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261297133 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.2261297133 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.466356881 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 3599190752 ps |
| CPU time | 245.77 seconds |
| Started | Aug 06 08:40:34 PM PDT 24 |
| Finished | Aug 06 08:44:40 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-003edaa6-1806-48e3-b8d2-144920d980e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466356881 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_clkmgr_smoketest.466356881 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1006355910 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 28750359260 ps |
| CPU time | 6837.02 seconds |
| Started | Aug 06 08:39:45 PM PDT 24 |
| Finished | Aug 06 10:33:42 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-d25cf23e-12a6-4cfd-b5b9-88ec1cc8297f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006355910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.1006355910 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.3426727806 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 17298644465 ps |
| CPU time | 3191.48 seconds |
| Started | Aug 06 08:38:52 PM PDT 24 |
| Finished | Aug 06 09:32:04 PM PDT 24 |
| Peak memory | 610320 kb |
| Host | smart-26b0cc01-d55e-4b7a-bfed-13b3c1bfe5e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +accelerate_ cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=3426727806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.3426727806 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1141969806 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 4672949464 ps |
| CPU time | 550.57 seconds |
| Started | Aug 06 08:37:51 PM PDT 24 |
| Finished | Aug 06 08:47:02 PM PDT 24 |
| Peak memory | 609548 kb |
| Host | smart-ed012b74-b543-43a0-b5fb-d16ed07754ac |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11419 69806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1141969806 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.1444377473 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2593652334 ps |
| CPU time | 287.99 seconds |
| Started | Aug 06 08:34:39 PM PDT 24 |
| Finished | Aug 06 08:39:28 PM PDT 24 |
| Peak memory | 609440 kb |
| Host | smart-1e8ddb96-de6f-4afa-8905-36f40d49ca0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444377473 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1444377473 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3803131004 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 6692627522 ps |
| CPU time | 790.02 seconds |
| Started | Aug 06 08:34:50 PM PDT 24 |
| Finished | Aug 06 08:48:00 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-1322da3e-c35b-4b34-b66f-19e6f93cf61f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803131004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.3803131004 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.175700657 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 2949409704 ps |
| CPU time | 234.87 seconds |
| Started | Aug 06 08:41:31 PM PDT 24 |
| Finished | Aug 06 08:45:26 PM PDT 24 |
| Peak memory | 609572 kb |
| Host | smart-432b2568-5dd6-4881-aadd-0a246d13c185 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175700657 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_csrng_smoketest.175700657 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.2281291259 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 4244019412 ps |
| CPU time | 964.36 seconds |
| Started | Aug 06 08:35:34 PM PDT 24 |
| Finished | Aug 06 08:51:39 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-3725a0bb-92b7-4c25-8e92-a87d17f117ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281291259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2281291259 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.3714142275 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 3542782600 ps |
| CPU time | 576.8 seconds |
| Started | Aug 06 08:34:50 PM PDT 24 |
| Finished | Aug 06 08:44:27 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-180c2843-5198-4153-99cf-b0a52e111ce8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_ build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714142275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ boot_mode.3714142275 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2501705192 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 6482200820 ps |
| CPU time | 1483.98 seconds |
| Started | Aug 06 08:36:01 PM PDT 24 |
| Finished | Aug 06 09:00:45 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-ef83a8aa-cd90-470c-a701-251d996f5d78 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=2501705192 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.2501705192 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4286946488 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 7172957361 ps |
| CPU time | 1462.9 seconds |
| Started | Aug 06 08:35:00 PM PDT 24 |
| Finished | Aug 06 08:59:23 PM PDT 24 |
| Peak memory | 611016 kb |
| Host | smart-1be06951-3cbd-487a-b30c-97e575edbe36 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286946488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.4286946488 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.3864053939 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 3157878096 ps |
| CPU time | 779.92 seconds |
| Started | Aug 06 08:35:12 PM PDT 24 |
| Finished | Aug 06 08:48:12 PM PDT 24 |
| Peak memory | 615388 kb |
| Host | smart-85ac54c6-97ac-4fab-8bcf-dd5d44b79a15 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=edn_kat:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864053939 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.3864053939 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.3509739403 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 5804158284 ps |
| CPU time | 1225.35 seconds |
| Started | Aug 06 08:37:02 PM PDT 24 |
| Finished | Aug 06 08:57:28 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-cae1dc58-7466-46ed-a66d-48294f14ec2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509739403 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.3509739403 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2225104553 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 2844134210 ps |
| CPU time | 203.71 seconds |
| Started | Aug 06 08:35:54 PM PDT 24 |
| Finished | Aug 06 08:39:18 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-0d924181-7762-4816-b690-af9321452740 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22 25104553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.2225104553 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.293081367 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 7965026824 ps |
| CPU time | 2106.45 seconds |
| Started | Aug 06 08:36:37 PM PDT 24 |
| Finished | Aug 06 09:11:44 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-8fe1e770-9862-4bbe-9391-d83bd762421e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=293081367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.293081367 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.202718064 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 2931907174 ps |
| CPU time | 251.2 seconds |
| Started | Aug 06 08:34:15 PM PDT 24 |
| Finished | Aug 06 08:38:27 PM PDT 24 |
| Peak memory | 608572 kb |
| Host | smart-a55c7e73-01ee-4442-b7b5-277ed16f63f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202718064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.202718064 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2762680552 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 3861228350 ps |
| CPU time | 526.71 seconds |
| Started | Aug 06 08:41:35 PM PDT 24 |
| Finished | Aug 06 08:50:22 PM PDT 24 |
| Peak memory | 609648 kb |
| Host | smart-968bfed5-fb6f-4bb4-bf94-03db6e98f0c2 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2762680552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.2762680552 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.3543312896 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 3143705778 ps |
| CPU time | 247.24 seconds |
| Started | Aug 06 08:32:23 PM PDT 24 |
| Finished | Aug 06 08:36:31 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-6e75ff1a-ae4d-4117-a133-b2202fc884be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543312896 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.3543312896 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.3551225298 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 3279560040 ps |
| CPU time | 244.07 seconds |
| Started | Aug 06 08:27:38 PM PDT 24 |
| Finished | Aug 06 08:31:42 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-8971d2b6-15c4-4ca3-9aea-862814f42e49 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3551225298 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.3551225298 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.317274810 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 2645521024 ps |
| CPU time | 287.24 seconds |
| Started | Aug 06 08:32:24 PM PDT 24 |
| Finished | Aug 06 08:37:12 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-7d6037e2-31f8-4d86-8b1f-baa3b93748d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317274810 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_example_manufacturer.317274810 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.2402682994 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 2757104648 ps |
| CPU time | 120.04 seconds |
| Started | Aug 06 08:31:15 PM PDT 24 |
| Finished | Aug 06 08:33:16 PM PDT 24 |
| Peak memory | 607900 kb |
| Host | smart-d247b073-435d-47c7-b0c5-6d5fc835eaae |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402682994 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2402682994 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.815034275 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 57740161270 ps |
| CPU time | 11574.7 seconds |
| Started | Aug 06 08:25:56 PM PDT 24 |
| Finished | Aug 06 11:38:53 PM PDT 24 |
| Peak memory | 624828 kb |
| Host | smart-b0886445-404c-4377-a221-7b914d7ccd94 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=815034275 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.815034275 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.4175162800 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 4302649248 ps |
| CPU time | 635.11 seconds |
| Started | Aug 06 08:38:37 PM PDT 24 |
| Finished | Aug 06 08:49:12 PM PDT 24 |
| Peak memory | 611160 kb |
| Host | smart-b705fbd0-1e58-421c-80e1-376955f065ae |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=4175162800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.4175162800 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2184726526 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 5670692476 ps |
| CPU time | 1031.21 seconds |
| Started | Aug 06 08:25:27 PM PDT 24 |
| Finished | Aug 06 08:42:38 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-a5b9824b-91fc-4faf-9993-c1f6c1b605dd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184726526 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.2184726526 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2811716424 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 6108974620 ps |
| CPU time | 1316.25 seconds |
| Started | Aug 06 08:28:25 PM PDT 24 |
| Finished | Aug 06 08:50:22 PM PDT 24 |
| Peak memory | 610044 kb |
| Host | smart-e5204894-d5fd-4298-99e1-3285e7ba5382 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811716424 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.2811716424 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1953991465 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 7141602916 ps |
| CPU time | 1439.22 seconds |
| Started | Aug 06 08:39:10 PM PDT 24 |
| Finished | Aug 06 09:03:10 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-acdcc140-f989-4dce-9824-0dbf39077130 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953991465 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1953991465 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.157183088 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 6257126416 ps |
| CPU time | 1237.16 seconds |
| Started | Aug 06 08:29:42 PM PDT 24 |
| Finished | Aug 06 08:50:19 PM PDT 24 |
| Peak memory | 610084 kb |
| Host | smart-23e13d0b-d7cd-496c-9853-bc00cd1b19a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157183088 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.157183088 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.979979187 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 3108804200 ps |
| CPU time | 299.71 seconds |
| Started | Aug 06 08:27:27 PM PDT 24 |
| Finished | Aug 06 08:32:27 PM PDT 24 |
| Peak memory | 609732 kb |
| Host | smart-dc1b95b6-1048-46aa-8626-d45319187931 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=979979187 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.979979187 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2403705446 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 5051288544 ps |
| CPU time | 583.26 seconds |
| Started | Aug 06 08:30:27 PM PDT 24 |
| Finished | Aug 06 08:40:11 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-96bdac67-a95d-403d-a79a-d78994bfbf5c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24 03705446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.2403705446 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2887982491 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 5529189580 ps |
| CPU time | 1087.73 seconds |
| Started | Aug 06 08:40:55 PM PDT 24 |
| Finished | Aug 06 08:59:03 PM PDT 24 |
| Peak memory | 609876 kb |
| Host | smart-9c1b98fd-ed09-43fd-9ffa-701f860f1c62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887982491 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2887982491 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2395211140 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 3568573220 ps |
| CPU time | 704.95 seconds |
| Started | Aug 06 08:26:48 PM PDT 24 |
| Finished | Aug 06 08:38:33 PM PDT 24 |
| Peak memory | 609864 kb |
| Host | smart-ee4f01c4-0044-41b7-b832-72b5d1d2439e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395211140 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2395211140 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1074089553 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 4340424014 ps |
| CPU time | 782.18 seconds |
| Started | Aug 06 08:40:44 PM PDT 24 |
| Finished | Aug 06 08:53:46 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-e0cd2c03-5c15-43e2-82fe-61380ee956fa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1074089553 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1074089553 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2767052867 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 2988967936 ps |
| CPU time | 372.42 seconds |
| Started | Aug 06 08:39:39 PM PDT 24 |
| Finished | Aug 06 08:45:52 PM PDT 24 |
| Peak memory | 609436 kb |
| Host | smart-e8c34993-2764-436e-b62b-b1130bba09f6 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767052 867 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.2767052867 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.3613866915 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 16056833215 ps |
| CPU time | 1938.68 seconds |
| Started | Aug 06 08:26:28 PM PDT 24 |
| Finished | Aug 06 08:58:47 PM PDT 24 |
| Peak memory | 613508 kb |
| Host | smart-490d5e0a-4883-44af-85ec-ba7d77ccdec2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613866915 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.3613866915 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.144066509 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 19479033510 ps |
| CPU time | 2498.09 seconds |
| Started | Aug 06 08:39:05 PM PDT 24 |
| Finished | Aug 06 09:20:44 PM PDT 24 |
| Peak memory | 611588 kb |
| Host | smart-e296c62d-31fe-45bd-97df-b7ccefbc4a3c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=144066509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.144066509 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1179987255 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 3276636900 ps |
| CPU time | 265.03 seconds |
| Started | Aug 06 08:41:28 PM PDT 24 |
| Finished | Aug 06 08:45:54 PM PDT 24 |
| Peak memory | 609580 kb |
| Host | smart-67ab36bc-c6fd-4011-9640-84d225302a02 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1179987255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1179987255 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.1303053980 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 4197525968 ps |
| CPU time | 482.9 seconds |
| Started | Aug 06 08:24:35 PM PDT 24 |
| Finished | Aug 06 08:32:39 PM PDT 24 |
| Peak memory | 610372 kb |
| Host | smart-7067cc36-b44c-42d3-a0be-0f937513e175 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303053980 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 2.chip_sw_gpio.1303053980 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.1120707453 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 2941723059 ps |
| CPU time | 230.98 seconds |
| Started | Aug 06 08:40:12 PM PDT 24 |
| Finished | Aug 06 08:44:03 PM PDT 24 |
| Peak memory | 609028 kb |
| Host | smart-5d793127-a173-4f8a-aebd-c92a3da1ec48 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1120707453 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.1120707453 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.2261083054 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 3395680700 ps |
| CPU time | 270.95 seconds |
| Started | Aug 06 08:35:19 PM PDT 24 |
| Finished | Aug 06 08:39:50 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-40e84f60-e96f-497e-abef-35a10266a6c5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261083054 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.2261083054 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.2814894503 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 3247590768 ps |
| CPU time | 328.16 seconds |
| Started | Aug 06 08:34:55 PM PDT 24 |
| Finished | Aug 06 08:40:23 PM PDT 24 |
| Peak memory | 609740 kb |
| Host | smart-1c49537e-0723-4c7a-959e-101cbfb59112 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814894503 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_hmac_enc_idle.2814894503 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.866910678 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 2727581987 ps |
| CPU time | 335.9 seconds |
| Started | Aug 06 08:40:24 PM PDT 24 |
| Finished | Aug 06 08:46:00 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-6264c859-5907-4f35-9fbf-b60538906190 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866910678 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.866910678 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2185242330 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 3108042548 ps |
| CPU time | 238.5 seconds |
| Started | Aug 06 08:40:50 PM PDT 24 |
| Finished | Aug 06 08:44:48 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-49ea6236-461a-4e95-96f1-0977a2eb7a50 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185242330 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2185242330 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.957169924 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 7488611348 ps |
| CPU time | 2059.1 seconds |
| Started | Aug 06 08:36:32 PM PDT 24 |
| Finished | Aug 06 09:10:51 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-1d25915e-a661-4df5-83c2-f09b8f6050eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957169924 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_hmac_multistream.957169924 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.2782930632 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 2651173240 ps |
| CPU time | 307.44 seconds |
| Started | Aug 06 08:36:20 PM PDT 24 |
| Finished | Aug 06 08:41:28 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-622464c1-219a-4476-9922-77f06b78500f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782930632 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.2782930632 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.3962831301 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 3176156040 ps |
| CPU time | 457.59 seconds |
| Started | Aug 06 08:39:44 PM PDT 24 |
| Finished | Aug 06 08:47:22 PM PDT 24 |
| Peak memory | 609724 kb |
| Host | smart-e696490e-f721-48fd-aae4-c8a47a1b2924 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962831301 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.3962831301 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.728052810 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 4617556818 ps |
| CPU time | 499.34 seconds |
| Started | Aug 06 08:25:16 PM PDT 24 |
| Finished | Aug 06 08:33:35 PM PDT 24 |
| Peak memory | 609524 kb |
| Host | smart-3eeac696-c0db-4563-a7ea-e418061694b1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728052810 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.728052810 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3512883719 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 5639462960 ps |
| CPU time | 880.89 seconds |
| Started | Aug 06 08:28:16 PM PDT 24 |
| Finished | Aug 06 08:42:58 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-25d2c875-753f-4d12-89e7-e8410bf293fe |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512883719 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.3512883719 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1308484597 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 4606770052 ps |
| CPU time | 751.77 seconds |
| Started | Aug 06 08:27:13 PM PDT 24 |
| Finished | Aug 06 08:39:45 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-0e4d6358-02aa-46e7-9d4a-65c06452ec2c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308484597 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.1308484597 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4139246700 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 4217284784 ps |
| CPU time | 567.99 seconds |
| Started | Aug 06 08:25:19 PM PDT 24 |
| Finished | Aug 06 08:34:47 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-9b1fa46e-ea3f-4a5e-8830-988b17e1bcf6 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4139246700 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.4139246700 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.3583083943 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 66003267989 ps |
| CPU time | 11030.9 seconds |
| Started | Aug 06 08:25:14 PM PDT 24 |
| Finished | Aug 06 11:29:07 PM PDT 24 |
| Peak memory | 624800 kb |
| Host | smart-06e9d814-e3d9-4248-a44d-27b85df0d8f8 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3583083943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.3583083943 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.902186246 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 12871103068 ps |
| CPU time | 3044.08 seconds |
| Started | Aug 06 08:35:32 PM PDT 24 |
| Finished | Aug 06 09:26:17 PM PDT 24 |
| Peak memory | 617860 kb |
| Host | smart-e4fe7610-44b7-4f6c-b047-acc7fc63de3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9021 86246 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.902186246 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.1099350520 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 9016228870 ps |
| CPU time | 1843.85 seconds |
| Started | Aug 06 08:35:13 PM PDT 24 |
| Finished | Aug 06 09:05:57 PM PDT 24 |
| Peak memory | 617888 kb |
| Host | smart-9a9c99bf-db81-4630-a309-a22813f0c843 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1099350520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.1099350520 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3932492281 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 10875481970 ps |
| CPU time | 1471.65 seconds |
| Started | Aug 06 08:38:47 PM PDT 24 |
| Finished | Aug 06 09:03:19 PM PDT 24 |
| Peak memory | 617852 kb |
| Host | smart-581d7b09-98cd-4a2e-b7b5-ceb49efe409f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3932492281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.3932492281 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1369877488 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 9869109480 ps |
| CPU time | 2646.58 seconds |
| Started | Aug 06 08:35:41 PM PDT 24 |
| Finished | Aug 06 09:19:48 PM PDT 24 |
| Peak memory | 617676 kb |
| Host | smart-abecf178-5090-46b6-a7ca-69f82c874b2e |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1369877488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.1369877488 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1640515535 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 11492501880 ps |
| CPU time | 2374.46 seconds |
| Started | Aug 06 08:35:52 PM PDT 24 |
| Finished | Aug 06 09:15:27 PM PDT 24 |
| Peak memory | 610160 kb |
| Host | smart-4b65359a-c089-4358-8f3a-919d33b3ebbf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16405 15535 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.1640515535 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2427354229 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 11850089700 ps |
| CPU time | 2891.69 seconds |
| Started | Aug 06 08:36:59 PM PDT 24 |
| Finished | Aug 06 09:25:11 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-318a1116-1687-4be9-9155-37e63a4d5c82 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24273 54229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2427354229 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.159944786 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 3253497226 ps |
| CPU time | 273.99 seconds |
| Started | Aug 06 08:35:44 PM PDT 24 |
| Finished | Aug 06 08:40:18 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-6244266a-7f92-4fe9-aa7d-99e897e6cd4a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159944786 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.159944786 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.3386625276 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 2714625312 ps |
| CPU time | 275.29 seconds |
| Started | Aug 06 08:24:50 PM PDT 24 |
| Finished | Aug 06 08:29:25 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-eb79ed2f-b37b-4442-9622-247e403d3583 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386625276 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_kmac_entropy.3386625276 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.3056162555 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 2876713184 ps |
| CPU time | 284.02 seconds |
| Started | Aug 06 08:35:39 PM PDT 24 |
| Finished | Aug 06 08:40:23 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-3a217b87-dad6-4b42-afe6-6dfd0ea65ea5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056162555 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.3056162555 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2420988652 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 3524139282 ps |
| CPU time | 310.78 seconds |
| Started | Aug 06 08:35:12 PM PDT 24 |
| Finished | Aug 06 08:40:23 PM PDT 24 |
| Peak memory | 609344 kb |
| Host | smart-f058a595-367b-43a3-89d2-0f1202b20426 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420988652 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2420988652 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2910093557 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 2500452000 ps |
| CPU time | 255.21 seconds |
| Started | Aug 06 08:34:52 PM PDT 24 |
| Finished | Aug 06 08:39:07 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-7eff2a45-6f94-4d4e-a312-b42c6cd43828 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910093557 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_kmac_mode_kmac.2910093557 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.4107507084 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 3047093861 ps |
| CPU time | 364.53 seconds |
| Started | Aug 06 08:36:36 PM PDT 24 |
| Finished | Aug 06 08:42:41 PM PDT 24 |
| Peak memory | 609704 kb |
| Host | smart-94991fe9-318c-44c9-96a2-721a801c49b8 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107507084 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.4107507084 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1776624572 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 3235817265 ps |
| CPU time | 341.93 seconds |
| Started | Aug 06 08:37:41 PM PDT 24 |
| Finished | Aug 06 08:43:23 PM PDT 24 |
| Peak memory | 609784 kb |
| Host | smart-2d1be372-aac1-4ce2-8c29-a3ff2a71aa1e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17766245 72 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1776624572 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2112611884 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 2825971656 ps |
| CPU time | 270.6 seconds |
| Started | Aug 06 08:41:39 PM PDT 24 |
| Finished | Aug 06 08:46:10 PM PDT 24 |
| Peak memory | 609180 kb |
| Host | smart-8da3023e-f354-4dc4-8b6e-3782fd9ba38c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112611884 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2112611884 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.2294290493 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 2313997460 ps |
| CPU time | 305.79 seconds |
| Started | Aug 06 08:29:23 PM PDT 24 |
| Finished | Aug 06 08:34:29 PM PDT 24 |
| Peak memory | 609564 kb |
| Host | smart-ce080a13-9797-4bb8-aa1d-a0e8a0f70dfe |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294290493 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.2294290493 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1182500418 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4290046282 ps |
| CPU time | 602.52 seconds |
| Started | Aug 06 08:39:09 PM PDT 24 |
| Finished | Aug 06 08:49:12 PM PDT 24 |
| Peak memory | 610828 kb |
| Host | smart-b537eee9-3a85-4ae9-9902-f0e7d016058f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1182500418 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1182500418 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2944279696 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 2957338653 ps |
| CPU time | 142.01 seconds |
| Started | Aug 06 08:30:23 PM PDT 24 |
| Finished | Aug 06 08:32:45 PM PDT 24 |
| Peak memory | 620076 kb |
| Host | smart-eff175d8-1ce1-458f-830d-49191ec30dd3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29442796 96 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2944279696 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.6625170 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 12677719857 ps |
| CPU time | 968.87 seconds |
| Started | Aug 06 08:23:11 PM PDT 24 |
| Finished | Aug 06 08:39:21 PM PDT 24 |
| Peak memory | 621392 kb |
| Host | smart-483f4215-3666-45f3-a52c-272a3582169d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6625170 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.6625170 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2656706651 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2418476402 ps |
| CPU time | 137.38 seconds |
| Started | Aug 06 08:28:46 PM PDT 24 |
| Finished | Aug 06 08:31:03 PM PDT 24 |
| Peak memory | 618048 kb |
| Host | smart-5fdc7687-a297-4593-8846-06781b2a0af4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2656706651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.2656706651 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3263800149 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 3043130032 ps |
| CPU time | 139.5 seconds |
| Started | Aug 06 08:37:06 PM PDT 24 |
| Finished | Aug 06 08:39:25 PM PDT 24 |
| Peak memory | 618084 kb |
| Host | smart-30356b8f-e861-40ee-8a13-6f39293dbc26 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263800149 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3263800149 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3693338262 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 47460450380 ps |
| CPU time | 6105.85 seconds |
| Started | Aug 06 08:31:15 PM PDT 24 |
| Finished | Aug 06 10:13:02 PM PDT 24 |
| Peak memory | 620424 kb |
| Host | smart-c1a4a3b9-1494-42d6-b437-3773d773d742 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693338262 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.3693338262 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1342285877 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 49943787380 ps |
| CPU time | 6355.69 seconds |
| Started | Aug 06 08:24:47 PM PDT 24 |
| Finished | Aug 06 10:10:44 PM PDT 24 |
| Peak memory | 620900 kb |
| Host | smart-1d14810b-4dec-4553-bee8-6dd9bb37b040 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342285877 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.1342285877 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2561090584 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 10028369384 ps |
| CPU time | 999.77 seconds |
| Started | Aug 06 08:27:49 PM PDT 24 |
| Finished | Aug 06 08:44:29 PM PDT 24 |
| Peak memory | 620396 kb |
| Host | smart-bbd3c2cc-94d6-4450-98d1-59f927dafcd4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561090584 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.2561090584 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.211113032 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 49256088764 ps |
| CPU time | 5794.03 seconds |
| Started | Aug 06 08:30:04 PM PDT 24 |
| Finished | Aug 06 10:06:39 PM PDT 24 |
| Peak memory | 620392 kb |
| Host | smart-0339a108-1f52-49f6-9365-1b0df943e361 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211113032 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_rma.211113032 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1034860783 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 30634090783 ps |
| CPU time | 2536.59 seconds |
| Started | Aug 06 08:26:10 PM PDT 24 |
| Finished | Aug 06 09:08:27 PM PDT 24 |
| Peak memory | 620272 kb |
| Host | smart-5184a2dd-2d71-4954-b7ac-38b3b68d1241 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1034860783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.1034860783 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2095389933 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 17814999784 ps |
| CPU time | 3306.88 seconds |
| Started | Aug 06 08:32:21 PM PDT 24 |
| Finished | Aug 06 09:27:28 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-6e228185-8574-4ac8-ad03-296dd121da2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2095389933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.2095389933 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3686048344 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 18806300869 ps |
| CPU time | 4141.38 seconds |
| Started | Aug 06 08:33:07 PM PDT 24 |
| Finished | Aug 06 09:42:09 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-2dc25a1b-4880-4373-a315-15259ce410e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3686048344 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.3686048344 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1781401266 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 24898764720 ps |
| CPU time | 4069.94 seconds |
| Started | Aug 06 08:38:16 PM PDT 24 |
| Finished | Aug 06 09:46:06 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-9e89ec2d-af52-4533-8709-3dc55fcbf02f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781401266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1781401266 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.645503374 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 3761323640 ps |
| CPU time | 556.95 seconds |
| Started | Aug 06 08:32:32 PM PDT 24 |
| Finished | Aug 06 08:41:49 PM PDT 24 |
| Peak memory | 609728 kb |
| Host | smart-24eb5fc3-2307-4da9-bcb7-405736e7cb9f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645503374 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.645503374 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.1709250229 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 5922454296 ps |
| CPU time | 988.08 seconds |
| Started | Aug 06 08:31:51 PM PDT 24 |
| Finished | Aug 06 08:48:19 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-e0b26df2-fc72-4056-85e8-7fabd15e3db8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1709250229 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.1709250229 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.2290068796 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 7562516594 ps |
| CPU time | 1431.42 seconds |
| Started | Aug 06 08:39:23 PM PDT 24 |
| Finished | Aug 06 09:03:15 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-4fd11229-3e46-4aef-b09a-0131748bcadf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2290068796 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.2290068796 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3543128785 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 2855195004 ps |
| CPU time | 277.12 seconds |
| Started | Aug 06 08:28:52 PM PDT 24 |
| Finished | Aug 06 08:33:29 PM PDT 24 |
| Peak memory | 609836 kb |
| Host | smart-03c061cb-56c7-44c3-9927-3ad8cf2ac81f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543128785 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.3543128785 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.466063359 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 7427371230 ps |
| CPU time | 935.82 seconds |
| Started | Aug 06 08:23:45 PM PDT 24 |
| Finished | Aug 06 08:39:21 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-d7be5a77-39b0-4ad4-ac13-85b49aec8e7f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=466063359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.466063359 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1784220087 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 7343190740 ps |
| CPU time | 1412.25 seconds |
| Started | Aug 06 08:29:43 PM PDT 24 |
| Finished | Aug 06 08:53:15 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-359080f2-ab10-4e7c-bf7b-c79e69522b48 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1784220087 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1784220087 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.653003861 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 6806723952 ps |
| CPU time | 1053.32 seconds |
| Started | Aug 06 08:23:55 PM PDT 24 |
| Finished | Aug 06 08:41:29 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-fcbbadd7-020f-4e6c-98d4-75c2892b08e3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=653003861 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.653003861 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1025889916 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 4177460460 ps |
| CPU time | 599.03 seconds |
| Started | Aug 06 08:23:23 PM PDT 24 |
| Finished | Aug 06 08:33:22 PM PDT 24 |
| Peak memory | 608420 kb |
| Host | smart-3e4bfbd9-4394-42dd-879b-2e74fa178549 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1025889916 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1025889916 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.400642583 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3552767112 ps |
| CPU time | 384.72 seconds |
| Started | Aug 06 08:41:11 PM PDT 24 |
| Finished | Aug 06 08:47:36 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-1a631ab1-8b5b-4ef9-b34c-9dc7981cf086 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400642583 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.chip_sw_otp_ctrl_smoketest.400642583 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.2064562170 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 2594347320 ps |
| CPU time | 312.22 seconds |
| Started | Aug 06 08:30:13 PM PDT 24 |
| Finished | Aug 06 08:35:26 PM PDT 24 |
| Peak memory | 612344 kb |
| Host | smart-0add9a04-4197-4393-9c2d-fc3720623d6f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064562170 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.2064562170 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.3623803671 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 3161417258 ps |
| CPU time | 232.87 seconds |
| Started | Aug 06 08:37:01 PM PDT 24 |
| Finished | Aug 06 08:40:54 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-f5f9f5f4-3b3f-4e48-8382-e848425bb7f7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623803671 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.3623803671 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.1855788623 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 3624601960 ps |
| CPU time | 669.12 seconds |
| Started | Aug 06 08:40:51 PM PDT 24 |
| Finished | Aug 06 08:52:01 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-adcc23fe-80d6-4243-a65b-1fc827c30ce8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855788623 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1855788623 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.1911475003 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 10835074384 ps |
| CPU time | 868.23 seconds |
| Started | Aug 06 08:38:37 PM PDT 24 |
| Finished | Aug 06 08:53:06 PM PDT 24 |
| Peak memory | 610972 kb |
| Host | smart-d35560eb-773f-4735-89b9-a62e09ffa7bf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911475003 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.1911475003 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.629385357 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 6151374552 ps |
| CPU time | 1557.05 seconds |
| Started | Aug 06 08:43:17 PM PDT 24 |
| Finished | Aug 06 09:09:15 PM PDT 24 |
| Peak memory | 625088 kb |
| Host | smart-c96dd9d1-5f53-4468-9e5f-77d88ccee5cc |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +accelerate_cold_ power_up_time=3 +accelerate_regulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtes t_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=629385357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.629385357 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3776144526 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 12990995652 ps |
| CPU time | 1887.34 seconds |
| Started | Aug 06 08:27:10 PM PDT 24 |
| Finished | Aug 06 08:58:38 PM PDT 24 |
| Peak memory | 611236 kb |
| Host | smart-ed0150de-fbce-4344-a2f8-5a93a07eaf18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776 144526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.3776144526 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1148640433 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 23978321016 ps |
| CPU time | 2010.03 seconds |
| Started | Aug 06 08:41:14 PM PDT 24 |
| Finished | Aug 06 09:14:44 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-11d3ff39-265f-43e5-ae91-56562c45ea3d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114 8640433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.1148640433 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1407358891 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 16456581911 ps |
| CPU time | 1484.57 seconds |
| Started | Aug 06 08:27:06 PM PDT 24 |
| Finished | Aug 06 08:51:51 PM PDT 24 |
| Peak memory | 611564 kb |
| Host | smart-b99a0f3f-5eaa-49ee-a2a6-fb7742fd54a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1407358891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1407358891 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.123632490 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 10135205232 ps |
| CPU time | 641.18 seconds |
| Started | Aug 06 08:28:33 PM PDT 24 |
| Finished | Aug 06 08:39:15 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-50a1c62c-f9b8-4995-ad77-0ff60fa94325 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123632490 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.123632490 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1718523633 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 6680012604 ps |
| CPU time | 385.07 seconds |
| Started | Aug 06 08:30:11 PM PDT 24 |
| Finished | Aug 06 08:36:36 PM PDT 24 |
| Peak memory | 617476 kb |
| Host | smart-5a59f756-b046-4a1c-8110-7ad81f713073 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1718523633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1718523633 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.110747582 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 6688598963 ps |
| CPU time | 562.07 seconds |
| Started | Aug 06 08:29:11 PM PDT 24 |
| Finished | Aug 06 08:38:34 PM PDT 24 |
| Peak memory | 610724 kb |
| Host | smart-b3d6387b-c1d1-40f0-885a-0aab979ffe45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110747582 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.110747582 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.2123656641 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 3975031870 ps |
| CPU time | 378.6 seconds |
| Started | Aug 06 08:37:10 PM PDT 24 |
| Finished | Aug 06 08:43:29 PM PDT 24 |
| Peak memory | 609460 kb |
| Host | smart-5c17b91a-b905-4472-8a6a-11b46d4179ac |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123656641 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.2123656641 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2980641412 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 4118466887 ps |
| CPU time | 386.37 seconds |
| Started | Aug 06 08:26:43 PM PDT 24 |
| Finished | Aug 06 08:33:09 PM PDT 24 |
| Peak memory | 616088 kb |
| Host | smart-6c161753-20ee-4412-88f3-4b97a8611822 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2980641412 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.2980641412 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4055098784 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 11598507575 ps |
| CPU time | 1646.16 seconds |
| Started | Aug 06 08:29:26 PM PDT 24 |
| Finished | Aug 06 08:56:53 PM PDT 24 |
| Peak memory | 611548 kb |
| Host | smart-923f184e-7236-44cb-a8c4-f4a0a2264bd9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055098784 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4055098784 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3814981159 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 7582867152 ps |
| CPU time | 470.05 seconds |
| Started | Aug 06 08:36:41 PM PDT 24 |
| Finished | Aug 06 08:44:31 PM PDT 24 |
| Peak memory | 610664 kb |
| Host | smart-f73c06d8-9e58-42d9-98b1-bc36e90271b7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814981159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3814981159 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1586965633 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 6495069211 ps |
| CPU time | 485.63 seconds |
| Started | Aug 06 08:27:53 PM PDT 24 |
| Finished | Aug 06 08:35:59 PM PDT 24 |
| Peak memory | 610584 kb |
| Host | smart-e99a4d3e-4c2e-4f12-b1af-60532515e840 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586965633 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1586965633 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2529161196 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 22719909244 ps |
| CPU time | 2472.59 seconds |
| Started | Aug 06 08:33:25 PM PDT 24 |
| Finished | Aug 06 09:14:38 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-e49c9579-2ce4-4d1c-8db6-d3f121d2e201 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2529161196 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2529161196 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2277252973 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 21927414140 ps |
| CPU time | 1466.82 seconds |
| Started | Aug 06 08:39:45 PM PDT 24 |
| Finished | Aug 06 09:04:13 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-4e1f71a0-855e-4565-9190-76eb3eb85dd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2277252973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.2277252973 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2370200788 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 38331902212 ps |
| CPU time | 3846.25 seconds |
| Started | Aug 06 08:30:14 PM PDT 24 |
| Finished | Aug 06 09:34:21 PM PDT 24 |
| Peak memory | 612344 kb |
| Host | smart-10c183ad-d485-4fab-91a0-a43d6817cf68 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370200788 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2370200788 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3153378109 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 4707932170 ps |
| CPU time | 344.07 seconds |
| Started | Aug 06 08:38:07 PM PDT 24 |
| Finished | Aug 06 08:43:52 PM PDT 24 |
| Peak memory | 611452 kb |
| Host | smart-24912bd2-f2b7-451d-a3ca-bc975e8724f7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3153378109 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3153378109 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.191035765 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 3800893466 ps |
| CPU time | 283.33 seconds |
| Started | Aug 06 08:28:45 PM PDT 24 |
| Finished | Aug 06 08:33:29 PM PDT 24 |
| Peak memory | 609444 kb |
| Host | smart-d4f810a9-8534-4747-884d-5ebd6f1f2025 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=191035765 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.191035765 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4170924845 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 6504777064 ps |
| CPU time | 375.62 seconds |
| Started | Aug 06 08:32:13 PM PDT 24 |
| Finished | Aug 06 08:38:30 PM PDT 24 |
| Peak memory | 616592 kb |
| Host | smart-76daf5a7-43f7-484f-b208-150bbccd2972 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_power_glitch_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=4170924845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_power_glitch_reset.4170924845 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.774516237 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 5639246560 ps |
| CPU time | 670.34 seconds |
| Started | Aug 06 08:38:05 PM PDT 24 |
| Finished | Aug 06 08:49:16 PM PDT 24 |
| Peak memory | 608760 kb |
| Host | smart-403af0c8-895f-4889-9d64-a7750061b463 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77451623 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.774516237 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.115002219 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 6895482048 ps |
| CPU time | 511.42 seconds |
| Started | Aug 06 08:39:46 PM PDT 24 |
| Finished | Aug 06 08:48:18 PM PDT 24 |
| Peak memory | 610276 kb |
| Host | smart-20af0f29-fe46-4a53-a439-0c3f0e4ec2b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115002219 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.115002219 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1168749553 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 7386726700 ps |
| CPU time | 1085.3 seconds |
| Started | Aug 06 08:27:18 PM PDT 24 |
| Finished | Aug 06 08:45:24 PM PDT 24 |
| Peak memory | 610620 kb |
| Host | smart-016c5556-ca99-4a73-a3d0-bf98f5a037e8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168749553 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.1168749553 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.174041706 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 4879087208 ps |
| CPU time | 390.37 seconds |
| Started | Aug 06 08:32:48 PM PDT 24 |
| Finished | Aug 06 08:39:18 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-a8796135-1970-4469-9c74-24d72780ba12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174041706 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.174041706 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2416186954 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 5091611450 ps |
| CPU time | 399.13 seconds |
| Started | Aug 06 08:42:01 PM PDT 24 |
| Finished | Aug 06 08:48:40 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-dedeca9d-41bd-4503-9a8a-ca64f59c1e79 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416186954 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.2416186954 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2275110422 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 5350441896 ps |
| CPU time | 591.63 seconds |
| Started | Aug 06 08:31:46 PM PDT 24 |
| Finished | Aug 06 08:41:38 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-b418528d-638f-4368-9b4f-543a008963ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227 5110422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2275110422 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3908498031 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 8654172050 ps |
| CPU time | 531.34 seconds |
| Started | Aug 06 08:35:35 PM PDT 24 |
| Finished | Aug 06 08:44:26 PM PDT 24 |
| Peak memory | 624636 kb |
| Host | smart-909e8d8f-69e7-4620-9196-2933b8dcf1e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908498031 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.3908498031 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1483909795 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 11936376000 ps |
| CPU time | 1817.88 seconds |
| Started | Aug 06 08:32:03 PM PDT 24 |
| Finished | Aug 06 09:02:21 PM PDT 24 |
| Peak memory | 610668 kb |
| Host | smart-ff30093c-1cad-444a-955b-0bc95c05e243 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1483909795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.1483909795 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2881166155 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 6283208164 ps |
| CPU time | 512.98 seconds |
| Started | Aug 06 08:26:42 PM PDT 24 |
| Finished | Aug 06 08:35:15 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-da751285-31a4-4225-a84c-2a85e7ac2932 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2881166155 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2881166155 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.362849716 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 4943093400 ps |
| CPU time | 695.12 seconds |
| Started | Aug 06 08:25:18 PM PDT 24 |
| Finished | Aug 06 08:36:54 PM PDT 24 |
| Peak memory | 641552 kb |
| Host | smart-84ce30e5-20e7-443a-9d44-7ca2f133446f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 362849716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.362849716 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.22159243 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 2235613748 ps |
| CPU time | 218.71 seconds |
| Started | Aug 06 08:40:15 PM PDT 24 |
| Finished | Aug 06 08:43:54 PM PDT 24 |
| Peak memory | 609332 kb |
| Host | smart-b0ae73d8-1dfb-4705-810f-3b7516c4cd63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159243 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_rstmgr_smoketest.22159243 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1839871840 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4165521816 ps |
| CPU time | 405.9 seconds |
| Started | Aug 06 08:30:09 PM PDT 24 |
| Finished | Aug 06 08:36:55 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-f7e90629-8ef3-4509-a409-fa277c3443d3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839871840 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.1839871840 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3893070529 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 2501706120 ps |
| CPU time | 202.11 seconds |
| Started | Aug 06 08:25:11 PM PDT 24 |
| Finished | Aug 06 08:28:33 PM PDT 24 |
| Peak memory | 609788 kb |
| Host | smart-95d81e45-f01c-4e0d-9d1b-6887886dbed8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893070529 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.3893070529 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1630561433 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2915206256 ps |
| CPU time | 278.94 seconds |
| Started | Aug 06 08:37:59 PM PDT 24 |
| Finished | Aug 06 08:42:38 PM PDT 24 |
| Peak memory | 608796 kb |
| Host | smart-e226abce-d900-4506-9f35-49887bffabf6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1630561433 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.1630561433 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.4153234654 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3450771902 ps |
| CPU time | 271.41 seconds |
| Started | Aug 06 08:38:30 PM PDT 24 |
| Finished | Aug 06 08:43:02 PM PDT 24 |
| Peak memory | 608804 kb |
| Host | smart-91c3f6c3-10c1-4ec9-939f-7f2153980719 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153234654 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.4153234654 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1422941615 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 3106159632 ps |
| CPU time | 159.71 seconds |
| Started | Aug 06 08:39:32 PM PDT 24 |
| Finished | Aug 06 08:42:11 PM PDT 24 |
| Peak memory | 616776 kb |
| Host | smart-bddb443c-b7b7-4e4b-8319-af7e5d1dfef3 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422941615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.1422941615 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2597101305 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 4731217744 ps |
| CPU time | 1041.88 seconds |
| Started | Aug 06 08:33:38 PM PDT 24 |
| Finished | Aug 06 08:51:00 PM PDT 24 |
| Peak memory | 609488 kb |
| Host | smart-9d5e527c-7eaa-4850-b0b2-bfa22ba57177 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25971 01305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.2597101305 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.1089858808 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 5288651514 ps |
| CPU time | 1048.64 seconds |
| Started | Aug 06 08:33:25 PM PDT 24 |
| Finished | Aug 06 08:50:54 PM PDT 24 |
| Peak memory | 610020 kb |
| Host | smart-c93f8e73-c14a-4226-916e-4c9a15913b2d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1089858808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.1089858808 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.1010495095 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 5597031284 ps |
| CPU time | 514.11 seconds |
| Started | Aug 06 08:37:37 PM PDT 24 |
| Finished | Aug 06 08:46:12 PM PDT 24 |
| Peak memory | 624328 kb |
| Host | smart-a89e863c-84a0-409e-986e-53997c8c9a15 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010495095 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.1010495095 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.2665474460 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 6697394240 ps |
| CPU time | 449.97 seconds |
| Started | Aug 06 08:38:42 PM PDT 24 |
| Finished | Aug 06 08:46:12 PM PDT 24 |
| Peak memory | 620428 kb |
| Host | smart-d767a150-5d7a-40b8-b531-36b8ec9aa2d9 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665474460 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.2665474460 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1548216029 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 4547897540 ps |
| CPU time | 602.84 seconds |
| Started | Aug 06 08:38:51 PM PDT 24 |
| Finished | Aug 06 08:48:54 PM PDT 24 |
| Peak memory | 620068 kb |
| Host | smart-077892b8-d046-49ee-9e97-257de4e000d2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154821 6029 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1548216029 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.754180048 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2847459008 ps |
| CPU time | 181.71 seconds |
| Started | Aug 06 08:40:09 PM PDT 24 |
| Finished | Aug 06 08:43:10 PM PDT 24 |
| Peak memory | 608308 kb |
| Host | smart-14238ada-276e-4c58-ac40-a328cb6c9619 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754180048 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_plic_smoketest.754180048 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.3500199076 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 2761770420 ps |
| CPU time | 214.16 seconds |
| Started | Aug 06 08:28:07 PM PDT 24 |
| Finished | Aug 06 08:31:41 PM PDT 24 |
| Peak memory | 609612 kb |
| Host | smart-3f28e140-b1e2-4d42-a05a-fe7cf44527a1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3500199076 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.3500199076 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2237076876 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2718136944 ps |
| CPU time | 276.79 seconds |
| Started | Aug 06 08:40:15 PM PDT 24 |
| Finished | Aug 06 08:44:52 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-bb3ff1c9-62fa-496b-925b-0b65d9b92717 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237076876 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.2237076876 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.777313312 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 3123664000 ps |
| CPU time | 266.34 seconds |
| Started | Aug 06 08:36:10 PM PDT 24 |
| Finished | Aug 06 08:40:36 PM PDT 24 |
| Peak memory | 610732 kb |
| Host | smart-e3220bd7-a065-4dc4-9346-efbef55164b6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7773133 12 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.777313312 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.806819288 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 3410789444 ps |
| CPU time | 397.82 seconds |
| Started | Aug 06 08:25:05 PM PDT 24 |
| Finished | Aug 06 08:31:43 PM PDT 24 |
| Peak memory | 608928 kb |
| Host | smart-4b6cc66a-6378-41db-9c6e-3679479c0051 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=806819288 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.806819288 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2517146734 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 8779490808 ps |
| CPU time | 1438.06 seconds |
| Started | Aug 06 08:25:43 PM PDT 24 |
| Finished | Aug 06 08:49:41 PM PDT 24 |
| Peak memory | 610836 kb |
| Host | smart-e1a666d6-c0b3-43ec-9e93-6a033d628c04 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517146734 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.2517146734 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.394099036 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 8326713348 ps |
| CPU time | 531.65 seconds |
| Started | Aug 06 08:36:23 PM PDT 24 |
| Finished | Aug 06 08:45:15 PM PDT 24 |
| Peak memory | 610756 kb |
| Host | smart-363aaf6d-78f0-4194-8b11-d5726f056510 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394099036 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sle ep_sram_ret_contents_no_scramble.394099036 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.930937960 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 7781514488 ps |
| CPU time | 950.45 seconds |
| Started | Aug 06 08:35:52 PM PDT 24 |
| Finished | Aug 06 08:51:43 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-4f77693f-5614-42c6-8a9c-2be30db42f85 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=930937960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_ sram_ret_contents_scramble.930937960 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1276939694 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 6658304865 ps |
| CPU time | 833.66 seconds |
| Started | Aug 06 08:27:21 PM PDT 24 |
| Finished | Aug 06 08:41:15 PM PDT 24 |
| Peak memory | 624864 kb |
| Host | smart-1d98b8be-0023-4aef-a32a-e8f700578077 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276939694 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.1276939694 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3738464254 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 4394101431 ps |
| CPU time | 555.21 seconds |
| Started | Aug 06 08:23:35 PM PDT 24 |
| Finished | Aug 06 08:32:51 PM PDT 24 |
| Peak memory | 624500 kb |
| Host | smart-21c7e7cf-6d6b-4362-9b27-168952806730 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3738464254 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through_collision.3738464254 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.2459160676 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 3541558737 ps |
| CPU time | 356.04 seconds |
| Started | Aug 06 08:27:35 PM PDT 24 |
| Finished | Aug 06 08:33:31 PM PDT 24 |
| Peak memory | 615592 kb |
| Host | smart-f0e7142c-739f-4f34-8eca-be096969fcfc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459160676 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.2459160676 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.752745714 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 9613109237 ps |
| CPU time | 609.37 seconds |
| Started | Aug 06 08:35:32 PM PDT 24 |
| Finished | Aug 06 08:45:41 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-56c71be2-1199-4479-8f7d-5752cf9b3fb7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752745714 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.752745714 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.824019963 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 5312855090 ps |
| CPU time | 737.58 seconds |
| Started | Aug 06 08:36:27 PM PDT 24 |
| Finished | Aug 06 08:48:45 PM PDT 24 |
| Peak memory | 611212 kb |
| Host | smart-98615208-0581-422f-8442-d8b72e1590ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824019963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl _scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ sram_ctrl_scrambled_access.824019963 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.362447408 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 3840712778 ps |
| CPU time | 512.34 seconds |
| Started | Aug 06 08:35:25 PM PDT 24 |
| Finished | Aug 06 08:43:58 PM PDT 24 |
| Peak memory | 609624 kb |
| Host | smart-b3788578-3331-4b28-addf-a79e98c72220 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362447408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.362447408 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1199393908 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 5422412170 ps |
| CPU time | 711.32 seconds |
| Started | Aug 06 08:39:46 PM PDT 24 |
| Finished | Aug 06 08:51:38 PM PDT 24 |
| Peak memory | 610928 kb |
| Host | smart-b98cb3ea-3c4c-4ad4-8d7d-e5402c58509a |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199393908 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1199393908 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.2863395427 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2456049200 ps |
| CPU time | 178.3 seconds |
| Started | Aug 06 08:39:54 PM PDT 24 |
| Finished | Aug 06 08:42:53 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-d7572ce2-918c-4ec1-bd3e-fac568012b87 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863395427 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.2863395427 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2175254758 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 4759660107 ps |
| CPU time | 686.46 seconds |
| Started | Aug 06 08:29:08 PM PDT 24 |
| Finished | Aug 06 08:40:37 PM PDT 24 |
| Peak memory | 613564 kb |
| Host | smart-e3ed0f45-d141-4909-9f67-6aab3d7c8000 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175254758 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2175254758 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1244896490 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 3365314441 ps |
| CPU time | 435.82 seconds |
| Started | Aug 06 08:33:04 PM PDT 24 |
| Finished | Aug 06 08:40:21 PM PDT 24 |
| Peak memory | 613172 kb |
| Host | smart-31163f95-849a-4bbd-8cc3-3048bdf5fa8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244896490 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1244896490 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3525676712 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3314830404 ps |
| CPU time | 358.15 seconds |
| Started | Aug 06 08:29:58 PM PDT 24 |
| Finished | Aug 06 08:35:56 PM PDT 24 |
| Peak memory | 610156 kb |
| Host | smart-e4eb0659-1be6-45c8-9ee5-3204b43631af |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525676712 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.3525676712 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.4035983718 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 24136608488 ps |
| CPU time | 1623.46 seconds |
| Started | Aug 06 08:30:00 PM PDT 24 |
| Finished | Aug 06 08:57:04 PM PDT 24 |
| Peak memory | 615268 kb |
| Host | smart-4b3d8e7b-59c3-406e-8165-4d4fe0098dc8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40359837 18 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.4035983718 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2403572918 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5927010040 ps |
| CPU time | 455.52 seconds |
| Started | Aug 06 08:33:14 PM PDT 24 |
| Finished | Aug 06 08:40:49 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-087e14b7-62a2-4c4f-80ca-e9b554b48c8c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403572918 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2403572918 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3270987557 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 4671857016 ps |
| CPU time | 749.92 seconds |
| Started | Aug 06 08:27:55 PM PDT 24 |
| Finished | Aug 06 08:40:25 PM PDT 24 |
| Peak memory | 624488 kb |
| Host | smart-86fe6664-2764-48e9-878c-ca7d8d0b6a70 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3270987557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3270987557 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.194823006 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 3279066976 ps |
| CPU time | 250.18 seconds |
| Started | Aug 06 08:39:36 PM PDT 24 |
| Finished | Aug 06 08:43:47 PM PDT 24 |
| Peak memory | 615100 kb |
| Host | smart-b7a32d4e-8e6e-41b0-be54-50256a30baf0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194823006 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_uart_smoketest.194823006 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.1039316670 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 4200355784 ps |
| CPU time | 635.55 seconds |
| Started | Aug 06 08:25:40 PM PDT 24 |
| Finished | Aug 06 08:36:16 PM PDT 24 |
| Peak memory | 623636 kb |
| Host | smart-aa35a0b3-a904-4393-bc9a-91f495232b46 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1039316670 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.1039316670 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3438406444 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 4211777078 ps |
| CPU time | 477.37 seconds |
| Started | Aug 06 08:25:01 PM PDT 24 |
| Finished | Aug 06 08:32:59 PM PDT 24 |
| Peak memory | 623544 kb |
| Host | smart-53602544-19a5-4af7-a735-c931e4aea79d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438406444 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.3438406444 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2968713602 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 4009619123 ps |
| CPU time | 381.42 seconds |
| Started | Aug 06 08:27:05 PM PDT 24 |
| Finished | Aug 06 08:33:27 PM PDT 24 |
| Peak memory | 623556 kb |
| Host | smart-963cdd25-8a2f-421e-86f1-7e524f996d4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968713602 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2968713602 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.256416255 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 78255614184 ps |
| CPU time | 13083.6 seconds |
| Started | Aug 06 08:24:55 PM PDT 24 |
| Finished | Aug 07 12:03:00 AM PDT 24 |
| Peak memory | 634040 kb |
| Host | smart-0e70ffcd-e09b-4407-9f9b-207e6ef78112 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=256416255 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.256416255 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1617372898 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 3654411936 ps |
| CPU time | 484.7 seconds |
| Started | Aug 06 08:23:54 PM PDT 24 |
| Finished | Aug 06 08:32:00 PM PDT 24 |
| Peak memory | 623932 kb |
| Host | smart-5de17d55-416d-42da-9dd8-9eb500a2c0e5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617372898 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1617372898 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.682290594 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 4395816126 ps |
| CPU time | 493.65 seconds |
| Started | Aug 06 08:24:05 PM PDT 24 |
| Finished | Aug 06 08:32:20 PM PDT 24 |
| Peak memory | 623940 kb |
| Host | smart-0db60aff-1e66-42f6-b7d0-09a2798b3c4e |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=682290594 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.682290594 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.35410362 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 4178959096 ps |
| CPU time | 460.5 seconds |
| Started | Aug 06 08:24:41 PM PDT 24 |
| Finished | Aug 06 08:32:23 PM PDT 24 |
| Peak memory | 623668 kb |
| Host | smart-2b983051-22e1-4844-8220-447484633a4f |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35410362 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.35410362 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.3339360202 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 13086850011 ps |
| CPU time | 1507.66 seconds |
| Started | Aug 06 08:37:12 PM PDT 24 |
| Finished | Aug 06 09:02:20 PM PDT 24 |
| Peak memory | 624500 kb |
| Host | smart-f7f155eb-bf12-40fb-918d-710d9b1880e6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3339360202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.3339360202 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.807785532 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 12959458227 ps |
| CPU time | 1511.53 seconds |
| Started | Aug 06 08:37:08 PM PDT 24 |
| Finished | Aug 06 09:02:21 PM PDT 24 |
| Peak memory | 621016 kb |
| Host | smart-9cb06ba7-0ba2-4a41-8fbb-fac473a3e504 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807785532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.807785532 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.1920024116 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 4307666512 ps |
| CPU time | 515.38 seconds |
| Started | Aug 06 08:37:47 PM PDT 24 |
| Finished | Aug 06 08:46:23 PM PDT 24 |
| Peak memory | 621024 kb |
| Host | smart-07f27c98-07fb-4377-9355-4914cfb8aa6c |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1920024116 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.1920024116 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.2569230054 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 15172265818 ps |
| CPU time | 4185.52 seconds |
| Started | Aug 06 08:42:58 PM PDT 24 |
| Finished | Aug 06 09:52:44 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-51c3d236-cf33-49de-ac4f-728c870c7a0c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569230054 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.2569230054 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.1338538587 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 15292411865 ps |
| CPU time | 3788.58 seconds |
| Started | Aug 06 08:43:41 PM PDT 24 |
| Finished | Aug 06 09:46:50 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-fdf42aca-0b71-4ee8-8e55-b7bd6c36fa6a |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1338538587 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.1338538587 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.717373913 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 15041443940 ps |
| CPU time | 3813.73 seconds |
| Started | Aug 06 08:48:28 PM PDT 24 |
| Finished | Aug 06 09:52:03 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-858b9422-d698-4f60-a4c5-2cfbbce6b12d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717373913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 2.rom_e2e_asm_init_prod_end.717373913 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.414280448 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 14440628443 ps |
| CPU time | 3356.35 seconds |
| Started | Aug 06 08:44:48 PM PDT 24 |
| Finished | Aug 06 09:40:45 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-e8b5142f-6111-4459-88c0-d0572343cbbc |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414280448 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .rom_e2e_asm_init_rma.414280448 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1435213255 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 11165913446 ps |
| CPU time | 3078.96 seconds |
| Started | Aug 06 08:42:39 PM PDT 24 |
| Finished | Aug 06 09:33:59 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-af18bb6b-85d8-4b04-9e0e-4344fec975f3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435213255 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 2.rom_e2e_asm_init_test_unlocked0.1435213255 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.947420230 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 15308520820 ps |
| CPU time | 3557.97 seconds |
| Started | Aug 06 08:45:29 PM PDT 24 |
| Finished | Aug 06 09:44:47 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-038ba69f-8851-497f-a096-eeb46c2cd0fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947420230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_ini t_rom_ext_invalid_meas.947420230 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.943939446 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 14892071870 ps |
| CPU time | 3643.06 seconds |
| Started | Aug 06 08:44:14 PM PDT 24 |
| Finished | Aug 06 09:44:58 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-a031071a-1da2-4212-9d07-ed58c4cb689d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943939446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.943939446 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1445922898 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 15148317802 ps |
| CPU time | 3593.3 seconds |
| Started | Aug 06 08:43:42 PM PDT 24 |
| Finished | Aug 06 09:43:36 PM PDT 24 |
| Peak memory | 609892 kb |
| Host | smart-185c50b8-daaa-4589-bc17-b5d1a9c42639 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445922898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.1445922898 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.3089841410 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 26106789726 ps |
| CPU time | 6844.77 seconds |
| Started | Aug 06 08:45:41 PM PDT 24 |
| Finished | Aug 06 10:39:47 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-c82785ce-a51e-455c-8e5e-2e09620f6f28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089841410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.3089841410 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2668392674 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 14681601616 ps |
| CPU time | 3369.82 seconds |
| Started | Aug 06 08:43:25 PM PDT 24 |
| Finished | Aug 06 09:39:35 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-2316ec9f-34c2-41f1-aaba-7bf006d39e75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2668392674 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.2668392674 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.1927224459 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 23207740575 ps |
| CPU time | 3180.5 seconds |
| Started | Aug 06 08:43:05 PM PDT 24 |
| Finished | Aug 06 09:36:06 PM PDT 24 |
| Peak memory | 611432 kb |
| Host | smart-b5c0feb4-00a4-464a-84e4-690274b8c1c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927224459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.1927224459 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.390125613 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 15403035430 ps |
| CPU time | 4213.11 seconds |
| Started | Aug 06 08:43:20 PM PDT 24 |
| Finished | Aug 06 09:53:35 PM PDT 24 |
| Peak memory | 610052 kb |
| Host | smart-b1cd420b-2a05-453d-b211-f87cddf00ec9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=390125613 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.390125613 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.2864328182 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 17033206280 ps |
| CPU time | 3710.68 seconds |
| Started | Aug 06 08:45:42 PM PDT 24 |
| Finished | Aug 06 09:47:33 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-4d4923f1-257c-4c13-a1e2-141ab0595337 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864328182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.2864328182 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3292223737 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 3671209152 ps |
| CPU time | 549.5 seconds |
| Started | Aug 06 08:38:59 PM PDT 24 |
| Finished | Aug 06 08:48:09 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-79ce7ebe-52c4-4b9c-90bf-79f0f72abb12 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292223737 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3292223737 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.3332292722 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 6419405109 ps |
| CPU time | 272.08 seconds |
| Started | Aug 06 08:43:07 PM PDT 24 |
| Finished | Aug 06 08:47:40 PM PDT 24 |
| Peak memory | 619808 kb |
| Host | smart-f650e5b7-b240-4845-9d8b-f7f08a949eac |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3332292722 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.3332292722 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.2110433507 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 1954403113 ps |
| CPU time | 104.3 seconds |
| Started | Aug 06 08:39:14 PM PDT 24 |
| Finished | Aug 06 08:40:59 PM PDT 24 |
| Peak memory | 616988 kb |
| Host | smart-c6b45c25-b886-4f43-a507-779370b96863 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110433507 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.2110433507 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2186880582 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 4224633032 ps |
| CPU time | 478.64 seconds |
| Started | Aug 06 08:42:44 PM PDT 24 |
| Finished | Aug 06 08:50:43 PM PDT 24 |
| Peak memory | 649060 kb |
| Host | smart-3e72cc0e-26a9-4ca5-9146-2e3755d2a5fb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2186880582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2186880582 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.1318762167 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 5578642488 ps |
| CPU time | 617.73 seconds |
| Started | Aug 06 08:42:56 PM PDT 24 |
| Finished | Aug 06 08:53:14 PM PDT 24 |
| Peak memory | 649744 kb |
| Host | smart-3fdc1496-6dba-4298-bb62-3d7c02954bb1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1318762167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.1318762167 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452463327 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 4150700084 ps |
| CPU time | 331.4 seconds |
| Started | Aug 06 08:43:58 PM PDT 24 |
| Finished | Aug 06 08:49:30 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-6471c67a-1279-434a-bc3d-236e56677eab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452463327 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2452463327 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1356882015 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 3256052640 ps |
| CPU time | 432.77 seconds |
| Started | Aug 06 08:44:44 PM PDT 24 |
| Finished | Aug 06 08:51:57 PM PDT 24 |
| Peak memory | 648796 kb |
| Host | smart-314d1c50-4e37-445b-97a3-ccc84133e8a2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356882015 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1356882015 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.3037791985 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 4568438964 ps |
| CPU time | 794.82 seconds |
| Started | Aug 06 08:45:50 PM PDT 24 |
| Finished | Aug 06 08:59:05 PM PDT 24 |
| Peak memory | 649956 kb |
| Host | smart-38729e5d-76c2-46e6-9350-65e732e65f32 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3037791985 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.3037791985 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.2363412973 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5931195000 ps |
| CPU time | 615.8 seconds |
| Started | Aug 06 08:44:47 PM PDT 24 |
| Finished | Aug 06 08:55:03 PM PDT 24 |
| Peak memory | 650000 kb |
| Host | smart-b0467429-339f-450b-9b60-cf61a7ec26f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2363412973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.2363412973 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.1978396272 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 4711758200 ps |
| CPU time | 782.25 seconds |
| Started | Aug 06 08:42:59 PM PDT 24 |
| Finished | Aug 06 08:56:02 PM PDT 24 |
| Peak memory | 649812 kb |
| Host | smart-95d9b9fd-0810-4dad-9244-e74810426442 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1978396272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.1978396272 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3200841646 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 4873802010 ps |
| CPU time | 739.31 seconds |
| Started | Aug 06 08:43:17 PM PDT 24 |
| Finished | Aug 06 08:55:36 PM PDT 24 |
| Peak memory | 649980 kb |
| Host | smart-375252a5-b98a-44cb-8482-6fc78e23f393 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3200841646 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3200841646 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.259983541 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 6651952616 ps |
| CPU time | 526.02 seconds |
| Started | Aug 06 08:40:13 PM PDT 24 |
| Finished | Aug 06 08:49:00 PM PDT 24 |
| Peak memory | 610444 kb |
| Host | smart-70107ca3-effc-4b1e-bb56-a21defdb5455 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=259983541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.259983541 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4294562677 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 20481808208 ps |
| CPU time | 5102.05 seconds |
| Started | Aug 06 08:40:40 PM PDT 24 |
| Finished | Aug 06 10:05:43 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-ed5ac7fe-de12-4654-bcc4-02fc7fbb2c76 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4294562677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.4294562677 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3416166435 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 5272915428 ps |
| CPU time | 786.41 seconds |
| Started | Aug 06 08:40:35 PM PDT 24 |
| Finished | Aug 06 08:53:42 PM PDT 24 |
| Peak memory | 610800 kb |
| Host | smart-02f2f41b-6d2a-4d8b-aedc-5ebaaf5dad28 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3416166435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.3416166435 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2370204796 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 6432975431 ps |
| CPU time | 547.06 seconds |
| Started | Aug 06 08:42:56 PM PDT 24 |
| Finished | Aug 06 08:52:04 PM PDT 24 |
| Peak memory | 620420 kb |
| Host | smart-ac7624f1-1400-4df5-b72b-444e21caef88 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370204796 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.2370204796 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1902147245 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4325077440 ps |
| CPU time | 536.58 seconds |
| Started | Aug 06 08:40:12 PM PDT 24 |
| Finished | Aug 06 08:49:09 PM PDT 24 |
| Peak memory | 609496 kb |
| Host | smart-5598a8d2-7c64-49f1-aa34-3024dfe9c758 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19021472 45 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.1902147245 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3285129561 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 8043266884 ps |
| CPU time | 1255.9 seconds |
| Started | Aug 06 08:40:36 PM PDT 24 |
| Finished | Aug 06 09:01:33 PM PDT 24 |
| Peak memory | 624436 kb |
| Host | smart-cecbc8ed-5faa-4ec2-a0b8-ece7c037b9ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3285129561 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3285129561 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.558518421 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 4742463068 ps |
| CPU time | 884.36 seconds |
| Started | Aug 06 08:41:49 PM PDT 24 |
| Finished | Aug 06 08:56:35 PM PDT 24 |
| Peak memory | 624192 kb |
| Host | smart-37a45e4a-829d-4fa6-b5a3-4179d3aa4f08 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558518421 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.558518421 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2760038820 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 7609841458 ps |
| CPU time | 1586.19 seconds |
| Started | Aug 06 08:40:52 PM PDT 24 |
| Finished | Aug 06 09:07:19 PM PDT 24 |
| Peak memory | 624588 kb |
| Host | smart-99272adc-5832-4898-9e01-43a7444c707e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760038820 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq.2760038820 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1358377840 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 4676149808 ps |
| CPU time | 566.69 seconds |
| Started | Aug 06 08:39:42 PM PDT 24 |
| Finished | Aug 06 08:49:09 PM PDT 24 |
| Peak memory | 623628 kb |
| Host | smart-64acd222-2c97-4404-ace9-ff7f74bcfd09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358377840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1358377840 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2155797998 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4189751600 ps |
| CPU time | 437.76 seconds |
| Started | Aug 06 08:40:51 PM PDT 24 |
| Finished | Aug 06 08:48:09 PM PDT 24 |
| Peak memory | 622860 kb |
| Host | smart-f8c0e6a2-1bd6-4412-8438-8be37895afdb |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155797998 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.2155797998 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1047375500 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 4045569212 ps |
| CPU time | 733.3 seconds |
| Started | Aug 06 08:40:44 PM PDT 24 |
| Finished | Aug 06 08:52:58 PM PDT 24 |
| Peak memory | 623932 kb |
| Host | smart-249e816e-b450-4087-a1c9-562e8145827d |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047375500 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1047375500 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1598672547 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 4728018540 ps |
| CPU time | 869.4 seconds |
| Started | Aug 06 08:39:42 PM PDT 24 |
| Finished | Aug 06 08:54:11 PM PDT 24 |
| Peak memory | 624208 kb |
| Host | smart-6dfb9a0c-0f50-47cb-bdea-406e4135d3ad |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598672547 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.1598672547 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.3591767047 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 15375240845 ps |
| CPU time | 1544.77 seconds |
| Started | Aug 06 08:40:10 PM PDT 24 |
| Finished | Aug 06 09:05:55 PM PDT 24 |
| Peak memory | 620992 kb |
| Host | smart-cecddb36-3bf4-468a-b6fb-c2d21198b011 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3591767047 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.3591767047 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.3931366151 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3145154977 ps |
| CPU time | 134.27 seconds |
| Started | Aug 06 08:40:04 PM PDT 24 |
| Finished | Aug 06 08:42:19 PM PDT 24 |
| Peak memory | 622332 kb |
| Host | smart-4db866ef-31f6-4837-afc0-7a7bd3dc1552 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931366151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.3931366151 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.1818977210 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 2791288707 ps |
| CPU time | 155.73 seconds |
| Started | Aug 06 08:39:22 PM PDT 24 |
| Finished | Aug 06 08:41:58 PM PDT 24 |
| Peak memory | 632376 kb |
| Host | smart-6ea47d61-e68a-4592-903b-16f6a17787bb |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818977210 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.1818977210 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283176724 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 4017511582 ps |
| CPU time | 450.42 seconds |
| Started | Aug 06 08:41:52 PM PDT 24 |
| Finished | Aug 06 08:49:22 PM PDT 24 |
| Peak memory | 648480 kb |
| Host | smart-531d202a-9d72-44fe-9dc9-0575dbaea4cd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283176724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2283176724 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.1614194008 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 5816608306 ps |
| CPU time | 607.46 seconds |
| Started | Aug 06 08:44:23 PM PDT 24 |
| Finished | Aug 06 08:54:31 PM PDT 24 |
| Peak memory | 649884 kb |
| Host | smart-6752df17-b3fd-485e-a677-1afaff9bd16c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1614194008 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.1614194008 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.951945325 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 4461196712 ps |
| CPU time | 446.07 seconds |
| Started | Aug 06 08:47:10 PM PDT 24 |
| Finished | Aug 06 08:54:36 PM PDT 24 |
| Peak memory | 648948 kb |
| Host | smart-d4055de9-d32d-42b6-b668-379e14b5faee |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951945325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_s w_alert_handler_lpg_sleep_mode_alerts.951945325 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.529482299 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 5027436400 ps |
| CPU time | 742.33 seconds |
| Started | Aug 06 08:43:57 PM PDT 24 |
| Finished | Aug 06 08:56:21 PM PDT 24 |
| Peak memory | 649596 kb |
| Host | smart-d95a3838-8f72-4e63-9d73-912a04a90e2b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 529482299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.529482299 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2103127686 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 4208792688 ps |
| CPU time | 442.26 seconds |
| Started | Aug 06 08:46:18 PM PDT 24 |
| Finished | Aug 06 08:53:41 PM PDT 24 |
| Peak memory | 648804 kb |
| Host | smart-86a269bd-4f29-4833-8b75-424306e0f940 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103127686 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2103127686 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.3262312202 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 4342537240 ps |
| CPU time | 554.3 seconds |
| Started | Aug 06 08:43:46 PM PDT 24 |
| Finished | Aug 06 08:53:01 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-acc4cc4b-46f2-4e4e-acb2-53e38e317f8c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3262312202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.3262312202 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989469380 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 3123118400 ps |
| CPU time | 435.36 seconds |
| Started | Aug 06 08:51:04 PM PDT 24 |
| Finished | Aug 06 08:58:19 PM PDT 24 |
| Peak memory | 648764 kb |
| Host | smart-3995c6b5-c9c4-4505-be0f-243955359665 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989469380 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3989469380 |
| Directory | /workspace/38.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.3732672307 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 4865053240 ps |
| CPU time | 703.03 seconds |
| Started | Aug 06 08:45:29 PM PDT 24 |
| Finished | Aug 06 08:57:12 PM PDT 24 |
| Peak memory | 649904 kb |
| Host | smart-d8e23e1e-c5dd-4173-ac98-3a28acafa6d5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3732672307 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.3732672307 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452137800 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 3450888294 ps |
| CPU time | 582.31 seconds |
| Started | Aug 06 08:43:25 PM PDT 24 |
| Finished | Aug 06 08:53:07 PM PDT 24 |
| Peak memory | 649028 kb |
| Host | smart-4dadac25-9456-43cf-a433-3a3a87885d15 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452137800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2452137800 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.1466961912 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 4802056264 ps |
| CPU time | 589.15 seconds |
| Started | Aug 06 08:43:15 PM PDT 24 |
| Finished | Aug 06 08:53:04 PM PDT 24 |
| Peak memory | 649808 kb |
| Host | smart-67b115ba-1e11-4058-867e-5ec47e1a6e86 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1466961912 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.1466961912 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1318776595 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3339612086 ps |
| CPU time | 490.71 seconds |
| Started | Aug 06 08:41:26 PM PDT 24 |
| Finished | Aug 06 08:49:37 PM PDT 24 |
| Peak memory | 649140 kb |
| Host | smart-87035286-a50d-4084-8e66-1b85885232aa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318776595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.1318776595 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2896397464 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 6705860000 ps |
| CPU time | 600 seconds |
| Started | Aug 06 08:40:11 PM PDT 24 |
| Finished | Aug 06 08:50:11 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-9a34e614-49ca-4f1d-bb53-214689e6fc68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2896397464 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2896397464 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.995895477 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 22044206680 ps |
| CPU time | 4549.14 seconds |
| Started | Aug 06 08:40:41 PM PDT 24 |
| Finished | Aug 06 09:56:31 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-3eb0b145-ff56-4cf3-9d2b-54cc4711186c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995895477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.995895477 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2236395314 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 6377989000 ps |
| CPU time | 778 seconds |
| Started | Aug 06 08:42:08 PM PDT 24 |
| Finished | Aug 06 08:55:07 PM PDT 24 |
| Peak memory | 611172 kb |
| Host | smart-72925b68-772d-4f68-95eb-20c140463783 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2236395314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.2236395314 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.1612690455 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 6273052078 ps |
| CPU time | 538.8 seconds |
| Started | Aug 06 08:40:02 PM PDT 24 |
| Finished | Aug 06 08:49:02 PM PDT 24 |
| Peak memory | 621456 kb |
| Host | smart-2966d9a5-23a1-4e51-b5fa-d47d12cc4386 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612690455 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.1612690455 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.148318204 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 8518614950 ps |
| CPU time | 766.49 seconds |
| Started | Aug 06 08:40:48 PM PDT 24 |
| Finished | Aug 06 08:53:34 PM PDT 24 |
| Peak memory | 610296 kb |
| Host | smart-186d6eb6-63f7-4e77-9603-186b07d1785e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14831820 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.148318204 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4049131098 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 8058564832 ps |
| CPU time | 1559.76 seconds |
| Started | Aug 06 08:42:30 PM PDT 24 |
| Finished | Aug 06 09:08:30 PM PDT 24 |
| Peak memory | 624484 kb |
| Host | smart-8fa2dc34-7320-4d77-804c-f15e65205a4e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4049131098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.4049131098 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.628727410 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 4547079480 ps |
| CPU time | 664.97 seconds |
| Started | Aug 06 08:40:42 PM PDT 24 |
| Finished | Aug 06 08:51:48 PM PDT 24 |
| Peak memory | 624180 kb |
| Host | smart-c5d17d89-4735-45fb-9462-6bde81f9d2dd |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628727410 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.628727410 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3236169169 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 8443819198 ps |
| CPU time | 1760.61 seconds |
| Started | Aug 06 08:40:22 PM PDT 24 |
| Finished | Aug 06 09:09:43 PM PDT 24 |
| Peak memory | 618800 kb |
| Host | smart-51a1d16d-5580-4461-9bba-1c6472f9613f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236169169 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.3236169169 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2762918583 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4403959832 ps |
| CPU time | 870.15 seconds |
| Started | Aug 06 08:40:22 PM PDT 24 |
| Finished | Aug 06 08:54:53 PM PDT 24 |
| Peak memory | 623924 kb |
| Host | smart-a7c9a1f4-a8ed-4050-9b34-4212059366fd |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762918583 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.2762918583 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.4125542880 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 4156309500 ps |
| CPU time | 873.63 seconds |
| Started | Aug 06 08:40:31 PM PDT 24 |
| Finished | Aug 06 08:55:05 PM PDT 24 |
| Peak memory | 623852 kb |
| Host | smart-361571c2-d251-46e8-875c-4a46c02864e1 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125542880 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.4125542880 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1145481536 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 4238563944 ps |
| CPU time | 753.6 seconds |
| Started | Aug 06 08:42:02 PM PDT 24 |
| Finished | Aug 06 08:54:36 PM PDT 24 |
| Peak memory | 624012 kb |
| Host | smart-dcffa517-60b4-4e25-af7b-6471616d04c6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145481536 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.1145481536 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.2528481625 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 3027819433 ps |
| CPU time | 206.58 seconds |
| Started | Aug 06 08:40:23 PM PDT 24 |
| Finished | Aug 06 08:43:49 PM PDT 24 |
| Peak memory | 622024 kb |
| Host | smart-ac8be7d8-b569-431a-b889-eda40fcef0a7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2528481625 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.2528481625 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.2481515477 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 8393755101 ps |
| CPU time | 1107.02 seconds |
| Started | Aug 06 08:41:11 PM PDT 24 |
| Finished | Aug 06 08:59:38 PM PDT 24 |
| Peak memory | 624556 kb |
| Host | smart-5c0f3f95-d02a-4f0b-ae38-45af48c5c4d4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481515477 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.2481515477 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.1366449004 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 4191966779 ps |
| CPU time | 431.65 seconds |
| Started | Aug 06 08:41:10 PM PDT 24 |
| Finished | Aug 06 08:48:21 PM PDT 24 |
| Peak memory | 624904 kb |
| Host | smart-56c887fd-49f7-4d11-88ab-0aed5f591f7b |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366449004 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.1366449004 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.1654945808 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3393162449 ps |
| CPU time | 412.88 seconds |
| Started | Aug 06 08:40:06 PM PDT 24 |
| Finished | Aug 06 08:46:59 PM PDT 24 |
| Peak memory | 632580 kb |
| Host | smart-9993b0aa-a9da-4755-9e5a-0be1c757651c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1654945808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.1654945808 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.3251961434 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 4480246948 ps |
| CPU time | 728.78 seconds |
| Started | Aug 06 08:44:39 PM PDT 24 |
| Finished | Aug 06 08:56:48 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-75a4e867-e725-44df-9990-5d6151c75f6b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3251961434 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.3251961434 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.4120324400 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 4946854096 ps |
| CPU time | 618.97 seconds |
| Started | Aug 06 08:45:00 PM PDT 24 |
| Finished | Aug 06 08:55:19 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-7c39a8df-9ffc-4f35-be4e-82ffcc3b5fc6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4120324400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.4120324400 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.4070856526 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4917677580 ps |
| CPU time | 678.94 seconds |
| Started | Aug 06 08:44:40 PM PDT 24 |
| Finished | Aug 06 08:55:59 PM PDT 24 |
| Peak memory | 650500 kb |
| Host | smart-e3387528-2c7d-4fdd-a6a0-f23217ddbdb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4070856526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.4070856526 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1534460939 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 3654531264 ps |
| CPU time | 403.62 seconds |
| Started | Aug 06 08:48:28 PM PDT 24 |
| Finished | Aug 06 08:55:13 PM PDT 24 |
| Peak memory | 648344 kb |
| Host | smart-48346acc-6c17-4d6d-9c82-372290575a08 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534460939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1534460939 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.624085771 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 5554848652 ps |
| CPU time | 618.41 seconds |
| Started | Aug 06 08:44:25 PM PDT 24 |
| Finished | Aug 06 08:54:44 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-66126323-8652-47bc-aadc-7caebf6c2ba7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 624085771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.624085771 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.860435786 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 4750467852 ps |
| CPU time | 550.15 seconds |
| Started | Aug 06 08:51:35 PM PDT 24 |
| Finished | Aug 06 09:00:46 PM PDT 24 |
| Peak memory | 650092 kb |
| Host | smart-c4cd6a51-e07c-4002-b952-33d33fa751ef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 860435786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.860435786 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.2214800277 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3622151902 ps |
| CPU time | 401.26 seconds |
| Started | Aug 06 08:45:01 PM PDT 24 |
| Finished | Aug 06 08:51:42 PM PDT 24 |
| Peak memory | 648636 kb |
| Host | smart-97fce5c5-e2b1-4294-879f-0f450e4ddb50 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214800277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2214800277 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.3927617960 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 6178532080 ps |
| CPU time | 641.87 seconds |
| Started | Aug 06 08:48:55 PM PDT 24 |
| Finished | Aug 06 08:59:37 PM PDT 24 |
| Peak memory | 650164 kb |
| Host | smart-36e088fb-29d2-4c37-bbd0-897bdcf7c3d8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3927617960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.3927617960 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2631390493 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 5508390350 ps |
| CPU time | 667.24 seconds |
| Started | Aug 06 08:44:26 PM PDT 24 |
| Finished | Aug 06 08:55:34 PM PDT 24 |
| Peak memory | 619800 kb |
| Host | smart-bc02cf83-21a5-4f7d-adc9-f26ff045c71b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2631390493 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2631390493 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3070344980 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 3996712840 ps |
| CPU time | 429.02 seconds |
| Started | Aug 06 08:44:22 PM PDT 24 |
| Finished | Aug 06 08:51:31 PM PDT 24 |
| Peak memory | 648688 kb |
| Host | smart-a9de9ae6-1e74-478b-ba8e-edabd8f98c92 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070344980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3070344980 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.4081977410 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 6013135080 ps |
| CPU time | 744 seconds |
| Started | Aug 06 08:43:53 PM PDT 24 |
| Finished | Aug 06 08:56:17 PM PDT 24 |
| Peak memory | 650072 kb |
| Host | smart-f0cdbf94-db85-45fd-90cf-f72122313a9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4081977410 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.4081977410 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.105439193 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3524020960 ps |
| CPU time | 464.23 seconds |
| Started | Aug 06 08:41:20 PM PDT 24 |
| Finished | Aug 06 08:49:05 PM PDT 24 |
| Peak memory | 648620 kb |
| Host | smart-cfbeb2ba-e0a3-498a-8117-5aca1a776f32 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105439193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.105439193 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2320172633 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 4504364000 ps |
| CPU time | 772.01 seconds |
| Started | Aug 06 08:44:49 PM PDT 24 |
| Finished | Aug 06 08:57:43 PM PDT 24 |
| Peak memory | 649816 kb |
| Host | smart-71fe4406-9e09-4ca3-8572-cf1c1f1e25c8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2320172633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2320172633 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.346941422 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 25210543856 ps |
| CPU time | 6189.95 seconds |
| Started | Aug 06 08:42:21 PM PDT 24 |
| Finished | Aug 06 10:25:31 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-e0555f56-babc-4c6e-bfe3-c18eba276f3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346941422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.346941422 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.76008848 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 5307440750 ps |
| CPU time | 683.87 seconds |
| Started | Aug 06 08:40:27 PM PDT 24 |
| Finished | Aug 06 08:51:52 PM PDT 24 |
| Peak memory | 610860 kb |
| Host | smart-4c22d616-c26d-4c43-aa0c-5ac61701e5d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=76008848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.76008848 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4132535763 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 9375412554 ps |
| CPU time | 923.37 seconds |
| Started | Aug 06 08:41:01 PM PDT 24 |
| Finished | Aug 06 08:56:24 PM PDT 24 |
| Peak memory | 621192 kb |
| Host | smart-64ae7a42-6e04-4a63-a54f-d26f60220f0f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132535763 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.4132535763 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3177335610 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 4927294352 ps |
| CPU time | 584.32 seconds |
| Started | Aug 06 08:42:00 PM PDT 24 |
| Finished | Aug 06 08:51:45 PM PDT 24 |
| Peak memory | 623292 kb |
| Host | smart-bef766f7-32ec-43dc-b4ef-954887597067 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3177335610 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3177335610 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2386104095 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 3892994846 ps |
| CPU time | 345.08 seconds |
| Started | Aug 06 08:49:52 PM PDT 24 |
| Finished | Aug 06 08:55:37 PM PDT 24 |
| Peak memory | 648704 kb |
| Host | smart-e51f3c58-7584-430b-baf3-c3b3cd6fa8fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386104095 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2386104095 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.742756913 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 5401104280 ps |
| CPU time | 722.05 seconds |
| Started | Aug 06 08:45:28 PM PDT 24 |
| Finished | Aug 06 08:57:30 PM PDT 24 |
| Peak memory | 649572 kb |
| Host | smart-5c0fd8b2-3a2e-419c-b50e-ab2e84ae382e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 742756913 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.742756913 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.3167560117 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 5386658040 ps |
| CPU time | 608.24 seconds |
| Started | Aug 06 08:44:03 PM PDT 24 |
| Finished | Aug 06 08:54:12 PM PDT 24 |
| Peak memory | 649960 kb |
| Host | smart-84d5ad7a-bbe9-4f5a-b304-d1a90f4118ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3167560117 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.3167560117 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.401179603 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 3944704400 ps |
| CPU time | 436.58 seconds |
| Started | Aug 06 08:44:55 PM PDT 24 |
| Finished | Aug 06 08:52:12 PM PDT 24 |
| Peak memory | 648848 kb |
| Host | smart-0ee4a482-9772-4623-afa6-1475d3869a01 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401179603 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_s w_alert_handler_lpg_sleep_mode_alerts.401179603 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/53.chip_sw_all_escalation_resets.2377178089 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 6033313788 ps |
| CPU time | 653.24 seconds |
| Started | Aug 06 08:43:50 PM PDT 24 |
| Finished | Aug 06 08:54:43 PM PDT 24 |
| Peak memory | 649620 kb |
| Host | smart-d076fd3a-d46f-46e4-9dc4-c63cc7bad616 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2377178089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_sw_all_escalation_resets.2377178089 |
| Directory | /workspace/53.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2522110248 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 4161975076 ps |
| CPU time | 472.15 seconds |
| Started | Aug 06 08:44:32 PM PDT 24 |
| Finished | Aug 06 08:52:25 PM PDT 24 |
| Peak memory | 648436 kb |
| Host | smart-0f9a0b45-4095-4376-88db-4ac0a21135d8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522110248 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2522110248 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.448048200 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 4535729150 ps |
| CPU time | 544.13 seconds |
| Started | Aug 06 08:49:48 PM PDT 24 |
| Finished | Aug 06 08:58:52 PM PDT 24 |
| Peak memory | 649772 kb |
| Host | smart-855a3b4a-13c8-47a8-961e-96b77fd5751f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 448048200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.448048200 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1400359385 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 3306050148 ps |
| CPU time | 407.17 seconds |
| Started | Aug 06 08:44:35 PM PDT 24 |
| Finished | Aug 06 08:51:23 PM PDT 24 |
| Peak memory | 649248 kb |
| Host | smart-9c30c742-540e-4cad-9880-318e4a30989e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400359385 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1400359385 |
| Directory | /workspace/55.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.4258400438 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 4208974704 ps |
| CPU time | 619.22 seconds |
| Started | Aug 06 08:45:01 PM PDT 24 |
| Finished | Aug 06 08:55:20 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-71879d8b-6936-4bb5-ac73-c52be87fbd04 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4258400438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.4258400438 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940371085 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 4140656640 ps |
| CPU time | 463.96 seconds |
| Started | Aug 06 08:45:31 PM PDT 24 |
| Finished | Aug 06 08:53:15 PM PDT 24 |
| Peak memory | 648372 kb |
| Host | smart-66363a2c-f454-4771-9940-4416b08fa162 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940371085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3940371085 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3793124626 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 4040998600 ps |
| CPU time | 489.83 seconds |
| Started | Aug 06 08:45:00 PM PDT 24 |
| Finished | Aug 06 08:53:10 PM PDT 24 |
| Peak memory | 648524 kb |
| Host | smart-c5dcc50d-da62-44a8-abd2-4e896829c131 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793124626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3793124626 |
| Directory | /workspace/57.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.3109428296 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 4971065850 ps |
| CPU time | 639.29 seconds |
| Started | Aug 06 08:45:01 PM PDT 24 |
| Finished | Aug 06 08:55:40 PM PDT 24 |
| Peak memory | 649824 kb |
| Host | smart-3c5651af-1d64-4b3a-b1d8-ba2de3ad1f08 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3109428296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.3109428296 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1965791899 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 3909321000 ps |
| CPU time | 489.08 seconds |
| Started | Aug 06 08:45:29 PM PDT 24 |
| Finished | Aug 06 08:53:38 PM PDT 24 |
| Peak memory | 648712 kb |
| Host | smart-ce9ba085-737d-4f32-963a-ccf0f2228dbf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965791899 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1965791899 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.289183388 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 3562883142 ps |
| CPU time | 526.82 seconds |
| Started | Aug 06 08:42:38 PM PDT 24 |
| Finished | Aug 06 08:51:26 PM PDT 24 |
| Peak memory | 648484 kb |
| Host | smart-269a6224-a2a9-4b2c-bc59-1552b7140326 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289183388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.289183388 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1138849854 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 15639143486 ps |
| CPU time | 3587.1 seconds |
| Started | Aug 06 08:42:23 PM PDT 24 |
| Finished | Aug 06 09:42:11 PM PDT 24 |
| Peak memory | 610368 kb |
| Host | smart-648f7dd7-2d34-4194-aa04-f23361f9359b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138849854 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.1138849854 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2037197971 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 7001537259 ps |
| CPU time | 515.63 seconds |
| Started | Aug 06 08:41:49 PM PDT 24 |
| Finished | Aug 06 08:50:25 PM PDT 24 |
| Peak memory | 622492 kb |
| Host | smart-67c9569a-9e73-49b1-8473-99623340e99d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037197971 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.2037197971 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.580988280 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 13625020400 ps |
| CPU time | 2744.75 seconds |
| Started | Aug 06 08:41:56 PM PDT 24 |
| Finished | Aug 06 09:27:41 PM PDT 24 |
| Peak memory | 624464 kb |
| Host | smart-3c5e37b3-fb24-426b-8320-afc5c3eb6e07 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=580988280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.580988280 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3126849696 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 4132966610 ps |
| CPU time | 431.97 seconds |
| Started | Aug 06 08:47:07 PM PDT 24 |
| Finished | Aug 06 08:54:19 PM PDT 24 |
| Peak memory | 648564 kb |
| Host | smart-363309c1-eebc-4b94-a8ad-711c2182d7a6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126849696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3126849696 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.2221079304 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 5599611176 ps |
| CPU time | 736.19 seconds |
| Started | Aug 06 08:45:10 PM PDT 24 |
| Finished | Aug 06 08:57:27 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-44aefda6-40da-4d91-b5c2-69a4020fc43f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2221079304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.2221079304 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.4006186707 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3436397904 ps |
| CPU time | 358.17 seconds |
| Started | Aug 06 08:44:48 PM PDT 24 |
| Finished | Aug 06 08:50:46 PM PDT 24 |
| Peak memory | 648512 kb |
| Host | smart-f4bb817c-646d-45fa-b840-fe56b06791b0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006186707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4006186707 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.1852391771 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 5732298012 ps |
| CPU time | 684.74 seconds |
| Started | Aug 06 08:45:12 PM PDT 24 |
| Finished | Aug 06 08:56:37 PM PDT 24 |
| Peak memory | 650272 kb |
| Host | smart-a67ced85-0baa-4726-a3b1-1bc1e53f4880 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1852391771 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.1852391771 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.824974924 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 3852943410 ps |
| CPU time | 364.9 seconds |
| Started | Aug 06 08:45:22 PM PDT 24 |
| Finished | Aug 06 08:51:27 PM PDT 24 |
| Peak memory | 648708 kb |
| Host | smart-0295d1e2-f22e-4553-98c5-ab3ce1a4f5ff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824974924 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.824974924 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.834230077 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 5174197744 ps |
| CPU time | 767.16 seconds |
| Started | Aug 06 08:45:49 PM PDT 24 |
| Finished | Aug 06 08:58:36 PM PDT 24 |
| Peak memory | 649876 kb |
| Host | smart-6e1e4d0d-7564-41d9-ba41-0afaac3763d1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 834230077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.834230077 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.3390107706 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 4818831674 ps |
| CPU time | 601.18 seconds |
| Started | Aug 06 08:53:10 PM PDT 24 |
| Finished | Aug 06 09:03:11 PM PDT 24 |
| Peak memory | 649876 kb |
| Host | smart-364735e5-d084-44a9-94f5-31cf987722fb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3390107706 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.3390107706 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3381494484 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 3513550224 ps |
| CPU time | 402.51 seconds |
| Started | Aug 06 08:47:41 PM PDT 24 |
| Finished | Aug 06 08:54:24 PM PDT 24 |
| Peak memory | 648536 kb |
| Host | smart-20af8010-8198-4ee2-910b-2594f2d48ca7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381494484 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3381494484 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2710600841 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 6040025374 ps |
| CPU time | 729.27 seconds |
| Started | Aug 06 08:45:49 PM PDT 24 |
| Finished | Aug 06 08:57:58 PM PDT 24 |
| Peak memory | 649880 kb |
| Host | smart-32e6cf4c-864b-4802-a4db-30b464873649 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2710600841 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2710600841 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526053746 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 3656291366 ps |
| CPU time | 452.6 seconds |
| Started | Aug 06 08:44:50 PM PDT 24 |
| Finished | Aug 06 08:52:22 PM PDT 24 |
| Peak memory | 648992 kb |
| Host | smart-e7a029ec-f172-44eb-9802-5de5f3966236 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526053746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3526053746 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.4266875552 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 5682470750 ps |
| CPU time | 783.28 seconds |
| Started | Aug 06 08:53:14 PM PDT 24 |
| Finished | Aug 06 09:06:18 PM PDT 24 |
| Peak memory | 649628 kb |
| Host | smart-4a878ad0-ad34-461a-a0f5-addb10c58937 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4266875552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.4266875552 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1446830311 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2826237056 ps |
| CPU time | 357.33 seconds |
| Started | Aug 06 08:44:36 PM PDT 24 |
| Finished | Aug 06 08:50:33 PM PDT 24 |
| Peak memory | 618732 kb |
| Host | smart-6455214c-90c6-4ba0-a7fe-7263a7f6f97c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446830311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1446830311 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.2444332381 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 5661844784 ps |
| CPU time | 579.35 seconds |
| Started | Aug 06 08:45:01 PM PDT 24 |
| Finished | Aug 06 08:54:41 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-46c5ee0b-a99b-45b5-bf2a-0d6b3fb076f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2444332381 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.2444332381 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.478783951 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 3864315620 ps |
| CPU time | 439.35 seconds |
| Started | Aug 06 08:53:12 PM PDT 24 |
| Finished | Aug 06 09:00:32 PM PDT 24 |
| Peak memory | 648736 kb |
| Host | smart-ba4c671a-d477-4585-b1e9-b2c3174c2b2f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478783951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_s w_alert_handler_lpg_sleep_mode_alerts.478783951 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.1914814407 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 5611704052 ps |
| CPU time | 625.68 seconds |
| Started | Aug 06 08:45:09 PM PDT 24 |
| Finished | Aug 06 08:55:35 PM PDT 24 |
| Peak memory | 649828 kb |
| Host | smart-58be9e1b-1aa3-4c4a-9dc3-d80293794827 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1914814407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.1914814407 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.641500309 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 5876457704 ps |
| CPU time | 757.25 seconds |
| Started | Aug 06 08:41:09 PM PDT 24 |
| Finished | Aug 06 08:53:47 PM PDT 24 |
| Peak memory | 649888 kb |
| Host | smart-7a453213-821f-4d6e-953a-7c5a2e2020db |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 641500309 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.641500309 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3072412119 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 20841490492 ps |
| CPU time | 5586.74 seconds |
| Started | Aug 06 08:43:02 PM PDT 24 |
| Finished | Aug 06 10:16:10 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-1f9b169e-33f9-472b-ba1c-e3ef4bffc196 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072412119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.3072412119 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2824375289 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 12509361348 ps |
| CPU time | 806.19 seconds |
| Started | Aug 06 08:41:57 PM PDT 24 |
| Finished | Aug 06 08:55:23 PM PDT 24 |
| Peak memory | 622472 kb |
| Host | smart-1738443a-c159-462d-9572-bfd81f5fc314 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824375289 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.2824375289 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3402324415 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 8492401580 ps |
| CPU time | 1774.17 seconds |
| Started | Aug 06 08:46:47 PM PDT 24 |
| Finished | Aug 06 09:16:24 PM PDT 24 |
| Peak memory | 623448 kb |
| Host | smart-00aa8285-bc9b-48af-b850-e9ac1eb420ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3402324415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.3402324415 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3850921141 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 3989571620 ps |
| CPU time | 405.82 seconds |
| Started | Aug 06 08:45:37 PM PDT 24 |
| Finished | Aug 06 08:52:23 PM PDT 24 |
| Peak memory | 649092 kb |
| Host | smart-aabe18b7-e718-491a-9345-87c64a6354a6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3850921141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3850921141 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793534884 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 3710631464 ps |
| CPU time | 366.6 seconds |
| Started | Aug 06 08:49:17 PM PDT 24 |
| Finished | Aug 06 08:55:24 PM PDT 24 |
| Peak memory | 648404 kb |
| Host | smart-8f7e7dfe-7fb2-40e8-9e6e-2dc3b9ae9e3a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793534884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2793534884 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.2383721099 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 4791426640 ps |
| CPU time | 499.39 seconds |
| Started | Aug 06 08:45:45 PM PDT 24 |
| Finished | Aug 06 08:54:04 PM PDT 24 |
| Peak memory | 649884 kb |
| Host | smart-a9b06167-04e0-4ecf-a701-9b9f3829b22c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2383721099 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.2383721099 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1340832509 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 3234385872 ps |
| CPU time | 362.4 seconds |
| Started | Aug 06 08:44:49 PM PDT 24 |
| Finished | Aug 06 08:50:52 PM PDT 24 |
| Peak memory | 648684 kb |
| Host | smart-db196967-cb0b-4918-8e1b-7476053e7000 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340832509 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1340832509 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.3808254889 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 5783944928 ps |
| CPU time | 714.52 seconds |
| Started | Aug 06 08:44:46 PM PDT 24 |
| Finished | Aug 06 08:56:41 PM PDT 24 |
| Peak memory | 649912 kb |
| Host | smart-822c02c9-8ff0-43eb-bf16-44dcc498b277 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3808254889 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3808254889 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.59846703 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 3892997702 ps |
| CPU time | 378.38 seconds |
| Started | Aug 06 08:45:49 PM PDT 24 |
| Finished | Aug 06 08:52:07 PM PDT 24 |
| Peak memory | 648740 kb |
| Host | smart-f544f7c8-8350-466e-a9c1-b1387368e14a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59846703 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw _alert_handler_lpg_sleep_mode_alerts.59846703 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.3357485341 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 4070442976 ps |
| CPU time | 585.61 seconds |
| Started | Aug 06 08:46:40 PM PDT 24 |
| Finished | Aug 06 08:56:26 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-2d3ffff7-d525-49b3-abe4-ecb0e6e9df8c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3357485341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.3357485341 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1420436405 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 3902196092 ps |
| CPU time | 412.7 seconds |
| Started | Aug 06 08:45:50 PM PDT 24 |
| Finished | Aug 06 08:52:43 PM PDT 24 |
| Peak memory | 648688 kb |
| Host | smart-635e155a-37cf-44ab-8595-171387abed8a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420436405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1420436405 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.1042628176 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 6228419630 ps |
| CPU time | 695.36 seconds |
| Started | Aug 06 08:46:07 PM PDT 24 |
| Finished | Aug 06 08:57:42 PM PDT 24 |
| Peak memory | 649928 kb |
| Host | smart-5b99ce40-6538-417f-af20-aa9d3710af1d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1042628176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.1042628176 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.473121618 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 3964443220 ps |
| CPU time | 355.48 seconds |
| Started | Aug 06 08:45:09 PM PDT 24 |
| Finished | Aug 06 08:51:04 PM PDT 24 |
| Peak memory | 648740 kb |
| Host | smart-298c5eb8-2c0a-44cd-a691-ddd1a84a3100 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473121618 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_s w_alert_handler_lpg_sleep_mode_alerts.473121618 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3261818565 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 3106218770 ps |
| CPU time | 407.62 seconds |
| Started | Aug 06 08:46:02 PM PDT 24 |
| Finished | Aug 06 08:52:50 PM PDT 24 |
| Peak memory | 648748 kb |
| Host | smart-3a40e420-da54-4898-a74c-46df7d2ae548 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261818565 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3261818565 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.867843220 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 4769925228 ps |
| CPU time | 715.55 seconds |
| Started | Aug 06 08:49:13 PM PDT 24 |
| Finished | Aug 06 09:01:08 PM PDT 24 |
| Peak memory | 649824 kb |
| Host | smart-c092ad2f-96c4-4a88-8b9a-92148d45af46 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 867843220 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.867843220 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1345162113 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 3917919684 ps |
| CPU time | 489.03 seconds |
| Started | Aug 06 08:45:45 PM PDT 24 |
| Finished | Aug 06 08:53:54 PM PDT 24 |
| Peak memory | 648640 kb |
| Host | smart-5cdbbe59-a1f4-4913-82c2-cc73aec6e40e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345162113 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1345162113 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.4185462554 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 5015707324 ps |
| CPU time | 658.95 seconds |
| Started | Aug 06 08:47:26 PM PDT 24 |
| Finished | Aug 06 08:58:26 PM PDT 24 |
| Peak memory | 649892 kb |
| Host | smart-05ababb9-eac5-4985-a8f9-177fb155d3ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4185462554 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.4185462554 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1256427338 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 4347724650 ps |
| CPU time | 415.28 seconds |
| Started | Aug 06 08:45:27 PM PDT 24 |
| Finished | Aug 06 08:52:23 PM PDT 24 |
| Peak memory | 619024 kb |
| Host | smart-8a9410ab-d486-4cbd-8e42-802b5f2b9afa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256427338 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1256427338 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1794937172 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 4826901680 ps |
| CPU time | 593.6 seconds |
| Started | Aug 06 08:46:49 PM PDT 24 |
| Finished | Aug 06 08:56:43 PM PDT 24 |
| Peak memory | 649880 kb |
| Host | smart-1f58eb32-cb99-4fe3-936b-62e708cfc518 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1794937172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1794937172 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.320402635 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 3605960810 ps |
| CPU time | 406.75 seconds |
| Started | Aug 06 08:46:51 PM PDT 24 |
| Finished | Aug 06 08:53:38 PM PDT 24 |
| Peak memory | 649056 kb |
| Host | smart-9f5bdf54-bded-4c37-9c66-0863e48eabd8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320402635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_s w_alert_handler_lpg_sleep_mode_alerts.320402635 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3215391560 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 4979025638 ps |
| CPU time | 682.75 seconds |
| Started | Aug 06 08:46:28 PM PDT 24 |
| Finished | Aug 06 08:57:51 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-8b893128-39b5-4035-8e64-bafa02bf22b9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3215391560 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3215391560 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3723439987 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 3504206024 ps |
| CPU time | 342.15 seconds |
| Started | Aug 06 08:41:52 PM PDT 24 |
| Finished | Aug 06 08:47:34 PM PDT 24 |
| Peak memory | 648784 kb |
| Host | smart-c0ce92c1-8049-48e0-ae50-161ce7465839 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723439987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3723439987 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3832555325 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 17837101296 ps |
| CPU time | 4196.49 seconds |
| Started | Aug 06 08:41:52 PM PDT 24 |
| Finished | Aug 06 09:51:49 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-565bd6bd-3ad0-40dc-b087-9c44796c7e20 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832555325 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.3832555325 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3751151116 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 6614951804 ps |
| CPU time | 595.53 seconds |
| Started | Aug 06 08:40:53 PM PDT 24 |
| Finished | Aug 06 08:50:49 PM PDT 24 |
| Peak memory | 622500 kb |
| Host | smart-f9f643d0-8e83-4f3c-afab-1fd62bb1299d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751151116 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.3751151116 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.646556033 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 8034095300 ps |
| CPU time | 1714.97 seconds |
| Started | Aug 06 08:41:12 PM PDT 24 |
| Finished | Aug 06 09:09:47 PM PDT 24 |
| Peak memory | 624440 kb |
| Host | smart-19b39a48-e8e4-42be-a88a-9ff579d61c3a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=646556033 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.646556033 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2437816947 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 3628701872 ps |
| CPU time | 406.15 seconds |
| Started | Aug 06 08:46:43 PM PDT 24 |
| Finished | Aug 06 08:53:29 PM PDT 24 |
| Peak memory | 648492 kb |
| Host | smart-6e29e451-2b0d-4840-8059-4e171a560c88 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437816947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2437816947 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3439764800 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 4203163636 ps |
| CPU time | 329.89 seconds |
| Started | Aug 06 08:48:23 PM PDT 24 |
| Finished | Aug 06 08:53:53 PM PDT 24 |
| Peak memory | 648512 kb |
| Host | smart-299d0402-0dbe-4849-8d2f-b32bf691d5b6 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439764800 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3439764800 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.857062917 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 3879839000 ps |
| CPU time | 464.23 seconds |
| Started | Aug 06 08:47:16 PM PDT 24 |
| Finished | Aug 06 08:55:00 PM PDT 24 |
| Peak memory | 649144 kb |
| Host | smart-47fb1530-1bf2-417a-aabe-bed2347be991 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857062917 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_s w_alert_handler_lpg_sleep_mode_alerts.857062917 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.1787662061 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 5136439428 ps |
| CPU time | 707.03 seconds |
| Started | Aug 06 08:46:47 PM PDT 24 |
| Finished | Aug 06 08:58:34 PM PDT 24 |
| Peak memory | 619784 kb |
| Host | smart-04b31e15-f16a-4b03-a15f-b53163d2669b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1787662061 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.1787662061 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1775538828 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3732911800 ps |
| CPU time | 381.74 seconds |
| Started | Aug 06 08:48:19 PM PDT 24 |
| Finished | Aug 06 08:54:41 PM PDT 24 |
| Peak memory | 648940 kb |
| Host | smart-faf5c677-418b-4d3b-b8a8-bd1a49992c80 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775538828 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1775538828 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.1164841379 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 5641889418 ps |
| CPU time | 627.48 seconds |
| Started | Aug 06 08:53:04 PM PDT 24 |
| Finished | Aug 06 09:03:32 PM PDT 24 |
| Peak memory | 650108 kb |
| Host | smart-07f1dd0f-ce4c-4880-b5ed-230e7aeb2771 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1164841379 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.1164841379 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.4029387204 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4416261616 ps |
| CPU time | 471.34 seconds |
| Started | Aug 06 08:47:57 PM PDT 24 |
| Finished | Aug 06 08:55:49 PM PDT 24 |
| Peak memory | 649044 kb |
| Host | smart-359712b1-d9c7-4884-acc0-a49964f82ec4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029387204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4029387204 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.3322754146 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 4988963320 ps |
| CPU time | 724.79 seconds |
| Started | Aug 06 08:45:14 PM PDT 24 |
| Finished | Aug 06 08:57:19 PM PDT 24 |
| Peak memory | 649964 kb |
| Host | smart-1c11d0fc-7698-4e09-b8fb-21fac6e4e05f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3322754146 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.3322754146 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.3210209975 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 3940006862 ps |
| CPU time | 413.11 seconds |
| Started | Aug 06 08:48:05 PM PDT 24 |
| Finished | Aug 06 08:54:59 PM PDT 24 |
| Peak memory | 648812 kb |
| Host | smart-57386820-f8af-44af-8989-a2c2c01fe477 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210209975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3210209975 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.826772786 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 4412735448 ps |
| CPU time | 500.03 seconds |
| Started | Aug 06 08:45:57 PM PDT 24 |
| Finished | Aug 06 08:54:17 PM PDT 24 |
| Peak memory | 649660 kb |
| Host | smart-58112101-29c3-495c-8273-8107dff2b22b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 826772786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.826772786 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1862658199 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 4045239504 ps |
| CPU time | 388.96 seconds |
| Started | Aug 06 08:49:14 PM PDT 24 |
| Finished | Aug 06 08:55:43 PM PDT 24 |
| Peak memory | 648840 kb |
| Host | smart-3e7debf8-ca28-479f-8e0a-af02d839e9c2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1862658199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1862658199 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.1826566873 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 6007691580 ps |
| CPU time | 789.7 seconds |
| Started | Aug 06 08:46:00 PM PDT 24 |
| Finished | Aug 06 08:59:10 PM PDT 24 |
| Peak memory | 619812 kb |
| Host | smart-93d82a85-f310-492e-8ef8-c493894f7949 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1826566873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.1826566873 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1856368779 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 3627199408 ps |
| CPU time | 441.73 seconds |
| Started | Aug 06 08:47:41 PM PDT 24 |
| Finished | Aug 06 08:55:03 PM PDT 24 |
| Peak memory | 648980 kb |
| Host | smart-cc762ed6-8dc4-4e33-b4af-d4b93d949050 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1856368779 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1856368779 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.94104492 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4701091486 ps |
| CPU time | 524.57 seconds |
| Started | Aug 06 08:46:46 PM PDT 24 |
| Finished | Aug 06 08:55:30 PM PDT 24 |
| Peak memory | 649804 kb |
| Host | smart-c7560557-f613-46e8-a6f5-b5a96d1d1549 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 94104492 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.94104492 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541241678 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 4153315972 ps |
| CPU time | 409.75 seconds |
| Started | Aug 06 08:46:59 PM PDT 24 |
| Finished | Aug 06 08:53:49 PM PDT 24 |
| Peak memory | 648536 kb |
| Host | smart-35a3a640-234b-4974-8d94-4c4913307d06 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541241678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2541241678 |
| Directory | /workspace/88.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.1975054534 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 5405571992 ps |
| CPU time | 592.25 seconds |
| Started | Aug 06 08:48:11 PM PDT 24 |
| Finished | Aug 06 08:58:03 PM PDT 24 |
| Peak memory | 649816 kb |
| Host | smart-9dadea49-0d94-403d-97d3-e34ca0c9eedc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1975054534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.1975054534 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.913801757 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 3467463928 ps |
| CPU time | 471.34 seconds |
| Started | Aug 06 08:45:48 PM PDT 24 |
| Finished | Aug 06 08:53:39 PM PDT 24 |
| Peak memory | 649072 kb |
| Host | smart-86c6f54c-abf4-4e7a-ba50-2270ebfe8fb9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913801757 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_s w_alert_handler_lpg_sleep_mode_alerts.913801757 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.2208846408 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 5510605128 ps |
| CPU time | 753.44 seconds |
| Started | Aug 06 08:46:56 PM PDT 24 |
| Finished | Aug 06 08:59:29 PM PDT 24 |
| Peak memory | 649924 kb |
| Host | smart-dbb03ac4-5c6e-45e4-a2be-605c87825afc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2208846408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.2208846408 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3423125783 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4349552516 ps |
| CPU time | 431.22 seconds |
| Started | Aug 06 08:41:54 PM PDT 24 |
| Finished | Aug 06 08:49:05 PM PDT 24 |
| Peak memory | 648760 kb |
| Host | smart-fbe090e6-13a5-4d46-95ca-a8588ef16b40 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423125783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.3423125783 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.3969234331 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5382511208 ps |
| CPU time | 608.26 seconds |
| Started | Aug 06 08:47:49 PM PDT 24 |
| Finished | Aug 06 08:57:58 PM PDT 24 |
| Peak memory | 649588 kb |
| Host | smart-3b6bd429-afca-4e10-8ba5-8859ac6758be |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3969234331 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3969234331 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.2251950808 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 20486513496 ps |
| CPU time | 4569.83 seconds |
| Started | Aug 06 08:48:28 PM PDT 24 |
| Finished | Aug 06 10:04:38 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-439a5304-b031-4fbb-ace9-3ce7f948097a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +accelerate_cold_power_up_time=3 +accelerate_r egulators_power_up_time=2 +sw_build_device=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251950808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.2251950808 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.982338608 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 8954237295 ps |
| CPU time | 1044.62 seconds |
| Started | Aug 06 08:47:21 PM PDT 24 |
| Finished | Aug 06 09:04:47 PM PDT 24 |
| Peak memory | 622496 kb |
| Host | smart-97044ded-54da-4ebf-b162-8534d5e82759 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982338608 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.982338608 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2109245649 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 4337324720 ps |
| CPU time | 579.94 seconds |
| Started | Aug 06 08:43:29 PM PDT 24 |
| Finished | Aug 06 08:53:09 PM PDT 24 |
| Peak memory | 624408 kb |
| Host | smart-39354220-93fb-449b-a60f-e8b3c6de0b18 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2109245649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.2109245649 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.887114864 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 5740719640 ps |
| CPU time | 683.07 seconds |
| Started | Aug 06 08:45:51 PM PDT 24 |
| Finished | Aug 06 08:57:14 PM PDT 24 |
| Peak memory | 649684 kb |
| Host | smart-69b05904-f089-441a-854e-c72fd489470d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 887114864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.887114864 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.371008527 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 5480263440 ps |
| CPU time | 598.69 seconds |
| Started | Aug 06 08:48:40 PM PDT 24 |
| Finished | Aug 06 08:58:39 PM PDT 24 |
| Peak memory | 649824 kb |
| Host | smart-f563c1ba-0f55-4ed4-beac-03e85af4133b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 371008527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.371008527 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.758433042 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 5995176312 ps |
| CPU time | 982.92 seconds |
| Started | Aug 06 08:46:54 PM PDT 24 |
| Finished | Aug 06 09:03:17 PM PDT 24 |
| Peak memory | 649580 kb |
| Host | smart-8c8def6b-aeb3-459e-baed-40c3288513f2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 758433042 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.758433042 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.2655307007 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 4421330500 ps |
| CPU time | 517 seconds |
| Started | Aug 06 08:46:51 PM PDT 24 |
| Finished | Aug 06 08:55:28 PM PDT 24 |
| Peak memory | 650216 kb |
| Host | smart-2d3b8f77-8b80-4576-9b7c-1d46b1f4d5c6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2655307007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.2655307007 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.41302538 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 4576540400 ps |
| CPU time | 689.59 seconds |
| Started | Aug 06 08:46:27 PM PDT 24 |
| Finished | Aug 06 08:57:57 PM PDT 24 |
| Peak memory | 649788 kb |
| Host | smart-3ac3548d-a323-4267-9814-36d35257acf7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 41302538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.41302538 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.3358280890 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 5314328000 ps |
| CPU time | 746.49 seconds |
| Started | Aug 06 08:46:19 PM PDT 24 |
| Finished | Aug 06 08:58:46 PM PDT 24 |
| Peak memory | 650176 kb |
| Host | smart-2c9534ca-9480-4b34-af4d-acd5eec1283f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3358280890 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.3358280890 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.3831378189 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 4869337164 ps |
| CPU time | 629.36 seconds |
| Started | Aug 06 08:48:00 PM PDT 24 |
| Finished | Aug 06 08:58:29 PM PDT 24 |
| Peak memory | 649596 kb |
| Host | smart-ad208bdb-e15c-499d-a4d5-dbb38fb5bed3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3831378189 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.3831378189 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.3187502548 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5403515560 ps |
| CPU time | 748.38 seconds |
| Started | Aug 06 08:47:06 PM PDT 24 |
| Finished | Aug 06 08:59:34 PM PDT 24 |
| Peak memory | 649904 kb |
| Host | smart-58d1720e-36fb-4a8d-8323-8d8bee128a8d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3187502548 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.3187502548 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.377294301 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 4803528620 ps |
| CPU time | 664.66 seconds |
| Started | Aug 06 08:47:39 PM PDT 24 |
| Finished | Aug 06 08:58:44 PM PDT 24 |
| Peak memory | 650128 kb |
| Host | smart-129aa570-8ff2-45d5-b7a3-7012f881329c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 377294301 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.377294301 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.2149797186 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 5491534508 ps |
| CPU time | 282.3 seconds |
| Started | Aug 06 08:39:47 PM PDT 24 |
| Finished | Aug 06 08:44:29 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-6bf22b76-657d-48f6-893e-0d4262910fe4 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149797186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 1.chip_padctrl_attributes.2149797186 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.1948658276 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 4559882900 ps |
| CPU time | 340.37 seconds |
| Started | Aug 06 08:39:50 PM PDT 24 |
| Finished | Aug 06 08:45:30 PM PDT 24 |
| Peak memory | 657344 kb |
| Host | smart-d73a88c0-4057-47f4-bd05-188e3335dfca |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948658276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.1948658276 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.1726404817 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 5262593925 ps |
| CPU time | 320.14 seconds |
| Started | Aug 06 08:40:47 PM PDT 24 |
| Finished | Aug 06 08:46:07 PM PDT 24 |
| Peak memory | 640968 kb |
| Host | smart-8c3ff195-f621-42d6-beed-3a8744054800 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726404817 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 3.chip_padctrl_attributes.1726404817 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.1221262080 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4526596866 ps |
| CPU time | 292.58 seconds |
| Started | Aug 06 08:39:57 PM PDT 24 |
| Finished | Aug 06 08:44:49 PM PDT 24 |
| Peak memory | 649164 kb |
| Host | smart-5b3ad985-1944-45a4-a2dd-2f50bdbecb16 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221262080 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.1221262080 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.598668445 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5325613366 ps |
| CPU time | 267.48 seconds |
| Started | Aug 06 08:40:04 PM PDT 24 |
| Finished | Aug 06 08:44:33 PM PDT 24 |
| Peak memory | 657320 kb |
| Host | smart-f8a32b0c-49c5-43f0-b3b6-ff176ef2c41e |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598668445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 5.chip_padctrl_attributes.598668445 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3420465919 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 5527628594 ps |
| CPU time | 308.3 seconds |
| Started | Aug 06 08:40:00 PM PDT 24 |
| Finished | Aug 06 08:45:09 PM PDT 24 |
| Peak memory | 649804 kb |
| Host | smart-be91ca82-549e-44be-84e4-573e60817f19 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420465919 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.3420465919 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3414783364 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4769818113 ps |
| CPU time | 203.38 seconds |
| Started | Aug 06 08:40:07 PM PDT 24 |
| Finished | Aug 06 08:43:31 PM PDT 24 |
| Peak memory | 640948 kb |
| Host | smart-2cc7f795-38af-4c38-be6c-cb7e63b8e2aa |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414783364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.3414783364 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2530429001 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 4276649088 ps |
| CPU time | 261.86 seconds |
| Started | Aug 06 08:40:28 PM PDT 24 |
| Finished | Aug 06 08:44:51 PM PDT 24 |
| Peak memory | 639936 kb |
| Host | smart-f7ffc7a6-5ff2-4a5a-9c8d-318923a97602 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530429001 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2530429001 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
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