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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.49 93.82 95.32 94.57 97.35 99.55


Total test records in report: 2932
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T1218 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1617372898 Aug 06 08:23:54 PM PDT 24 Aug 06 08:32:00 PM PDT 24 3654411936 ps
T1219 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.742570616 Aug 06 08:36:47 PM PDT 24 Aug 06 09:07:20 PM PDT 24 10386924160 ps
T782 /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.2283176724 Aug 06 08:41:52 PM PDT 24 Aug 06 08:49:22 PM PDT 24 4017511582 ps
T58 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.771492183 Aug 06 08:24:20 PM PDT 24 Aug 06 08:28:37 PM PDT 24 3204310240 ps
T429 /workspace/coverage/default/52.chip_sw_all_escalation_resets.3167560117 Aug 06 08:44:03 PM PDT 24 Aug 06 08:54:12 PM PDT 24 5386658040 ps
T430 /workspace/coverage/default/0.chip_sw_coremark.3614474491 Aug 06 08:26:39 PM PDT 24 Aug 07 12:16:50 AM PDT 24 72034697560 ps
T431 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1334157983 Aug 06 08:27:06 PM PDT 24 Aug 06 08:31:55 PM PDT 24 2457430296 ps
T432 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.2237076876 Aug 06 08:40:15 PM PDT 24 Aug 06 08:44:52 PM PDT 24 2718136944 ps
T201 /workspace/coverage/default/1.chip_sw_power_virus.3950448717 Aug 06 08:35:45 PM PDT 24 Aug 06 09:07:32 PM PDT 24 6031697376 ps
T230 /workspace/coverage/default/1.chip_sw_power_sleep_load.255429711 Aug 06 08:26:54 PM PDT 24 Aug 06 08:34:14 PM PDT 24 4609119496 ps
T433 /workspace/coverage/default/57.chip_sw_all_escalation_resets.3109428296 Aug 06 08:45:01 PM PDT 24 Aug 06 08:55:40 PM PDT 24 4971065850 ps
T434 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.3416166435 Aug 06 08:40:35 PM PDT 24 Aug 06 08:53:42 PM PDT 24 5272915428 ps
T170 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.4269079737 Aug 06 08:26:59 PM PDT 24 Aug 06 08:35:14 PM PDT 24 4630038894 ps
T1220 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1532244275 Aug 06 08:26:14 PM PDT 24 Aug 06 08:34:20 PM PDT 24 5314949880 ps
T1221 /workspace/coverage/default/0.rom_e2e_asm_init_rma.583466395 Aug 06 08:28:52 PM PDT 24 Aug 06 09:33:16 PM PDT 24 15285759283 ps
T1222 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2968713602 Aug 06 08:27:05 PM PDT 24 Aug 06 08:33:27 PM PDT 24 4009619123 ps
T1223 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1781401266 Aug 06 08:38:16 PM PDT 24 Aug 06 09:46:06 PM PDT 24 24898764720 ps
T274 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.752745714 Aug 06 08:35:32 PM PDT 24 Aug 06 08:45:41 PM PDT 24 9613109237 ps
T1224 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3070344980 Aug 06 08:44:22 PM PDT 24 Aug 06 08:51:31 PM PDT 24 3996712840 ps
T1225 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3263800149 Aug 06 08:37:06 PM PDT 24 Aug 06 08:39:25 PM PDT 24 3043130032 ps
T1226 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3406844342 Aug 06 08:35:09 PM PDT 24 Aug 06 09:39:47 PM PDT 24 15210583840 ps
T1227 /workspace/coverage/default/2.chip_sw_example_manufacturer.317274810 Aug 06 08:32:24 PM PDT 24 Aug 06 08:37:12 PM PDT 24 2645521024 ps
T329 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1224760714 Aug 06 08:25:32 PM PDT 24 Aug 06 08:40:55 PM PDT 24 5342855010 ps
T1228 /workspace/coverage/default/1.chip_tap_straps_testunlock0.2749370407 Aug 06 08:21:30 PM PDT 24 Aug 06 08:29:18 PM PDT 24 5674946404 ps
T849 /workspace/coverage/default/35.chip_sw_all_escalation_resets.3035567060 Aug 06 08:43:52 PM PDT 24 Aug 06 08:57:47 PM PDT 24 5376891854 ps
T231 /workspace/coverage/default/2.chip_sw_plic_sw_irq.3623803671 Aug 06 08:37:01 PM PDT 24 Aug 06 08:40:54 PM PDT 24 3161417258 ps
T739 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.191035765 Aug 06 08:28:45 PM PDT 24 Aug 06 08:33:29 PM PDT 24 3800893466 ps
T1229 /workspace/coverage/default/53.chip_sw_all_escalation_resets.2377178089 Aug 06 08:43:50 PM PDT 24 Aug 06 08:54:43 PM PDT 24 6033313788 ps
T1230 /workspace/coverage/default/0.chip_sw_hmac_multistream.1727133838 Aug 06 08:26:01 PM PDT 24 Aug 06 08:58:15 PM PDT 24 8313866996 ps
T1231 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1520802644 Aug 06 08:34:37 PM PDT 24 Aug 06 08:40:53 PM PDT 24 3411103404 ps
T758 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2175254758 Aug 06 08:29:08 PM PDT 24 Aug 06 08:40:37 PM PDT 24 4759660107 ps
T299 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2403705446 Aug 06 08:30:27 PM PDT 24 Aug 06 08:40:11 PM PDT 24 5051288544 ps
T1232 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.79128939 Aug 06 08:24:08 PM PDT 24 Aug 06 08:47:04 PM PDT 24 11477564184 ps
T1233 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2621755100 Aug 06 08:24:38 PM PDT 24 Aug 06 08:28:20 PM PDT 24 2988457008 ps
T767 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.300782981 Aug 06 08:43:49 PM PDT 24 Aug 06 08:51:53 PM PDT 24 3928233000 ps
T1234 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1441137757 Aug 06 08:19:18 PM PDT 24 Aug 06 08:43:03 PM PDT 24 7904392710 ps
T1235 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.3912384991 Aug 06 08:24:17 PM PDT 24 Aug 06 10:09:38 PM PDT 24 49508322869 ps
T1236 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.691049104 Aug 06 08:31:41 PM PDT 24 Aug 06 08:42:19 PM PDT 24 18440315720 ps
T759 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.191782904 Aug 06 08:25:51 PM PDT 24 Aug 06 08:35:50 PM PDT 24 4012137244 ps
T1237 /workspace/coverage/default/0.chip_sw_kmac_smoketest.1495816831 Aug 06 08:24:48 PM PDT 24 Aug 06 08:29:40 PM PDT 24 3047477832 ps
T1238 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.400642583 Aug 06 08:41:11 PM PDT 24 Aug 06 08:47:36 PM PDT 24 3552767112 ps
T140 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3225326394 Aug 06 08:27:54 PM PDT 24 Aug 06 08:35:04 PM PDT 24 3153557614 ps
T1239 /workspace/coverage/default/1.chip_sw_kmac_idle.3181601636 Aug 06 08:25:22 PM PDT 24 Aug 06 08:29:29 PM PDT 24 2802057816 ps
T1240 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2037197971 Aug 06 08:41:49 PM PDT 24 Aug 06 08:50:25 PM PDT 24 7001537259 ps
T1241 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.645503374 Aug 06 08:32:32 PM PDT 24 Aug 06 08:41:49 PM PDT 24 3761323640 ps
T1242 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2185242330 Aug 06 08:40:50 PM PDT 24 Aug 06 08:44:48 PM PDT 24 3108042548 ps
T1243 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3005532903 Aug 06 08:31:15 PM PDT 24 Aug 06 09:46:54 PM PDT 24 15641630478 ps
T1244 /workspace/coverage/default/0.chip_sw_aes_idle.2880542850 Aug 06 08:20:38 PM PDT 24 Aug 06 08:24:00 PM PDT 24 2576658912 ps
T1245 /workspace/coverage/default/22.chip_sw_all_escalation_resets.1318762167 Aug 06 08:42:56 PM PDT 24 Aug 06 08:53:14 PM PDT 24 5578642488 ps
T1246 /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1435213255 Aug 06 08:42:39 PM PDT 24 Aug 06 09:33:59 PM PDT 24 11165913446 ps
T1247 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3771614721 Aug 06 08:20:50 PM PDT 24 Aug 06 08:24:50 PM PDT 24 3279790890 ps
T1248 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2522110248 Aug 06 08:44:32 PM PDT 24 Aug 06 08:52:25 PM PDT 24 4161975076 ps
T827 /workspace/coverage/default/13.chip_sw_all_escalation_resets.2940862743 Aug 06 08:43:09 PM PDT 24 Aug 06 08:54:15 PM PDT 24 4482510200 ps
T1249 /workspace/coverage/default/2.chip_sw_aes_enc.3559482715 Aug 06 08:34:00 PM PDT 24 Aug 06 08:39:33 PM PDT 24 3438775528 ps
T1250 /workspace/coverage/default/1.chip_sw_otbn_smoketest.1268774689 Aug 06 08:32:16 PM PDT 24 Aug 06 09:01:42 PM PDT 24 7847346026 ps
T1251 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1358377840 Aug 06 08:39:42 PM PDT 24 Aug 06 08:49:09 PM PDT 24 4676149808 ps
T1252 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.708421464 Aug 06 08:27:54 PM PDT 24 Aug 06 09:25:31 PM PDT 24 14849806750 ps
T1253 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.943939446 Aug 06 08:44:14 PM PDT 24 Aug 06 09:44:58 PM PDT 24 14892071870 ps
T1254 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2314087998 Aug 06 08:26:27 PM PDT 24 Aug 06 08:42:34 PM PDT 24 9777525560 ps
T1255 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3816881948 Aug 06 08:31:10 PM PDT 24 Aug 06 08:53:14 PM PDT 24 7650095724 ps
T1256 /workspace/coverage/default/0.rom_e2e_self_hash.2751530542 Aug 06 08:31:43 PM PDT 24 Aug 06 10:13:37 PM PDT 24 26593213276 ps
T105 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.1262002241 Aug 06 08:26:49 PM PDT 24 Aug 06 08:34:53 PM PDT 24 3653553080 ps
T110 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.2149354546 Aug 06 08:22:29 PM PDT 24 Aug 06 09:08:55 PM PDT 24 18380214326 ps
T1257 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2883525180 Aug 06 08:22:39 PM PDT 24 Aug 06 08:52:19 PM PDT 24 9616935571 ps
T1258 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1718523633 Aug 06 08:30:11 PM PDT 24 Aug 06 08:36:36 PM PDT 24 6680012604 ps
T1259 /workspace/coverage/default/2.chip_sw_edn_sw_mode.3509739403 Aug 06 08:37:02 PM PDT 24 Aug 06 08:57:28 PM PDT 24 5804158284 ps
T1260 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2581035721 Aug 06 08:22:22 PM PDT 24 Aug 06 08:53:06 PM PDT 24 15937787367 ps
T372 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1773416057 Aug 06 08:22:19 PM PDT 24 Aug 06 08:29:12 PM PDT 24 4813975760 ps
T1261 /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3803131004 Aug 06 08:34:50 PM PDT 24 Aug 06 08:48:00 PM PDT 24 6692627522 ps
T1262 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2859943426 Aug 06 08:22:36 PM PDT 24 Aug 06 08:27:55 PM PDT 24 2666969264 ps
T1263 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2147489603 Aug 06 08:22:31 PM PDT 24 Aug 06 08:32:28 PM PDT 24 4907655480 ps
T854 /workspace/coverage/default/90.chip_sw_all_escalation_resets.887114864 Aug 06 08:45:51 PM PDT 24 Aug 06 08:57:14 PM PDT 24 5740719640 ps
T1264 /workspace/coverage/default/1.rom_e2e_shutdown_output.211892744 Aug 06 08:31:03 PM PDT 24 Aug 06 09:42:30 PM PDT 24 25894440990 ps
T1265 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2517146734 Aug 06 08:25:43 PM PDT 24 Aug 06 08:49:41 PM PDT 24 8779490808 ps
T1266 /workspace/coverage/default/4.chip_sw_uart_tx_rx.628727410 Aug 06 08:40:42 PM PDT 24 Aug 06 08:51:48 PM PDT 24 4547079480 ps
T202 /workspace/coverage/default/2.chip_sw_power_virus.629385357 Aug 06 08:43:17 PM PDT 24 Aug 06 09:09:15 PM PDT 24 6151374552 ps
T794 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3904596659 Aug 06 08:41:59 PM PDT 24 Aug 06 08:49:22 PM PDT 24 4087065600 ps
T243 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1484427886 Aug 06 08:27:38 PM PDT 24 Aug 06 08:36:00 PM PDT 24 4943012348 ps
T226 /workspace/coverage/default/96.chip_sw_all_escalation_resets.3831378189 Aug 06 08:48:00 PM PDT 24 Aug 06 08:58:29 PM PDT 24 4869337164 ps
T823 /workspace/coverage/default/2.chip_sw_all_escalation_resets.3770136438 Aug 06 08:24:23 PM PDT 24 Aug 06 08:37:49 PM PDT 24 6039753328 ps
T1267 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3808917641 Aug 06 08:27:24 PM PDT 24 Aug 06 08:32:34 PM PDT 24 2469188270 ps
T804 /workspace/coverage/default/98.chip_sw_all_escalation_resets.3187502548 Aug 06 08:47:06 PM PDT 24 Aug 06 08:59:34 PM PDT 24 5403515560 ps
T1268 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2058109746 Aug 06 08:43:54 PM PDT 24 Aug 06 09:02:09 PM PDT 24 10004457235 ps
T1269 /workspace/coverage/default/38.chip_sw_all_escalation_resets.3732672307 Aug 06 08:45:29 PM PDT 24 Aug 06 08:57:12 PM PDT 24 4865053240 ps
T106 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2395170943 Aug 06 08:25:41 PM PDT 24 Aug 06 08:34:09 PM PDT 24 3908965432 ps
T141 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3616163101 Aug 06 08:25:42 PM PDT 24 Aug 06 08:33:20 PM PDT 24 5455427080 ps
T750 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2027617051 Aug 06 08:23:49 PM PDT 24 Aug 06 08:32:33 PM PDT 24 4109534412 ps
T347 /workspace/coverage/default/2.chip_sival_flash_info_access.3084534322 Aug 06 08:29:50 PM PDT 24 Aug 06 08:35:16 PM PDT 24 3255367082 ps
T751 /workspace/coverage/default/4.chip_tap_straps_testunlock0.1654945808 Aug 06 08:40:06 PM PDT 24 Aug 06 08:46:59 PM PDT 24 3393162449 ps
T752 /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.998155161 Aug 06 08:23:28 PM PDT 24 Aug 06 08:29:16 PM PDT 24 4376944530 ps
T753 /workspace/coverage/default/99.chip_sw_all_escalation_resets.377294301 Aug 06 08:47:39 PM PDT 24 Aug 06 08:58:44 PM PDT 24 4803528620 ps
T754 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.3072412119 Aug 06 08:43:02 PM PDT 24 Aug 06 10:16:10 PM PDT 24 20841490492 ps
T332 /workspace/coverage/default/1.chip_plic_all_irqs_20.977097340 Aug 06 08:27:15 PM PDT 24 Aug 06 08:39:19 PM PDT 24 4891076600 ps
T755 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.3259146194 Aug 06 08:22:54 PM PDT 24 Aug 06 09:59:13 PM PDT 24 50137326536 ps
T857 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1221188860 Aug 06 08:43:10 PM PDT 24 Aug 06 08:49:15 PM PDT 24 3483721892 ps
T339 /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.1112728768 Aug 06 08:21:37 PM PDT 24 Aug 06 08:27:58 PM PDT 24 4143266368 ps
T1270 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.643533569 Aug 06 08:24:15 PM PDT 24 Aug 06 08:30:35 PM PDT 24 3671338450 ps
T1271 /workspace/coverage/default/0.rom_e2e_shutdown_output.1208048618 Aug 06 08:31:18 PM PDT 24 Aug 06 09:37:25 PM PDT 24 25585794092 ps
T335 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.1308484597 Aug 06 08:27:13 PM PDT 24 Aug 06 08:39:45 PM PDT 24 4606770052 ps
T1272 /workspace/coverage/default/0.chip_sw_flash_crash_alert.492653977 Aug 06 08:21:03 PM PDT 24 Aug 06 08:33:53 PM PDT 24 5417883480 ps
T1273 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4204899308 Aug 06 08:23:06 PM PDT 24 Aug 06 08:32:55 PM PDT 24 4441478824 ps
T1274 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1575820156 Aug 06 08:27:04 PM PDT 24 Aug 06 08:30:52 PM PDT 24 2825260592 ps
T1275 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2087058628 Aug 06 08:25:54 PM PDT 24 Aug 06 08:35:20 PM PDT 24 3886573336 ps
T263 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1439427261 Aug 06 08:27:17 PM PDT 24 Aug 06 08:33:22 PM PDT 24 3575520968 ps
T436 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1038880742 Aug 06 08:21:33 PM PDT 24 Aug 06 08:55:56 PM PDT 24 21346112840 ps
T756 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1726737268 Aug 06 08:26:04 PM PDT 24 Aug 06 08:41:08 PM PDT 24 4581958296 ps
T802 /workspace/coverage/default/85.chip_sw_all_escalation_resets.826772786 Aug 06 08:45:57 PM PDT 24 Aug 06 08:54:17 PM PDT 24 4412735448 ps
T784 /workspace/coverage/default/33.chip_sw_all_escalation_resets.529482299 Aug 06 08:43:57 PM PDT 24 Aug 06 08:56:21 PM PDT 24 5027436400 ps
T1276 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3489196363 Aug 06 08:25:02 PM PDT 24 Aug 06 09:38:55 PM PDT 24 15395397410 ps
T1277 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.115002219 Aug 06 08:39:46 PM PDT 24 Aug 06 08:48:18 PM PDT 24 6895482048 ps
T55 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3971934626 Aug 06 08:25:01 PM PDT 24 Aug 06 08:32:01 PM PDT 24 3561316053 ps
T1278 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.982338608 Aug 06 08:47:21 PM PDT 24 Aug 06 09:04:47 PM PDT 24 8954237295 ps
T1279 /workspace/coverage/default/1.chip_sw_flash_ctrl_access.2616366146 Aug 06 08:19:55 PM PDT 24 Aug 06 08:34:01 PM PDT 24 6150487812 ps
T92 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1400359385 Aug 06 08:44:35 PM PDT 24 Aug 06 08:51:23 PM PDT 24 3306050148 ps
T805 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2383721099 Aug 06 08:45:45 PM PDT 24 Aug 06 08:54:04 PM PDT 24 4791426640 ps
T1280 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.1503106294 Aug 06 08:28:43 PM PDT 24 Aug 06 08:33:12 PM PDT 24 3459692586 ps
T1281 /workspace/coverage/default/1.chip_sw_aes_entropy.2959550291 Aug 06 08:23:30 PM PDT 24 Aug 06 08:27:40 PM PDT 24 3230225030 ps
T1282 /workspace/coverage/default/0.chip_sw_otbn_randomness.3074636011 Aug 06 08:24:57 PM PDT 24 Aug 06 08:43:51 PM PDT 24 5510010700 ps
T1283 /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.951945325 Aug 06 08:47:10 PM PDT 24 Aug 06 08:54:36 PM PDT 24 4461196712 ps
T1284 /workspace/coverage/default/0.chip_sw_usbdev_dpi.2331091656 Aug 06 08:24:08 PM PDT 24 Aug 06 09:12:16 PM PDT 24 12054993792 ps
T1285 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1439597087 Aug 06 08:28:41 PM PDT 24 Aug 07 12:04:18 AM PDT 24 89967814749 ps
T1286 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1151649071 Aug 06 08:25:47 PM PDT 24 Aug 06 08:46:59 PM PDT 24 9459647944 ps
T1287 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.2484759570 Aug 06 08:22:05 PM PDT 24 Aug 06 08:26:07 PM PDT 24 3355306992 ps
T1288 /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2619889714 Aug 06 08:26:42 PM PDT 24 Aug 06 08:35:14 PM PDT 24 6348691176 ps
T264 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.1636447865 Aug 06 08:24:30 PM PDT 24 Aug 06 08:29:36 PM PDT 24 2634824095 ps
T1289 /workspace/coverage/default/0.chip_sw_example_manufacturer.2554017496 Aug 06 08:23:41 PM PDT 24 Aug 06 08:27:34 PM PDT 24 2211917410 ps
T9 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.295766705 Aug 06 08:26:39 PM PDT 24 Aug 06 08:31:52 PM PDT 24 3042811301 ps
T1290 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3832555325 Aug 06 08:41:52 PM PDT 24 Aug 06 09:51:49 PM PDT 24 17837101296 ps
T1291 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2685128735 Aug 06 08:30:11 PM PDT 24 Aug 06 09:32:12 PM PDT 24 15327559410 ps
T740 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.2824984536 Aug 06 08:25:35 PM PDT 24 Aug 06 08:31:28 PM PDT 24 3798039172 ps
T369 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2475065037 Aug 06 08:24:20 PM PDT 24 Aug 06 08:28:55 PM PDT 24 3412434374 ps
T1292 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1645146997 Aug 06 08:24:08 PM PDT 24 Aug 06 09:25:50 PM PDT 24 16934077400 ps
T1293 /workspace/coverage/default/0.chip_sw_csrng_kat_test.317297 Aug 06 08:24:10 PM PDT 24 Aug 06 08:27:50 PM PDT 24 2909831368 ps
T1294 /workspace/coverage/default/2.rom_e2e_self_hash.3089841410 Aug 06 08:45:41 PM PDT 24 Aug 06 10:39:47 PM PDT 24 26106789726 ps
T1295 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3334755246 Aug 06 08:26:48 PM PDT 24 Aug 06 08:34:05 PM PDT 24 6115422886 ps
T1296 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2350391045 Aug 06 08:35:53 PM PDT 24 Aug 06 10:00:04 PM PDT 24 14724663982 ps
T1297 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2501688197 Aug 06 08:21:28 PM PDT 24 Aug 06 08:26:37 PM PDT 24 3105812754 ps
T1298 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3680239396 Aug 06 08:23:43 PM PDT 24 Aug 06 08:52:13 PM PDT 24 8053601168 ps
T855 /workspace/coverage/default/5.chip_sw_all_escalation_resets.2320172633 Aug 06 08:44:49 PM PDT 24 Aug 06 08:57:43 PM PDT 24 4504364000 ps
T1299 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.3594972084 Aug 06 08:26:14 PM PDT 24 Aug 06 08:31:33 PM PDT 24 2942947661 ps
T352 /workspace/coverage/default/1.chip_sw_pattgen_ios.4252089037 Aug 06 08:27:09 PM PDT 24 Aug 06 08:31:59 PM PDT 24 2901973550 ps
T320 /workspace/coverage/default/0.chip_plic_all_irqs_20.1935565643 Aug 06 08:22:11 PM PDT 24 Aug 06 08:36:37 PM PDT 24 5216349584 ps
T1300 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2070913860 Aug 06 08:25:22 PM PDT 24 Aug 06 09:35:22 PM PDT 24 17129556550 ps
T337 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.865427196 Aug 06 08:24:55 PM PDT 24 Aug 06 08:40:26 PM PDT 24 5368038160 ps
T1301 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.4035666571 Aug 06 08:32:39 PM PDT 24 Aug 06 08:37:29 PM PDT 24 2917224165 ps
T810 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1965791899 Aug 06 08:45:29 PM PDT 24 Aug 06 08:53:38 PM PDT 24 3909321000 ps
T1302 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.504355369 Aug 06 08:24:04 PM PDT 24 Aug 06 08:48:20 PM PDT 24 8221887998 ps
T1303 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2841255789 Aug 06 08:20:25 PM PDT 24 Aug 06 08:26:09 PM PDT 24 3302490340 ps
T147 /workspace/coverage/default/2.chip_jtag_csr_rw.1790879889 Aug 06 08:30:09 PM PDT 24 Aug 06 08:35:36 PM PDT 24 4415348988 ps
T1304 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.930937960 Aug 06 08:35:52 PM PDT 24 Aug 06 08:51:43 PM PDT 24 7781514488 ps
T331 /workspace/coverage/default/2.chip_plic_all_irqs_0.4062465587 Aug 06 08:37:27 PM PDT 24 Aug 06 08:56:24 PM PDT 24 6109317640 ps
T1305 /workspace/coverage/default/94.chip_sw_all_escalation_resets.41302538 Aug 06 08:46:27 PM PDT 24 Aug 06 08:57:57 PM PDT 24 4576540400 ps
T1306 /workspace/coverage/default/0.chip_tap_straps_prod.2812718466 Aug 06 08:24:29 PM PDT 24 Aug 06 08:36:19 PM PDT 24 7219964589 ps
T186 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.2905619347 Aug 06 08:23:40 PM PDT 24 Aug 06 09:52:59 PM PDT 24 42928522800 ps
T1307 /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.473121618 Aug 06 08:45:09 PM PDT 24 Aug 06 08:51:04 PM PDT 24 3964443220 ps
T1308 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3127129744 Aug 06 08:22:37 PM PDT 24 Aug 06 08:33:23 PM PDT 24 3660539999 ps
T1309 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.670766918 Aug 06 08:22:26 PM PDT 24 Aug 06 08:34:16 PM PDT 24 5027212908 ps
T145 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.3684450800 Aug 06 08:38:07 PM PDT 24 Aug 06 09:31:11 PM PDT 24 20477894059 ps
T1310 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1762418439 Aug 06 08:35:30 PM PDT 24 Aug 06 09:54:50 PM PDT 24 18408272392 ps
T1311 /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2668392674 Aug 06 08:43:25 PM PDT 24 Aug 06 09:39:35 PM PDT 24 14681601616 ps
T837 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1340832509 Aug 06 08:44:49 PM PDT 24 Aug 06 08:50:52 PM PDT 24 3234385872 ps
T1312 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.3366664842 Aug 06 08:29:48 PM PDT 24 Aug 06 09:38:07 PM PDT 24 15525469456 ps
T1313 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1863726421 Aug 06 08:26:00 PM PDT 24 Aug 06 09:04:09 PM PDT 24 11519923732 ps
T780 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.3461837482 Aug 06 08:41:30 PM PDT 24 Aug 06 08:49:58 PM PDT 24 3750600008 ps
T1314 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3293898717 Aug 06 08:23:24 PM PDT 24 Aug 06 08:34:41 PM PDT 24 5683485416 ps
T798 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.857062917 Aug 06 08:47:16 PM PDT 24 Aug 06 08:55:00 PM PDT 24 3879839000 ps
T1315 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.1202528114 Aug 06 08:23:20 PM PDT 24 Aug 06 08:41:09 PM PDT 24 5831540444 ps
T1316 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.367073059 Aug 06 08:24:07 PM PDT 24 Aug 06 08:57:52 PM PDT 24 11143616620 ps
T1317 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1850407688 Aug 06 08:44:04 PM PDT 24 Aug 06 08:56:26 PM PDT 24 6339454570 ps
T1318 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.860964711 Aug 06 08:37:18 PM PDT 24 Aug 06 08:47:16 PM PDT 24 4841495886 ps
T845 /workspace/coverage/default/81.chip_sw_all_escalation_resets.3659491860 Aug 06 08:45:39 PM PDT 24 Aug 06 08:57:36 PM PDT 24 5702348980 ps
T1319 /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2494517803 Aug 06 08:25:08 PM PDT 24 Aug 06 08:35:36 PM PDT 24 9190747507 ps
T1320 /workspace/coverage/default/2.chip_tap_straps_rma.1920024116 Aug 06 08:37:47 PM PDT 24 Aug 06 08:46:23 PM PDT 24 4307666512 ps
T351 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.897097055 Aug 06 08:23:09 PM PDT 24 Aug 06 08:37:08 PM PDT 24 4529224946 ps
T1321 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.4170924845 Aug 06 08:32:13 PM PDT 24 Aug 06 08:38:30 PM PDT 24 6504777064 ps
T1322 /workspace/coverage/default/2.chip_sw_pattgen_ios.2064562170 Aug 06 08:30:13 PM PDT 24 Aug 06 08:35:26 PM PDT 24 2594347320 ps
T1323 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1344412847 Aug 06 08:26:34 PM PDT 24 Aug 06 08:33:08 PM PDT 24 3307173952 ps
T1324 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.59846703 Aug 06 08:45:49 PM PDT 24 Aug 06 08:52:07 PM PDT 24 3892997702 ps
T1325 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2490667686 Aug 06 08:31:45 PM PDT 24 Aug 06 09:46:42 PM PDT 24 17954339592 ps
T1326 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1313374118 Aug 06 08:26:00 PM PDT 24 Aug 06 08:39:06 PM PDT 24 10336647563 ps
T378 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940371085 Aug 06 08:45:31 PM PDT 24 Aug 06 08:53:15 PM PDT 24 4140656640 ps
T56 /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2599111504 Aug 06 08:22:45 PM PDT 24 Aug 06 08:28:12 PM PDT 24 3883884127 ps
T1327 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.408593689 Aug 06 08:34:30 PM PDT 24 Aug 06 08:42:23 PM PDT 24 4136223551 ps
T1328 /workspace/coverage/default/55.chip_sw_all_escalation_resets.4258400438 Aug 06 08:45:01 PM PDT 24 Aug 06 08:55:20 PM PDT 24 4208974704 ps
T1329 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.2318452653 Aug 06 08:22:33 PM PDT 24 Aug 06 08:25:47 PM PDT 24 3513540413 ps
T1330 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3869783342 Aug 06 08:23:54 PM PDT 24 Aug 06 11:42:11 PM PDT 24 58995231309 ps
T1331 /workspace/coverage/default/0.rom_e2e_asm_init_dev.1375927191 Aug 06 08:31:51 PM PDT 24 Aug 06 09:45:45 PM PDT 24 14899349440 ps
T1332 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2461850853 Aug 06 08:25:37 PM PDT 24 Aug 06 09:14:02 PM PDT 24 11273135240 ps
T1333 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2561090584 Aug 06 08:27:49 PM PDT 24 Aug 06 08:44:29 PM PDT 24 10028369384 ps
T1334 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3631416057 Aug 06 08:23:34 PM PDT 24 Aug 06 08:45:06 PM PDT 24 9483047070 ps
T1335 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.745072922 Aug 06 08:28:37 PM PDT 24 Aug 06 08:36:09 PM PDT 24 4012733720 ps
T1336 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1922510437 Aug 06 08:35:09 PM PDT 24 Aug 06 09:56:34 PM PDT 24 14782571544 ps
T1337 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.320402635 Aug 06 08:46:51 PM PDT 24 Aug 06 08:53:38 PM PDT 24 3605960810 ps
T856 /workspace/coverage/default/4.chip_sw_all_escalation_resets.3829822570 Aug 06 08:40:13 PM PDT 24 Aug 06 08:49:47 PM PDT 24 4365907898 ps
T1338 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2896397464 Aug 06 08:40:11 PM PDT 24 Aug 06 08:50:11 PM PDT 24 6705860000 ps
T205 /workspace/coverage/default/0.chip_jtag_csr_rw.2590363335 Aug 06 08:10:36 PM PDT 24 Aug 06 08:32:28 PM PDT 24 12640650651 ps
T1339 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2971996887 Aug 06 08:25:33 PM PDT 24 Aug 06 08:36:47 PM PDT 24 5606856925 ps
T1340 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2153792280 Aug 06 08:20:21 PM PDT 24 Aug 06 08:23:54 PM PDT 24 3130204808 ps
T395 /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2570325751 Aug 06 08:19:57 PM PDT 24 Aug 06 08:24:45 PM PDT 24 3480400664 ps
T1341 /workspace/coverage/default/0.chip_sw_plic_sw_irq.1016258031 Aug 06 08:23:31 PM PDT 24 Aug 06 08:27:27 PM PDT 24 2776246484 ps
T1342 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.110747582 Aug 06 08:29:11 PM PDT 24 Aug 06 08:38:34 PM PDT 24 6688598963 ps
T852 /workspace/coverage/default/37.chip_sw_all_escalation_resets.1055623228 Aug 06 08:42:18 PM PDT 24 Aug 06 08:52:41 PM PDT 24 5587043912 ps
T1343 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.3178642894 Aug 06 08:30:01 PM PDT 24 Aug 06 09:41:15 PM PDT 24 14929973320 ps
T1344 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.646556033 Aug 06 08:41:12 PM PDT 24 Aug 06 09:09:47 PM PDT 24 8034095300 ps
T1345 /workspace/coverage/default/2.chip_sw_example_concurrency.3543312896 Aug 06 08:32:23 PM PDT 24 Aug 06 08:36:31 PM PDT 24 3143705778 ps
T171 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1674629677 Aug 06 08:26:47 PM PDT 24 Aug 06 08:36:58 PM PDT 24 5925992784 ps
T1346 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3856578078 Aug 06 08:35:11 PM PDT 24 Aug 06 09:39:30 PM PDT 24 14721445970 ps
T50 /workspace/coverage/default/2.chip_sw_alert_test.2100437861 Aug 06 08:33:16 PM PDT 24 Aug 06 08:38:40 PM PDT 24 2819685752 ps
T325 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2585311960 Aug 06 08:23:50 PM PDT 24 Aug 06 08:59:10 PM PDT 24 11781366072 ps
T1347 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.1768687853 Aug 06 08:23:35 PM PDT 24 Aug 06 08:32:25 PM PDT 24 5001018760 ps
T1348 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3285129561 Aug 06 08:40:36 PM PDT 24 Aug 06 09:01:33 PM PDT 24 8043266884 ps
T1349 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1534460939 Aug 06 08:48:28 PM PDT 24 Aug 06 08:55:13 PM PDT 24 3654531264 ps
T1350 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2501705192 Aug 06 08:36:01 PM PDT 24 Aug 06 09:00:45 PM PDT 24 6482200820 ps
T1351 /workspace/coverage/default/0.chip_sw_hmac_enc.3049959548 Aug 06 08:22:21 PM PDT 24 Aug 06 08:28:53 PM PDT 24 3534867232 ps
T1352 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.2111956 Aug 06 08:23:05 PM PDT 24 Aug 06 08:32:49 PM PDT 24 4237852128 ps
T1353 /workspace/coverage/default/2.chip_sw_example_rom.2402682994 Aug 06 08:31:15 PM PDT 24 Aug 06 08:33:16 PM PDT 24 2757104648 ps
T1354 /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.1148640433 Aug 06 08:41:14 PM PDT 24 Aug 06 09:14:44 PM PDT 24 23978321016 ps
T1355 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1350047036 Aug 06 08:36:32 PM PDT 24 Aug 06 08:44:09 PM PDT 24 5186862748 ps
T256 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2817063588 Aug 06 08:45:09 PM PDT 24 Aug 06 08:52:19 PM PDT 24 4139532778 ps
T1356 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2677596201 Aug 06 08:26:22 PM PDT 24 Aug 06 08:38:27 PM PDT 24 4976048320 ps
T1357 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.362849716 Aug 06 08:25:18 PM PDT 24 Aug 06 08:36:54 PM PDT 24 4943093400 ps
T714 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.1739492040 Aug 06 08:26:15 PM PDT 24 Aug 06 08:34:26 PM PDT 24 4644005580 ps
T1358 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.692572180 Aug 06 08:40:04 PM PDT 24 Aug 06 08:43:25 PM PDT 24 2228229072 ps
T1359 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.211113032 Aug 06 08:30:04 PM PDT 24 Aug 06 10:06:39 PM PDT 24 49256088764 ps
T327 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.444197273 Aug 06 08:26:32 PM PDT 24 Aug 06 08:54:13 PM PDT 24 6185816416 ps
T1360 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1856368779 Aug 06 08:47:41 PM PDT 24 Aug 06 08:55:03 PM PDT 24 3627199408 ps
T1361 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.847283575 Aug 06 08:26:37 PM PDT 24 Aug 06 09:26:30 PM PDT 24 14067543698 ps
T1362 /workspace/coverage/default/2.chip_sw_power_idle_load.1855788623 Aug 06 08:40:51 PM PDT 24 Aug 06 08:52:01 PM PDT 24 3624601960 ps
T1363 /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.989468244 Aug 06 08:26:20 PM PDT 24 Aug 06 08:37:35 PM PDT 24 9590908042 ps
T1364 /workspace/coverage/default/1.rom_e2e_smoke.3778472843 Aug 06 08:29:55 PM PDT 24 Aug 06 09:34:52 PM PDT 24 14695043150 ps
T1365 /workspace/coverage/default/2.chip_sw_otbn_randomness.1709250229 Aug 06 08:31:51 PM PDT 24 Aug 06 08:48:19 PM PDT 24 5922454296 ps
T1366 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3999240746 Aug 06 08:24:40 PM PDT 24 Aug 06 08:57:25 PM PDT 24 7550269200 ps
T1367 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.1553528824 Aug 06 08:30:07 PM PDT 24 Aug 06 09:28:36 PM PDT 24 14891202620 ps
T203 /workspace/coverage/default/2.chip_sw_spi_device_pass_through.1276939694 Aug 06 08:27:21 PM PDT 24 Aug 06 08:41:15 PM PDT 24 6658304865 ps
T1368 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1797707820 Aug 06 08:25:19 PM PDT 24 Aug 06 08:34:29 PM PDT 24 6043594440 ps
T1369 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3261812877 Aug 06 08:27:06 PM PDT 24 Aug 06 08:31:33 PM PDT 24 3439710040 ps
T1370 /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.913801757 Aug 06 08:45:48 PM PDT 24 Aug 06 08:53:39 PM PDT 24 3467463928 ps
T1371 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.4020731795 Aug 06 08:21:44 PM PDT 24 Aug 06 08:30:01 PM PDT 24 4351480890 ps
T1372 /workspace/coverage/default/3.chip_sw_uart_tx_rx.558518421 Aug 06 08:41:49 PM PDT 24 Aug 06 08:56:35 PM PDT 24 4742463068 ps
T1373 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1841295717 Aug 06 08:41:47 PM PDT 24 Aug 06 08:56:36 PM PDT 24 11379952491 ps
T1374 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1763713973 Aug 06 08:27:46 PM PDT 24 Aug 06 10:05:29 PM PDT 24 45908930520 ps
T1375 /workspace/coverage/default/2.chip_sw_flash_init.3613866915 Aug 06 08:26:28 PM PDT 24 Aug 06 08:58:47 PM PDT 24 16056833215 ps
T373 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.826276720 Aug 06 08:25:38 PM PDT 24 Aug 06 08:33:40 PM PDT 24 6835429926 ps
T1376 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1861195647 Aug 06 08:41:24 PM PDT 24 Aug 06 08:55:15 PM PDT 24 5578515256 ps
T1377 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.843929731 Aug 06 08:28:34 PM PDT 24 Aug 06 08:30:07 PM PDT 24 2224250170 ps
T1378 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2222951458 Aug 06 08:25:11 PM PDT 24 Aug 06 08:28:52 PM PDT 24 2338799141 ps
T1379 /workspace/coverage/default/1.rom_e2e_static_critical.3150859882 Aug 06 08:30:47 PM PDT 24 Aug 06 09:46:06 PM PDT 24 16828380100 ps
T1380 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.2933768564 Aug 06 08:22:18 PM PDT 24 Aug 06 08:57:31 PM PDT 24 9288049859 ps
T839 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3261818565 Aug 06 08:46:02 PM PDT 24 Aug 06 08:52:50 PM PDT 24 3106218770 ps
T1381 /workspace/coverage/default/0.chip_sw_hmac_smoketest.2935772697 Aug 06 08:26:23 PM PDT 24 Aug 06 08:33:01 PM PDT 24 3465041168 ps
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