Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.49 93.82 95.32 94.57 97.35 99.55


Total test records in report: 2932
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html
T426 /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3203396307 Aug 06 08:43:00 PM PDT 24 Aug 06 09:25:02 PM PDT 24 12877203214 ps
T427 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.4269959473 Aug 06 08:22:14 PM PDT 24 Aug 06 08:51:45 PM PDT 24 25868861092 ps
T1063 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.123632490 Aug 06 08:28:33 PM PDT 24 Aug 06 08:39:15 PM PDT 24 10135205232 ps
T1064 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3880527937 Aug 06 08:21:36 PM PDT 24 Aug 06 08:35:40 PM PDT 24 4633703730 ps
T1065 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.1678286915 Aug 06 08:31:51 PM PDT 24 Aug 06 08:38:49 PM PDT 24 6287259724 ps
T716 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2285985251 Aug 06 08:21:46 PM PDT 24 Aug 06 08:23:42 PM PDT 24 3217185618 ps
T1066 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2603346537 Aug 06 08:38:26 PM PDT 24 Aug 06 08:50:06 PM PDT 24 4321337728 ps
T1067 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3881482916 Aug 06 08:23:03 PM PDT 24 Aug 06 08:33:20 PM PDT 24 5223834941 ps
T813 /workspace/coverage/default/39.chip_sw_all_escalation_resets.1466961912 Aug 06 08:43:15 PM PDT 24 Aug 06 08:53:04 PM PDT 24 4802056264 ps
T104 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3216974581 Aug 06 08:37:48 PM PDT 24 Aug 06 08:43:59 PM PDT 24 3856163260 ps
T441 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2302845681 Aug 06 08:36:29 PM PDT 24 Aug 06 08:48:09 PM PDT 24 3814922630 ps
T442 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.3595142534 Aug 06 08:27:21 PM PDT 24 Aug 06 09:08:56 PM PDT 24 11772326625 ps
T443 /workspace/coverage/default/2.rom_keymgr_functest.3292223737 Aug 06 08:38:59 PM PDT 24 Aug 06 08:48:09 PM PDT 24 3671209152 ps
T444 /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2261297133 Aug 06 08:36:47 PM PDT 24 Aug 06 08:48:35 PM PDT 24 4539548248 ps
T445 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1869862670 Aug 06 08:29:36 PM PDT 24 Aug 06 09:32:47 PM PDT 24 15008586077 ps
T446 /workspace/coverage/default/32.chip_sw_all_escalation_resets.1614194008 Aug 06 08:44:23 PM PDT 24 Aug 06 08:54:31 PM PDT 24 5816608306 ps
T447 /workspace/coverage/default/0.chip_sw_otbn_smoketest.1797465559 Aug 06 08:22:02 PM PDT 24 Aug 06 08:43:05 PM PDT 24 4973335604 ps
T448 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2209607252 Aug 06 08:25:33 PM PDT 24 Aug 06 08:29:50 PM PDT 24 3294288428 ps
T449 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.4132535763 Aug 06 08:41:01 PM PDT 24 Aug 06 08:56:24 PM PDT 24 9375412554 ps
T838 /workspace/coverage/default/61.chip_sw_all_escalation_resets.2221079304 Aug 06 08:45:10 PM PDT 24 Aug 06 08:57:27 PM PDT 24 5599611176 ps
T1068 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.3451257898 Aug 06 08:28:10 PM PDT 24 Aug 06 09:23:47 PM PDT 24 10693144152 ps
T1069 /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2674288542 Aug 06 08:39:09 PM PDT 24 Aug 06 08:43:43 PM PDT 24 3735577200 ps
T1070 /workspace/coverage/default/0.chip_sival_flash_info_access.1039651912 Aug 06 08:21:31 PM PDT 24 Aug 06 08:27:00 PM PDT 24 2864311960 ps
T1071 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2275110422 Aug 06 08:31:46 PM PDT 24 Aug 06 08:41:38 PM PDT 24 5350441896 ps
T1072 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.777313312 Aug 06 08:36:10 PM PDT 24 Aug 06 08:40:36 PM PDT 24 3123664000 ps
T1073 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2656002266 Aug 06 08:23:45 PM PDT 24 Aug 06 08:36:55 PM PDT 24 5857225022 ps
T39 /workspace/coverage/default/0.chip_sw_power_virus.2952561319 Aug 06 08:29:33 PM PDT 24 Aug 06 08:57:50 PM PDT 24 5926983824 ps
T35 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3515521960 Aug 06 08:23:05 PM PDT 24 Aug 06 08:30:23 PM PDT 24 6588262096 ps
T1074 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3671978585 Aug 06 08:21:57 PM PDT 24 Aug 06 08:29:37 PM PDT 24 5036519472 ps
T1075 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3478457666 Aug 06 08:29:18 PM PDT 24 Aug 06 08:34:09 PM PDT 24 3557429160 ps
T1076 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.372196735 Aug 06 08:25:03 PM PDT 24 Aug 06 08:46:29 PM PDT 24 11233046580 ps
T1077 /workspace/coverage/default/2.chip_sw_power_sleep_load.1911475003 Aug 06 08:38:37 PM PDT 24 Aug 06 08:53:06 PM PDT 24 10835074384 ps
T834 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.2793534884 Aug 06 08:49:17 PM PDT 24 Aug 06 08:55:24 PM PDT 24 3710631464 ps
T1078 /workspace/coverage/default/0.chip_sw_edn_kat.2539763920 Aug 06 08:23:48 PM PDT 24 Aug 06 08:35:12 PM PDT 24 3855069908 ps
T1079 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2046048143 Aug 06 08:24:55 PM PDT 24 Aug 06 08:37:33 PM PDT 24 4561117572 ps
T1080 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2600066730 Aug 06 08:25:34 PM PDT 24 Aug 06 08:36:23 PM PDT 24 4473020220 ps
T1081 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3756265819 Aug 06 08:24:53 PM PDT 24 Aug 06 08:45:40 PM PDT 24 6200980016 ps
T1082 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.756556135 Aug 06 08:25:07 PM PDT 24 Aug 06 09:13:32 PM PDT 24 13481909000 ps
T787 /workspace/coverage/default/3.chip_sw_all_escalation_resets.3347024186 Aug 06 08:40:13 PM PDT 24 Aug 06 08:49:20 PM PDT 24 5557918300 ps
T791 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2386104095 Aug 06 08:49:52 PM PDT 24 Aug 06 08:55:37 PM PDT 24 3892994846 ps
T1083 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.902186246 Aug 06 08:35:32 PM PDT 24 Aug 06 09:26:17 PM PDT 24 12871103068 ps
T1084 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.41133650 Aug 06 08:23:17 PM PDT 24 Aug 06 08:31:10 PM PDT 24 4778991058 ps
T853 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3251961434 Aug 06 08:44:39 PM PDT 24 Aug 06 08:56:48 PM PDT 24 4480246948 ps
T1085 /workspace/coverage/default/0.chip_sw_kmac_idle.1697477724 Aug 06 08:25:18 PM PDT 24 Aug 06 08:29:13 PM PDT 24 2565325082 ps
T1086 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.970922359 Aug 06 08:27:34 PM PDT 24 Aug 06 10:20:53 PM PDT 24 23916351736 ps
T795 /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.1318776595 Aug 06 08:41:26 PM PDT 24 Aug 06 08:49:37 PM PDT 24 3339612086 ps
T778 /workspace/coverage/default/15.chip_sw_all_escalation_resets.2980753835 Aug 06 08:44:27 PM PDT 24 Aug 06 08:56:19 PM PDT 24 5008470800 ps
T1087 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2155797998 Aug 06 08:40:51 PM PDT 24 Aug 06 08:48:09 PM PDT 24 4189751600 ps
T1088 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.466063359 Aug 06 08:23:45 PM PDT 24 Aug 06 08:39:21 PM PDT 24 7427371230 ps
T1089 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.35410362 Aug 06 08:24:41 PM PDT 24 Aug 06 08:32:23 PM PDT 24 4178959096 ps
T1090 /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.1715222778 Aug 06 08:28:30 PM PDT 24 Aug 06 08:35:34 PM PDT 24 4531717764 ps
T796 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3850921141 Aug 06 08:45:37 PM PDT 24 Aug 06 08:52:23 PM PDT 24 3989571620 ps
T1091 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1098614272 Aug 06 08:42:41 PM PDT 24 Aug 06 08:54:40 PM PDT 24 7410973351 ps
T1092 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.700892667 Aug 06 08:21:54 PM PDT 24 Aug 06 08:26:51 PM PDT 24 5193606888 ps
T1093 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1395784388 Aug 06 08:22:00 PM PDT 24 Aug 06 08:29:23 PM PDT 24 4533184520 ps
T1094 /workspace/coverage/default/2.chip_sw_csrng_kat_test.1444377473 Aug 06 08:34:39 PM PDT 24 Aug 06 08:39:28 PM PDT 24 2593652334 ps
T273 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.2603205200 Aug 06 08:25:41 PM PDT 24 Aug 06 08:47:00 PM PDT 24 10667360556 ps
T1095 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.734607216 Aug 06 08:20:47 PM PDT 24 Aug 06 08:31:40 PM PDT 24 4501348828 ps
T1096 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.2050076421 Aug 06 08:23:14 PM PDT 24 Aug 07 12:43:59 AM PDT 24 78869753000 ps
T1097 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4056928394 Aug 06 08:33:26 PM PDT 24 Aug 06 10:19:40 PM PDT 24 24484244072 ps
T1098 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.979979187 Aug 06 08:27:27 PM PDT 24 Aug 06 08:32:27 PM PDT 24 3108804200 ps
T1099 /workspace/coverage/default/1.chip_sw_edn_sw_mode.2489807156 Aug 06 08:24:14 PM PDT 24 Aug 06 08:57:27 PM PDT 24 8305608692 ps
T1100 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1168749553 Aug 06 08:27:18 PM PDT 24 Aug 06 08:45:24 PM PDT 24 7386726700 ps
T1101 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1047375500 Aug 06 08:40:44 PM PDT 24 Aug 06 08:52:58 PM PDT 24 4045569212 ps
T1102 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1431080186 Aug 06 08:32:11 PM PDT 24 Aug 06 09:41:34 PM PDT 24 15096036622 ps
T304 /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1548216029 Aug 06 08:38:51 PM PDT 24 Aug 06 08:48:54 PM PDT 24 4547897540 ps
T199 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3738464254 Aug 06 08:23:35 PM PDT 24 Aug 06 08:32:51 PM PDT 24 4394101431 ps
T1103 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2102874690 Aug 06 08:42:26 PM PDT 24 Aug 06 09:09:27 PM PDT 24 8035672592 ps
T717 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.4134241356 Aug 06 08:22:07 PM PDT 24 Aug 06 08:24:35 PM PDT 24 2789417131 ps
T836 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2265639762 Aug 06 08:47:05 PM PDT 24 Aug 06 08:53:49 PM PDT 24 4023055420 ps
T1104 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.2485016673 Aug 06 08:23:53 PM PDT 24 Aug 06 08:28:13 PM PDT 24 2576406120 ps
T1105 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.636738800 Aug 06 08:22:52 PM PDT 24 Aug 06 08:52:32 PM PDT 24 8958866424 ps
T1106 /workspace/coverage/default/0.chip_sw_example_concurrency.4002771857 Aug 06 08:22:20 PM PDT 24 Aug 06 08:27:37 PM PDT 24 3011895500 ps
T1107 /workspace/coverage/default/2.chip_sw_hmac_enc.2261083054 Aug 06 08:35:19 PM PDT 24 Aug 06 08:39:50 PM PDT 24 3395680700 ps
T1108 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1772225753 Aug 06 08:25:44 PM PDT 24 Aug 06 08:32:10 PM PDT 24 2803519902 ps
T549 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2089877238 Aug 06 08:23:50 PM PDT 24 Aug 06 08:41:12 PM PDT 24 5362244080 ps
T1109 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.1710264314 Aug 06 08:26:09 PM PDT 24 Aug 06 08:33:10 PM PDT 24 6178511049 ps
T835 /workspace/coverage/default/10.chip_sw_all_escalation_resets.1006954320 Aug 06 08:41:46 PM PDT 24 Aug 06 08:52:14 PM PDT 24 5972655898 ps
T1110 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1784220087 Aug 06 08:29:43 PM PDT 24 Aug 06 08:53:15 PM PDT 24 7343190740 ps
T324 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.1483909795 Aug 06 08:32:03 PM PDT 24 Aug 06 09:02:21 PM PDT 24 11936376000 ps
T1111 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.2030695266 Aug 06 08:37:13 PM PDT 24 Aug 06 08:51:09 PM PDT 24 6624078328 ps
T1112 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2107747215 Aug 06 08:24:58 PM PDT 24 Aug 06 08:28:21 PM PDT 24 2246873208 ps
T1113 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1407358891 Aug 06 08:27:06 PM PDT 24 Aug 06 08:51:51 PM PDT 24 16456581911 ps
T825 /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3126849696 Aug 06 08:47:07 PM PDT 24 Aug 06 08:54:19 PM PDT 24 4132966610 ps
T96 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.456230457 Aug 06 08:25:39 PM PDT 24 Aug 06 08:54:09 PM PDT 24 24136533356 ps
T799 /workspace/coverage/default/68.chip_sw_all_escalation_resets.2444332381 Aug 06 08:45:01 PM PDT 24 Aug 06 08:54:41 PM PDT 24 5661844784 ps
T1114 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.1122072911 Aug 06 08:28:35 PM PDT 24 Aug 06 09:49:28 PM PDT 24 15560992344 ps
T1115 /workspace/coverage/default/1.chip_tap_straps_prod.3587455685 Aug 06 08:22:53 PM PDT 24 Aug 06 08:24:58 PM PDT 24 2739308354 ps
T155 /workspace/coverage/default/2.chip_plic_all_irqs_10.1084494591 Aug 06 08:37:46 PM PDT 24 Aug 06 08:48:56 PM PDT 24 4089815848 ps
T409 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.2782115361 Aug 06 08:25:49 PM PDT 24 Aug 06 08:35:32 PM PDT 24 8725640128 ps
T1116 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1386988661 Aug 06 08:24:50 PM PDT 24 Aug 06 09:09:31 PM PDT 24 9465718300 ps
T764 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3398041158 Aug 06 08:44:18 PM PDT 24 Aug 06 08:50:52 PM PDT 24 4471005564 ps
T377 /workspace/coverage/default/20.chip_sw_all_escalation_resets.201565691 Aug 06 08:42:40 PM PDT 24 Aug 06 08:53:37 PM PDT 24 5370821470 ps
T136 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.148318204 Aug 06 08:40:48 PM PDT 24 Aug 06 08:53:34 PM PDT 24 8518614950 ps
T1117 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.394391547 Aug 06 08:22:22 PM PDT 24 Aug 06 08:28:18 PM PDT 24 2429746574 ps
T461 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1408938354 Aug 06 08:21:49 PM PDT 24 Aug 06 09:28:27 PM PDT 24 25134550033 ps
T1118 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2909561761 Aug 06 08:25:04 PM PDT 24 Aug 06 09:09:42 PM PDT 24 36518847629 ps
T1119 /workspace/coverage/default/4.chip_sw_data_integrity_escalation.2236395314 Aug 06 08:42:08 PM PDT 24 Aug 06 08:55:07 PM PDT 24 6377989000 ps
T1120 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.523689812 Aug 06 08:22:42 PM PDT 24 Aug 06 08:26:56 PM PDT 24 2678658836 ps
T1121 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3247211089 Aug 06 08:25:29 PM PDT 24 Aug 06 08:28:45 PM PDT 24 3053903780 ps
T1122 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1257096919 Aug 06 08:36:59 PM PDT 24 Aug 06 08:46:56 PM PDT 24 4213743178 ps
T1123 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.976664697 Aug 06 08:21:34 PM PDT 24 Aug 06 08:29:12 PM PDT 24 6151195552 ps
T1124 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.492834055 Aug 06 08:24:31 PM PDT 24 Aug 06 08:36:18 PM PDT 24 4471907320 ps
T1125 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.2362536013 Aug 06 08:22:34 PM PDT 24 Aug 06 08:30:06 PM PDT 24 4093593256 ps
T803 /workspace/coverage/default/59.chip_sw_all_escalation_resets.4213492262 Aug 06 08:45:53 PM PDT 24 Aug 06 08:55:38 PM PDT 24 4607317212 ps
T1126 /workspace/coverage/default/2.chip_sw_hmac_multistream.957169924 Aug 06 08:36:32 PM PDT 24 Aug 06 09:10:51 PM PDT 24 7488611348 ps
T32 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2496459659 Aug 06 08:27:16 PM PDT 24 Aug 06 08:32:55 PM PDT 24 3563269336 ps
T842 /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1420436405 Aug 06 08:45:50 PM PDT 24 Aug 06 08:52:43 PM PDT 24 3902196092 ps
T1127 /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3686110133 Aug 06 08:28:44 PM PDT 24 Aug 06 09:00:38 PM PDT 24 28284953933 ps
T766 /workspace/coverage/default/76.chip_sw_all_escalation_resets.867843220 Aug 06 08:49:13 PM PDT 24 Aug 06 09:01:08 PM PDT 24 4769925228 ps
T1128 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3845682283 Aug 06 08:21:59 PM PDT 24 Aug 06 08:47:04 PM PDT 24 7865048011 ps
T1129 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1952645318 Aug 06 08:25:43 PM PDT 24 Aug 06 08:49:06 PM PDT 24 7595779212 ps
T1130 /workspace/coverage/default/28.chip_sw_all_escalation_resets.1978396272 Aug 06 08:42:59 PM PDT 24 Aug 06 08:56:02 PM PDT 24 4711758200 ps
T815 /workspace/coverage/default/31.chip_sw_all_escalation_resets.1277529765 Aug 06 08:43:56 PM PDT 24 Aug 06 08:56:59 PM PDT 24 5958908496 ps
T1131 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3765869275 Aug 06 08:24:31 PM PDT 24 Aug 06 08:29:25 PM PDT 24 3138820750 ps
T814 /workspace/coverage/default/88.chip_sw_all_escalation_resets.1975054534 Aug 06 08:48:11 PM PDT 24 Aug 06 08:58:03 PM PDT 24 5405571992 ps
T1132 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.4294562677 Aug 06 08:40:40 PM PDT 24 Aug 06 10:05:43 PM PDT 24 20481808208 ps
T1133 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3933207364 Aug 06 08:25:42 PM PDT 24 Aug 06 08:38:46 PM PDT 24 4409813066 ps
T70 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3279787525 Aug 06 08:20:58 PM PDT 24 Aug 06 08:28:53 PM PDT 24 5416301094 ps
T1134 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.2109245649 Aug 06 08:43:29 PM PDT 24 Aug 06 08:53:09 PM PDT 24 4337324720 ps
T242 /workspace/coverage/default/83.chip_sw_all_escalation_resets.1164841379 Aug 06 08:53:04 PM PDT 24 Aug 06 09:03:32 PM PDT 24 5641889418 ps
T1135 /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3525958576 Aug 06 08:22:28 PM PDT 24 Aug 06 08:28:05 PM PDT 24 4478785420 ps
T68 /workspace/coverage/default/3.chip_tap_straps_rma.1818977210 Aug 06 08:39:22 PM PDT 24 Aug 06 08:41:58 PM PDT 24 2791288707 ps
T817 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3227528419 Aug 06 08:46:35 PM PDT 24 Aug 06 09:00:41 PM PDT 24 6144831928 ps
T1136 /workspace/coverage/default/3.chip_tap_straps_dev.3591767047 Aug 06 08:40:10 PM PDT 24 Aug 06 09:05:55 PM PDT 24 15375240845 ps
T1137 /workspace/coverage/default/4.chip_tap_straps_dev.2528481625 Aug 06 08:40:23 PM PDT 24 Aug 06 08:43:49 PM PDT 24 3027819433 ps
T1138 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1816062365 Aug 06 08:27:22 PM PDT 24 Aug 06 08:51:09 PM PDT 24 9255427400 ps
T91 /workspace/coverage/default/43.chip_sw_all_escalation_resets.4070856526 Aug 06 08:44:40 PM PDT 24 Aug 06 08:55:59 PM PDT 24 4917677580 ps
T1139 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.618778118 Aug 06 08:23:45 PM PDT 24 Aug 06 08:34:47 PM PDT 24 5801888202 ps
T330 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.4139246700 Aug 06 08:25:19 PM PDT 24 Aug 06 08:34:47 PM PDT 24 4217284784 ps
T1140 /workspace/coverage/default/1.rom_e2e_asm_init_dev.278487551 Aug 06 08:35:22 PM PDT 24 Aug 06 09:49:31 PM PDT 24 16181406176 ps
T54 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.576182080 Aug 06 08:24:02 PM PDT 24 Aug 06 08:30:32 PM PDT 24 4120558470 ps
T200 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1765944596 Aug 06 08:24:07 PM PDT 24 Aug 06 08:33:40 PM PDT 24 5078623964 ps
T1141 /workspace/coverage/default/2.chip_sw_aes_idle.3094966105 Aug 06 08:34:51 PM PDT 24 Aug 06 08:41:04 PM PDT 24 3090820466 ps
T1142 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.3661368915 Aug 06 08:26:26 PM PDT 24 Aug 06 08:52:05 PM PDT 24 7853076612 ps
T1143 /workspace/coverage/default/0.chip_sw_uart_smoketest.3269341144 Aug 06 08:26:10 PM PDT 24 Aug 06 08:29:58 PM PDT 24 3440825048 ps
T1144 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3840396290 Aug 06 08:21:59 PM PDT 24 Aug 06 08:43:12 PM PDT 24 6393249734 ps
T793 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2452463327 Aug 06 08:43:58 PM PDT 24 Aug 06 08:49:30 PM PDT 24 4150700084 ps
T1145 /workspace/coverage/default/0.rom_keymgr_functest.1656454323 Aug 06 08:23:46 PM PDT 24 Aug 06 08:33:26 PM PDT 24 4475459990 ps
T1146 /workspace/coverage/default/0.rom_volatile_raw_unlock.3639024571 Aug 06 08:27:01 PM PDT 24 Aug 06 08:28:57 PM PDT 24 2739827076 ps
T1147 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.1030327940 Aug 06 08:43:23 PM PDT 24 Aug 06 09:08:28 PM PDT 24 8501275774 ps
T848 /workspace/coverage/default/34.chip_sw_all_escalation_resets.4251166554 Aug 06 08:45:00 PM PDT 24 Aug 06 08:56:42 PM PDT 24 5492437080 ps
T1148 /workspace/coverage/default/2.chip_sw_edn_kat.3864053939 Aug 06 08:35:12 PM PDT 24 Aug 06 08:48:12 PM PDT 24 3157878096 ps
T1149 /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.202718064 Aug 06 08:34:15 PM PDT 24 Aug 06 08:38:27 PM PDT 24 2931907174 ps
T1150 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1025889916 Aug 06 08:23:23 PM PDT 24 Aug 06 08:33:22 PM PDT 24 4177460460 ps
T1151 /workspace/coverage/default/0.chip_sw_gpio_smoketest.1911841253 Aug 06 08:26:13 PM PDT 24 Aug 06 08:30:21 PM PDT 24 2746173560 ps
T1152 /workspace/coverage/default/1.chip_sw_example_rom.4227894235 Aug 06 08:25:18 PM PDT 24 Aug 06 08:27:22 PM PDT 24 2365592512 ps
T826 /workspace/coverage/default/77.chip_sw_all_escalation_resets.4185462554 Aug 06 08:47:26 PM PDT 24 Aug 06 08:58:26 PM PDT 24 5015707324 ps
T388 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.997338354 Aug 06 08:21:14 PM PDT 24 Aug 06 08:31:47 PM PDT 24 5609369264 ps
T1153 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.1836709637 Aug 06 08:42:42 PM PDT 24 Aug 06 09:23:38 PM PDT 24 13281249644 ps
T1154 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3855799051 Aug 06 08:24:04 PM PDT 24 Aug 06 08:35:55 PM PDT 24 6690335753 ps
T1155 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2099800485 Aug 06 08:21:44 PM PDT 24 Aug 06 08:33:24 PM PDT 24 4007310502 ps
T1156 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1141969806 Aug 06 08:37:51 PM PDT 24 Aug 06 08:47:02 PM PDT 24 4672949464 ps
T1157 /workspace/coverage/default/1.chip_sw_uart_smoketest.1475699981 Aug 06 08:23:04 PM PDT 24 Aug 06 08:27:16 PM PDT 24 2840572840 ps
T1158 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2942785353 Aug 06 08:29:06 PM PDT 24 Aug 06 09:29:11 PM PDT 24 15560661188 ps
T1159 /workspace/coverage/default/1.chip_sw_aes_smoketest.568103243 Aug 06 08:25:22 PM PDT 24 Aug 06 08:29:15 PM PDT 24 2936494040 ps
T25 /workspace/coverage/default/0.chip_sw_gpio.2867460019 Aug 06 08:24:26 PM PDT 24 Aug 06 08:32:55 PM PDT 24 3149828840 ps
T1160 /workspace/coverage/default/2.chip_sw_aes_smoketest.3735528113 Aug 06 08:38:52 PM PDT 24 Aug 06 08:45:32 PM PDT 24 3042442808 ps
T1161 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.607508589 Aug 06 08:19:46 PM PDT 24 Aug 06 08:36:16 PM PDT 24 6046139594 ps
T204 /workspace/coverage/default/0.chip_jtag_mem_access.2115244555 Aug 06 08:10:29 PM PDT 24 Aug 06 08:32:20 PM PDT 24 13665686604 ps
T1162 /workspace/coverage/default/2.chip_tap_straps_prod.807785532 Aug 06 08:37:08 PM PDT 24 Aug 06 09:02:21 PM PDT 24 12959458227 ps
T1163 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3863060368 Aug 06 08:32:53 PM PDT 24 Aug 06 09:38:02 PM PDT 24 15065340574 ps
T336 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1611483813 Aug 06 08:20:40 PM PDT 24 Aug 06 08:36:31 PM PDT 24 5274870048 ps
T322 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1262025278 Aug 06 08:20:04 PM PDT 24 Aug 06 08:29:22 PM PDT 24 4938129704 ps
T213 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.2782897302 Aug 06 08:27:19 PM PDT 24 Aug 06 08:33:43 PM PDT 24 3189478472 ps
T1164 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.242115456 Aug 06 08:30:22 PM PDT 24 Aug 06 08:34:08 PM PDT 24 2221153168 ps
T296 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.486625958 Aug 06 08:23:34 PM PDT 24 Aug 06 08:57:19 PM PDT 24 25528410371 ps
T1165 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.969981071 Aug 06 08:37:57 PM PDT 24 Aug 06 08:48:36 PM PDT 24 6431381052 ps
T800 /workspace/coverage/default/49.chip_sw_all_escalation_resets.3647720133 Aug 06 08:44:23 PM PDT 24 Aug 06 08:56:11 PM PDT 24 6162645908 ps
T1166 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1472067923 Aug 06 08:23:53 PM PDT 24 Aug 06 08:48:32 PM PDT 24 13901624325 ps
T760 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.1381967447 Aug 06 08:23:11 PM PDT 24 Aug 06 08:59:19 PM PDT 24 11495159951 ps
T1167 /workspace/coverage/default/0.chip_sw_aon_timer_irq.4259293122 Aug 06 08:24:54 PM PDT 24 Aug 06 08:32:25 PM PDT 24 3202695128 ps
T462 /workspace/coverage/default/0.chip_sw_edn_boot_mode.1890095963 Aug 06 08:21:45 PM PDT 24 Aug 06 08:30:44 PM PDT 24 2735621458 ps
T1168 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.4280527675 Aug 06 08:21:20 PM PDT 24 Aug 06 08:25:55 PM PDT 24 3490789440 ps
T1169 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3438406444 Aug 06 08:25:01 PM PDT 24 Aug 06 08:32:59 PM PDT 24 4211777078 ps
T463 /workspace/coverage/default/2.chip_sw_edn_boot_mode.3714142275 Aug 06 08:34:50 PM PDT 24 Aug 06 08:44:27 PM PDT 24 3542782600 ps
T1170 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.112407920 Aug 06 08:38:03 PM PDT 24 Aug 06 08:48:43 PM PDT 24 4720860422 ps
T1171 /workspace/coverage/default/1.chip_sw_aes_masking_off.459644510 Aug 06 08:24:47 PM PDT 24 Aug 06 08:31:20 PM PDT 24 3403126246 ps
T410 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.232957865 Aug 06 08:28:21 PM PDT 24 Aug 06 09:03:26 PM PDT 24 26512468174 ps
T1172 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.1138849854 Aug 06 08:42:23 PM PDT 24 Aug 06 09:42:11 PM PDT 24 15639143486 ps
T851 /workspace/coverage/default/51.chip_sw_all_escalation_resets.742756913 Aug 06 08:45:28 PM PDT 24 Aug 06 08:57:30 PM PDT 24 5401104280 ps
T262 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.85769741 Aug 06 08:27:02 PM PDT 24 Aug 06 08:32:25 PM PDT 24 3265753634 ps
T781 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.289183388 Aug 06 08:42:38 PM PDT 24 Aug 06 08:51:26 PM PDT 24 3562883142 ps
T1173 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.2762680552 Aug 06 08:41:35 PM PDT 24 Aug 06 08:50:22 PM PDT 24 3861228350 ps
T1174 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2112611884 Aug 06 08:41:39 PM PDT 24 Aug 06 08:46:10 PM PDT 24 2825971656 ps
T1175 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.22159243 Aug 06 08:40:15 PM PDT 24 Aug 06 08:43:54 PM PDT 24 2235613748 ps
T1176 /workspace/coverage/default/0.chip_sw_aes_masking_off.1193982600 Aug 06 08:20:47 PM PDT 24 Aug 06 08:25:55 PM PDT 24 3129506590 ps
T1177 /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1119538264 Aug 06 08:37:55 PM PDT 24 Aug 06 08:46:31 PM PDT 24 3731557021 ps
T214 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.3525676712 Aug 06 08:29:58 PM PDT 24 Aug 06 08:35:56 PM PDT 24 3314830404 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.1966069780 Aug 06 08:21:04 PM PDT 24 Aug 06 10:15:11 PM PDT 24 31567584548 ps
T1178 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2910093557 Aug 06 08:34:52 PM PDT 24 Aug 06 08:39:07 PM PDT 24 2500452000 ps
T107 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.241935106 Aug 06 08:21:51 PM PDT 24 Aug 06 08:47:29 PM PDT 24 23514501880 ps
T1179 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.6625170 Aug 06 08:23:11 PM PDT 24 Aug 06 08:39:21 PM PDT 24 12677719857 ps
T1180 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2980641412 Aug 06 08:26:43 PM PDT 24 Aug 06 08:33:09 PM PDT 24 4118466887 ps
T1181 /workspace/coverage/default/1.chip_sw_csrng_kat_test.4283071958 Aug 06 08:24:45 PM PDT 24 Aug 06 08:30:00 PM PDT 24 3147515100 ps
T1182 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.653003861 Aug 06 08:23:55 PM PDT 24 Aug 06 08:41:29 PM PDT 24 6806723952 ps
T831 /workspace/coverage/default/19.chip_sw_all_escalation_resets.1948588996 Aug 06 08:42:27 PM PDT 24 Aug 06 08:52:52 PM PDT 24 5530535748 ps
T1183 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1074089553 Aug 06 08:40:44 PM PDT 24 Aug 06 08:53:46 PM PDT 24 4340424014 ps
T1184 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2801926845 Aug 06 08:32:37 PM PDT 24 Aug 06 08:43:14 PM PDT 24 6140909120 ps
T811 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541241678 Aug 06 08:46:59 PM PDT 24 Aug 06 08:53:49 PM PDT 24 4153315972 ps
T809 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3838352565 Aug 06 08:24:54 PM PDT 24 Aug 06 08:32:08 PM PDT 24 3714444666 ps
T435 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4176588808 Aug 06 08:26:17 PM PDT 24 Aug 06 08:35:22 PM PDT 24 7475549680 ps
T1185 /workspace/coverage/default/16.chip_sw_all_escalation_resets.1932124418 Aug 06 08:42:36 PM PDT 24 Aug 06 08:58:28 PM PDT 24 5915533080 ps
T1186 /workspace/coverage/default/1.chip_sw_edn_auto_mode.1388490831 Aug 06 08:23:10 PM PDT 24 Aug 06 08:44:10 PM PDT 24 5135445060 ps
T1187 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.2225104553 Aug 06 08:35:54 PM PDT 24 Aug 06 08:39:18 PM PDT 24 2844134210 ps
T1188 /workspace/coverage/default/69.chip_sw_all_escalation_resets.1914814407 Aug 06 08:45:09 PM PDT 24 Aug 06 08:55:35 PM PDT 24 5611704052 ps
T1189 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3626108821 Aug 06 08:29:08 PM PDT 24 Aug 06 08:51:35 PM PDT 24 9541772558 ps
T816 /workspace/coverage/default/74.chip_sw_all_escalation_resets.1042628176 Aug 06 08:46:07 PM PDT 24 Aug 06 08:57:42 PM PDT 24 6228419630 ps
T1190 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2767052867 Aug 06 08:39:39 PM PDT 24 Aug 06 08:45:52 PM PDT 24 2988967936 ps
T1191 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1316135202 Aug 06 08:21:10 PM PDT 24 Aug 06 08:26:56 PM PDT 24 3755849700 ps
T1192 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.2013440347 Aug 06 08:23:56 PM PDT 24 Aug 06 08:29:33 PM PDT 24 3436481856 ps
T1193 /workspace/coverage/default/2.rom_e2e_shutdown_output.1927224459 Aug 06 08:43:05 PM PDT 24 Aug 06 09:36:06 PM PDT 24 23207740575 ps
T1194 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.4049131098 Aug 06 08:42:30 PM PDT 24 Aug 06 09:08:30 PM PDT 24 8058564832 ps
T464 /workspace/coverage/default/1.chip_sw_edn_boot_mode.2197208913 Aug 06 08:27:17 PM PDT 24 Aug 06 08:37:14 PM PDT 24 3155065444 ps
T1195 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1199393908 Aug 06 08:39:46 PM PDT 24 Aug 06 08:51:38 PM PDT 24 5422412170 ps
T820 /workspace/coverage/default/42.chip_sw_all_escalation_resets.4120324400 Aug 06 08:45:00 PM PDT 24 Aug 06 08:55:19 PM PDT 24 4946854096 ps
T1196 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1120707453 Aug 06 08:40:12 PM PDT 24 Aug 06 08:44:03 PM PDT 24 2941723059 ps
T1197 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3204402219 Aug 06 08:21:03 PM PDT 24 Aug 06 08:31:07 PM PDT 24 3771019992 ps
T844 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3322754146 Aug 06 08:45:14 PM PDT 24 Aug 06 08:57:19 PM PDT 24 4988963320 ps
T1198 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.1145481536 Aug 06 08:42:02 PM PDT 24 Aug 06 08:54:36 PM PDT 24 4238563944 ps
T1199 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4055098784 Aug 06 08:29:26 PM PDT 24 Aug 06 08:56:53 PM PDT 24 11598507575 ps
T1200 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.3721938234 Aug 06 08:30:02 PM PDT 24 Aug 06 10:28:21 PM PDT 24 23047411937 ps
T1201 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2823968762 Aug 06 08:31:39 PM PDT 24 Aug 06 08:36:40 PM PDT 24 2686223334 ps
T779 /workspace/coverage/default/97.chip_sw_all_escalation_resets.1622084443 Aug 06 08:46:46 PM PDT 24 Aug 06 08:56:55 PM PDT 24 5798188060 ps
T821 /workspace/coverage/default/46.chip_sw_all_escalation_resets.3927617960 Aug 06 08:48:55 PM PDT 24 Aug 06 08:59:37 PM PDT 24 6178532080 ps
T1202 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2824375289 Aug 06 08:41:57 PM PDT 24 Aug 06 08:55:23 PM PDT 24 12509361348 ps
T1203 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.50919112 Aug 06 08:34:37 PM PDT 24 Aug 06 08:58:59 PM PDT 24 7730940894 ps
T763 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3388803271 Aug 06 08:44:28 PM PDT 24 Aug 06 08:53:04 PM PDT 24 3199186332 ps
T1204 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.256416255 Aug 06 08:24:55 PM PDT 24 Aug 07 12:03:00 AM PDT 24 78255614184 ps
T1205 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3508054895 Aug 06 08:20:54 PM PDT 24 Aug 06 08:38:41 PM PDT 24 5262403370 ps
T297 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.144066509 Aug 06 08:39:05 PM PDT 24 Aug 06 09:20:44 PM PDT 24 19479033510 ps
T1206 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1006355910 Aug 06 08:39:45 PM PDT 24 Aug 06 10:33:42 PM PDT 24 28750359260 ps
T1207 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.407222359 Aug 06 08:27:59 PM PDT 24 Aug 06 08:40:31 PM PDT 24 4682415324 ps
T1208 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1273988497 Aug 06 08:24:47 PM PDT 24 Aug 06 08:29:10 PM PDT 24 3209455632 ps
T1209 /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3989469380 Aug 06 08:51:04 PM PDT 24 Aug 06 08:58:19 PM PDT 24 3123118400 ps
T236 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3699063096 Aug 06 08:30:24 PM PDT 24 Aug 06 08:36:39 PM PDT 24 2584511540 ps
T1210 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2887982491 Aug 06 08:40:55 PM PDT 24 Aug 06 08:59:03 PM PDT 24 5529189580 ps
T801 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830087565 Aug 06 08:41:47 PM PDT 24 Aug 06 08:47:40 PM PDT 24 3783690800 ps
T215 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3548882454 Aug 06 08:27:20 PM PDT 24 Aug 06 08:55:25 PM PDT 24 24502581976 ps
T1211 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3932492281 Aug 06 08:38:47 PM PDT 24 Aug 06 09:03:19 PM PDT 24 10875481970 ps
T350 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.3512883719 Aug 06 08:28:16 PM PDT 24 Aug 06 08:42:58 PM PDT 24 5639462960 ps
T1212 /workspace/coverage/default/0.chip_sw_power_sleep_load.737927868 Aug 06 08:25:00 PM PDT 24 Aug 06 08:31:44 PM PDT 24 9965885000 ps
T1213 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.824019963 Aug 06 08:36:27 PM PDT 24 Aug 06 08:48:45 PM PDT 24 5312855090 ps
T326 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.293081367 Aug 06 08:36:37 PM PDT 24 Aug 06 09:11:44 PM PDT 24 7965026824 ps
T360 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.391782033 Aug 06 08:21:12 PM PDT 24 Aug 06 08:34:04 PM PDT 24 4682832086 ps
T1214 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.3776144526 Aug 06 08:27:10 PM PDT 24 Aug 06 08:58:38 PM PDT 24 12990995652 ps
T1215 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.2118718178 Aug 06 08:33:06 PM PDT 24 Aug 06 08:43:35 PM PDT 24 6030935144 ps
T818 /workspace/coverage/default/44.chip_sw_all_escalation_resets.624085771 Aug 06 08:44:25 PM PDT 24 Aug 06 08:54:44 PM PDT 24 5554848652 ps
T1216 /workspace/coverage/default/1.chip_sw_rv_timer_irq.1405028905 Aug 06 08:22:54 PM PDT 24 Aug 06 08:27:17 PM PDT 24 3224034644 ps
T1217 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3457929558 Aug 06 08:36:01 PM PDT 24 Aug 06 09:03:34 PM PDT 24 6803603478 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%