Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.49 93.82 95.32 94.57 97.35 99.55


Total test records in report: 2932
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html | tests27.html | tests28.html | tests29.html | tests30.html | tests31.html | tests32.html | tests33.html | tests34.html | tests35.html | tests36.html | tests37.html | tests38.html | tests39.html | tests40.html | tests41.html | tests42.html | tests43.html | tests44.html | tests45.html | tests46.html | tests47.html | tests48.html | tests49.html | tests50.html | tests51.html | tests52.html | tests53.html | tests54.html | tests55.html | tests56.html | tests57.html | tests58.html | tests59.html | tests60.html | tests61.html | tests62.html

T840 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2319849612 Aug 06 08:43:12 PM PDT 24 Aug 06 08:50:01 PM PDT 24 4452475872 ps
T1382 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.334810377 Aug 06 08:22:57 PM PDT 24 Aug 06 08:50:01 PM PDT 24 12840974736 ps
T437 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3814981159 Aug 06 08:36:41 PM PDT 24 Aug 06 08:44:31 PM PDT 24 7582867152 ps
T830 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3995771264 Aug 06 08:43:48 PM PDT 24 Aug 06 08:49:58 PM PDT 24 3052330792 ps
T832 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.63537488 Aug 06 08:45:38 PM PDT 24 Aug 06 08:53:54 PM PDT 24 3246469608 ps
T1383 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.930255530 Aug 06 08:25:42 PM PDT 24 Aug 06 08:44:39 PM PDT 24 6362067104 ps
T1384 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2674923521 Aug 06 08:24:02 PM PDT 24 Aug 06 08:26:01 PM PDT 24 2488080398 ps
T137 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3926652944 Aug 06 08:35:19 PM PDT 24 Aug 06 08:52:42 PM PDT 24 6838548350 ps
T1385 /workspace/coverage/default/2.chip_sw_example_flash.3551225298 Aug 06 08:27:38 PM PDT 24 Aug 06 08:31:42 PM PDT 24 3279560040 ps
T1386 /workspace/coverage/default/1.chip_sw_example_concurrency.76820688 Aug 06 08:29:03 PM PDT 24 Aug 06 08:32:25 PM PDT 24 2822048164 ps
T1387 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.3543128785 Aug 06 08:28:52 PM PDT 24 Aug 06 08:33:29 PM PDT 24 2855195004 ps
T1388 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.1369877488 Aug 06 08:35:41 PM PDT 24 Aug 06 09:19:48 PM PDT 24 9869109480 ps
T1389 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.947420230 Aug 06 08:45:29 PM PDT 24 Aug 06 09:44:47 PM PDT 24 15308520820 ps
T806 /workspace/coverage/default/6.chip_sw_all_escalation_resets.1839004634 Aug 06 08:40:24 PM PDT 24 Aug 06 08:50:44 PM PDT 24 5400903738 ps
T76 /workspace/coverage/cover_reg_top/60.xbar_random.4134476284 Aug 06 08:59:25 PM PDT 24 Aug 06 08:59:54 PM PDT 24 326649036 ps
T77 /workspace/coverage/cover_reg_top/29.xbar_same_source.1765297528 Aug 06 08:54:12 PM PDT 24 Aug 06 08:54:58 PM PDT 24 1608730870 ps
T78 /workspace/coverage/cover_reg_top/36.xbar_error_random.2352056020 Aug 06 08:55:39 PM PDT 24 Aug 06 08:56:52 PM PDT 24 2110951405 ps
T131 /workspace/coverage/cover_reg_top/28.xbar_error_random.925564937 Aug 06 08:54:09 PM PDT 24 Aug 06 08:54:49 PM PDT 24 412954419 ps
T227 /workspace/coverage/cover_reg_top/20.xbar_stress_all.1492729357 Aug 06 08:52:14 PM PDT 24 Aug 06 09:02:50 PM PDT 24 16850279869 ps
T559 /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.1808619689 Aug 06 08:57:19 PM PDT 24 Aug 06 08:58:29 PM PDT 24 6403540602 ps
T557 /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.1052990292 Aug 06 09:01:27 PM PDT 24 Aug 06 09:01:34 PM PDT 24 45912890 ps
T551 /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.1487036761 Aug 06 09:01:56 PM PDT 24 Aug 06 09:02:15 PM PDT 24 163111792 ps
T523 /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.2691600407 Aug 06 08:59:04 PM PDT 24 Aug 06 08:59:50 PM PDT 24 437294950 ps
T467 /workspace/coverage/cover_reg_top/52.xbar_error_random.3707729861 Aug 06 08:58:18 PM PDT 24 Aug 06 08:59:54 PM PDT 24 2219638998 ps
T558 /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.4275406128 Aug 06 09:02:02 PM PDT 24 Aug 06 09:02:44 PM PDT 24 1020960152 ps
T554 /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.346018567 Aug 06 08:59:04 PM PDT 24 Aug 06 08:59:11 PM PDT 24 50422994 ps
T777 /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.984674765 Aug 06 08:54:06 PM PDT 24 Aug 06 09:13:46 PM PDT 24 69804079230 ps
T428 /workspace/coverage/cover_reg_top/98.xbar_random.1161025935 Aug 06 09:05:24 PM PDT 24 Aug 06 09:06:47 PM PDT 24 2322067865 ps
T506 /workspace/coverage/cover_reg_top/9.xbar_smoke.1439547955 Aug 06 08:47:45 PM PDT 24 Aug 06 08:47:54 PM PDT 24 211416344 ps
T486 /workspace/coverage/cover_reg_top/91.xbar_random.2037363244 Aug 06 09:04:23 PM PDT 24 Aug 06 09:05:50 PM PDT 24 2452509553 ps
T561 /workspace/coverage/cover_reg_top/23.xbar_access_same_device.3834539747 Aug 06 08:52:56 PM PDT 24 Aug 06 08:53:31 PM PDT 24 842642470 ps
T555 /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.3017886983 Aug 06 08:52:15 PM PDT 24 Aug 06 08:52:55 PM PDT 24 841450123 ps
T741 /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.4255220115 Aug 06 08:41:40 PM PDT 24 Aug 06 08:51:06 PM PDT 24 5631375570 ps
T438 /workspace/coverage/cover_reg_top/59.xbar_random.1011240767 Aug 06 08:59:17 PM PDT 24 Aug 06 08:59:58 PM PDT 24 1092695099 ps
T677 /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3837620633 Aug 06 08:59:17 PM PDT 24 Aug 06 09:00:53 PM PDT 24 5429308814 ps
T148 /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2297040112 Aug 06 08:42:39 PM PDT 24 Aug 06 08:54:43 PM PDT 24 7297462408 ps
T553 /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.4237640258 Aug 06 09:03:35 PM PDT 24 Aug 06 09:12:15 PM PDT 24 48562227458 ps
T560 /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.579270742 Aug 06 08:52:36 PM PDT 24 Aug 06 08:54:05 PM PDT 24 8218407051 ps
T903 /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.628070270 Aug 06 09:00:17 PM PDT 24 Aug 06 09:00:22 PM PDT 24 8650737 ps
T149 /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.4088399610 Aug 06 08:48:40 PM PDT 24 Aug 06 09:03:53 PM PDT 24 11975349330 ps
T421 /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.3615360143 Aug 06 08:42:05 PM PDT 24 Aug 06 09:03:28 PM PDT 24 9650032746 ps
T886 /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.719938890 Aug 06 08:57:26 PM PDT 24 Aug 06 09:05:21 PM PDT 24 25605912993 ps
T664 /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.4232081704 Aug 06 08:46:29 PM PDT 24 Aug 06 08:47:34 PM PDT 24 3519423114 ps
T495 /workspace/coverage/cover_reg_top/2.xbar_stress_all.1242480656 Aug 06 08:43:38 PM PDT 24 Aug 06 08:46:53 PM PDT 24 2245654125 ps
T645 /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.1231673633 Aug 06 08:52:24 PM PDT 24 Aug 06 08:54:15 PM PDT 24 6586704615 ps
T556 /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.2620676216 Aug 06 08:55:50 PM PDT 24 Aug 06 09:04:34 PM PDT 24 8974190559 ps
T897 /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.733621781 Aug 06 08:50:16 PM PDT 24 Aug 06 08:53:47 PM PDT 24 774189648 ps
T419 /workspace/coverage/cover_reg_top/37.xbar_random.1723284351 Aug 06 08:55:38 PM PDT 24 Aug 06 08:56:14 PM PDT 24 922576912 ps
T1390 /workspace/coverage/cover_reg_top/63.xbar_smoke.4283152326 Aug 06 08:59:54 PM PDT 24 Aug 06 09:00:03 PM PDT 24 205976232 ps
T1391 /workspace/coverage/cover_reg_top/37.xbar_smoke.2320301928 Aug 06 08:55:36 PM PDT 24 Aug 06 08:55:46 PM PDT 24 230390097 ps
T650 /workspace/coverage/cover_reg_top/77.xbar_error_random.3298727068 Aug 06 09:02:19 PM PDT 24 Aug 06 09:02:58 PM PDT 24 408279033 ps
T500 /workspace/coverage/cover_reg_top/54.xbar_same_source.1511555307 Aug 06 08:58:32 PM PDT 24 Aug 06 08:59:40 PM PDT 24 1891155464 ps
T439 /workspace/coverage/cover_reg_top/0.xbar_random.2319320321 Aug 06 08:40:37 PM PDT 24 Aug 06 08:41:14 PM PDT 24 320732950 ps
T708 /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.3948266609 Aug 06 09:00:20 PM PDT 24 Aug 06 09:00:27 PM PDT 24 52943922 ps
T721 /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.1791758660 Aug 06 08:57:04 PM PDT 24 Aug 06 09:06:17 PM PDT 24 15511477444 ps
T1392 /workspace/coverage/cover_reg_top/74.xbar_smoke.1585025046 Aug 06 09:01:31 PM PDT 24 Aug 06 09:01:41 PM PDT 24 199998479 ps
T875 /workspace/coverage/cover_reg_top/30.xbar_access_same_device.4042010227 Aug 06 08:54:21 PM PDT 24 Aug 06 08:56:57 PM PDT 24 3353605944 ps
T1393 /workspace/coverage/cover_reg_top/13.xbar_error_random.3793581853 Aug 06 08:49:48 PM PDT 24 Aug 06 08:50:35 PM PDT 24 465404722 ps
T571 /workspace/coverage/cover_reg_top/22.xbar_same_source.1551580965 Aug 06 08:52:45 PM PDT 24 Aug 06 08:53:54 PM PDT 24 2173440725 ps
T668 /workspace/coverage/cover_reg_top/17.xbar_random.4044622057 Aug 06 08:51:13 PM PDT 24 Aug 06 08:51:43 PM PDT 24 324330726 ps
T440 /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1303726277 Aug 06 09:04:11 PM PDT 24 Aug 06 09:04:45 PM PDT 24 328928747 ps
T601 /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2783882988 Aug 06 08:59:53 PM PDT 24 Aug 06 09:01:57 PM PDT 24 6707120648 ps
T471 /workspace/coverage/cover_reg_top/29.xbar_stress_all.4194755083 Aug 06 08:54:18 PM PDT 24 Aug 06 09:04:01 PM PDT 24 15684521544 ps
T591 /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3369033856 Aug 06 09:03:42 PM PDT 24 Aug 06 09:13:36 PM PDT 24 57672521020 ps
T547 /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.3065848437 Aug 06 09:04:47 PM PDT 24 Aug 06 09:04:57 PM PDT 24 65290076 ps
T582 /workspace/coverage/cover_reg_top/54.xbar_random.2366809459 Aug 06 08:58:33 PM PDT 24 Aug 06 08:59:09 PM PDT 24 334996664 ps
T862 /workspace/coverage/cover_reg_top/95.xbar_access_same_device.2390829845 Aug 06 09:05:04 PM PDT 24 Aug 06 09:06:19 PM PDT 24 2072957390 ps
T1394 /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.3723273505 Aug 06 09:01:12 PM PDT 24 Aug 06 09:03:01 PM PDT 24 10269585959 ps
T382 /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.239026671 Aug 06 08:50:01 PM PDT 24 Aug 06 09:19:12 PM PDT 24 16849098306 ps
T545 /workspace/coverage/cover_reg_top/35.xbar_random.1499851796 Aug 06 08:55:15 PM PDT 24 Aug 06 08:56:01 PM PDT 24 413487157 ps
T1395 /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.799010327 Aug 06 08:55:00 PM PDT 24 Aug 06 08:55:06 PM PDT 24 34482065 ps
T670 /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.3613644690 Aug 06 08:40:46 PM PDT 24 Aug 06 08:41:31 PM PDT 24 3914988582 ps
T628 /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.2063172809 Aug 06 09:00:41 PM PDT 24 Aug 06 09:14:41 PM PDT 24 80292713441 ps
T718 /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.626258622 Aug 06 09:02:24 PM PDT 24 Aug 06 09:05:34 PM PDT 24 2384635483 ps
T579 /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.2660554195 Aug 06 09:01:10 PM PDT 24 Aug 06 09:08:44 PM PDT 24 44516419160 ps
T580 /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1397488096 Aug 06 08:54:29 PM PDT 24 Aug 06 08:55:58 PM PDT 24 8152527904 ps
T698 /workspace/coverage/cover_reg_top/30.xbar_same_source.2431022375 Aug 06 08:54:27 PM PDT 24 Aug 06 08:54:55 PM PDT 24 775144281 ps
T532 /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.2348335839 Aug 06 09:04:25 PM PDT 24 Aug 06 09:04:33 PM PDT 24 51691255 ps
T383 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2345730015 Aug 06 08:48:41 PM PDT 24 Aug 06 09:24:27 PM PDT 24 14748140850 ps
T653 /workspace/coverage/cover_reg_top/8.xbar_smoke.3647742900 Aug 06 08:47:10 PM PDT 24 Aug 06 08:47:17 PM PDT 24 49239049 ps
T488 /workspace/coverage/cover_reg_top/37.xbar_same_source.2809794187 Aug 06 08:55:43 PM PDT 24 Aug 06 08:56:59 PM PDT 24 2518837917 ps
T1396 /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.2472178487 Aug 06 08:43:53 PM PDT 24 Aug 06 08:44:00 PM PDT 24 41562749 ps
T468 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3231217690 Aug 06 08:53:56 PM PDT 24 Aug 06 08:58:29 PM PDT 24 4806224900 ps
T521 /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.1033818537 Aug 06 08:59:58 PM PDT 24 Aug 06 09:06:21 PM PDT 24 20431012176 ps
T876 /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.488976520 Aug 06 08:54:17 PM PDT 24 Aug 06 09:23:52 PM PDT 24 99655144818 ps
T472 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.4229229233 Aug 06 09:05:13 PM PDT 24 Aug 06 09:18:25 PM PDT 24 7271865108 ps
T921 /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.2648665751 Aug 06 08:52:35 PM PDT 24 Aug 06 08:53:41 PM PDT 24 206208861 ps
T1397 /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.2227501738 Aug 06 08:56:45 PM PDT 24 Aug 06 08:58:23 PM PDT 24 5683055078 ps
T1398 /workspace/coverage/cover_reg_top/0.xbar_error_random.3276400533 Aug 06 08:41:54 PM PDT 24 Aug 06 08:43:03 PM PDT 24 1697845506 ps
T896 /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.628294039 Aug 06 08:55:56 PM PDT 24 Aug 06 09:02:40 PM PDT 24 22137858269 ps
T1399 /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.1194484146 Aug 06 09:01:36 PM PDT 24 Aug 06 09:05:53 PM PDT 24 22829880171 ps
T1400 /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.3190007160 Aug 06 08:44:13 PM PDT 24 Aug 06 08:44:31 PM PDT 24 344807708 ps
T1401 /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.528969060 Aug 06 08:53:56 PM PDT 24 Aug 06 08:55:11 PM PDT 24 2177801692 ps
T1402 /workspace/coverage/cover_reg_top/72.xbar_error_random.1265925072 Aug 06 09:01:20 PM PDT 24 Aug 06 09:01:32 PM PDT 24 284335235 ps
T1403 /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.3565691292 Aug 06 09:03:09 PM PDT 24 Aug 06 09:03:23 PM PDT 24 116206389 ps
T904 /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.2955155048 Aug 06 08:48:31 PM PDT 24 Aug 06 08:50:04 PM PDT 24 231252091 ps
T900 /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.123219157 Aug 06 08:54:44 PM PDT 24 Aug 06 08:58:52 PM PDT 24 13404945311 ps
T1404 /workspace/coverage/cover_reg_top/11.xbar_smoke.1626486995 Aug 06 08:48:39 PM PDT 24 Aug 06 08:48:46 PM PDT 24 46916528 ps
T1405 /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.1959013618 Aug 06 09:05:28 PM PDT 24 Aug 06 09:06:00 PM PDT 24 290628115 ps
T920 /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1624455327 Aug 06 08:55:26 PM PDT 24 Aug 06 08:56:24 PM PDT 24 214263133 ps
T884 /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.204819881 Aug 06 08:52:28 PM PDT 24 Aug 06 09:20:23 PM PDT 24 98639670305 ps
T481 /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3956112980 Aug 06 09:02:28 PM PDT 24 Aug 06 09:02:57 PM PDT 24 235239969 ps
T385 /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.2050514726 Aug 06 08:47:45 PM PDT 24 Aug 06 09:00:00 PM PDT 24 9337766877 ps
T476 /workspace/coverage/cover_reg_top/58.xbar_smoke.484485343 Aug 06 08:59:07 PM PDT 24 Aug 06 08:59:14 PM PDT 24 42503322 ps
T672 /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3668499358 Aug 06 09:00:34 PM PDT 24 Aug 06 09:00:48 PM PDT 24 91225268 ps
T477 /workspace/coverage/cover_reg_top/79.xbar_stress_all.1957021179 Aug 06 09:02:36 PM PDT 24 Aug 06 09:08:41 PM PDT 24 10340983715 ps
T1406 /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.2177962234 Aug 06 08:58:09 PM PDT 24 Aug 06 08:59:01 PM PDT 24 4975377455 ps
T1407 /workspace/coverage/cover_reg_top/22.xbar_error_random.2012237371 Aug 06 08:52:45 PM PDT 24 Aug 06 08:52:53 PM PDT 24 115443556 ps
T1408 /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.339052853 Aug 06 08:58:55 PM PDT 24 Aug 06 09:01:56 PM PDT 24 10473143384 ps
T386 /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.3061306128 Aug 06 08:49:41 PM PDT 24 Aug 06 09:04:45 PM PDT 24 11634842510 ps
T867 /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.3931820364 Aug 06 09:05:41 PM PDT 24 Aug 06 09:08:02 PM PDT 24 410465699 ps
T624 /workspace/coverage/cover_reg_top/55.xbar_same_source.3767877645 Aug 06 08:58:44 PM PDT 24 Aug 06 09:00:04 PM PDT 24 2446890388 ps
T902 /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.3978492079 Aug 06 08:44:14 PM PDT 24 Aug 06 08:52:29 PM PDT 24 28098116319 ps
T1409 /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1484889580 Aug 06 08:51:38 PM PDT 24 Aug 06 08:52:28 PM PDT 24 4633255708 ps
T411 /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3824083576 Aug 06 08:51:28 PM PDT 24 Aug 06 09:50:18 PM PDT 24 29088152915 ps
T487 /workspace/coverage/cover_reg_top/98.xbar_stress_all.4070679198 Aug 06 09:05:33 PM PDT 24 Aug 06 09:07:31 PM PDT 24 3258303373 ps
T497 /workspace/coverage/cover_reg_top/13.xbar_stress_all.2333568451 Aug 06 08:49:55 PM PDT 24 Aug 06 08:52:40 PM PDT 24 1782452499 ps
T864 /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.614552175 Aug 06 08:50:31 PM PDT 24 Aug 06 09:10:41 PM PDT 24 68731215465 ps
T1410 /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.2225579893 Aug 06 08:53:02 PM PDT 24 Aug 06 08:54:32 PM PDT 24 8629219724 ps
T562 /workspace/coverage/cover_reg_top/3.chip_tl_errors.200057364 Aug 06 08:43:50 PM PDT 24 Aug 06 08:47:13 PM PDT 24 2918132583 ps
T1411 /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.1414285860 Aug 06 08:45:53 PM PDT 24 Aug 06 08:47:48 PM PDT 24 6269971361 ps
T1412 /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.178331806 Aug 06 08:57:37 PM PDT 24 Aug 06 08:57:44 PM PDT 24 52673215 ps
T878 /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.1273678406 Aug 06 08:55:37 PM PDT 24 Aug 06 08:56:19 PM PDT 24 166793224 ps
T873 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.3604557266 Aug 06 09:02:36 PM PDT 24 Aug 06 09:03:52 PM PDT 24 224870439 ps
T654 /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.707106428 Aug 06 08:55:58 PM PDT 24 Aug 06 08:56:55 PM PDT 24 1169472399 ps
T1413 /workspace/coverage/cover_reg_top/80.xbar_error_random.2675473758 Aug 06 09:02:44 PM PDT 24 Aug 06 09:02:56 PM PDT 24 116424705 ps
T515 /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3038266901 Aug 06 08:43:33 PM PDT 24 Aug 06 08:44:10 PM PDT 24 656695776 ps
T469 /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.686886265 Aug 06 08:50:26 PM PDT 24 Aug 06 08:51:07 PM PDT 24 414727084 ps
T470 /workspace/coverage/cover_reg_top/23.xbar_random.3158462055 Aug 06 08:52:54 PM PDT 24 Aug 06 08:53:16 PM PDT 24 513080905 ps
T722 /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3237032500 Aug 06 09:03:39 PM PDT 24 Aug 06 09:06:05 PM PDT 24 3556809709 ps
T1414 /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.2879804050 Aug 06 09:03:46 PM PDT 24 Aug 06 09:04:06 PM PDT 24 144045542 ps
T1415 /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2238584068 Aug 06 08:57:35 PM PDT 24 Aug 06 08:58:11 PM PDT 24 298403459 ps
T482 /workspace/coverage/cover_reg_top/31.xbar_same_source.4084782460 Aug 06 08:54:45 PM PDT 24 Aug 06 08:55:07 PM PDT 24 577128705 ps
T1416 /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.1100524300 Aug 06 08:53:04 PM PDT 24 Aug 06 08:53:28 PM PDT 24 170001290 ps
T635 /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1264899824 Aug 06 08:54:38 PM PDT 24 Aug 06 08:54:57 PM PDT 24 375649035 ps
T607 /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.3079472895 Aug 06 08:59:17 PM PDT 24 Aug 06 09:00:01 PM PDT 24 105807465 ps
T892 /workspace/coverage/cover_reg_top/43.xbar_access_same_device.878014569 Aug 06 08:56:48 PM PDT 24 Aug 06 08:57:16 PM PDT 24 237692544 ps
T574 /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.1179186605 Aug 06 09:03:09 PM PDT 24 Aug 06 09:10:21 PM PDT 24 6050021842 ps
T585 /workspace/coverage/cover_reg_top/13.xbar_same_source.2742567516 Aug 06 08:49:47 PM PDT 24 Aug 06 08:50:21 PM PDT 24 1015622338 ps
T563 /workspace/coverage/cover_reg_top/10.chip_tl_errors.516273748 Aug 06 08:48:09 PM PDT 24 Aug 06 08:51:24 PM PDT 24 2798440379 ps
T613 /workspace/coverage/cover_reg_top/71.xbar_random.1690281611 Aug 06 09:01:06 PM PDT 24 Aug 06 09:01:46 PM PDT 24 1142298729 ps
T761 /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.2659403195 Aug 06 09:04:56 PM PDT 24 Aug 06 09:07:59 PM PDT 24 2201756375 ps
T865 /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.4178921316 Aug 06 08:58:52 PM PDT 24 Aug 06 09:01:02 PM PDT 24 1640997723 ps
T1417 /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.1265217650 Aug 06 08:46:31 PM PDT 24 Aug 06 08:48:07 PM PDT 24 8981816700 ps
T1418 /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1809117515 Aug 06 09:03:13 PM PDT 24 Aug 06 09:03:53 PM PDT 24 335485095 ps
T686 /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.2879343464 Aug 06 08:56:37 PM PDT 24 Aug 06 08:57:32 PM PDT 24 1084645676 ps
T473 /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.2923825088 Aug 06 09:05:09 PM PDT 24 Aug 06 09:13:31 PM PDT 24 27876854361 ps
T502 /workspace/coverage/cover_reg_top/25.xbar_stress_all.1488142492 Aug 06 08:53:30 PM PDT 24 Aug 06 08:58:58 PM PDT 24 3569167371 ps
T1419 /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.3749801181 Aug 06 08:55:57 PM PDT 24 Aug 06 08:56:27 PM PDT 24 261052455 ps
T1420 /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.71121719 Aug 06 08:48:13 PM PDT 24 Aug 06 08:49:08 PM PDT 24 5026944026 ps
T706 /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.2529721368 Aug 06 08:52:54 PM PDT 24 Aug 06 08:54:24 PM PDT 24 7989018175 ps
T490 /workspace/coverage/cover_reg_top/38.xbar_same_source.3754975585 Aug 06 08:55:57 PM PDT 24 Aug 06 08:57:12 PM PDT 24 2239019707 ps
T1421 /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.3116822256 Aug 06 08:56:39 PM PDT 24 Aug 06 08:57:18 PM PDT 24 788164351 ps
T1422 /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.3431332691 Aug 06 08:53:31 PM PDT 24 Aug 06 08:53:37 PM PDT 24 38102824 ps
T868 /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3628346023 Aug 06 08:59:51 PM PDT 24 Aug 06 09:05:22 PM PDT 24 8694376154 ps
T1423 /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.861142514 Aug 06 08:55:23 PM PDT 24 Aug 06 08:55:43 PM PDT 24 408969756 ps
T723 /workspace/coverage/cover_reg_top/13.chip_tl_errors.1374144683 Aug 06 08:49:38 PM PDT 24 Aug 06 08:51:13 PM PDT 24 2280081408 ps
T384 /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2265149996 Aug 06 08:46:25 PM PDT 24 Aug 06 09:48:16 PM PDT 24 31600662860 ps
T517 /workspace/coverage/cover_reg_top/49.xbar_random.4159656616 Aug 06 08:57:42 PM PDT 24 Aug 06 08:59:04 PM PDT 24 1945916644 ps
T1424 /workspace/coverage/cover_reg_top/74.xbar_error_random.2774090524 Aug 06 09:01:42 PM PDT 24 Aug 06 09:02:09 PM PDT 24 331843469 ps
T1425 /workspace/coverage/cover_reg_top/83.xbar_error_random.2961706884 Aug 06 09:03:08 PM PDT 24 Aug 06 09:03:17 PM PDT 24 160515316 ps
T536 /workspace/coverage/cover_reg_top/50.xbar_same_source.1444267431 Aug 06 08:58:00 PM PDT 24 Aug 06 08:58:18 PM PDT 24 222514612 ps
T858 /workspace/coverage/cover_reg_top/98.xbar_access_same_device.18884464 Aug 06 09:05:25 PM PDT 24 Aug 06 09:06:00 PM PDT 24 449228422 ps
T1426 /workspace/coverage/cover_reg_top/90.xbar_smoke.3157923445 Aug 06 09:04:08 PM PDT 24 Aug 06 09:04:17 PM PDT 24 171364158 ps
T863 /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.2817657602 Aug 06 09:00:14 PM PDT 24 Aug 06 09:14:57 PM PDT 24 48265292962 ps
T474 /workspace/coverage/cover_reg_top/49.xbar_same_source.1997866462 Aug 06 08:57:44 PM PDT 24 Aug 06 08:59:02 PM PDT 24 2155121258 ps
T575 /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2028509780 Aug 06 09:05:14 PM PDT 24 Aug 06 09:06:16 PM PDT 24 1422724882 ps
T662 /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.3692205103 Aug 06 09:01:06 PM PDT 24 Aug 06 09:01:41 PM PDT 24 293257125 ps
T537 /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.1960327857 Aug 06 08:58:28 PM PDT 24 Aug 06 09:15:24 PM PDT 24 93325745570 ps
T1427 /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1203438766 Aug 06 09:01:26 PM PDT 24 Aug 06 09:03:15 PM PDT 24 6060561180 ps
T565 /workspace/coverage/cover_reg_top/2.chip_tl_errors.1997149711 Aug 06 08:42:58 PM PDT 24 Aug 06 08:46:22 PM PDT 24 3595029396 ps
T1428 /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.2357979020 Aug 06 08:58:58 PM PDT 24 Aug 06 08:59:56 PM PDT 24 1299178048 ps
T604 /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.596695285 Aug 06 09:05:26 PM PDT 24 Aug 06 09:05:55 PM PDT 24 371504908 ps
T412 /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1529121274 Aug 06 08:43:46 PM PDT 24 Aug 06 09:46:07 PM PDT 24 26757018207 ps
T1429 /workspace/coverage/cover_reg_top/95.xbar_smoke.2004953167 Aug 06 09:04:57 PM PDT 24 Aug 06 09:05:06 PM PDT 24 182186625 ps
T885 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.27747487 Aug 06 08:44:27 PM PDT 24 Aug 06 08:45:46 PM PDT 24 314643054 ps
T478 /workspace/coverage/cover_reg_top/60.xbar_stress_all.2217803714 Aug 06 08:59:32 PM PDT 24 Aug 06 09:03:20 PM PDT 24 3028833051 ps
T1430 /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.4092130482 Aug 06 09:02:33 PM PDT 24 Aug 06 09:03:44 PM PDT 24 6607012165 ps
T618 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.1408107801 Aug 06 09:03:57 PM PDT 24 Aug 06 09:09:06 PM PDT 24 1303848874 ps
T887 /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.3020884555 Aug 06 09:04:00 PM PDT 24 Aug 06 09:08:40 PM PDT 24 819478444 ps
T890 /workspace/coverage/cover_reg_top/79.xbar_access_same_device.2661634028 Aug 06 09:02:30 PM PDT 24 Aug 06 09:02:52 PM PDT 24 237104589 ps
T866 /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.2007098483 Aug 06 08:59:35 PM PDT 24 Aug 06 09:21:04 PM PDT 24 76497023033 ps
T675 /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.2683541462 Aug 06 08:54:29 PM PDT 24 Aug 06 08:54:48 PM PDT 24 184306063 ps
T507 /workspace/coverage/cover_reg_top/33.xbar_random.1260738866 Aug 06 08:54:53 PM PDT 24 Aug 06 08:55:47 PM PDT 24 533723909 ps
T420 /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.1815109502 Aug 06 08:42:54 PM PDT 24 Aug 06 09:11:34 PM PDT 24 17091397364 ps
T641 /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.2105256467 Aug 06 08:57:32 PM PDT 24 Aug 06 09:12:18 PM PDT 24 51577777818 ps
T594 /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.821344457 Aug 06 08:42:26 PM PDT 24 Aug 06 08:48:11 PM PDT 24 2939691794 ps
T927 /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.429512609 Aug 06 09:04:21 PM PDT 24 Aug 06 09:05:20 PM PDT 24 222231029 ps
T590 /workspace/coverage/cover_reg_top/68.xbar_same_source.3642710238 Aug 06 09:00:47 PM PDT 24 Aug 06 09:01:58 PM PDT 24 2077504904 ps
T589 /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.3110554285 Aug 06 08:51:54 PM PDT 24 Aug 06 08:52:29 PM PDT 24 371135340 ps
T611 /workspace/coverage/cover_reg_top/20.xbar_same_source.1228270442 Aug 06 08:52:14 PM PDT 24 Aug 06 08:52:51 PM PDT 24 520289469 ps
T512 /workspace/coverage/cover_reg_top/14.xbar_access_same_device.2328978290 Aug 06 08:50:08 PM PDT 24 Aug 06 08:51:33 PM PDT 24 1802036458 ps
T893 /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3231064229 Aug 06 09:03:23 PM PDT 24 Aug 06 09:19:34 PM PDT 24 57288276461 ps
T869 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.1509722413 Aug 06 08:54:34 PM PDT 24 Aug 06 08:57:19 PM PDT 24 2103125752 ps
T1431 /workspace/coverage/cover_reg_top/20.xbar_smoke.101396456 Aug 06 08:52:08 PM PDT 24 Aug 06 08:52:17 PM PDT 24 209080351 ps
T1432 /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1662244135 Aug 06 08:42:44 PM PDT 24 Aug 06 09:36:20 PM PDT 24 31469270250 ps
T679 /workspace/coverage/cover_reg_top/16.xbar_same_source.2718177857 Aug 06 08:51:02 PM PDT 24 Aug 06 08:51:47 PM PDT 24 1403703658 ps
T479 /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.1997581066 Aug 06 08:52:12 PM PDT 24 Aug 06 08:58:12 PM PDT 24 5526021572 ps
T1433 /workspace/coverage/cover_reg_top/43.xbar_smoke.187222711 Aug 06 08:56:40 PM PDT 24 Aug 06 08:56:50 PM PDT 24 192144025 ps
T881 /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.3710063907 Aug 06 09:02:34 PM PDT 24 Aug 06 09:13:04 PM PDT 24 19079758598 ps
T404 /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1113774718 Aug 06 08:45:17 PM PDT 24 Aug 06 09:44:17 PM PDT 24 30089584739 ps
T577 /workspace/coverage/cover_reg_top/89.xbar_stress_all.376451055 Aug 06 09:04:05 PM PDT 24 Aug 06 09:05:04 PM PDT 24 1455509072 ps
T1434 /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.118181457 Aug 06 08:56:25 PM PDT 24 Aug 06 08:57:46 PM PDT 24 4770986942 ps
T631 /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.4135392985 Aug 06 09:01:42 PM PDT 24 Aug 06 09:02:30 PM PDT 24 1099095998 ps
T870 /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1171435878 Aug 06 08:53:08 PM PDT 24 Aug 06 09:03:28 PM PDT 24 35666276096 ps
T614 /workspace/coverage/cover_reg_top/7.xbar_stress_all.2488402263 Aug 06 08:46:57 PM PDT 24 Aug 06 08:51:17 PM PDT 24 6278486271 ps
T1435 /workspace/coverage/cover_reg_top/31.xbar_smoke.83971827 Aug 06 08:54:37 PM PDT 24 Aug 06 08:54:45 PM PDT 24 148533262 ps
T888 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.285698236 Aug 06 08:45:44 PM PDT 24 Aug 06 08:51:44 PM PDT 24 9712700992 ps
T620 /workspace/coverage/cover_reg_top/61.xbar_stress_all.1932186900 Aug 06 08:59:41 PM PDT 24 Aug 06 09:05:33 PM PDT 24 9993509107 ps
T1436 /workspace/coverage/cover_reg_top/53.xbar_error_random.3174040779 Aug 06 08:58:28 PM PDT 24 Aug 06 08:59:33 PM PDT 24 1674863720 ps
T516 /workspace/coverage/cover_reg_top/56.xbar_stress_all.2146044510 Aug 06 08:58:57 PM PDT 24 Aug 06 09:04:01 PM PDT 24 6937393051 ps
T637 /workspace/coverage/cover_reg_top/39.xbar_random.1724579932 Aug 06 08:56:05 PM PDT 24 Aug 06 08:56:39 PM PDT 24 302424200 ps
T397 /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.415919262 Aug 06 08:50:06 PM PDT 24 Aug 06 09:05:17 PM PDT 24 10133503763 ps
T621 /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3737583633 Aug 06 08:52:55 PM PDT 24 Aug 06 09:10:30 PM PDT 24 64424325772 ps
T483 /workspace/coverage/cover_reg_top/1.xbar_random.1730034185 Aug 06 08:42:10 PM PDT 24 Aug 06 08:43:59 PM PDT 24 2596691181 ps
T1437 /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.550280942 Aug 06 08:50:17 PM PDT 24 Aug 06 09:44:21 PM PDT 24 32262869246 ps
T1438 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.3194211877 Aug 06 09:03:47 PM PDT 24 Aug 06 09:05:44 PM PDT 24 446277637 ps
T619 /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.383218700 Aug 06 08:53:51 PM PDT 24 Aug 06 09:14:41 PM PDT 24 110535366486 ps
T499 /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1529096910 Aug 06 08:43:19 PM PDT 24 Aug 06 08:43:46 PM PDT 24 251467353 ps
T898 /workspace/coverage/cover_reg_top/70.xbar_access_same_device.2191441191 Aug 06 09:01:04 PM PDT 24 Aug 06 09:01:59 PM PDT 24 535192117 ps
T711 /workspace/coverage/cover_reg_top/25.xbar_smoke.698919945 Aug 06 08:53:17 PM PDT 24 Aug 06 08:53:23 PM PDT 24 40727001 ps
T1439 /workspace/coverage/cover_reg_top/54.xbar_error_random.4217842035 Aug 06 08:58:50 PM PDT 24 Aug 06 08:58:57 PM PDT 24 111356695 ps
T1440 /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.2613669280 Aug 06 08:49:18 PM PDT 24 Aug 06 08:49:26 PM PDT 24 47381233 ps
T703 /workspace/coverage/cover_reg_top/70.xbar_same_source.2507727164 Aug 06 09:01:10 PM PDT 24 Aug 06 09:01:24 PM PDT 24 150653492 ps
T695 /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.1671208622 Aug 06 08:57:09 PM PDT 24 Aug 06 09:10:03 PM PDT 24 66068688365 ps
T880 /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.2663166852 Aug 06 08:55:35 PM PDT 24 Aug 06 09:04:52 PM PDT 24 30945916651 ps
T572 /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.1400807417 Aug 06 09:01:27 PM PDT 24 Aug 06 09:17:07 PM PDT 24 88873709177 ps
T1441 /workspace/coverage/cover_reg_top/58.xbar_error_random.2425558308 Aug 06 08:59:12 PM PDT 24 Aug 06 08:59:58 PM PDT 24 1169499299 ps
T1442 /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2523143722 Aug 06 08:43:23 PM PDT 24 Aug 06 08:45:36 PM PDT 24 12374173477 ps
T1443 /workspace/coverage/cover_reg_top/68.xbar_stress_all.3702365468 Aug 06 09:00:46 PM PDT 24 Aug 06 09:00:53 PM PDT 24 55393747 ps
T520 /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.3710391841 Aug 06 08:47:40 PM PDT 24 Aug 06 08:49:23 PM PDT 24 6486237559 ps
T1444 /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3552516192 Aug 06 09:05:22 PM PDT 24 Aug 06 09:06:21 PM PDT 24 1449531227 ps
T475 /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.2301119262 Aug 06 08:51:13 PM PDT 24 Aug 06 09:20:49 PM PDT 24 96694147217 ps
T709 /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.1046361744 Aug 06 08:44:54 PM PDT 24 Aug 06 08:46:13 PM PDT 24 6889165946 ps
T646 /workspace/coverage/cover_reg_top/92.xbar_same_source.1345549094 Aug 06 09:04:26 PM PDT 24 Aug 06 09:05:41 PM PDT 24 2218147145 ps
T531 /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.3789168843 Aug 06 08:52:27 PM PDT 24 Aug 06 09:09:14 PM PDT 24 52693501424 ps
T1445 /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.2751969229 Aug 06 09:03:23 PM PDT 24 Aug 06 09:04:18 PM PDT 24 1259627730 ps
T1446 /workspace/coverage/cover_reg_top/5.chip_csr_rw.779634779 Aug 06 08:45:47 PM PDT 24 Aug 06 08:56:36 PM PDT 24 5710537065 ps
T1447 /workspace/coverage/cover_reg_top/19.xbar_smoke.1889431882 Aug 06 08:51:47 PM PDT 24 Aug 06 08:51:54 PM PDT 24 46593007 ps
T1448 /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.2648155350 Aug 06 08:55:05 PM PDT 24 Aug 06 08:57:05 PM PDT 24 10598299405 ps
T1449 /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.3638543665 Aug 06 09:02:07 PM PDT 24 Aug 06 09:03:59 PM PDT 24 6130117066 ps
T627 /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.263374456 Aug 06 09:02:30 PM PDT 24 Aug 06 09:15:14 PM PDT 24 42614172688 ps
T1450 /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.920940497 Aug 06 09:04:43 PM PDT 24 Aug 06 09:04:51 PM PDT 24 60331340 ps
T871 /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.2061336820 Aug 06 08:53:38 PM PDT 24 Aug 06 09:16:30 PM PDT 24 79044647222 ps
T1451 /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1323440720 Aug 06 08:59:50 PM PDT 24 Aug 06 09:01:30 PM PDT 24 5875789771 ps
T587 /workspace/coverage/cover_reg_top/31.xbar_access_same_device.3970225909 Aug 06 08:54:36 PM PDT 24 Aug 06 08:55:40 PM PDT 24 829428297 ps
T1452 /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.1422005599 Aug 06 08:58:44 PM PDT 24 Aug 06 08:58:51 PM PDT 24 48685688 ps
T513 /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.1641485891 Aug 06 09:01:50 PM PDT 24 Aug 06 09:12:43 PM PDT 24 37848422419 ps
T667 /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.3026353049 Aug 06 09:03:57 PM PDT 24 Aug 06 09:04:37 PM PDT 24 420879704 ps
T1453 /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.19475989 Aug 06 09:01:07 PM PDT 24 Aug 06 09:01:40 PM PDT 24 85573074 ps
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%