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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 95.39 93.88 95.50 94.82 97.35 99.58


Total test records in report: 2935
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T938 /workspace/coverage/default/2.chip_sw_aes_masking_off.2052469016 Aug 10 08:32:50 PM PDT 24 Aug 10 08:36:55 PM PDT 24 3419064787 ps
T745 /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.940867611 Aug 10 08:46:08 PM PDT 24 Aug 10 08:54:34 PM PDT 24 4360645754 ps
T275 /workspace/coverage/default/2.chip_sw_flash_init.342338541 Aug 10 08:29:30 PM PDT 24 Aug 10 09:01:30 PM PDT 24 18011683115 ps
T669 /workspace/coverage/default/2.rom_volatile_raw_unlock.3541360567 Aug 10 08:39:16 PM PDT 24 Aug 10 08:41:08 PM PDT 24 2219848789 ps
T232 /workspace/coverage/default/83.chip_sw_all_escalation_resets.3607151083 Aug 10 08:50:25 PM PDT 24 Aug 10 08:58:29 PM PDT 24 4388507320 ps
T732 /workspace/coverage/default/59.chip_sw_all_escalation_resets.1192483144 Aug 10 08:47:35 PM PDT 24 Aug 10 08:56:22 PM PDT 24 5421177224 ps
T760 /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.40248471 Aug 10 08:49:01 PM PDT 24 Aug 10 08:55:38 PM PDT 24 3702607256 ps
T939 /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.3225491938 Aug 10 08:17:56 PM PDT 24 Aug 10 08:24:19 PM PDT 24 4976468440 ps
T35 /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.2466680364 Aug 10 08:19:56 PM PDT 24 Aug 10 08:25:15 PM PDT 24 3646737560 ps
T277 /workspace/coverage/default/1.chip_sw_flash_init.255831530 Aug 10 08:20:12 PM PDT 24 Aug 10 09:00:17 PM PDT 24 25393501796 ps
T940 /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.482428419 Aug 10 08:41:47 PM PDT 24 Aug 10 08:49:11 PM PDT 24 6885085650 ps
T312 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.4271234163 Aug 10 08:30:49 PM PDT 24 Aug 10 08:39:58 PM PDT 24 4380283144 ps
T941 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.3996198607 Aug 10 08:17:31 PM PDT 24 Aug 10 08:26:23 PM PDT 24 3947426554 ps
T942 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.3670751609 Aug 10 08:17:38 PM PDT 24 Aug 10 08:21:07 PM PDT 24 3277466946 ps
T943 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.517954519 Aug 10 08:13:34 PM PDT 24 Aug 10 08:41:44 PM PDT 24 16562589287 ps
T313 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2828970952 Aug 10 08:17:37 PM PDT 24 Aug 10 08:28:30 PM PDT 24 4677068730 ps
T170 /workspace/coverage/default/2.chip_sw_all_escalation_resets.33919784 Aug 10 08:31:26 PM PDT 24 Aug 10 08:41:42 PM PDT 24 3877212144 ps
T944 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.4218926459 Aug 10 08:27:56 PM PDT 24 Aug 10 08:32:50 PM PDT 24 3162126210 ps
T741 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1454726231 Aug 10 08:22:45 PM PDT 24 Aug 10 08:30:22 PM PDT 24 3703873428 ps
T83 /workspace/coverage/default/1.chip_jtag_mem_access.3556436665 Aug 10 08:19:04 PM PDT 24 Aug 10 08:45:14 PM PDT 24 13784002940 ps
T263 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4157690095 Aug 10 08:22:58 PM PDT 24 Aug 10 08:48:05 PM PDT 24 9228923716 ps
T411 /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.3992241867 Aug 10 08:44:29 PM PDT 24 Aug 10 09:34:17 PM PDT 24 14437703918 ps
T744 /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.102734781 Aug 10 08:50:10 PM PDT 24 Aug 10 08:56:30 PM PDT 24 4007330088 ps
T685 /workspace/coverage/default/91.chip_sw_all_escalation_resets.3379894938 Aug 10 08:51:16 PM PDT 24 Aug 10 09:01:21 PM PDT 24 5364026168 ps
T945 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2790242708 Aug 10 08:19:44 PM PDT 24 Aug 10 09:34:35 PM PDT 24 14665858632 ps
T121 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.3736153032 Aug 10 08:31:21 PM PDT 24 Aug 10 09:26:13 PM PDT 24 18543249038 ps
T227 /workspace/coverage/default/0.chip_sw_rv_timer_irq.1747695664 Aug 10 08:12:19 PM PDT 24 Aug 10 08:17:05 PM PDT 24 2608212836 ps
T946 /workspace/coverage/default/2.chip_sw_edn_sw_mode.884554821 Aug 10 08:33:46 PM PDT 24 Aug 10 09:03:24 PM PDT 24 7758346734 ps
T720 /workspace/coverage/default/18.chip_sw_all_escalation_resets.3221300025 Aug 10 08:45:22 PM PDT 24 Aug 10 08:54:23 PM PDT 24 4754016280 ps
T296 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3981514214 Aug 10 08:29:47 PM PDT 24 Aug 10 08:44:38 PM PDT 24 5323089090 ps
T947 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.713403888 Aug 10 08:26:14 PM PDT 24 Aug 10 10:20:40 PM PDT 24 17661260343 ps
T63 /workspace/coverage/default/2.chip_sw_sleep_pin_wake.1089429863 Aug 10 08:29:20 PM PDT 24 Aug 10 08:33:50 PM PDT 24 3407070920 ps
T948 /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.3896771499 Aug 10 08:43:47 PM PDT 24 Aug 10 10:12:40 PM PDT 24 22212936952 ps
T949 /workspace/coverage/default/1.chip_sw_kmac_app_rom.3733174221 Aug 10 08:27:59 PM PDT 24 Aug 10 08:32:16 PM PDT 24 3058577760 ps
T125 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1181695164 Aug 10 08:35:59 PM PDT 24 Aug 10 08:47:19 PM PDT 24 3523444916 ps
T324 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3240393244 Aug 10 08:18:31 PM PDT 24 Aug 10 08:27:24 PM PDT 24 3896990120 ps
T950 /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3082143968 Aug 10 08:32:15 PM PDT 24 Aug 10 08:39:14 PM PDT 24 6936411828 ps
T667 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3197468301 Aug 10 08:14:45 PM PDT 24 Aug 10 10:34:08 PM PDT 24 35344361334 ps
T195 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2316991325 Aug 10 08:18:22 PM PDT 24 Aug 10 08:27:42 PM PDT 24 4921428971 ps
T119 /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.1736712541 Aug 10 08:38:39 PM PDT 24 Aug 10 09:11:33 PM PDT 24 16918616625 ps
T951 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3747231646 Aug 10 08:33:41 PM PDT 24 Aug 10 08:38:46 PM PDT 24 3201635000 ps
T952 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1120112165 Aug 10 08:35:39 PM PDT 24 Aug 10 08:40:04 PM PDT 24 3273748311 ps
T953 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1795038212 Aug 10 08:34:15 PM PDT 24 Aug 10 09:05:44 PM PDT 24 8920582224 ps
T954 /workspace/coverage/default/1.rom_e2e_self_hash.2126180144 Aug 10 08:34:14 PM PDT 24 Aug 10 10:31:22 PM PDT 24 26193547400 ps
T955 /workspace/coverage/default/2.chip_sw_aes_enc.1937557323 Aug 10 08:34:53 PM PDT 24 Aug 10 08:38:52 PM PDT 24 2846638160 ps
T956 /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.4073010427 Aug 10 08:23:02 PM PDT 24 Aug 10 08:46:21 PM PDT 24 7270325970 ps
T306 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.3084006993 Aug 10 08:34:04 PM PDT 24 Aug 10 09:05:47 PM PDT 24 6996564942 ps
T155 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3823956316 Aug 10 08:38:59 PM PDT 24 Aug 10 09:36:00 PM PDT 24 25124198417 ps
T957 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1935068379 Aug 10 08:20:48 PM PDT 24 Aug 10 08:53:52 PM PDT 24 25042816260 ps
T958 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.889213470 Aug 10 08:43:39 PM PDT 24 Aug 10 09:12:33 PM PDT 24 8266398152 ps
T959 /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.3265448004 Aug 10 08:41:19 PM PDT 24 Aug 10 08:44:06 PM PDT 24 2139742370 ps
T960 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3218678214 Aug 10 08:33:55 PM PDT 24 Aug 10 09:30:26 PM PDT 24 14533082114 ps
T410 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.1483251700 Aug 10 08:23:34 PM PDT 24 Aug 10 08:40:26 PM PDT 24 6582235278 ps
T961 /workspace/coverage/default/1.chip_sw_hmac_oneshot.2173553728 Aug 10 08:24:24 PM PDT 24 Aug 10 08:28:35 PM PDT 24 3298359724 ps
T256 /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3050276896 Aug 10 08:36:14 PM PDT 24 Aug 10 08:40:19 PM PDT 24 2656055520 ps
T36 /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.2069899894 Aug 10 08:30:10 PM PDT 24 Aug 10 08:35:10 PM PDT 24 2824554680 ps
T962 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.882345268 Aug 10 08:13:20 PM PDT 24 Aug 10 08:19:08 PM PDT 24 3167855084 ps
T511 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.3773589582 Aug 10 08:11:54 PM PDT 24 Aug 10 08:39:55 PM PDT 24 10503073267 ps
T963 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3853890899 Aug 10 08:13:51 PM PDT 24 Aug 10 08:17:52 PM PDT 24 2351146984 ps
T964 /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.4028537786 Aug 10 08:19:28 PM PDT 24 Aug 10 08:27:08 PM PDT 24 5369753663 ps
T965 /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.2474363019 Aug 10 08:45:00 PM PDT 24 Aug 10 09:09:43 PM PDT 24 8985997474 ps
T265 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1813915572 Aug 10 08:14:43 PM PDT 24 Aug 10 08:55:59 PM PDT 24 11370324858 ps
T712 /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2999467558 Aug 10 08:47:50 PM PDT 24 Aug 10 08:54:20 PM PDT 24 3586872492 ps
T966 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2679284653 Aug 10 08:41:28 PM PDT 24 Aug 10 09:13:10 PM PDT 24 8929425240 ps
T804 /workspace/coverage/default/48.chip_sw_all_escalation_resets.2240638459 Aug 10 08:47:47 PM PDT 24 Aug 10 08:58:00 PM PDT 24 5396408000 ps
T967 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.201605968 Aug 10 08:31:29 PM PDT 24 Aug 10 08:42:15 PM PDT 24 5399202386 ps
T796 /workspace/coverage/default/7.chip_sw_all_escalation_resets.2874043366 Aug 10 08:43:32 PM PDT 24 Aug 10 08:51:51 PM PDT 24 5239385000 ps
T968 /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.997753791 Aug 10 08:32:03 PM PDT 24 Aug 10 08:41:20 PM PDT 24 3733859070 ps
T711 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.2330403331 Aug 10 08:16:58 PM PDT 24 Aug 10 08:53:15 PM PDT 24 11103182443 ps
T969 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.728513015 Aug 10 08:09:36 PM PDT 24 Aug 10 08:19:23 PM PDT 24 4751371744 ps
T293 /workspace/coverage/default/2.chip_plic_all_irqs_0.612030182 Aug 10 08:37:02 PM PDT 24 Aug 10 08:54:59 PM PDT 24 6080269006 ps
T333 /workspace/coverage/default/0.chip_sw_flash_crash_alert.2739302777 Aug 10 08:13:47 PM PDT 24 Aug 10 08:23:29 PM PDT 24 4444408700 ps
T797 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.2044172973 Aug 10 08:49:13 PM PDT 24 Aug 10 08:55:28 PM PDT 24 3808777500 ps
T798 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.557706776 Aug 10 08:13:20 PM PDT 24 Aug 10 08:20:06 PM PDT 24 3795171688 ps
T257 /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.1631842157 Aug 10 08:26:02 PM PDT 24 Aug 10 08:30:22 PM PDT 24 3053715730 ps
T970 /workspace/coverage/default/0.chip_sw_aes_entropy.3008521110 Aug 10 08:13:08 PM PDT 24 Aug 10 08:17:40 PM PDT 24 2302440640 ps
T971 /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.393802328 Aug 10 08:11:48 PM PDT 24 Aug 10 08:35:11 PM PDT 24 9133565000 ps
T972 /workspace/coverage/default/2.chip_sw_csrng_smoketest.304843125 Aug 10 08:38:30 PM PDT 24 Aug 10 08:43:39 PM PDT 24 2653908524 ps
T668 /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.184326007 Aug 10 08:47:49 PM PDT 24 Aug 10 08:54:36 PM PDT 24 3536627012 ps
T973 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3323401021 Aug 10 08:18:22 PM PDT 24 Aug 10 08:21:51 PM PDT 24 2770797960 ps
T974 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.679410953 Aug 10 08:22:32 PM PDT 24 Aug 10 09:34:11 PM PDT 24 15336889472 ps
T975 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4205000687 Aug 10 08:25:26 PM PDT 24 Aug 10 08:33:20 PM PDT 24 6595112760 ps
T670 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2639833905 Aug 10 08:13:07 PM PDT 24 Aug 10 08:14:54 PM PDT 24 1784725049 ps
T730 /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.77396001 Aug 10 08:43:11 PM PDT 24 Aug 10 08:51:51 PM PDT 24 3755075208 ps
T284 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3940164373 Aug 10 08:45:26 PM PDT 24 Aug 10 08:52:05 PM PDT 24 3940605170 ps
T671 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3086860454 Aug 10 08:10:44 PM PDT 24 Aug 10 08:12:15 PM PDT 24 2965514402 ps
T976 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.2300714135 Aug 10 08:33:02 PM PDT 24 Aug 10 08:42:47 PM PDT 24 6777003975 ps
T977 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.4218381533 Aug 10 08:26:06 PM PDT 24 Aug 10 10:37:17 PM PDT 24 24052887394 ps
T21 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.1201584163 Aug 10 08:26:30 PM PDT 24 Aug 10 09:00:16 PM PDT 24 24257249468 ps
T672 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.2225098486 Aug 10 08:24:12 PM PDT 24 Aug 10 08:25:56 PM PDT 24 2013046085 ps
T978 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2138740031 Aug 10 08:37:15 PM PDT 24 Aug 10 08:45:39 PM PDT 24 3470157832 ps
T979 /workspace/coverage/default/2.rom_keymgr_functest.1635562368 Aug 10 08:40:19 PM PDT 24 Aug 10 08:48:56 PM PDT 24 5027202868 ps
T264 /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2922457344 Aug 10 08:38:39 PM PDT 24 Aug 10 08:46:09 PM PDT 24 4894065339 ps
T980 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.2910525531 Aug 10 08:11:22 PM PDT 24 Aug 10 08:22:35 PM PDT 24 7247909090 ps
T400 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.3254468003 Aug 10 08:15:35 PM PDT 24 Aug 10 09:04:05 PM PDT 24 32504087515 ps
T276 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.383523489 Aug 10 08:37:11 PM PDT 24 Aug 10 09:05:55 PM PDT 24 19531004699 ps
T981 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1614970653 Aug 10 08:22:19 PM PDT 24 Aug 10 09:23:57 PM PDT 24 15338876152 ps
T982 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2187406574 Aug 10 08:14:39 PM PDT 24 Aug 10 08:19:53 PM PDT 24 3311953845 ps
T771 /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2430336146 Aug 10 08:46:04 PM PDT 24 Aug 10 08:53:21 PM PDT 24 3874438440 ps
T983 /workspace/coverage/default/0.chip_tap_straps_testunlock0.3597866164 Aug 10 08:14:52 PM PDT 24 Aug 10 08:23:05 PM PDT 24 4632465505 ps
T984 /workspace/coverage/default/2.chip_tap_straps_prod.3401963345 Aug 10 08:36:24 PM PDT 24 Aug 10 08:39:12 PM PDT 24 3423987887 ps
T985 /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.2564150109 Aug 10 08:37:41 PM PDT 24 Aug 10 08:43:40 PM PDT 24 2789045000 ps
T986 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.1710749476 Aug 10 08:28:11 PM PDT 24 Aug 10 08:32:55 PM PDT 24 3246825460 ps
T224 /workspace/coverage/default/2.chip_sw_plic_sw_irq.452569088 Aug 10 08:35:33 PM PDT 24 Aug 10 08:40:25 PM PDT 24 2739548220 ps
T295 /workspace/coverage/default/0.chip_plic_all_irqs_20.504287819 Aug 10 08:13:58 PM PDT 24 Aug 10 08:30:50 PM PDT 24 4726377176 ps
T270 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4168696519 Aug 10 08:27:39 PM PDT 24 Aug 10 08:53:53 PM PDT 24 10054055340 ps
T987 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.723144949 Aug 10 08:21:49 PM PDT 24 Aug 10 09:52:33 PM PDT 24 23448775390 ps
T764 /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.1936090354 Aug 10 08:45:17 PM PDT 24 Aug 10 08:50:23 PM PDT 24 2794854100 ps
T722 /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536267937 Aug 10 08:47:20 PM PDT 24 Aug 10 08:53:52 PM PDT 24 3712059900 ps
T988 /workspace/coverage/default/0.rom_keymgr_functest.2834962582 Aug 10 08:16:15 PM PDT 24 Aug 10 08:25:51 PM PDT 24 3954053790 ps
T989 /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.535153230 Aug 10 08:31:10 PM PDT 24 Aug 10 08:37:38 PM PDT 24 4053592312 ps
T673 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.551746891 Aug 10 08:20:00 PM PDT 24 Aug 10 08:21:46 PM PDT 24 2154633738 ps
T990 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.910074652 Aug 10 08:13:25 PM PDT 24 Aug 10 09:16:58 PM PDT 24 21098150591 ps
T991 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3303989675 Aug 10 08:36:24 PM PDT 24 Aug 10 08:47:34 PM PDT 24 4184919790 ps
T992 /workspace/coverage/default/2.rom_e2e_self_hash.4220090982 Aug 10 08:42:50 PM PDT 24 Aug 10 10:25:16 PM PDT 24 26551273600 ps
T355 /workspace/coverage/default/74.chip_sw_all_escalation_resets.2579078876 Aug 10 08:48:59 PM PDT 24 Aug 10 08:58:06 PM PDT 24 5346118022 ps
T993 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.4234172846 Aug 10 08:35:14 PM PDT 24 Aug 10 08:39:51 PM PDT 24 3140884296 ps
T273 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.1284387660 Aug 10 08:32:35 PM PDT 24 Aug 10 08:41:49 PM PDT 24 5733962880 ps
T994 /workspace/coverage/default/41.chip_sw_all_escalation_resets.3660505606 Aug 10 08:45:39 PM PDT 24 Aug 10 08:54:50 PM PDT 24 6110810312 ps
T800 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.3812126697 Aug 10 08:47:50 PM PDT 24 Aug 10 08:54:36 PM PDT 24 4130162016 ps
T61 /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3310940200 Aug 10 08:20:23 PM PDT 24 Aug 10 08:25:33 PM PDT 24 3680699202 ps
T995 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3277008032 Aug 10 08:12:41 PM PDT 24 Aug 10 08:36:33 PM PDT 24 4664235560 ps
T996 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3241938537 Aug 10 08:35:48 PM PDT 24 Aug 10 08:47:58 PM PDT 24 4515634450 ps
T997 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.446127489 Aug 10 08:12:12 PM PDT 24 Aug 10 08:20:29 PM PDT 24 4678147000 ps
T160 /workspace/coverage/default/1.chip_plic_all_irqs_10.3697949231 Aug 10 08:25:00 PM PDT 24 Aug 10 08:35:02 PM PDT 24 4232525968 ps
T819 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.2299463042 Aug 10 08:50:08 PM PDT 24 Aug 10 08:56:23 PM PDT 24 4016148938 ps
T998 /workspace/coverage/default/2.chip_sw_example_rom.4266261615 Aug 10 08:28:26 PM PDT 24 Aug 10 08:30:40 PM PDT 24 2948979168 ps
T999 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.290110356 Aug 10 08:12:10 PM PDT 24 Aug 10 08:18:07 PM PDT 24 4516014182 ps
T1000 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3143255263 Aug 10 08:26:06 PM PDT 24 Aug 10 08:33:21 PM PDT 24 3365698340 ps
T742 /workspace/coverage/default/80.chip_sw_all_escalation_resets.2639297803 Aug 10 08:49:54 PM PDT 24 Aug 10 08:58:38 PM PDT 24 5275938280 ps
T11 /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.449080180 Aug 10 08:28:44 PM PDT 24 Aug 10 08:34:11 PM PDT 24 3277183532 ps
T1001 /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3007192541 Aug 10 08:44:36 PM PDT 24 Aug 10 08:52:45 PM PDT 24 4264598712 ps
T327 /workspace/coverage/default/3.chip_sw_uart_tx_rx.1717705977 Aug 10 08:41:10 PM PDT 24 Aug 10 08:55:04 PM PDT 24 4028508484 ps
T1002 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.4173532055 Aug 10 08:42:51 PM PDT 24 Aug 10 08:50:32 PM PDT 24 5942500812 ps
T87 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.776490124 Aug 10 08:33:08 PM PDT 24 Aug 10 11:39:09 PM PDT 24 255930396560 ps
T210 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.267358892 Aug 10 08:34:02 PM PDT 24 Aug 10 09:03:48 PM PDT 24 8444290758 ps
T1003 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.630769047 Aug 10 08:12:27 PM PDT 24 Aug 10 09:05:20 PM PDT 24 38313515972 ps
T156 /workspace/coverage/default/2.chip_sw_otbn_smoketest.2854614124 Aug 10 08:39:54 PM PDT 24 Aug 10 08:55:25 PM PDT 24 5928458352 ps
T807 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2404130522 Aug 10 08:45:57 PM PDT 24 Aug 10 08:51:23 PM PDT 24 3140211904 ps
T1004 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1592411154 Aug 10 08:40:57 PM PDT 24 Aug 10 08:58:55 PM PDT 24 8727621942 ps
T747 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1521433925 Aug 10 08:50:24 PM PDT 24 Aug 10 08:58:59 PM PDT 24 5125816792 ps
T171 /workspace/coverage/default/92.chip_sw_all_escalation_resets.3169348177 Aug 10 08:51:25 PM PDT 24 Aug 10 08:59:22 PM PDT 24 5087769384 ps
T1005 /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.2485457168 Aug 10 08:49:37 PM PDT 24 Aug 10 08:57:15 PM PDT 24 3603609882 ps
T1006 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1802927270 Aug 10 08:13:30 PM PDT 24 Aug 10 08:56:41 PM PDT 24 32847226046 ps
T151 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3557359852 Aug 10 08:31:07 PM PDT 24 Aug 10 08:39:17 PM PDT 24 7602474854 ps
T1007 /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.4015328396 Aug 10 08:11:53 PM PDT 24 Aug 10 08:19:48 PM PDT 24 3847637380 ps
T78 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3848879913 Aug 10 08:37:06 PM PDT 24 Aug 10 09:07:15 PM PDT 24 24676921776 ps
T1008 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1476768117 Aug 10 08:36:30 PM PDT 24 Aug 10 08:47:20 PM PDT 24 5916706700 ps
T1009 /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.4034617799 Aug 10 08:34:57 PM PDT 24 Aug 10 09:08:41 PM PDT 24 28044839842 ps
T1010 /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3707170874 Aug 10 08:46:17 PM PDT 24 Aug 10 08:56:40 PM PDT 24 3831819496 ps
T367 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.1296883232 Aug 10 08:20:24 PM PDT 24 Aug 10 08:24:42 PM PDT 24 2930995350 ps
T1011 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3197024405 Aug 10 08:31:55 PM PDT 24 Aug 10 08:48:09 PM PDT 24 5238247834 ps
T70 /workspace/coverage/default/1.chip_tap_straps_testunlock0.3553532687 Aug 10 08:25:23 PM PDT 24 Aug 10 08:34:41 PM PDT 24 6426254715 ps
T799 /workspace/coverage/default/57.chip_sw_all_escalation_resets.1007401920 Aug 10 08:48:12 PM PDT 24 Aug 10 09:00:23 PM PDT 24 5060870518 ps
T113 /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.63079378 Aug 10 08:15:27 PM PDT 24 Aug 10 08:24:23 PM PDT 24 4515998916 ps
T340 /workspace/coverage/default/47.chip_sw_all_escalation_resets.3738016324 Aug 10 08:46:37 PM PDT 24 Aug 10 08:56:42 PM PDT 24 5638800034 ps
T1012 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1354047011 Aug 10 08:37:30 PM PDT 24 Aug 10 08:42:28 PM PDT 24 3441498881 ps
T820 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.4055454898 Aug 10 08:50:00 PM PDT 24 Aug 10 08:55:48 PM PDT 24 3752672250 ps
T1013 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2540756419 Aug 10 08:21:05 PM PDT 24 Aug 10 09:18:55 PM PDT 24 20537772971 ps
T1014 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.3741750430 Aug 10 08:42:35 PM PDT 24 Aug 10 08:51:33 PM PDT 24 3889686367 ps
T721 /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1072501103 Aug 10 08:45:24 PM PDT 24 Aug 10 08:51:36 PM PDT 24 3910561164 ps
T104 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3762471154 Aug 10 08:13:33 PM PDT 24 Aug 10 08:44:02 PM PDT 24 26378249160 ps
T1015 /workspace/coverage/default/1.chip_sw_aes_idle.664010748 Aug 10 08:22:56 PM PDT 24 Aug 10 08:28:58 PM PDT 24 3423834442 ps
T1016 /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3187867736 Aug 10 08:46:26 PM PDT 24 Aug 10 08:53:18 PM PDT 24 4027403664 ps
T1017 /workspace/coverage/default/4.chip_tap_straps_dev.2314586352 Aug 10 08:42:21 PM PDT 24 Aug 10 08:47:05 PM PDT 24 3467057534 ps
T25 /workspace/coverage/default/0.chip_sw_usbdev_dpi.1501209175 Aug 10 08:11:39 PM PDT 24 Aug 10 09:03:37 PM PDT 24 12018819768 ps
T1018 /workspace/coverage/default/1.chip_sw_hmac_smoketest.1873883900 Aug 10 08:28:37 PM PDT 24 Aug 10 08:33:03 PM PDT 24 3393660768 ps
T207 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4186315547 Aug 10 08:11:30 PM PDT 24 Aug 10 08:23:57 PM PDT 24 4950959943 ps
T163 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.222233581 Aug 10 08:22:43 PM PDT 24 Aug 10 08:45:55 PM PDT 24 12094120420 ps
T221 /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.3686306021 Aug 10 08:45:34 PM PDT 24 Aug 10 08:53:12 PM PDT 24 4265931380 ps
T248 /workspace/coverage/default/13.chip_sw_all_escalation_resets.3585491280 Aug 10 08:45:11 PM PDT 24 Aug 10 08:54:59 PM PDT 24 5394017216 ps
T249 /workspace/coverage/default/2.chip_sw_csrng_kat_test.526069447 Aug 10 08:33:33 PM PDT 24 Aug 10 08:38:01 PM PDT 24 2245290528 ps
T62 /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.3723243619 Aug 10 08:30:30 PM PDT 24 Aug 10 08:37:00 PM PDT 24 4088185038 ps
T250 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.503389321 Aug 10 08:18:29 PM PDT 24 Aug 10 08:23:02 PM PDT 24 2490990640 ps
T251 /workspace/coverage/default/45.chip_sw_all_escalation_resets.3814144535 Aug 10 08:46:04 PM PDT 24 Aug 10 08:54:05 PM PDT 24 4464627052 ps
T252 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2489189219 Aug 10 08:12:27 PM PDT 24 Aug 10 08:20:35 PM PDT 24 4540725194 ps
T253 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1990395479 Aug 10 08:25:59 PM PDT 24 Aug 10 08:33:38 PM PDT 24 4740017980 ps
T254 /workspace/coverage/default/1.chip_sw_flash_crash_alert.3010276767 Aug 10 08:27:55 PM PDT 24 Aug 10 08:39:04 PM PDT 24 5285282400 ps
T246 /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1247805568 Aug 10 08:33:14 PM PDT 24 Aug 10 08:41:15 PM PDT 24 3758184342 ps
T161 /workspace/coverage/default/2.chip_plic_all_irqs_10.4002482627 Aug 10 08:38:33 PM PDT 24 Aug 10 08:48:57 PM PDT 24 3288812442 ps
T1019 /workspace/coverage/default/1.chip_sw_otbn_smoketest.2681828978 Aug 10 08:30:53 PM PDT 24 Aug 10 09:05:14 PM PDT 24 9953378186 ps
T778 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1234731202 Aug 10 08:47:44 PM PDT 24 Aug 10 08:54:38 PM PDT 24 3647600872 ps
T1020 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2191066532 Aug 10 08:20:11 PM PDT 24 Aug 10 08:34:41 PM PDT 24 4649586694 ps
T1021 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3442994468 Aug 10 08:33:56 PM PDT 24 Aug 10 08:43:32 PM PDT 24 6228365210 ps
T1022 /workspace/coverage/default/1.chip_sw_kmac_idle.1115435534 Aug 10 08:28:24 PM PDT 24 Aug 10 08:33:20 PM PDT 24 3424871296 ps
T1023 /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2606443355 Aug 10 08:17:46 PM PDT 24 Aug 10 08:21:55 PM PDT 24 2906001992 ps
T310 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.1291922617 Aug 10 08:18:58 PM PDT 24 Aug 10 08:32:42 PM PDT 24 4689645320 ps
T723 /workspace/coverage/default/49.chip_sw_all_escalation_resets.2358901654 Aug 10 08:48:19 PM PDT 24 Aug 10 09:00:53 PM PDT 24 6061796684 ps
T1024 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.3953176346 Aug 10 08:41:50 PM PDT 24 Aug 10 08:52:31 PM PDT 24 3792361804 ps
T1025 /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.847934506 Aug 10 08:10:51 PM PDT 24 Aug 10 09:33:53 PM PDT 24 28089192970 ps
T1026 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2344707308 Aug 10 08:16:31 PM PDT 24 Aug 10 08:20:17 PM PDT 24 2406551450 ps
T1027 /workspace/coverage/default/1.rom_e2e_shutdown_output.3380778928 Aug 10 08:32:22 PM PDT 24 Aug 10 09:24:34 PM PDT 24 24755781424 ps
T28 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.1169806227 Aug 10 08:19:00 PM PDT 24 Aug 10 08:23:44 PM PDT 24 3897120516 ps
T58 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.2890250510 Aug 10 08:10:18 PM PDT 24 Aug 10 08:15:01 PM PDT 24 4215685880 ps
T725 /workspace/coverage/default/61.chip_sw_all_escalation_resets.1959480958 Aug 10 08:46:56 PM PDT 24 Aug 10 08:56:11 PM PDT 24 5393363114 ps
T311 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.1886211473 Aug 10 08:29:48 PM PDT 24 Aug 10 08:41:53 PM PDT 24 4867680000 ps
T1028 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3809821863 Aug 10 08:10:59 PM PDT 24 Aug 10 08:19:24 PM PDT 24 6558980808 ps
T1029 /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.693290698 Aug 10 08:39:22 PM PDT 24 Aug 10 08:42:28 PM PDT 24 2275985444 ps
T1030 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.4014588730 Aug 10 08:12:23 PM PDT 24 Aug 10 08:29:58 PM PDT 24 8111489365 ps
T1031 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2614079244 Aug 10 08:35:51 PM PDT 24 Aug 10 08:40:56 PM PDT 24 2833813076 ps
T1032 /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.753336048 Aug 10 08:28:21 PM PDT 24 Aug 10 08:46:14 PM PDT 24 5666379126 ps
T754 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3866594794 Aug 10 08:47:10 PM PDT 24 Aug 10 08:53:00 PM PDT 24 3034637692 ps
T743 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.711218237 Aug 10 08:44:45 PM PDT 24 Aug 10 08:51:54 PM PDT 24 4153804672 ps
T782 /workspace/coverage/default/68.chip_sw_all_escalation_resets.218348914 Aug 10 08:48:28 PM PDT 24 Aug 10 08:59:00 PM PDT 24 4718862216 ps
T1033 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3664976074 Aug 10 08:12:25 PM PDT 24 Aug 10 08:18:13 PM PDT 24 5104350290 ps
T1034 /workspace/coverage/default/1.chip_sw_uart_tx_rx.1914473895 Aug 10 08:19:03 PM PDT 24 Aug 10 08:29:36 PM PDT 24 4192385604 ps
T297 /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2825875609 Aug 10 08:31:09 PM PDT 24 Aug 10 08:46:09 PM PDT 24 5124862372 ps
T1035 /workspace/coverage/default/11.chip_sw_all_escalation_resets.1147662361 Aug 10 08:44:30 PM PDT 24 Aug 10 08:54:15 PM PDT 24 5850181576 ps
T664 /workspace/coverage/default/0.chip_sw_edn_boot_mode.2833870172 Aug 10 08:11:56 PM PDT 24 Aug 10 08:21:44 PM PDT 24 3346969800 ps
T329 /workspace/coverage/default/1.chip_sw_pattgen_ios.2042185266 Aug 10 08:18:21 PM PDT 24 Aug 10 08:22:21 PM PDT 24 3404064900 ps
T1036 /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.281275227 Aug 10 08:27:02 PM PDT 24 Aug 10 08:33:10 PM PDT 24 3480235364 ps
T781 /workspace/coverage/default/71.chip_sw_all_escalation_resets.2225387907 Aug 10 08:47:55 PM PDT 24 Aug 10 08:59:22 PM PDT 24 4463504210 ps
T1037 /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2400036884 Aug 10 08:46:24 PM PDT 24 Aug 10 08:52:55 PM PDT 24 3590038440 ps
T247 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3784996020 Aug 10 08:36:56 PM PDT 24 Aug 10 08:44:59 PM PDT 24 3924983207 ps
T1038 /workspace/coverage/default/1.chip_sw_aes_smoketest.2341220906 Aug 10 08:28:17 PM PDT 24 Aug 10 08:32:40 PM PDT 24 2491801816 ps
T1039 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.2159867617 Aug 10 08:26:50 PM PDT 24 Aug 10 08:34:09 PM PDT 24 6561097480 ps
T1040 /workspace/coverage/default/44.chip_sw_all_escalation_resets.177563633 Aug 10 08:46:12 PM PDT 24 Aug 10 08:56:31 PM PDT 24 5624596176 ps
T233 /workspace/coverage/default/30.chip_sw_all_escalation_resets.4198748736 Aug 10 08:45:16 PM PDT 24 Aug 10 08:55:23 PM PDT 24 4962090728 ps
T92 /workspace/coverage/default/16.chip_sw_all_escalation_resets.4163301232 Aug 10 08:44:37 PM PDT 24 Aug 10 08:54:28 PM PDT 24 3971076634 ps
T1041 /workspace/coverage/default/0.chip_sw_uart_smoketest.3585717637 Aug 10 08:17:34 PM PDT 24 Aug 10 08:21:43 PM PDT 24 3069552752 ps
T1042 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1572448841 Aug 10 08:13:28 PM PDT 24 Aug 10 08:29:57 PM PDT 24 5226802388 ps
T1043 /workspace/coverage/default/2.chip_sw_hmac_oneshot.4132110561 Aug 10 08:34:14 PM PDT 24 Aug 10 08:41:13 PM PDT 24 3531686544 ps
T1044 /workspace/coverage/default/0.chip_sw_kmac_smoketest.3411499702 Aug 10 08:18:25 PM PDT 24 Aug 10 08:22:33 PM PDT 24 3032995828 ps
T1045 /workspace/coverage/default/0.chip_sw_example_rom.348986880 Aug 10 08:10:57 PM PDT 24 Aug 10 08:13:08 PM PDT 24 1935182296 ps
T149 /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.4081735079 Aug 10 08:15:33 PM PDT 24 Aug 10 08:53:48 PM PDT 24 16983374837 ps
T784 /workspace/coverage/default/32.chip_sw_all_escalation_resets.69909742 Aug 10 08:46:29 PM PDT 24 Aug 10 08:56:46 PM PDT 24 4416102040 ps
T1046 /workspace/coverage/default/82.chip_sw_all_escalation_resets.621566700 Aug 10 08:49:24 PM PDT 24 Aug 10 08:58:54 PM PDT 24 5902579876 ps
T1047 /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.4270789534 Aug 10 08:27:49 PM PDT 24 Aug 10 09:00:00 PM PDT 24 9925038800 ps
T1048 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.899272005 Aug 10 08:13:26 PM PDT 24 Aug 10 08:38:28 PM PDT 24 11418356160 ps
T1049 /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.3779326508 Aug 10 08:11:11 PM PDT 24 Aug 10 08:25:44 PM PDT 24 7777220420 ps
T665 /workspace/coverage/default/1.chip_sw_edn_boot_mode.3377756151 Aug 10 08:23:31 PM PDT 24 Aug 10 08:33:09 PM PDT 24 3527688752 ps
T1050 /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3248640596 Aug 10 08:32:54 PM PDT 24 Aug 10 08:42:00 PM PDT 24 5720922920 ps
T29 /workspace/coverage/default/0.chip_sw_gpio.2170967905 Aug 10 08:13:56 PM PDT 24 Aug 10 08:21:34 PM PDT 24 3791248904 ps
T93 /workspace/coverage/default/42.chip_sw_all_escalation_resets.840667258 Aug 10 08:46:34 PM PDT 24 Aug 10 08:56:00 PM PDT 24 4941406784 ps
T1051 /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.1350660935 Aug 10 08:17:21 PM PDT 24 Aug 10 08:23:43 PM PDT 24 3038724120 ps
T1052 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.3015078109 Aug 10 08:35:00 PM PDT 24 Aug 10 08:51:51 PM PDT 24 9058436792 ps
T1053 /workspace/coverage/default/4.chip_tap_straps_prod.689854334 Aug 10 08:41:24 PM PDT 24 Aug 10 09:14:01 PM PDT 24 17314544679 ps
T345 /workspace/coverage/default/1.chip_sw_hmac_enc.3427554203 Aug 10 08:23:23 PM PDT 24 Aug 10 08:29:01 PM PDT 24 2766300480 ps
T1054 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.633700219 Aug 10 08:16:56 PM PDT 24 Aug 10 08:20:03 PM PDT 24 2191622026 ps
T301 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2211420567 Aug 10 08:11:55 PM PDT 24 Aug 10 08:38:52 PM PDT 24 12711937700 ps
T84 /workspace/coverage/default/1.chip_jtag_csr_rw.950449942 Aug 10 08:19:10 PM PDT 24 Aug 10 08:39:54 PM PDT 24 10683460768 ps
T274 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1477295339 Aug 10 08:12:43 PM PDT 24 Aug 10 08:45:58 PM PDT 24 26191920137 ps
T1055 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2454491596 Aug 10 08:36:05 PM PDT 24 Aug 10 08:46:33 PM PDT 24 4339378212 ps
T748 /workspace/coverage/default/58.chip_sw_all_escalation_resets.2503169580 Aug 10 08:48:03 PM PDT 24 Aug 10 08:56:54 PM PDT 24 4611783680 ps
T666 /workspace/coverage/default/2.chip_sw_edn_boot_mode.1184643337 Aug 10 08:35:07 PM PDT 24 Aug 10 08:47:21 PM PDT 24 2983360500 ps
T775 /workspace/coverage/default/21.chip_sw_all_escalation_resets.94834973 Aug 10 08:45:24 PM PDT 24 Aug 10 08:53:29 PM PDT 24 5077192584 ps
T1056 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.293005787 Aug 10 08:25:12 PM PDT 24 Aug 10 08:36:12 PM PDT 24 4523396302 ps
T751 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1638461263 Aug 10 08:46:16 PM PDT 24 Aug 10 08:53:03 PM PDT 24 3049499782 ps
T1057 /workspace/coverage/default/0.rom_e2e_static_critical.3675968290 Aug 10 08:22:07 PM PDT 24 Aug 10 09:40:17 PM PDT 24 17130688540 ps
T1058 /workspace/coverage/default/0.chip_sw_alert_handler_entropy.782841288 Aug 10 08:12:12 PM PDT 24 Aug 10 08:16:50 PM PDT 24 2838819041 ps
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