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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 95.39 93.88 95.50 94.82 97.35 99.58


Total test records in report: 2935
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T1220 /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2712482129 Aug 10 08:43:45 PM PDT 24 Aug 10 09:36:53 PM PDT 24 15863333992 ps
T1221 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.1391395568 Aug 10 08:12:58 PM PDT 24 Aug 10 08:18:04 PM PDT 24 3034253901 ps
T175 /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.3638266345 Aug 10 08:26:57 PM PDT 24 Aug 10 08:36:49 PM PDT 24 5232937584 ps
T1222 /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.1303654403 Aug 10 08:42:16 PM PDT 24 Aug 10 10:17:30 PM PDT 24 26860752648 ps
T1223 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3210919716 Aug 10 08:50:20 PM PDT 24 Aug 10 08:57:57 PM PDT 24 5427206808 ps
T158 /workspace/coverage/default/2.rom_raw_unlock.2079547211 Aug 10 08:40:05 PM PDT 24 Aug 10 08:44:11 PM PDT 24 5826444740 ps
T30 /workspace/coverage/default/2.chip_sw_gpio.1640209366 Aug 10 08:31:17 PM PDT 24 Aug 10 08:39:58 PM PDT 24 3749000200 ps
T1224 /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.499904926 Aug 10 08:38:52 PM PDT 24 Aug 10 08:56:03 PM PDT 24 5959076764 ps
T1225 /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2255238596 Aug 10 08:33:30 PM PDT 24 Aug 10 08:43:35 PM PDT 24 19180042952 ps
T1226 /workspace/coverage/default/0.chip_sw_aes_enc.582811767 Aug 10 08:12:33 PM PDT 24 Aug 10 08:17:30 PM PDT 24 3435777814 ps
T309 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.1825657923 Aug 10 08:12:33 PM PDT 24 Aug 10 08:23:24 PM PDT 24 4735844440 ps
T809 /workspace/coverage/default/14.chip_sw_all_escalation_resets.1055572937 Aug 10 08:44:53 PM PDT 24 Aug 10 08:55:29 PM PDT 24 5404079352 ps
T1227 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.940794840 Aug 10 08:43:21 PM PDT 24 Aug 10 09:34:21 PM PDT 24 15214230932 ps
T791 /workspace/coverage/default/37.chip_sw_all_escalation_resets.920094935 Aug 10 08:46:56 PM PDT 24 Aug 10 08:57:47 PM PDT 24 5111081168 ps
T1228 /workspace/coverage/default/1.chip_sw_kmac_smoketest.3157469541 Aug 10 08:29:59 PM PDT 24 Aug 10 08:36:12 PM PDT 24 3313818760 ps
T1229 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1703819779 Aug 10 08:43:43 PM PDT 24 Aug 10 08:50:31 PM PDT 24 6678449129 ps
T1230 /workspace/coverage/default/0.chip_sw_gpio_smoketest.4091443741 Aug 10 08:17:38 PM PDT 24 Aug 10 08:22:25 PM PDT 24 2780263142 ps
T1231 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.2850355539 Aug 10 08:26:26 PM PDT 24 Aug 10 08:42:39 PM PDT 24 6561284266 ps
T1232 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.1470225826 Aug 10 08:14:21 PM PDT 24 Aug 10 08:54:58 PM PDT 24 28931086896 ps
T1233 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.43240223 Aug 10 08:20:15 PM PDT 24 Aug 10 09:32:30 PM PDT 24 14909876608 ps
T1234 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2751815302 Aug 10 08:34:43 PM PDT 24 Aug 10 08:56:07 PM PDT 24 5940942108 ps
T237 /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1383688094 Aug 10 08:10:44 PM PDT 24 Aug 10 08:23:47 PM PDT 24 5835608948 ps
T1235 /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.2724326729 Aug 10 08:34:07 PM PDT 24 Aug 10 08:59:28 PM PDT 24 6258483160 ps
T759 /workspace/coverage/default/77.chip_sw_all_escalation_resets.3221795304 Aug 10 08:48:31 PM PDT 24 Aug 10 08:59:05 PM PDT 24 4565337600 ps
T1236 /workspace/coverage/default/0.chip_sw_flash_init.659931423 Aug 10 08:10:29 PM PDT 24 Aug 10 08:49:14 PM PDT 24 22541875015 ps
T1237 /workspace/coverage/default/2.chip_sw_edn_kat.3996572818 Aug 10 08:34:01 PM PDT 24 Aug 10 08:44:24 PM PDT 24 3346334384 ps
T1238 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2000773147 Aug 10 08:24:45 PM PDT 24 Aug 10 08:52:24 PM PDT 24 6846206052 ps
T1239 /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.1712244903 Aug 10 08:44:51 PM PDT 24 Aug 10 09:13:20 PM PDT 24 9117573420 ps
T1240 /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1625537407 Aug 10 08:26:02 PM PDT 24 Aug 10 08:37:17 PM PDT 24 4498351856 ps
T1241 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2840128108 Aug 10 08:35:20 PM PDT 24 Aug 10 09:00:26 PM PDT 24 12238788940 ps
T1242 /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3744946683 Aug 10 08:23:21 PM PDT 24 Aug 10 08:27:17 PM PDT 24 2706763440 ps
T94 /workspace/coverage/default/72.chip_sw_all_escalation_resets.608169817 Aug 10 08:48:37 PM PDT 24 Aug 10 09:00:09 PM PDT 24 6125955030 ps
T1243 /workspace/coverage/default/2.chip_sw_otbn_randomness.485910655 Aug 10 08:33:04 PM PDT 24 Aug 10 08:49:28 PM PDT 24 5323742048 ps
T1244 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3472229186 Aug 10 08:13:53 PM PDT 24 Aug 10 08:41:23 PM PDT 24 7336337302 ps
T1245 /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3868459889 Aug 10 08:22:13 PM PDT 24 Aug 10 09:20:35 PM PDT 24 15094057132 ps
T1246 /workspace/coverage/default/2.chip_sw_hmac_smoketest.2829075062 Aug 10 08:39:52 PM PDT 24 Aug 10 08:46:29 PM PDT 24 3051480392 ps
T1247 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.560508315 Aug 10 08:29:07 PM PDT 24 Aug 10 08:36:29 PM PDT 24 5394080388 ps
T1248 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.4068719109 Aug 10 08:22:27 PM PDT 24 Aug 10 09:24:33 PM PDT 24 14284118652 ps
T77 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1370974350 Aug 10 08:11:59 PM PDT 24 Aug 10 08:15:24 PM PDT 24 2496577160 ps
T1249 /workspace/coverage/default/34.chip_sw_all_escalation_resets.1483098602 Aug 10 08:46:11 PM PDT 24 Aug 10 08:54:47 PM PDT 24 5119229452 ps
T1250 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.559566824 Aug 10 08:31:12 PM PDT 24 Aug 10 09:02:06 PM PDT 24 23240472526 ps
T42 /workspace/coverage/default/1.chip_sw_spi_device_tpm.3933020209 Aug 10 08:17:46 PM PDT 24 Aug 10 08:25:09 PM PDT 24 4157902654 ps
T1251 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4208370180 Aug 10 08:42:55 PM PDT 24 Aug 10 08:50:01 PM PDT 24 3596958650 ps
T162 /workspace/coverage/default/0.chip_plic_all_irqs_10.1571659053 Aug 10 08:13:58 PM PDT 24 Aug 10 08:23:55 PM PDT 24 4110457712 ps
T281 /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.2678070490 Aug 10 08:19:45 PM PDT 24 Aug 10 09:52:29 PM PDT 24 47933035160 ps
T1252 /workspace/coverage/default/2.chip_sw_rv_timer_irq.809666219 Aug 10 08:33:01 PM PDT 24 Aug 10 08:39:14 PM PDT 24 2781694120 ps
T794 /workspace/coverage/default/93.chip_sw_all_escalation_resets.362424133 Aug 10 08:50:48 PM PDT 24 Aug 10 09:02:41 PM PDT 24 5543877480 ps
T815 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.162278523 Aug 10 08:46:29 PM PDT 24 Aug 10 08:52:43 PM PDT 24 3941315178 ps
T1253 /workspace/coverage/default/2.rom_e2e_asm_init_prod.2952201316 Aug 10 08:43:21 PM PDT 24 Aug 10 09:33:52 PM PDT 24 15373840283 ps
T1254 /workspace/coverage/default/0.chip_sw_example_manufacturer.1341673075 Aug 10 08:10:54 PM PDT 24 Aug 10 08:15:06 PM PDT 24 2758619380 ps
T1255 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2120601635 Aug 10 08:25:17 PM PDT 24 Aug 10 09:14:54 PM PDT 24 27584281682 ps
T1256 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3483808372 Aug 10 08:12:23 PM PDT 24 Aug 10 08:20:12 PM PDT 24 4252408008 ps
T1257 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.792281568 Aug 10 08:19:30 PM PDT 24 Aug 10 08:41:08 PM PDT 24 7159279428 ps
T370 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.72584424 Aug 10 08:21:09 PM PDT 24 Aug 10 09:40:43 PM PDT 24 18564753584 ps
T1258 /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.1617960509 Aug 10 08:22:43 PM PDT 24 Aug 10 08:36:38 PM PDT 24 5692752024 ps
T271 /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.479007232 Aug 10 08:11:45 PM PDT 24 Aug 10 09:11:50 PM PDT 24 13204697818 ps
T769 /workspace/coverage/default/8.chip_sw_all_escalation_resets.3114368488 Aug 10 08:44:27 PM PDT 24 Aug 10 08:55:10 PM PDT 24 5650640728 ps
T1259 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3594338075 Aug 10 08:15:01 PM PDT 24 Aug 10 08:24:12 PM PDT 24 5013658162 ps
T1260 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3326285423 Aug 10 08:33:57 PM PDT 24 Aug 10 08:38:37 PM PDT 24 3506660252 ps
T1261 /workspace/coverage/default/2.chip_tap_straps_testunlock0.682803678 Aug 10 08:35:58 PM PDT 24 Aug 10 08:45:34 PM PDT 24 5647568847 ps
T1262 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3976291675 Aug 10 08:13:18 PM PDT 24 Aug 10 08:24:43 PM PDT 24 7665973036 ps
T1263 /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.2913098980 Aug 10 08:43:30 PM PDT 24 Aug 10 09:06:32 PM PDT 24 8592788302 ps
T1264 /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2635989191 Aug 10 08:13:00 PM PDT 24 Aug 10 08:31:54 PM PDT 24 8104037784 ps
T1265 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.676563086 Aug 10 08:29:02 PM PDT 24 Aug 10 08:33:45 PM PDT 24 3186256656 ps
T1266 /workspace/coverage/default/1.rom_e2e_static_critical.1640356615 Aug 10 08:38:32 PM PDT 24 Aug 10 09:51:14 PM PDT 24 16640803248 ps
T765 /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.2328671900 Aug 10 08:48:32 PM PDT 24 Aug 10 08:54:44 PM PDT 24 3654722172 ps
T1267 /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.3382249455 Aug 10 08:17:02 PM PDT 24 Aug 10 08:22:42 PM PDT 24 3158646960 ps
T53 /workspace/coverage/default/0.chip_jtag_csr_rw.794713476 Aug 10 08:05:20 PM PDT 24 Aug 10 08:37:45 PM PDT 24 16898855668 ps
T1268 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2699364024 Aug 10 08:33:02 PM PDT 24 Aug 10 10:02:23 PM PDT 24 48219706070 ps
T1269 /workspace/coverage/default/2.chip_sw_example_concurrency.2701651740 Aug 10 08:29:03 PM PDT 24 Aug 10 08:33:22 PM PDT 24 2961855710 ps
T1270 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.142809070 Aug 10 08:15:14 PM PDT 24 Aug 10 08:27:58 PM PDT 24 3877886916 ps
T1271 /workspace/coverage/default/0.chip_sival_flash_info_access.255860137 Aug 10 08:11:23 PM PDT 24 Aug 10 08:17:26 PM PDT 24 3165364968 ps
T1272 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1497634398 Aug 10 08:17:39 PM PDT 24 Aug 10 08:35:05 PM PDT 24 7521999142 ps
T1273 /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.2229515517 Aug 10 08:15:03 PM PDT 24 Aug 10 08:20:35 PM PDT 24 2587125672 ps
T1274 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3016753037 Aug 10 08:12:32 PM PDT 24 Aug 10 08:21:40 PM PDT 24 5679064480 ps
T1275 /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.4249522749 Aug 10 08:18:44 PM PDT 24 Aug 10 09:42:13 PM PDT 24 44211571682 ps
T795 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.4191890060 Aug 10 08:45:27 PM PDT 24 Aug 10 08:52:53 PM PDT 24 3897162724 ps
T1276 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3328025965 Aug 10 08:23:12 PM PDT 24 Aug 10 08:33:16 PM PDT 24 5644558456 ps
T1277 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4074088490 Aug 10 08:43:05 PM PDT 24 Aug 10 08:59:52 PM PDT 24 13232374322 ps
T1278 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.2446555345 Aug 10 08:23:01 PM PDT 24 Aug 10 10:27:49 PM PDT 24 24076934360 ps
T1279 /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1343665837 Aug 10 08:41:58 PM PDT 24 Aug 10 08:57:21 PM PDT 24 8244408739 ps
T1280 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2466428747 Aug 10 08:24:36 PM PDT 24 Aug 10 08:31:46 PM PDT 24 3825400172 ps
T1281 /workspace/coverage/default/2.chip_sw_example_flash.3206247686 Aug 10 08:29:49 PM PDT 24 Aug 10 08:34:28 PM PDT 24 2315677880 ps
T1282 /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1916332050 Aug 10 08:34:36 PM PDT 24 Aug 10 08:39:27 PM PDT 24 3458509652 ps
T1283 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2377939569 Aug 10 08:22:17 PM PDT 24 Aug 10 09:14:18 PM PDT 24 11417324400 ps
T1284 /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2281007624 Aug 10 08:24:03 PM PDT 24 Aug 10 08:26:48 PM PDT 24 4019002172 ps
T287 /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1320975695 Aug 10 08:46:42 PM PDT 24 Aug 10 08:53:32 PM PDT 24 3174280640 ps
T1285 /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3252956865 Aug 10 08:11:55 PM PDT 24 Aug 10 08:21:40 PM PDT 24 18572476960 ps
T686 /workspace/coverage/default/27.chip_sw_all_escalation_resets.2906093149 Aug 10 08:45:41 PM PDT 24 Aug 10 08:54:17 PM PDT 24 6358044184 ps
T810 /workspace/coverage/default/99.chip_sw_all_escalation_resets.1991969145 Aug 10 08:51:31 PM PDT 24 Aug 10 09:01:11 PM PDT 24 6299803522 ps
T1286 /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2579728742 Aug 10 08:49:16 PM PDT 24 Aug 10 08:55:22 PM PDT 24 4203812224 ps
T211 /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3168135730 Aug 10 08:18:28 PM PDT 24 Aug 10 08:23:09 PM PDT 24 3091950312 ps
T1287 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3480222004 Aug 10 08:35:19 PM PDT 24 Aug 10 08:52:29 PM PDT 24 13093880445 ps
T1288 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2150112219 Aug 10 08:30:31 PM PDT 24 Aug 10 08:51:44 PM PDT 24 7859048575 ps
T817 /workspace/coverage/default/66.chip_sw_all_escalation_resets.2611661096 Aug 10 08:49:39 PM PDT 24 Aug 10 09:00:02 PM PDT 24 4784348420 ps
T1289 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.4206007404 Aug 10 08:22:20 PM PDT 24 Aug 10 10:01:36 PM PDT 24 50628374670 ps
T1290 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3687586530 Aug 10 08:12:41 PM PDT 24 Aug 10 08:21:14 PM PDT 24 3844405548 ps
T1291 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.19394204 Aug 10 08:14:06 PM PDT 24 Aug 10 08:35:29 PM PDT 24 5670672757 ps
T1292 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.471750142 Aug 10 08:51:19 PM PDT 24 Aug 10 08:58:23 PM PDT 24 3392446520 ps
T1293 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1831377618 Aug 10 08:15:24 PM PDT 24 Aug 10 09:20:37 PM PDT 24 24643406074 ps
T824 /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.3454953335 Aug 10 08:44:48 PM PDT 24 Aug 10 08:53:25 PM PDT 24 3731989210 ps
T1294 /workspace/coverage/default/2.chip_sw_kmac_entropy.2217020138 Aug 10 08:31:15 PM PDT 24 Aug 10 08:36:30 PM PDT 24 2666430336 ps
T1295 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.675099436 Aug 10 08:14:26 PM PDT 24 Aug 10 08:19:09 PM PDT 24 3332293913 ps
T1296 /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.821620393 Aug 10 08:32:24 PM PDT 24 Aug 10 09:37:03 PM PDT 24 15696257848 ps
T1297 /workspace/coverage/default/0.chip_sw_example_concurrency.2681475426 Aug 10 08:10:52 PM PDT 24 Aug 10 08:14:01 PM PDT 24 2484684200 ps
T1298 /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.1216123689 Aug 10 08:13:51 PM PDT 24 Aug 10 08:41:16 PM PDT 24 7740024212 ps
T1299 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3598778213 Aug 10 08:14:02 PM PDT 24 Aug 10 08:18:14 PM PDT 24 3160809320 ps
T1300 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1576126871 Aug 10 08:19:22 PM PDT 24 Aug 10 08:37:04 PM PDT 24 6681578568 ps
T1301 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2937869292 Aug 10 08:45:01 PM PDT 24 Aug 10 09:13:20 PM PDT 24 8997760606 ps
T1302 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2349188624 Aug 10 08:13:43 PM PDT 24 Aug 10 08:25:58 PM PDT 24 5724756108 ps
T1303 /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.3818688566 Aug 10 08:25:16 PM PDT 24 Aug 10 08:35:52 PM PDT 24 5061659176 ps
T1304 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2015698409 Aug 10 08:12:44 PM PDT 24 Aug 10 08:46:24 PM PDT 24 7137480972 ps
T1305 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.678996323 Aug 10 08:21:02 PM PDT 24 Aug 10 08:50:15 PM PDT 24 14310042162 ps
T1306 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3206236875 Aug 10 08:29:53 PM PDT 24 Aug 10 08:41:33 PM PDT 24 4436709739 ps
T1307 /workspace/coverage/default/2.chip_tap_straps_rma.1467254807 Aug 10 08:36:13 PM PDT 24 Aug 10 08:55:20 PM PDT 24 11673607483 ps
T1308 /workspace/coverage/default/2.chip_sw_edn_auto_mode.2430179107 Aug 10 08:34:47 PM PDT 24 Aug 10 08:53:28 PM PDT 24 4384642152 ps
T1309 /workspace/coverage/default/0.chip_sw_usbdev_config_host.488780100 Aug 10 08:11:47 PM PDT 24 Aug 10 08:41:16 PM PDT 24 8612544840 ps
T1310 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1324117513 Aug 10 08:38:32 PM PDT 24 Aug 10 09:30:36 PM PDT 24 20570119307 ps
T1311 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2048767597 Aug 10 08:32:09 PM PDT 24 Aug 10 09:31:19 PM PDT 24 15003784802 ps
T1312 /workspace/coverage/default/0.rom_raw_unlock.3473108983 Aug 10 08:18:19 PM PDT 24 Aug 10 08:22:10 PM PDT 24 6814808545 ps
T792 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1781313398 Aug 10 08:49:28 PM PDT 24 Aug 10 08:59:45 PM PDT 24 4485147616 ps
T1313 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3908606389 Aug 10 08:25:28 PM PDT 24 Aug 10 08:32:13 PM PDT 24 3404026024 ps
T1314 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.2036036548 Aug 10 08:36:40 PM PDT 24 Aug 10 08:45:53 PM PDT 24 4976205738 ps
T774 /workspace/coverage/default/29.chip_sw_all_escalation_resets.1098232768 Aug 10 08:45:56 PM PDT 24 Aug 10 08:53:06 PM PDT 24 4502207390 ps
T1315 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2486229917 Aug 10 08:18:03 PM PDT 24 Aug 10 08:31:25 PM PDT 24 5235729094 ps
T789 /workspace/coverage/default/19.chip_sw_all_escalation_resets.4256530466 Aug 10 08:45:05 PM PDT 24 Aug 10 08:54:17 PM PDT 24 5865406760 ps
T1316 /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.3689265229 Aug 10 08:33:36 PM PDT 24 Aug 10 08:46:38 PM PDT 24 8906894636 ps
T756 /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2282158805 Aug 10 08:48:22 PM PDT 24 Aug 10 08:53:03 PM PDT 24 3578265400 ps
T166 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.996566862 Aug 10 08:10:50 PM PDT 24 Aug 10 08:12:37 PM PDT 24 2860995523 ps
T1317 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.778551127 Aug 10 08:20:08 PM PDT 24 Aug 10 09:24:46 PM PDT 24 14404537534 ps
T1318 /workspace/coverage/default/0.chip_tap_straps_prod.3317594933 Aug 10 08:13:24 PM PDT 24 Aug 10 08:22:32 PM PDT 24 5742610341 ps
T59 /workspace/coverage/default/2.chip_sw_sleep_pin_retention.3428185573 Aug 10 08:30:17 PM PDT 24 Aug 10 08:36:55 PM PDT 24 4233042444 ps
T1319 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4048656935 Aug 10 08:37:57 PM PDT 24 Aug 10 08:49:42 PM PDT 24 4506061700 ps
T1320 /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.3035448038 Aug 10 08:47:15 PM PDT 24 Aug 10 08:54:17 PM PDT 24 3942312398 ps
T1321 /workspace/coverage/default/3.chip_tap_straps_dev.3507030816 Aug 10 08:40:23 PM PDT 24 Aug 10 08:44:12 PM PDT 24 3282809958 ps
T1322 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.4026655391 Aug 10 08:32:25 PM PDT 24 Aug 10 08:41:48 PM PDT 24 4712925700 ps
T1323 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1891375105 Aug 10 08:18:45 PM PDT 24 Aug 10 08:36:25 PM PDT 24 6014957924 ps
T758 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1139355666 Aug 10 08:44:58 PM PDT 24 Aug 10 08:57:50 PM PDT 24 5720920576 ps
T1324 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.686753868 Aug 10 08:19:30 PM PDT 24 Aug 10 09:17:16 PM PDT 24 14336661768 ps
T1325 /workspace/coverage/default/0.chip_sw_uart_tx_rx.3968665864 Aug 10 08:10:43 PM PDT 24 Aug 10 08:21:12 PM PDT 24 4132795030 ps
T1326 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2730387183 Aug 10 08:10:23 PM PDT 24 Aug 10 08:18:18 PM PDT 24 4336018772 ps
T344 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3270854219 Aug 10 08:14:15 PM PDT 24 Aug 10 08:24:43 PM PDT 24 3403514728 ps
T39 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.919964909 Aug 10 08:12:31 PM PDT 24 Aug 10 08:20:22 PM PDT 24 6402380194 ps
T1327 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.2432496903 Aug 10 08:22:54 PM PDT 24 Aug 10 08:29:01 PM PDT 24 3717042783 ps
T1328 /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.606322277 Aug 10 08:42:49 PM PDT 24 Aug 10 10:07:25 PM PDT 24 22523872802 ps
T1329 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.4058278122 Aug 10 08:41:11 PM PDT 24 Aug 10 08:53:42 PM PDT 24 6997175486 ps
T1330 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2950004223 Aug 10 08:33:22 PM PDT 24 Aug 10 08:40:05 PM PDT 24 3879565742 ps
T1331 /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3953145377 Aug 10 08:44:23 PM PDT 24 Aug 10 09:13:06 PM PDT 24 8790599956 ps
T394 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.869032630 Aug 10 08:37:14 PM PDT 24 Aug 10 08:44:51 PM PDT 24 7223052272 ps
T1332 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.116661340 Aug 10 08:31:02 PM PDT 24 Aug 10 09:00:53 PM PDT 24 9876491599 ps
T1333 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.847364479 Aug 10 08:30:10 PM PDT 24 Aug 10 09:42:04 PM PDT 24 24676121087 ps
T1334 /workspace/coverage/default/2.chip_sw_kmac_smoketest.2020871012 Aug 10 08:39:53 PM PDT 24 Aug 10 08:44:45 PM PDT 24 2426497540 ps
T1335 /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.3642393590 Aug 10 08:33:58 PM PDT 24 Aug 10 09:08:29 PM PDT 24 9801374936 ps
T1336 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.410987802 Aug 10 08:11:46 PM PDT 24 Aug 10 08:21:53 PM PDT 24 9125585800 ps
T1337 /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3306258849 Aug 10 08:10:30 PM PDT 24 Aug 10 09:37:04 PM PDT 24 44403442090 ps
T1338 /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3425217878 Aug 10 08:23:16 PM PDT 24 Aug 10 08:27:55 PM PDT 24 3227302908 ps
T1339 /workspace/coverage/default/1.chip_sw_data_integrity_escalation.1252325379 Aug 10 08:16:43 PM PDT 24 Aug 10 08:26:42 PM PDT 24 5226077340 ps
T1340 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.613386981 Aug 10 08:14:49 PM PDT 24 Aug 10 08:33:42 PM PDT 24 5844902880 ps
T142 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1649346316 Aug 10 08:41:06 PM PDT 24 Aug 10 08:48:10 PM PDT 24 5343449338 ps
T1341 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.1506082511 Aug 10 08:43:32 PM PDT 24 Aug 10 09:05:35 PM PDT 24 8638146940 ps
T1342 /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.1577128368 Aug 10 08:12:46 PM PDT 24 Aug 10 08:36:21 PM PDT 24 7815091341 ps
T1343 /workspace/coverage/default/1.rom_e2e_asm_init_dev.3346432196 Aug 10 08:32:44 PM PDT 24 Aug 10 09:48:33 PM PDT 24 15083111768 ps
T770 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.1399811282 Aug 10 08:45:52 PM PDT 24 Aug 10 08:53:43 PM PDT 24 3721179404 ps
T1344 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.243592812 Aug 10 08:23:33 PM PDT 24 Aug 10 09:40:13 PM PDT 24 15772722370 ps
T1345 /workspace/coverage/default/2.chip_sw_aes_smoketest.3628644028 Aug 10 08:39:45 PM PDT 24 Aug 10 08:43:58 PM PDT 24 2821189680 ps
T719 /workspace/coverage/default/10.chip_sw_all_escalation_resets.3385530131 Aug 10 08:44:24 PM PDT 24 Aug 10 08:55:41 PM PDT 24 5405849364 ps
T1346 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2097430284 Aug 10 08:32:14 PM PDT 24 Aug 10 08:39:25 PM PDT 24 7611617418 ps
T1347 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3690398349 Aug 10 08:31:05 PM PDT 24 Aug 10 08:45:33 PM PDT 24 4583980440 ps
T786 /workspace/coverage/default/69.chip_sw_all_escalation_resets.4029565829 Aug 10 08:48:46 PM PDT 24 Aug 10 09:00:15 PM PDT 24 5641155336 ps
T1348 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2074029441 Aug 10 08:20:17 PM PDT 24 Aug 10 08:32:24 PM PDT 24 4543279170 ps
T1349 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1331132353 Aug 10 08:10:38 PM PDT 24 Aug 10 08:36:50 PM PDT 24 24629065824 ps
T1350 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4211060965 Aug 10 08:13:16 PM PDT 24 Aug 10 08:24:13 PM PDT 24 4071722536 ps
T180 /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.865660838 Aug 10 08:29:35 PM PDT 24 Aug 10 09:54:29 PM PDT 24 43058747528 ps
T95 /workspace/coverage/default/40.chip_sw_all_escalation_resets.1347136815 Aug 10 08:44:44 PM PDT 24 Aug 10 08:56:03 PM PDT 24 5703800100 ps
T1351 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.2057176553 Aug 10 08:42:25 PM PDT 24 Aug 10 09:44:31 PM PDT 24 15855217272 ps
T1352 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1463787198 Aug 10 08:20:37 PM PDT 24 Aug 10 08:29:32 PM PDT 24 7008795634 ps
T223 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1265082691 Aug 10 08:49:15 PM PDT 24 Aug 10 08:54:39 PM PDT 24 3681500222 ps
T1353 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.170085570 Aug 10 08:30:26 PM PDT 24 Aug 10 08:55:44 PM PDT 24 8067695680 ps
T750 /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.3526419876 Aug 10 08:48:49 PM PDT 24 Aug 10 08:55:23 PM PDT 24 4132281234 ps
T1354 /workspace/coverage/default/2.chip_sw_gpio_smoketest.1142086467 Aug 10 08:40:52 PM PDT 24 Aug 10 08:46:10 PM PDT 24 2581968860 ps
T1355 /workspace/coverage/default/2.chip_sw_kmac_app_rom.2484936527 Aug 10 08:34:49 PM PDT 24 Aug 10 08:39:17 PM PDT 24 3389702652 ps
T816 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3897203509 Aug 10 08:48:09 PM PDT 24 Aug 10 08:53:51 PM PDT 24 3490028680 ps
T757 /workspace/coverage/default/64.chip_sw_all_escalation_resets.1405543559 Aug 10 08:47:36 PM PDT 24 Aug 10 08:56:06 PM PDT 24 4835107944 ps
T1356 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2562336087 Aug 10 08:11:48 PM PDT 24 Aug 10 11:11:43 PM PDT 24 64805144167 ps
T1357 /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3535796497 Aug 10 08:45:29 PM PDT 24 Aug 10 09:08:11 PM PDT 24 8152091980 ps
T1358 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1968204075 Aug 10 08:31:22 PM PDT 24 Aug 10 08:40:57 PM PDT 24 4057326828 ps
T1359 /workspace/coverage/default/0.chip_sw_aes_masking_off.925675248 Aug 10 08:12:59 PM PDT 24 Aug 10 08:16:53 PM PDT 24 2836226187 ps
T1360 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4282550736 Aug 10 08:10:42 PM PDT 24 Aug 10 08:32:05 PM PDT 24 7684456600 ps
T1361 /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.1421804123 Aug 10 08:50:10 PM PDT 24 Aug 10 08:56:19 PM PDT 24 3458287132 ps
T317 /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.3282923435 Aug 10 08:37:51 PM PDT 24 Aug 10 08:45:53 PM PDT 24 4183730940 ps
T1362 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2468651675 Aug 10 08:22:17 PM PDT 24 Aug 10 09:24:52 PM PDT 24 14425057758 ps
T1363 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.318192375 Aug 10 08:11:11 PM PDT 24 Aug 10 08:13:26 PM PDT 24 2788044322 ps
T1364 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3835200867 Aug 10 08:48:04 PM PDT 24 Aug 10 08:54:43 PM PDT 24 4216139340 ps
T755 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2805638992 Aug 10 08:45:22 PM PDT 24 Aug 10 08:52:36 PM PDT 24 4171637852 ps
T299 /workspace/coverage/default/1.chip_plic_all_irqs_0.3788250889 Aug 10 08:26:35 PM PDT 24 Aug 10 08:47:12 PM PDT 24 6027649768 ps
T1365 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1516851425 Aug 10 08:12:17 PM PDT 24 Aug 10 09:11:10 PM PDT 24 17313874850 ps
T1366 /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1560971783 Aug 10 08:38:22 PM PDT 24 Aug 10 09:33:14 PM PDT 24 15185661020 ps
T707 /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2976839685 Aug 10 08:23:15 PM PDT 24 Aug 10 08:36:57 PM PDT 24 4870259480 ps
T43 /workspace/coverage/default/0.chip_sw_spi_device_tpm.1754952811 Aug 10 08:14:10 PM PDT 24 Aug 10 08:20:54 PM PDT 24 2859658780 ps
T1367 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2732845873 Aug 10 08:12:43 PM PDT 24 Aug 10 08:23:56 PM PDT 24 7397909720 ps
T1368 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2989746029 Aug 10 08:31:20 PM PDT 24 Aug 10 08:47:31 PM PDT 24 7484676656 ps
T1369 /workspace/coverage/default/2.chip_sw_kmac_idle.2922458991 Aug 10 08:38:15 PM PDT 24 Aug 10 08:43:28 PM PDT 24 2860816162 ps
T1370 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.620018576 Aug 10 08:11:35 PM PDT 24 Aug 10 11:14:42 PM PDT 24 59056790921 ps
T777 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2712668335 Aug 10 08:48:25 PM PDT 24 Aug 10 09:00:13 PM PDT 24 6627470424 ps
T1371 /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.3350165750 Aug 10 08:44:45 PM PDT 24 Aug 10 09:28:18 PM PDT 24 13942942320 ps
T1372 /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.3252740564 Aug 10 08:18:39 PM PDT 24 Aug 10 08:36:05 PM PDT 24 5135499002 ps
T1373 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3396135017 Aug 10 08:35:50 PM PDT 24 Aug 10 09:32:19 PM PDT 24 11602050621 ps
T1374 /workspace/coverage/default/1.chip_sw_csrng_smoketest.1061076065 Aug 10 08:28:36 PM PDT 24 Aug 10 08:33:45 PM PDT 24 2705473604 ps
T319 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.306734933 Aug 10 08:20:19 PM PDT 24 Aug 10 08:31:51 PM PDT 24 3899806702 ps
T1375 /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.606489604 Aug 10 08:13:20 PM PDT 24 Aug 10 08:22:59 PM PDT 24 4593229100 ps
T1376 /workspace/coverage/default/3.chip_tap_straps_prod.247631152 Aug 10 08:40:23 PM PDT 24 Aug 10 08:42:56 PM PDT 24 2081220575 ps
T1377 /workspace/coverage/default/2.chip_sw_data_integrity_escalation.3339721191 Aug 10 08:28:22 PM PDT 24 Aug 10 08:38:00 PM PDT 24 5595167454 ps
T1378 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3913129789 Aug 10 08:30:59 PM PDT 24 Aug 10 10:11:12 PM PDT 24 49069799216 ps
T300 /workspace/coverage/default/0.chip_plic_all_irqs_0.1556478945 Aug 10 08:12:54 PM PDT 24 Aug 10 08:29:22 PM PDT 24 5522350696 ps
T772 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.177691561 Aug 10 08:45:57 PM PDT 24 Aug 10 08:52:00 PM PDT 24 3468647976 ps
T1379 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.3217963686 Aug 10 08:11:47 PM PDT 24 Aug 10 08:35:33 PM PDT 24 7895968196 ps
T1380 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.49362084 Aug 10 08:40:37 PM PDT 24 Aug 10 08:51:17 PM PDT 24 4153762734 ps
T708 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1512680640 Aug 10 08:14:09 PM PDT 24 Aug 10 08:28:19 PM PDT 24 5121773634 ps
T1381 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1337478351 Aug 10 08:27:55 PM PDT 24 Aug 10 08:31:21 PM PDT 24 2688312948 ps
T1382 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.441806803 Aug 10 08:20:34 PM PDT 24 Aug 10 09:35:45 PM PDT 24 15445416926 ps
T315 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.1202777714 Aug 10 08:20:25 PM PDT 24 Aug 10 08:31:25 PM PDT 24 4145163564 ps
T783 /workspace/coverage/default/75.chip_sw_all_escalation_resets.3007639572 Aug 10 08:47:56 PM PDT 24 Aug 10 08:56:05 PM PDT 24 5152098520 ps
T716 /workspace/coverage/default/79.chip_sw_all_escalation_resets.2475397272 Aug 10 08:49:05 PM PDT 24 Aug 10 08:58:05 PM PDT 24 4745394880 ps
T1383 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2878748235 Aug 10 08:34:29 PM PDT 24 Aug 10 10:15:33 PM PDT 24 44899658920 ps
T1384 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3641604438 Aug 10 08:20:53 PM PDT 24 Aug 10 08:26:27 PM PDT 24 5000702382 ps
T1385 /workspace/coverage/default/1.rom_e2e_smoke.259655493 Aug 10 08:32:45 PM PDT 24 Aug 10 09:45:44 PM PDT 24 14601060546 ps
T766 /workspace/coverage/default/20.chip_sw_all_escalation_resets.894290073 Aug 10 08:44:20 PM PDT 24 Aug 10 08:56:37 PM PDT 24 5114658306 ps
T1386 /workspace/coverage/default/0.chip_sw_hmac_enc.4248903229 Aug 10 08:14:02 PM PDT 24 Aug 10 08:19:48 PM PDT 24 3402730324 ps
T1387 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3793882001 Aug 10 08:41:41 PM PDT 24 Aug 10 08:48:40 PM PDT 24 3354390574 ps
T753 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2827323296 Aug 10 08:42:00 PM PDT 24 Aug 10 08:48:50 PM PDT 24 3825792650 ps
T1388 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2538694526 Aug 10 08:22:12 PM PDT 24 Aug 10 10:04:46 PM PDT 24 23921755074 ps
T1389 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.1498712318 Aug 10 08:33:04 PM PDT 24 Aug 10 08:44:12 PM PDT 24 4777023376 ps
T337 /workspace/coverage/default/2.chip_sw_pattgen_ios.2228552971 Aug 10 08:29:31 PM PDT 24 Aug 10 08:34:39 PM PDT 24 2990276202 ps
T1390 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3559338183 Aug 10 08:44:22 PM PDT 24 Aug 10 08:52:23 PM PDT 24 6615624465 ps
T1391 /workspace/coverage/default/0.chip_sw_usbdev_stream.2223369805 Aug 10 08:12:18 PM PDT 24 Aug 10 09:23:33 PM PDT 24 18972340428 ps
T1392 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2598529090 Aug 10 08:24:24 PM PDT 24 Aug 10 09:04:42 PM PDT 24 12338861754 ps
T1393 /workspace/coverage/default/1.chip_tap_straps_dev.1401090166 Aug 10 08:25:14 PM PDT 24 Aug 10 08:44:50 PM PDT 24 10578086707 ps
T352 /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2356888405 Aug 10 08:26:32 PM PDT 24 Aug 10 08:36:10 PM PDT 24 6783457440 ps
T1394 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1786086009 Aug 10 08:28:09 PM PDT 24 Aug 10 08:36:17 PM PDT 24 4085042847 ps
T1395 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3728591365 Aug 10 08:12:36 PM PDT 24 Aug 10 08:16:21 PM PDT 24 3093070064 ps
T1396 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2034228372 Aug 10 08:22:29 PM PDT 24 Aug 10 08:48:21 PM PDT 24 7865393950 ps
T1397 /workspace/coverage/default/87.chip_sw_all_escalation_resets.1527344093 Aug 10 08:49:48 PM PDT 24 Aug 10 09:01:49 PM PDT 24 5211557992 ps
T1398 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1639318682 Aug 10 08:16:02 PM PDT 24 Aug 10 08:26:06 PM PDT 24 5568810712 ps
T395 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.714834258 Aug 10 08:36:23 PM PDT 24 Aug 10 08:59:07 PM PDT 24 19401702100 ps
T167 /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1962269225 Aug 10 08:32:21 PM PDT 24 Aug 10 08:36:12 PM PDT 24 3252155095 ps
T1399 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2876090061 Aug 10 08:30:30 PM PDT 24 Aug 10 08:40:23 PM PDT 24 4372819866 ps
T199 /workspace/coverage/default/0.chip_sw_power_virus.1173927478 Aug 10 08:19:56 PM PDT 24 Aug 10 08:43:20 PM PDT 24 5999445800 ps
T1400 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2787356906 Aug 10 08:41:06 PM PDT 24 Aug 10 08:47:26 PM PDT 24 6338949560 ps
T320 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3874352960 Aug 10 08:37:00 PM PDT 24 Aug 10 08:47:50 PM PDT 24 5090941272 ps
T40 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.250872144 Aug 10 08:22:00 PM PDT 24 Aug 10 08:29:42 PM PDT 24 5844213270 ps
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