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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.09 95.39 93.88 95.50 94.82 97.35 99.58


Total test records in report: 2935
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T805 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.4046829066 Aug 10 08:49:01 PM PDT 24 Aug 10 08:54:21 PM PDT 24 3060843626 ps
T1059 /workspace/coverage/default/0.chip_sw_aes_idle.3359239455 Aug 10 08:14:07 PM PDT 24 Aug 10 08:19:17 PM PDT 24 3146298488 ps
T1060 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.1465713698 Aug 10 08:18:40 PM PDT 24 Aug 10 09:15:33 PM PDT 24 15061637798 ps
T787 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1129492605 Aug 10 08:46:07 PM PDT 24 Aug 10 08:53:41 PM PDT 24 5378142768 ps
T715 /workspace/coverage/default/94.chip_sw_all_escalation_resets.3078634178 Aug 10 08:49:51 PM PDT 24 Aug 10 09:03:07 PM PDT 24 4586416596 ps
T749 /workspace/coverage/default/22.chip_sw_all_escalation_resets.424308594 Aug 10 08:44:49 PM PDT 24 Aug 10 08:54:52 PM PDT 24 4861880560 ps
T165 /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4277842061 Aug 10 08:19:18 PM PDT 24 Aug 10 08:22:45 PM PDT 24 3065283590 ps
T1061 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.626349485 Aug 10 08:20:15 PM PDT 24 Aug 10 09:08:24 PM PDT 24 12100665421 ps
T1062 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2196802149 Aug 10 08:16:12 PM PDT 24 Aug 10 08:19:37 PM PDT 24 3318472676 ps
T350 /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1928262956 Aug 10 08:13:35 PM PDT 24 Aug 10 08:20:16 PM PDT 24 5908093068 ps
T1063 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2570322921 Aug 10 08:12:06 PM PDT 24 Aug 10 08:21:15 PM PDT 24 5032196760 ps
T147 /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3263526636 Aug 10 08:40:35 PM PDT 24 Aug 10 08:53:07 PM PDT 24 7790115320 ps
T1064 /workspace/coverage/default/2.chip_sw_inject_scramble_seed.1612298905 Aug 10 08:30:27 PM PDT 24 Aug 10 11:42:38 PM PDT 24 63156642084 ps
T1065 /workspace/coverage/default/1.chip_sw_example_concurrency.1490376139 Aug 10 08:18:06 PM PDT 24 Aug 10 08:22:27 PM PDT 24 2687466072 ps
T826 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3954999461 Aug 10 08:45:30 PM PDT 24 Aug 10 08:56:11 PM PDT 24 4142577568 ps
T1066 /workspace/coverage/default/2.chip_sw_power_sleep_load.2881994624 Aug 10 08:38:15 PM PDT 24 Aug 10 08:50:14 PM PDT 24 11007188884 ps
T401 /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3995778564 Aug 10 08:16:50 PM PDT 24 Aug 10 09:02:21 PM PDT 24 24539250617 ps
T1067 /workspace/coverage/default/1.chip_sw_aes_entropy.1166386479 Aug 10 08:23:33 PM PDT 24 Aug 10 08:27:47 PM PDT 24 2516509364 ps
T308 /workspace/coverage/default/2.chip_plic_all_irqs_20.2871278134 Aug 10 08:36:55 PM PDT 24 Aug 10 08:49:17 PM PDT 24 4368181492 ps
T392 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.784309730 Aug 10 08:12:52 PM PDT 24 Aug 10 08:20:16 PM PDT 24 6892216140 ps
T343 /workspace/coverage/default/1.chip_sival_flash_info_access.4047611299 Aug 10 08:17:51 PM PDT 24 Aug 10 08:23:09 PM PDT 24 3210226468 ps
T825 /workspace/coverage/default/67.chip_sw_all_escalation_resets.1644042075 Aug 10 08:49:08 PM PDT 24 Aug 10 08:58:45 PM PDT 24 5541016788 ps
T1068 /workspace/coverage/default/0.rom_e2e_asm_init_dev.3183867804 Aug 10 08:20:19 PM PDT 24 Aug 10 09:20:47 PM PDT 24 15235255531 ps
T1069 /workspace/coverage/default/0.chip_tap_straps_rma.1106400984 Aug 10 08:11:59 PM PDT 24 Aug 10 08:18:54 PM PDT 24 5459789908 ps
T1070 /workspace/coverage/default/1.chip_tap_straps_prod.1064816390 Aug 10 08:26:14 PM PDT 24 Aug 10 08:29:20 PM PDT 24 2801247153 ps
T1071 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.2507351583 Aug 10 08:43:33 PM PDT 24 Aug 10 09:30:12 PM PDT 24 14903762478 ps
T1072 /workspace/coverage/default/2.rom_e2e_asm_init_rma.2619969589 Aug 10 08:43:45 PM PDT 24 Aug 10 09:30:09 PM PDT 24 15071577936 ps
T1073 /workspace/coverage/default/0.chip_sw_data_integrity_escalation.3271500261 Aug 10 08:11:08 PM PDT 24 Aug 10 08:22:30 PM PDT 24 5442569968 ps
T1074 /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2613748764 Aug 10 08:36:18 PM PDT 24 Aug 10 08:43:22 PM PDT 24 5189368928 ps
T1075 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.1764892265 Aug 10 08:30:33 PM PDT 24 Aug 10 08:40:11 PM PDT 24 3876684212 ps
T1076 /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.476807112 Aug 10 08:40:36 PM PDT 24 Aug 10 08:44:33 PM PDT 24 3651282498 ps
T1077 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.2520099449 Aug 10 08:29:41 PM PDT 24 Aug 11 12:17:08 AM PDT 24 77414757500 ps
T267 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1416013209 Aug 10 08:27:32 PM PDT 24 Aug 10 09:06:38 PM PDT 24 9695417500 ps
T1078 /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.1531902493 Aug 10 08:43:43 PM PDT 24 Aug 10 09:42:13 PM PDT 24 14770865088 ps
T351 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3475293607 Aug 10 08:39:06 PM PDT 24 Aug 10 08:47:08 PM PDT 24 5866204152 ps
T1079 /workspace/coverage/default/2.chip_sw_example_manufacturer.2342369402 Aug 10 08:30:15 PM PDT 24 Aug 10 08:35:12 PM PDT 24 3195526908 ps
T1080 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2737186492 Aug 10 08:31:09 PM PDT 24 Aug 10 08:34:56 PM PDT 24 2499410764 ps
T1081 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.986053275 Aug 10 08:20:49 PM PDT 24 Aug 10 09:12:08 PM PDT 24 29384049133 ps
T1082 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.1401234109 Aug 10 08:22:54 PM PDT 24 Aug 10 08:33:24 PM PDT 24 5099201848 ps
T55 /workspace/coverage/default/0.chip_sw_alert_test.607908876 Aug 10 08:11:44 PM PDT 24 Aug 10 08:15:47 PM PDT 24 2399371760 ps
T1083 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.108620185 Aug 10 08:10:10 PM PDT 24 Aug 10 08:22:18 PM PDT 24 4393232940 ps
T1084 /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4090885548 Aug 10 08:31:32 PM PDT 24 Aug 10 08:39:37 PM PDT 24 4321794348 ps
T1085 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3167989546 Aug 10 08:42:14 PM PDT 24 Aug 10 08:51:51 PM PDT 24 5095746918 ps
T1086 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.961041992 Aug 10 08:33:32 PM PDT 24 Aug 10 08:50:54 PM PDT 24 10452016620 ps
T827 /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1654777892 Aug 10 08:45:15 PM PDT 24 Aug 10 08:52:00 PM PDT 24 3522932014 ps
T1087 /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1316831921 Aug 10 08:30:58 PM PDT 24 Aug 10 08:41:48 PM PDT 24 6968906846 ps
T346 /workspace/coverage/default/2.chip_sw_hmac_enc.1294457637 Aug 10 08:34:26 PM PDT 24 Aug 10 08:40:41 PM PDT 24 2741703196 ps
T1088 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.1746086983 Aug 10 08:11:01 PM PDT 24 Aug 10 08:16:07 PM PDT 24 3188796878 ps
T1089 /workspace/coverage/default/0.rom_e2e_shutdown_output.1031600168 Aug 10 08:20:23 PM PDT 24 Aug 10 09:30:38 PM PDT 24 30378976620 ps
T1090 /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.1330896646 Aug 10 08:41:01 PM PDT 24 Aug 10 08:51:59 PM PDT 24 4065415548 ps
T1091 /workspace/coverage/default/0.chip_sw_csrng_smoketest.1915079137 Aug 10 08:17:22 PM PDT 24 Aug 10 08:20:14 PM PDT 24 2556406240 ps
T1092 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3467665532 Aug 10 08:15:56 PM PDT 24 Aug 10 08:22:32 PM PDT 24 3309035800 ps
T1093 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.752778940 Aug 10 08:12:36 PM PDT 24 Aug 10 08:24:03 PM PDT 24 4090245664 ps
T279 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.923864760 Aug 10 08:10:09 PM PDT 24 Aug 10 09:38:31 PM PDT 24 45716124294 ps
T1094 /workspace/coverage/default/1.rom_volatile_raw_unlock.1456648880 Aug 10 08:29:23 PM PDT 24 Aug 10 08:31:10 PM PDT 24 1931681613 ps
T1095 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1228295604 Aug 10 08:12:13 PM PDT 24 Aug 10 08:20:32 PM PDT 24 4111215160 ps
T1096 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3038458144 Aug 10 08:30:40 PM PDT 24 Aug 10 08:32:24 PM PDT 24 2689546425 ps
T1097 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3603128228 Aug 10 08:14:03 PM PDT 24 Aug 10 08:23:37 PM PDT 24 4273383964 ps
T1098 /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.968002343 Aug 10 08:26:50 PM PDT 24 Aug 10 08:31:38 PM PDT 24 3155280025 ps
T208 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2184479244 Aug 10 08:21:11 PM PDT 24 Aug 10 08:30:16 PM PDT 24 3920243991 ps
T1099 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1566603212 Aug 10 08:36:03 PM PDT 24 Aug 10 08:49:08 PM PDT 24 5007649640 ps
T779 /workspace/coverage/default/56.chip_sw_all_escalation_resets.2684669685 Aug 10 08:46:26 PM PDT 24 Aug 10 08:57:32 PM PDT 24 4903637776 ps
T1100 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.1622434407 Aug 10 08:33:50 PM PDT 24 Aug 10 08:58:03 PM PDT 24 7159365420 ps
T1101 /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.2666428354 Aug 10 08:25:43 PM PDT 24 Aug 10 08:35:47 PM PDT 24 4827556846 ps
T1102 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3054078570 Aug 10 08:30:11 PM PDT 24 Aug 10 08:42:30 PM PDT 24 3942605696 ps
T334 /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3828302649 Aug 10 08:25:43 PM PDT 24 Aug 10 08:30:27 PM PDT 24 3101473140 ps
T1103 /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.1773903393 Aug 10 08:16:21 PM PDT 24 Aug 10 08:26:15 PM PDT 24 3598357616 ps
T1104 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1432809081 Aug 10 08:13:30 PM PDT 24 Aug 10 08:22:55 PM PDT 24 5868271864 ps
T1105 /workspace/coverage/default/2.chip_sw_ast_clk_outputs.3969851460 Aug 10 08:36:16 PM PDT 24 Aug 10 08:58:45 PM PDT 24 7131458344 ps
T38 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2455731388 Aug 10 08:31:58 PM PDT 24 Aug 10 08:41:05 PM PDT 24 6122072656 ps
T692 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3546258193 Aug 10 08:14:15 PM PDT 24 Aug 10 08:19:41 PM PDT 24 3322016566 ps
T335 /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.4018106056 Aug 10 08:35:35 PM PDT 24 Aug 10 08:39:52 PM PDT 24 2634423185 ps
T1106 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1777199738 Aug 10 08:11:44 PM PDT 24 Aug 10 08:21:40 PM PDT 24 4217679549 ps
T1107 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.346284255 Aug 10 08:30:45 PM PDT 24 Aug 10 09:38:46 PM PDT 24 23228536742 ps
T1108 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.2132478402 Aug 10 08:24:38 PM PDT 24 Aug 10 08:33:49 PM PDT 24 8007591906 ps
T767 /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.3447858232 Aug 10 08:44:28 PM PDT 24 Aug 10 08:51:20 PM PDT 24 4685829016 ps
T1109 /workspace/coverage/default/63.chip_sw_all_escalation_resets.1061662135 Aug 10 08:48:41 PM PDT 24 Aug 10 08:59:23 PM PDT 24 5407784826 ps
T1110 /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.526266059 Aug 10 08:42:16 PM PDT 24 Aug 10 08:50:34 PM PDT 24 7667793820 ps
T1111 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2355455178 Aug 10 08:10:24 PM PDT 24 Aug 10 08:25:47 PM PDT 24 5520141480 ps
T298 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1107449740 Aug 10 08:11:16 PM PDT 24 Aug 10 08:24:29 PM PDT 24 5255118390 ps
T1112 /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3464666440 Aug 10 08:43:19 PM PDT 24 Aug 10 09:06:44 PM PDT 24 8209408900 ps
T1113 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1687170636 Aug 10 08:27:05 PM PDT 24 Aug 10 08:35:01 PM PDT 24 6206532156 ps
T1114 /workspace/coverage/default/0.chip_sw_otbn_smoketest.2905181137 Aug 10 08:17:39 PM PDT 24 Aug 10 08:51:13 PM PDT 24 8821222032 ps
T1115 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.3446818537 Aug 10 08:22:09 PM PDT 24 Aug 10 08:26:27 PM PDT 24 3534099960 ps
T1116 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4292479784 Aug 10 08:12:51 PM PDT 24 Aug 10 08:26:30 PM PDT 24 9301368271 ps
T182 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.3377482175 Aug 10 08:15:13 PM PDT 24 Aug 10 08:27:04 PM PDT 24 6914865918 ps
T1117 /workspace/coverage/default/1.rom_e2e_asm_init_rma.612429829 Aug 10 08:34:05 PM PDT 24 Aug 10 09:44:03 PM PDT 24 14952883048 ps
T336 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.937213729 Aug 10 08:30:21 PM PDT 24 Aug 10 08:44:21 PM PDT 24 4587336923 ps
T222 /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.3041472744 Aug 10 08:48:13 PM PDT 24 Aug 10 08:54:14 PM PDT 24 3560902300 ps
T1118 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3723540114 Aug 10 08:37:15 PM PDT 24 Aug 10 08:42:22 PM PDT 24 2891895819 ps
T381 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3187267316 Aug 10 08:18:16 PM PDT 24 Aug 10 08:24:21 PM PDT 24 6116436084 ps
T1119 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.2004988549 Aug 10 08:25:50 PM PDT 24 Aug 10 08:36:43 PM PDT 24 5271776884 ps
T141 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.127048013 Aug 10 08:11:53 PM PDT 24 Aug 10 08:17:30 PM PDT 24 5243190678 ps
T1120 /workspace/coverage/default/0.rom_e2e_asm_init_rma.1735465789 Aug 10 08:21:13 PM PDT 24 Aug 10 09:24:28 PM PDT 24 15037619766 ps
T1121 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.476492416 Aug 10 08:13:28 PM PDT 24 Aug 10 08:16:22 PM PDT 24 1964963557 ps
T174 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1346979602 Aug 10 08:12:13 PM PDT 24 Aug 10 08:22:08 PM PDT 24 4529982720 ps
T1122 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.4188133089 Aug 10 08:28:03 PM PDT 24 Aug 10 08:34:41 PM PDT 24 3343349110 ps
T1123 /workspace/coverage/default/1.chip_sw_kmac_entropy.4179720755 Aug 10 08:19:55 PM PDT 24 Aug 10 08:24:45 PM PDT 24 2620045230 ps
T1124 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3482338556 Aug 10 08:21:39 PM PDT 24 Aug 10 08:27:46 PM PDT 24 3326534650 ps
T278 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1337015486 Aug 10 08:21:33 PM PDT 24 Aug 10 09:53:17 PM PDT 24 45391744600 ps
T1125 /workspace/coverage/default/0.chip_tap_straps_dev.1854576032 Aug 10 08:12:35 PM PDT 24 Aug 10 08:14:48 PM PDT 24 2203389895 ps
T1126 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.2682705442 Aug 10 08:23:42 PM PDT 24 Aug 10 08:35:17 PM PDT 24 6819034924 ps
T1127 /workspace/coverage/default/0.chip_sw_aes_smoketest.4218482020 Aug 10 08:18:55 PM PDT 24 Aug 10 08:22:20 PM PDT 24 2472354292 ps
T1128 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3691623595 Aug 10 08:13:38 PM PDT 24 Aug 10 08:42:35 PM PDT 24 8547202947 ps
T776 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2296847409 Aug 10 08:52:44 PM PDT 24 Aug 10 08:58:23 PM PDT 24 3378544338 ps
T1129 /workspace/coverage/default/2.rom_e2e_smoke.3822462374 Aug 10 08:42:44 PM PDT 24 Aug 10 09:38:31 PM PDT 24 14857113592 ps
T1130 /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.2906860568 Aug 10 08:25:02 PM PDT 24 Aug 10 08:49:18 PM PDT 24 11901075346 ps
T186 /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.2714678992 Aug 10 08:34:04 PM PDT 24 Aug 10 08:42:16 PM PDT 24 3508005000 ps
T285 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.3798598532 Aug 10 08:47:22 PM PDT 24 Aug 10 08:53:44 PM PDT 24 3320960488 ps
T1131 /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.1955177449 Aug 10 08:30:32 PM PDT 24 Aug 10 08:53:08 PM PDT 24 9624224588 ps
T196 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2447138909 Aug 10 08:31:25 PM PDT 24 Aug 10 08:44:47 PM PDT 24 4817469897 ps
T1132 /workspace/coverage/default/2.rom_e2e_asm_init_dev.1591256953 Aug 10 08:43:14 PM PDT 24 Aug 10 09:35:48 PM PDT 24 15809877645 ps
T1133 /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1803840595 Aug 10 08:43:26 PM PDT 24 Aug 10 09:03:43 PM PDT 24 9130461513 ps
T1134 /workspace/coverage/default/1.chip_sw_aes_enc.2160743341 Aug 10 08:23:52 PM PDT 24 Aug 10 08:27:48 PM PDT 24 2757199320 ps
T768 /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.4182591047 Aug 10 08:47:28 PM PDT 24 Aug 10 08:55:37 PM PDT 24 3967073800 ps
T780 /workspace/coverage/default/86.chip_sw_all_escalation_resets.1143429588 Aug 10 08:50:45 PM PDT 24 Aug 10 09:00:45 PM PDT 24 4777020072 ps
T1135 /workspace/coverage/default/0.chip_sw_power_idle_load.2342879780 Aug 10 08:15:29 PM PDT 24 Aug 10 08:25:55 PM PDT 24 4625478612 ps
T1136 /workspace/coverage/default/2.chip_sw_uart_smoketest.800341534 Aug 10 08:40:42 PM PDT 24 Aug 10 08:46:08 PM PDT 24 3244202976 ps
T1137 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1295317460 Aug 10 08:26:02 PM PDT 24 Aug 10 09:54:36 PM PDT 24 22334106032 ps
T1138 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.1038149755 Aug 10 08:30:56 PM PDT 24 Aug 10 08:42:05 PM PDT 24 5021621096 ps
T356 /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.356198862 Aug 10 08:48:30 PM PDT 24 Aug 10 08:54:55 PM PDT 24 3464749910 ps
T1139 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2440741622 Aug 10 08:27:34 PM PDT 24 Aug 10 08:40:22 PM PDT 24 5014199916 ps
T1140 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2550431165 Aug 10 08:20:06 PM PDT 24 Aug 10 09:15:59 PM PDT 24 14487644546 ps
T1141 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.956250053 Aug 10 08:14:04 PM PDT 24 Aug 10 08:24:20 PM PDT 24 3726858102 ps
T1142 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.4172405675 Aug 10 08:31:55 PM PDT 24 Aug 10 08:43:17 PM PDT 24 10225780296 ps
T1143 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.4181976085 Aug 10 08:19:49 PM PDT 24 Aug 10 09:25:37 PM PDT 24 15019060408 ps
T718 /workspace/coverage/default/60.chip_sw_all_escalation_resets.3069359258 Aug 10 08:47:32 PM PDT 24 Aug 10 08:56:27 PM PDT 24 6231898888 ps
T302 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3187016972 Aug 10 08:31:46 PM PDT 24 Aug 10 09:08:15 PM PDT 24 15043312760 ps
T822 /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2898910640 Aug 10 08:46:30 PM PDT 24 Aug 10 08:52:30 PM PDT 24 3906865576 ps
T1144 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4188747432 Aug 10 08:21:25 PM PDT 24 Aug 10 08:51:41 PM PDT 24 19006358911 ps
T813 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2758348703 Aug 10 08:47:11 PM PDT 24 Aug 10 08:53:47 PM PDT 24 4223216988 ps
T1145 /workspace/coverage/default/0.chip_sw_kmac_idle.4204670680 Aug 10 08:14:29 PM PDT 24 Aug 10 08:18:01 PM PDT 24 2476223608 ps
T1146 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.429511100 Aug 10 08:16:06 PM PDT 24 Aug 10 08:24:41 PM PDT 24 3880835456 ps
T268 /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.3241260221 Aug 10 08:34:27 PM PDT 24 Aug 10 09:09:11 PM PDT 24 10496888280 ps
T357 /workspace/coverage/default/5.chip_sw_all_escalation_resets.1277337346 Aug 10 08:42:44 PM PDT 24 Aug 10 08:55:47 PM PDT 24 5955736584 ps
T1147 /workspace/coverage/default/24.chip_sw_all_escalation_resets.3529707143 Aug 10 08:45:10 PM PDT 24 Aug 10 08:55:01 PM PDT 24 6197264422 ps
T1148 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2470865773 Aug 10 08:31:44 PM PDT 24 Aug 10 09:13:25 PM PDT 24 37730809605 ps
T280 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2987516846 Aug 10 08:27:05 PM PDT 24 Aug 10 09:02:40 PM PDT 24 25120697969 ps
T1149 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.152920823 Aug 10 08:35:00 PM PDT 24 Aug 10 08:52:44 PM PDT 24 6789069014 ps
T183 /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.4012996507 Aug 10 08:36:14 PM PDT 24 Aug 10 08:55:43 PM PDT 24 9736316864 ps
T806 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801628871 Aug 10 08:49:06 PM PDT 24 Aug 10 08:56:25 PM PDT 24 3541905938 ps
T1150 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.227354761 Aug 10 08:25:26 PM PDT 24 Aug 10 09:16:44 PM PDT 24 11827771491 ps
T1151 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.1294288914 Aug 10 08:33:33 PM PDT 24 Aug 10 08:39:50 PM PDT 24 3676789308 ps
T808 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2581206611 Aug 10 08:12:24 PM PDT 24 Aug 10 08:22:35 PM PDT 24 5687683968 ps
T1152 /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3080255936 Aug 10 08:34:40 PM PDT 24 Aug 10 08:38:32 PM PDT 24 2930641500 ps
T1153 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.451622105 Aug 10 08:20:45 PM PDT 24 Aug 10 08:26:37 PM PDT 24 4449525940 ps
T1154 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2447068886 Aug 10 08:30:00 PM PDT 24 Aug 10 08:51:02 PM PDT 24 8426765660 ps
T184 /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.4145870280 Aug 10 08:28:26 PM PDT 24 Aug 10 08:37:58 PM PDT 24 8590196610 ps
T197 /workspace/coverage/default/1.chip_sw_power_virus.2259736877 Aug 10 08:31:42 PM PDT 24 Aug 10 08:56:33 PM PDT 24 5347432750 ps
T733 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.2945192167 Aug 10 08:13:04 PM PDT 24 Aug 10 08:21:12 PM PDT 24 4878015948 ps
T802 /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2419033773 Aug 10 08:46:29 PM PDT 24 Aug 10 08:52:30 PM PDT 24 3077853284 ps
T1155 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.2584152145 Aug 10 08:43:12 PM PDT 24 Aug 10 08:53:17 PM PDT 24 4016602800 ps
T1156 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1867077923 Aug 10 08:44:33 PM PDT 24 Aug 10 09:09:20 PM PDT 24 8866709780 ps
T1157 /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.3485145936 Aug 10 08:41:07 PM PDT 24 Aug 10 09:20:13 PM PDT 24 9369270362 ps
T286 /workspace/coverage/default/70.chip_sw_all_escalation_resets.3713301547 Aug 10 08:49:53 PM PDT 24 Aug 10 09:00:41 PM PDT 24 4548751132 ps
T1158 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3588689626 Aug 10 08:16:41 PM PDT 24 Aug 10 08:20:15 PM PDT 24 3295016925 ps
T1159 /workspace/coverage/default/2.chip_sw_aes_entropy.2640748974 Aug 10 08:32:46 PM PDT 24 Aug 10 08:36:09 PM PDT 24 2323261672 ps
T1160 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.86365937 Aug 10 08:40:13 PM PDT 24 Aug 10 08:45:24 PM PDT 24 3378569656 ps
T1161 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1699011151 Aug 10 08:41:16 PM PDT 24 Aug 10 08:52:33 PM PDT 24 3995875212 ps
T1162 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1850655355 Aug 10 08:27:54 PM PDT 24 Aug 10 08:36:40 PM PDT 24 3922030727 ps
T402 /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.2587257766 Aug 10 08:15:09 PM PDT 24 Aug 10 09:02:06 PM PDT 24 24186327708 ps
T1163 /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3560260096 Aug 10 08:23:57 PM PDT 24 Aug 10 08:33:19 PM PDT 24 7224149112 ps
T793 /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.698682087 Aug 10 08:44:30 PM PDT 24 Aug 10 08:53:13 PM PDT 24 3788052428 ps
T1164 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.2468327633 Aug 10 08:20:55 PM PDT 24 Aug 10 08:50:02 PM PDT 24 10929099909 ps
T1165 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2811359259 Aug 10 08:25:12 PM PDT 24 Aug 10 08:30:13 PM PDT 24 2944693252 ps
T1166 /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.3188148836 Aug 10 08:28:16 PM PDT 24 Aug 10 08:39:01 PM PDT 24 6855532632 ps
T1167 /workspace/coverage/default/1.chip_tap_straps_rma.3761005302 Aug 10 08:25:55 PM PDT 24 Aug 10 08:35:43 PM PDT 24 5825569734 ps
T200 /workspace/coverage/default/0.chip_jtag_mem_access.3683494830 Aug 10 08:05:23 PM PDT 24 Aug 10 08:28:39 PM PDT 24 14021827296 ps
T790 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2252312159 Aug 10 08:44:21 PM PDT 24 Aug 10 08:54:32 PM PDT 24 5199753628 ps
T1168 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3487136508 Aug 10 08:32:40 PM PDT 24 Aug 10 09:28:30 PM PDT 24 17148799068 ps
T393 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2898804168 Aug 10 08:26:18 PM PDT 24 Aug 10 08:35:40 PM PDT 24 7827251234 ps
T116 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.683037201 Aug 10 08:12:56 PM PDT 24 Aug 10 08:36:17 PM PDT 24 21390478236 ps
T1169 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.4098149565 Aug 10 08:25:19 PM PDT 24 Aug 10 08:35:51 PM PDT 24 5686370280 ps
T1170 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2096601587 Aug 10 08:32:54 PM PDT 24 Aug 10 08:55:59 PM PDT 24 12767618775 ps
T1171 /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3201192132 Aug 10 08:33:42 PM PDT 24 Aug 10 08:56:03 PM PDT 24 7994222550 ps
T717 /workspace/coverage/default/54.chip_sw_all_escalation_resets.2523673823 Aug 10 08:46:33 PM PDT 24 Aug 10 08:56:53 PM PDT 24 6791514712 ps
T1172 /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2904725756 Aug 10 08:10:11 PM PDT 24 Aug 10 08:21:15 PM PDT 24 5685306108 ps
T1173 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.192603643 Aug 10 08:44:23 PM PDT 24 Aug 10 08:55:07 PM PDT 24 10812331166 ps
T1174 /workspace/coverage/default/1.chip_sw_example_flash.4206222681 Aug 10 08:18:22 PM PDT 24 Aug 10 08:22:09 PM PDT 24 3274903082 ps
T1175 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2093447495 Aug 10 08:13:06 PM PDT 24 Aug 10 11:52:08 PM PDT 24 255603627352 ps
T814 /workspace/coverage/default/38.chip_sw_all_escalation_resets.731323771 Aug 10 08:45:35 PM PDT 24 Aug 10 08:54:23 PM PDT 24 5669640556 ps
T1176 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2521221459 Aug 10 08:35:22 PM PDT 24 Aug 10 08:45:06 PM PDT 24 5696012822 ps
T26 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.309830379 Aug 10 08:11:56 PM PDT 24 Aug 10 08:21:17 PM PDT 24 3242198616 ps
T234 /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.4214801326 Aug 10 08:31:36 PM PDT 24 Aug 10 08:41:13 PM PDT 24 5315348712 ps
T1177 /workspace/coverage/default/1.rom_keymgr_functest.3325350003 Aug 10 08:27:46 PM PDT 24 Aug 10 08:35:50 PM PDT 24 3816044408 ps
T1178 /workspace/coverage/default/0.chip_sw_edn_kat.1937345631 Aug 10 08:12:32 PM PDT 24 Aug 10 08:25:02 PM PDT 24 3535345416 ps
T1179 /workspace/coverage/default/2.chip_sw_aes_idle.2730167893 Aug 10 08:33:29 PM PDT 24 Aug 10 08:37:01 PM PDT 24 2853517288 ps
T347 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1077688481 Aug 10 08:25:58 PM PDT 24 Aug 10 08:33:05 PM PDT 24 5534869292 ps
T1180 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3483159266 Aug 10 08:13:23 PM PDT 24 Aug 10 08:54:17 PM PDT 24 23377947451 ps
T1181 /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.4286109405 Aug 10 08:32:08 PM PDT 24 Aug 10 08:35:48 PM PDT 24 3271225600 ps
T1182 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3669237019 Aug 10 08:38:08 PM PDT 24 Aug 10 08:45:36 PM PDT 24 6614127480 ps
T763 /workspace/coverage/default/25.chip_sw_all_escalation_resets.2940084403 Aug 10 08:45:47 PM PDT 24 Aug 10 08:58:33 PM PDT 24 5536482376 ps
T801 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.2233770078 Aug 10 08:49:13 PM PDT 24 Aug 10 08:54:41 PM PDT 24 3728983070 ps
T1183 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.2830427122 Aug 10 08:32:30 PM PDT 24 Aug 10 08:52:10 PM PDT 24 8467255832 ps
T1184 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3968684119 Aug 10 08:30:21 PM PDT 24 Aug 10 08:36:40 PM PDT 24 3484421761 ps
T114 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2235342821 Aug 10 08:36:22 PM PDT 24 Aug 10 08:41:09 PM PDT 24 4761615324 ps
T235 /workspace/coverage/default/1.chip_sw_all_escalation_resets.4109830835 Aug 10 08:17:04 PM PDT 24 Aug 10 08:26:46 PM PDT 24 6153588500 ps
T1185 /workspace/coverage/default/1.chip_sw_clkmgr_jitter.1944089921 Aug 10 08:25:44 PM PDT 24 Aug 10 08:28:59 PM PDT 24 2574878857 ps
T1186 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2721813445 Aug 10 08:30:14 PM PDT 24 Aug 10 08:49:24 PM PDT 24 5918447132 ps
T1187 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3185474611 Aug 10 08:36:29 PM PDT 24 Aug 10 09:07:37 PM PDT 24 10692259147 ps
T1188 /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.333542756 Aug 10 08:31:35 PM PDT 24 Aug 10 08:43:40 PM PDT 24 18356762210 ps
T1189 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.884466217 Aug 10 08:36:16 PM PDT 24 Aug 10 08:46:53 PM PDT 24 7389365720 ps
T229 /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.84777487 Aug 10 08:16:09 PM PDT 24 Aug 10 08:52:45 PM PDT 24 11926402540 ps
T1190 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.151743946 Aug 10 08:32:40 PM PDT 24 Aug 10 09:02:28 PM PDT 24 22772704296 ps
T1191 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.342010999 Aug 10 08:12:37 PM PDT 24 Aug 10 09:19:00 PM PDT 24 18879841751 ps
T1192 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3162500779 Aug 10 08:42:20 PM PDT 24 Aug 10 08:53:24 PM PDT 24 3826461300 ps
T314 /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2342072906 Aug 10 08:12:23 PM PDT 24 Aug 10 08:20:14 PM PDT 24 3928092000 ps
T1193 /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3590039674 Aug 10 08:12:08 PM PDT 24 Aug 10 08:22:16 PM PDT 24 7295300492 ps
T1194 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1125057333 Aug 10 08:21:23 PM PDT 24 Aug 10 08:26:22 PM PDT 24 3930245892 ps
T1195 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2662987619 Aug 10 08:21:04 PM PDT 24 Aug 10 09:27:46 PM PDT 24 14261093770 ps
T1196 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.2527172825 Aug 10 08:32:44 PM PDT 24 Aug 10 09:28:47 PM PDT 24 18900400443 ps
T56 /workspace/coverage/default/1.chip_sw_alert_test.3720076278 Aug 10 08:22:50 PM PDT 24 Aug 10 08:27:54 PM PDT 24 2386036552 ps
T1197 /workspace/coverage/default/0.chip_sw_hmac_multistream.757955630 Aug 10 08:13:02 PM PDT 24 Aug 10 08:42:19 PM PDT 24 7890464464 ps
T198 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.3238378907 Aug 10 08:20:17 PM PDT 24 Aug 10 08:31:33 PM PDT 24 6553560927 ps
T316 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.718372724 Aug 10 08:13:22 PM PDT 24 Aug 10 08:25:31 PM PDT 24 4693455268 ps
T201 /workspace/coverage/default/2.chip_jtag_mem_access.1907453200 Aug 10 08:29:07 PM PDT 24 Aug 10 08:59:12 PM PDT 24 12973340090 ps
T1198 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1113605677 Aug 10 08:33:27 PM PDT 24 Aug 10 08:47:50 PM PDT 24 6774276520 ps
T185 /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.4151496967 Aug 10 08:11:21 PM PDT 24 Aug 10 08:24:54 PM PDT 24 7298641225 ps
T1199 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.235271194 Aug 10 08:33:02 PM PDT 24 Aug 10 08:37:34 PM PDT 24 2915117250 ps
T41 /workspace/coverage/default/2.chip_sw_spi_device_tpm.3987524170 Aug 10 08:29:41 PM PDT 24 Aug 10 08:34:26 PM PDT 24 2494892248 ps
T785 /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.551830163 Aug 10 08:49:28 PM PDT 24 Aug 10 08:56:08 PM PDT 24 4062329288 ps
T115 /workspace/coverage/default/0.chip_sw_sleep_pin_wake.3645180868 Aug 10 08:10:17 PM PDT 24 Aug 10 08:14:40 PM PDT 24 3845018336 ps
T369 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3611181500 Aug 10 08:22:03 PM PDT 24 Aug 10 09:58:40 PM PDT 24 23304219112 ps
T1200 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.1599116584 Aug 10 08:36:27 PM PDT 24 Aug 10 08:39:21 PM PDT 24 2626500350 ps
T1201 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3846335387 Aug 10 08:22:40 PM PDT 24 Aug 10 08:35:57 PM PDT 24 4141479744 ps
T1202 /workspace/coverage/default/2.rom_e2e_static_critical.144982113 Aug 10 08:43:01 PM PDT 24 Aug 10 09:48:32 PM PDT 24 17282727064 ps
T803 /workspace/coverage/default/31.chip_sw_all_escalation_resets.791317955 Aug 10 08:45:45 PM PDT 24 Aug 10 08:56:11 PM PDT 24 4331614662 ps
T811 /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.3827356921 Aug 10 08:44:04 PM PDT 24 Aug 10 08:51:29 PM PDT 24 4239578620 ps
T1203 /workspace/coverage/default/0.chip_sw_aon_timer_irq.1500091375 Aug 10 08:12:21 PM PDT 24 Aug 10 08:18:38 PM PDT 24 4017118880 ps
T1204 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.1639435322 Aug 10 08:23:54 PM PDT 24 Aug 10 09:24:37 PM PDT 24 17070172140 ps
T1205 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1560379305 Aug 10 08:13:29 PM PDT 24 Aug 10 08:20:59 PM PDT 24 7461809027 ps
T773 /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.1899212234 Aug 10 08:49:25 PM PDT 24 Aug 10 08:56:25 PM PDT 24 3876527576 ps
T761 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3820934977 Aug 10 08:45:39 PM PDT 24 Aug 10 08:52:23 PM PDT 24 3629746992 ps
T762 /workspace/coverage/default/28.chip_sw_all_escalation_resets.2407032094 Aug 10 08:45:29 PM PDT 24 Aug 10 08:57:11 PM PDT 24 5875459448 ps
T1206 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2729719543 Aug 10 08:22:01 PM PDT 24 Aug 10 08:30:24 PM PDT 24 6919292986 ps
T1207 /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2683699953 Aug 10 08:12:46 PM PDT 24 Aug 10 08:23:59 PM PDT 24 4556192860 ps
T1208 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2967533037 Aug 10 08:11:04 PM PDT 24 Aug 10 08:23:31 PM PDT 24 4589629742 ps
T1209 /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2297810524 Aug 10 08:11:20 PM PDT 24 Aug 10 08:14:42 PM PDT 24 2802975436 ps
T1210 /workspace/coverage/default/1.chip_sw_example_rom.3633403958 Aug 10 08:17:04 PM PDT 24 Aug 10 08:19:07 PM PDT 24 2697359902 ps
T1211 /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.2857382189 Aug 10 08:20:43 PM PDT 24 Aug 10 08:25:23 PM PDT 24 2337983685 ps
T1212 /workspace/coverage/default/0.chip_sw_hmac_oneshot.1758400589 Aug 10 08:11:23 PM PDT 24 Aug 10 08:15:51 PM PDT 24 3583793160 ps
T1213 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.107351234 Aug 10 08:39:20 PM PDT 24 Aug 10 09:05:52 PM PDT 24 13473715966 ps
T1214 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.451189549 Aug 10 08:13:37 PM PDT 24 Aug 10 08:23:22 PM PDT 24 4419842868 ps
T1215 /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.399417635 Aug 10 08:30:01 PM PDT 24 Aug 10 08:35:12 PM PDT 24 3278726064 ps
T236 /workspace/coverage/default/33.chip_sw_all_escalation_resets.23545203 Aug 10 08:44:49 PM PDT 24 Aug 10 08:55:25 PM PDT 24 5754454778 ps
T1216 /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1600692024 Aug 10 08:31:33 PM PDT 24 Aug 10 08:35:27 PM PDT 24 2663771640 ps
T1217 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.544032056 Aug 10 08:24:49 PM PDT 24 Aug 10 08:30:48 PM PDT 24 2985495070 ps
T788 /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.2032196756 Aug 10 08:42:43 PM PDT 24 Aug 10 08:49:59 PM PDT 24 3866249580 ps
T1218 /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1191950779 Aug 10 08:43:47 PM PDT 24 Aug 10 08:59:13 PM PDT 24 13233810572 ps
T1219 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.385918714 Aug 10 08:26:10 PM PDT 24 Aug 10 10:42:59 PM PDT 24 23611974900 ps
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