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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.19 95.55 94.14 95.45 94.94 97.53 99.52


Total test records in report: 2938
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T572 /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.502124446 Aug 16 06:56:29 PM PDT 24 Aug 16 06:56:53 PM PDT 24 211005298 ps
T515 /workspace/coverage/cover_reg_top/70.xbar_random.929322064 Aug 16 06:54:16 PM PDT 24 Aug 16 06:54:29 PM PDT 24 276704976 ps
T392 /workspace/coverage/cover_reg_top/10.chip_tl_errors.3058422823 Aug 16 06:44:41 PM PDT 24 Aug 16 06:52:55 PM PDT 24 5170826454 ps
T1401 /workspace/coverage/cover_reg_top/75.xbar_smoke.3816899249 Aug 16 06:55:03 PM PDT 24 Aug 16 06:55:13 PM PDT 24 243150942 ps
T851 /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.1215616264 Aug 16 06:48:11 PM PDT 24 Aug 16 06:53:06 PM PDT 24 2403008710 ps
T842 /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.407301853 Aug 16 06:54:49 PM PDT 24 Aug 16 06:59:35 PM PDT 24 1764556703 ps
T1402 /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.779391470 Aug 16 06:56:48 PM PDT 24 Aug 16 06:58:28 PM PDT 24 5866175386 ps
T1403 /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.3973740507 Aug 16 06:57:21 PM PDT 24 Aug 16 06:57:28 PM PDT 24 54058558 ps
T1404 /workspace/coverage/cover_reg_top/96.xbar_smoke.4222928884 Aug 16 06:58:09 PM PDT 24 Aug 16 06:58:15 PM PDT 24 40175930 ps
T813 /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.3933739861 Aug 16 06:45:19 PM PDT 24 Aug 16 06:46:27 PM PDT 24 2202593255 ps
T1405 /workspace/coverage/cover_reg_top/74.xbar_same_source.2272502060 Aug 16 06:55:01 PM PDT 24 Aug 16 06:55:17 PM PDT 24 432646356 ps
T587 /workspace/coverage/cover_reg_top/47.xbar_smoke.2794155762 Aug 16 06:50:50 PM PDT 24 Aug 16 06:51:01 PM PDT 24 269094789 ps
T786 /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3463087049 Aug 16 06:58:25 PM PDT 24 Aug 16 07:05:25 PM PDT 24 5157374259 ps
T1406 /workspace/coverage/cover_reg_top/29.xbar_error_random.658336531 Aug 16 06:47:54 PM PDT 24 Aug 16 06:48:20 PM PDT 24 284801067 ps
T1407 /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.1032958591 Aug 16 06:55:50 PM PDT 24 Aug 16 06:56:12 PM PDT 24 194325661 ps
T1408 /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.3076422451 Aug 16 06:56:57 PM PDT 24 Aug 16 06:58:34 PM PDT 24 9352244428 ps
T1409 /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.1067017843 Aug 16 06:57:50 PM PDT 24 Aug 16 06:58:14 PM PDT 24 220783376 ps
T588 /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.2564023436 Aug 16 06:58:44 PM PDT 24 Aug 16 06:59:07 PM PDT 24 569921214 ps
T477 /workspace/coverage/cover_reg_top/78.xbar_stress_all.1254763405 Aug 16 06:55:42 PM PDT 24 Aug 16 06:59:56 PM PDT 24 8637163522 ps
T667 /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3093680312 Aug 16 06:55:40 PM PDT 24 Aug 16 06:56:19 PM PDT 24 1003800288 ps
T631 /workspace/coverage/cover_reg_top/11.xbar_stress_all.3103989405 Aug 16 06:44:54 PM PDT 24 Aug 16 06:45:56 PM PDT 24 1687355741 ps
T552 /workspace/coverage/cover_reg_top/6.chip_tl_errors.854136412 Aug 16 06:43:58 PM PDT 24 Aug 16 06:48:56 PM PDT 24 4171067401 ps
T1410 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.3575362123 Aug 16 06:52:53 PM PDT 24 Aug 16 06:54:49 PM PDT 24 1469733033 ps
T1411 /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2377592439 Aug 16 06:43:12 PM PDT 24 Aug 16 06:48:19 PM PDT 24 3678128686 ps
T379 /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.2338592943 Aug 16 06:45:49 PM PDT 24 Aug 16 06:57:37 PM PDT 24 8368404512 ps
T474 /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.3364586666 Aug 16 06:54:42 PM PDT 24 Aug 16 07:05:57 PM PDT 24 61281004521 ps
T1412 /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.2098810467 Aug 16 06:53:15 PM PDT 24 Aug 16 06:54:35 PM PDT 24 4689146237 ps
T1413 /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.1684069404 Aug 16 06:48:24 PM PDT 24 Aug 16 06:48:56 PM PDT 24 313961348 ps
T625 /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.1062504855 Aug 16 06:51:42 PM PDT 24 Aug 16 06:52:06 PM PDT 24 274822700 ps
T583 /workspace/coverage/cover_reg_top/49.xbar_random.1953390160 Aug 16 06:51:21 PM PDT 24 Aug 16 06:52:13 PM PDT 24 1372418784 ps
T616 /workspace/coverage/cover_reg_top/76.xbar_random.3910794189 Aug 16 06:55:17 PM PDT 24 Aug 16 06:55:46 PM PDT 24 688140803 ps
T567 /workspace/coverage/cover_reg_top/80.xbar_stress_all.794561153 Aug 16 06:55:56 PM PDT 24 Aug 16 06:57:34 PM PDT 24 1350079266 ps
T512 /workspace/coverage/cover_reg_top/71.xbar_stress_all.3095539010 Aug 16 06:54:35 PM PDT 24 Aug 16 07:00:20 PM PDT 24 3890731919 ps
T1414 /workspace/coverage/cover_reg_top/39.xbar_smoke.3847389292 Aug 16 06:49:36 PM PDT 24 Aug 16 06:49:44 PM PDT 24 173950813 ps
T1415 /workspace/coverage/cover_reg_top/24.xbar_random.2884094450 Aug 16 06:47:00 PM PDT 24 Aug 16 06:48:19 PM PDT 24 2203389822 ps
T819 /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3663527124 Aug 16 06:47:03 PM PDT 24 Aug 16 06:52:00 PM PDT 24 3913656678 ps
T1416 /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.2308472401 Aug 16 06:58:04 PM PDT 24 Aug 16 06:59:00 PM PDT 24 1497882161 ps
T376 /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.1397305378 Aug 16 06:43:48 PM PDT 24 Aug 16 07:18:26 PM PDT 24 16843219952 ps
T1417 /workspace/coverage/cover_reg_top/70.xbar_access_same_device.3576731549 Aug 16 06:54:25 PM PDT 24 Aug 16 06:54:49 PM PDT 24 326738013 ps
T600 /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.2783275973 Aug 16 06:51:21 PM PDT 24 Aug 16 06:51:58 PM PDT 24 473704622 ps
T1418 /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.2216814393 Aug 16 06:43:05 PM PDT 24 Aug 16 06:52:33 PM PDT 24 56902903837 ps
T1419 /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.2556537881 Aug 16 06:55:01 PM PDT 24 Aug 16 06:56:58 PM PDT 24 10888839538 ps
T393 /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.997339110 Aug 16 06:43:20 PM PDT 24 Aug 16 06:52:13 PM PDT 24 7399854080 ps
T581 /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.1116962975 Aug 16 06:45:57 PM PDT 24 Aug 16 07:00:13 PM PDT 24 85469389279 ps
T1420 /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.3122984327 Aug 16 06:50:39 PM PDT 24 Aug 16 06:50:46 PM PDT 24 46998329 ps
T1421 /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.2196804544 Aug 16 06:57:00 PM PDT 24 Aug 16 07:01:11 PM PDT 24 2619424211 ps
T596 /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.214992402 Aug 16 06:51:34 PM PDT 24 Aug 16 07:00:48 PM PDT 24 31819846741 ps
T485 /workspace/coverage/cover_reg_top/88.xbar_stress_all.1464645298 Aug 16 06:57:05 PM PDT 24 Aug 16 07:02:17 PM PDT 24 8920871609 ps
T475 /workspace/coverage/cover_reg_top/1.xbar_stress_all.304483949 Aug 16 06:43:20 PM PDT 24 Aug 16 06:53:09 PM PDT 24 14709727704 ps
T495 /workspace/coverage/cover_reg_top/7.xbar_stress_all.3832117049 Aug 16 06:44:13 PM PDT 24 Aug 16 06:50:22 PM PDT 24 4501546020 ps
T1422 /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.1033547320 Aug 16 06:43:11 PM PDT 24 Aug 16 06:45:02 PM PDT 24 6641369890 ps
T377 /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.2025607769 Aug 16 06:44:08 PM PDT 24 Aug 16 07:19:26 PM PDT 24 15176249550 ps
T489 /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.3153364949 Aug 16 06:55:19 PM PDT 24 Aug 16 07:09:59 PM PDT 24 83377589970 ps
T1423 /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.136596607 Aug 16 06:53:43 PM PDT 24 Aug 16 06:53:49 PM PDT 24 40387285 ps
T557 /workspace/coverage/cover_reg_top/5.chip_tl_errors.2635682354 Aug 16 06:43:47 PM PDT 24 Aug 16 06:47:05 PM PDT 24 4077170089 ps
T555 /workspace/coverage/cover_reg_top/20.chip_tl_errors.2369177672 Aug 16 06:46:15 PM PDT 24 Aug 16 06:50:52 PM PDT 24 3992323864 ps
T521 /workspace/coverage/cover_reg_top/84.xbar_stress_all.1181046351 Aug 16 06:56:32 PM PDT 24 Aug 16 06:59:10 PM PDT 24 4525663357 ps
T1424 /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.2352888911 Aug 16 06:52:40 PM PDT 24 Aug 16 06:52:53 PM PDT 24 109228248 ps
T1425 /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.3323986834 Aug 16 06:56:10 PM PDT 24 Aug 16 07:11:36 PM PDT 24 52678578261 ps
T801 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.2332680355 Aug 16 06:56:41 PM PDT 24 Aug 16 07:02:34 PM PDT 24 4789805651 ps
T1426 /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.1310662794 Aug 16 06:47:36 PM PDT 24 Aug 16 06:47:43 PM PDT 24 50480212 ps
T390 /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.2430300666 Aug 16 06:44:49 PM PDT 24 Aug 16 07:54:34 PM PDT 24 31837835443 ps
T1427 /workspace/coverage/cover_reg_top/36.xbar_smoke.3431855567 Aug 16 06:49:01 PM PDT 24 Aug 16 06:49:09 PM PDT 24 156894921 ps
T1428 /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.4255342863 Aug 16 06:45:10 PM PDT 24 Aug 16 06:46:34 PM PDT 24 8370189645 ps
T853 /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.1283487816 Aug 16 06:43:58 PM PDT 24 Aug 16 06:50:06 PM PDT 24 3220164590 ps
T859 /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.905985659 Aug 16 06:48:32 PM PDT 24 Aug 16 06:51:02 PM PDT 24 219407136 ps
T1429 /workspace/coverage/cover_reg_top/54.xbar_error_random.775893022 Aug 16 06:51:58 PM PDT 24 Aug 16 06:52:25 PM PDT 24 788204710 ps
T558 /workspace/coverage/cover_reg_top/21.chip_tl_errors.2501452384 Aug 16 06:46:30 PM PDT 24 Aug 16 06:50:04 PM PDT 24 3366301032 ps
T1430 /workspace/coverage/cover_reg_top/31.xbar_same_source.3169819292 Aug 16 06:48:13 PM PDT 24 Aug 16 06:48:57 PM PDT 24 1420116588 ps
T1431 /workspace/coverage/cover_reg_top/51.xbar_random.322448749 Aug 16 06:51:37 PM PDT 24 Aug 16 06:51:51 PM PDT 24 150331804 ps
T1432 /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.1410870701 Aug 16 06:50:15 PM PDT 24 Aug 16 06:51:36 PM PDT 24 4406801622 ps
T839 /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.2672571073 Aug 16 06:56:41 PM PDT 24 Aug 16 07:00:24 PM PDT 24 759076357 ps
T493 /workspace/coverage/cover_reg_top/34.xbar_stress_all.2346526397 Aug 16 06:48:55 PM PDT 24 Aug 16 06:57:43 PM PDT 24 15660020234 ps
T1433 /workspace/coverage/cover_reg_top/38.xbar_smoke.881885230 Aug 16 06:49:29 PM PDT 24 Aug 16 06:49:35 PM PDT 24 39737111 ps
T519 /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.3661758772 Aug 16 06:52:31 PM PDT 24 Aug 16 06:53:16 PM PDT 24 560302244 ps
T1434 /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.116628558 Aug 16 06:43:27 PM PDT 24 Aug 16 06:58:50 PM PDT 24 54451462391 ps
T1435 /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.3046512767 Aug 16 06:43:34 PM PDT 24 Aug 16 06:49:32 PM PDT 24 7836030340 ps
T1436 /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.954028739 Aug 16 06:43:01 PM PDT 24 Aug 16 06:55:22 PM PDT 24 16515609477 ps
T802 /workspace/coverage/cover_reg_top/19.xbar_access_same_device.345858443 Aug 16 06:46:23 PM PDT 24 Aug 16 06:48:45 PM PDT 24 3732875618 ps
T1437 /workspace/coverage/cover_reg_top/33.xbar_access_same_device.2255659073 Aug 16 06:48:32 PM PDT 24 Aug 16 06:48:52 PM PDT 24 535787677 ps
T1438 /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.2686969953 Aug 16 06:55:57 PM PDT 24 Aug 16 07:00:49 PM PDT 24 31162933046 ps
T1439 /workspace/coverage/cover_reg_top/69.xbar_same_source.4066008065 Aug 16 06:54:14 PM PDT 24 Aug 16 06:55:22 PM PDT 24 2180391852 ps
T820 /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.3081239607 Aug 16 06:46:06 PM PDT 24 Aug 16 06:54:24 PM PDT 24 4900274821 ps
T821 /workspace/coverage/cover_reg_top/24.xbar_access_same_device.768945851 Aug 16 06:47:02 PM PDT 24 Aug 16 06:49:04 PM PDT 24 3016899275 ps
T1440 /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.2654784075 Aug 16 06:56:43 PM PDT 24 Aug 16 06:57:35 PM PDT 24 5256436167 ps
T822 /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.3284571960 Aug 16 06:53:01 PM PDT 24 Aug 16 06:59:41 PM PDT 24 24063582818 ps
T1441 /workspace/coverage/cover_reg_top/97.xbar_error_random.3738120628 Aug 16 06:58:34 PM PDT 24 Aug 16 06:58:59 PM PDT 24 729073329 ps
T1442 /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.839396375 Aug 16 06:54:34 PM PDT 24 Aug 16 06:54:55 PM PDT 24 239316891 ps
T787 /workspace/coverage/cover_reg_top/40.xbar_access_same_device.2387030366 Aug 16 06:49:44 PM PDT 24 Aug 16 06:51:55 PM PDT 24 3172829339 ps
T525 /workspace/coverage/cover_reg_top/27.xbar_random.2104948203 Aug 16 06:47:33 PM PDT 24 Aug 16 06:48:49 PM PDT 24 2090915002 ps
T1443 /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.3418581143 Aug 16 06:45:03 PM PDT 24 Aug 16 06:45:15 PM PDT 24 223633378 ps
T788 /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.2362709492 Aug 16 06:57:48 PM PDT 24 Aug 16 07:42:14 PM PDT 24 140725818069 ps
T1444 /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3127312384 Aug 16 06:48:18 PM PDT 24 Aug 16 06:48:24 PM PDT 24 43710184 ps
T461 /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.266150732 Aug 16 06:43:40 PM PDT 24 Aug 16 09:21:01 PM PDT 24 55320850898 ps
T1445 /workspace/coverage/cover_reg_top/67.xbar_random.2169604381 Aug 16 06:54:03 PM PDT 24 Aug 16 06:54:13 PM PDT 24 82899427 ps
T1446 /workspace/coverage/cover_reg_top/28.xbar_random.3755171129 Aug 16 06:47:37 PM PDT 24 Aug 16 06:47:59 PM PDT 24 486180759 ps
T462 /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.3977523695 Aug 16 06:43:57 PM PDT 24 Aug 16 06:51:58 PM PDT 24 5438689576 ps
T550 /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.3590957987 Aug 16 06:52:54 PM PDT 24 Aug 16 07:00:49 PM PDT 24 7201623433 ps
T1447 /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2078652519 Aug 16 06:52:23 PM PDT 24 Aug 16 06:54:38 PM PDT 24 13491011238 ps
T1448 /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.2899398834 Aug 16 06:49:07 PM PDT 24 Aug 16 06:49:36 PM PDT 24 792817128 ps
T1449 /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.2694284113 Aug 16 06:55:50 PM PDT 24 Aug 16 06:56:12 PM PDT 24 209754760 ps
T1450 /workspace/coverage/cover_reg_top/10.xbar_random.3407695826 Aug 16 06:44:57 PM PDT 24 Aug 16 06:46:12 PM PDT 24 2129381819 ps
T1451 /workspace/coverage/cover_reg_top/48.xbar_stress_all.2656655830 Aug 16 06:51:12 PM PDT 24 Aug 16 06:53:19 PM PDT 24 1756041635 ps
T1452 /workspace/coverage/cover_reg_top/22.xbar_same_source.687306260 Aug 16 06:46:45 PM PDT 24 Aug 16 06:47:55 PM PDT 24 2396165494 ps
T1453 /workspace/coverage/cover_reg_top/79.xbar_error_random.2416434615 Aug 16 06:55:47 PM PDT 24 Aug 16 06:56:47 PM PDT 24 1794011011 ps
T548 /workspace/coverage/cover_reg_top/27.chip_tl_errors.3512126180 Aug 16 06:47:26 PM PDT 24 Aug 16 06:56:26 PM PDT 24 5689387940 ps
T1454 /workspace/coverage/cover_reg_top/17.xbar_same_source.3847925646 Aug 16 06:45:50 PM PDT 24 Aug 16 06:46:08 PM PDT 24 207824085 ps
T1455 /workspace/coverage/cover_reg_top/72.xbar_access_same_device.1867873890 Aug 16 06:54:45 PM PDT 24 Aug 16 06:56:06 PM PDT 24 1230375758 ps
T1456 /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.553343192 Aug 16 06:57:04 PM PDT 24 Aug 16 06:58:30 PM PDT 24 8298239894 ps
T1457 /workspace/coverage/cover_reg_top/22.xbar_access_same_device.9178511 Aug 16 06:46:42 PM PDT 24 Aug 16 06:47:14 PM PDT 24 340916408 ps
T483 /workspace/coverage/cover_reg_top/5.xbar_stress_all.504509990 Aug 16 06:43:59 PM PDT 24 Aug 16 06:47:13 PM PDT 24 2295743364 ps
T1458 /workspace/coverage/cover_reg_top/63.xbar_error_random.2914739457 Aug 16 06:53:34 PM PDT 24 Aug 16 06:55:10 PM PDT 24 2521072025 ps
T1459 /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.2911666216 Aug 16 06:48:59 PM PDT 24 Aug 16 06:49:11 PM PDT 24 75525930 ps
T1460 /workspace/coverage/cover_reg_top/17.xbar_error_random.1530086210 Aug 16 06:45:52 PM PDT 24 Aug 16 06:47:13 PM PDT 24 2381516647 ps
T1461 /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.1588449475 Aug 16 06:58:42 PM PDT 24 Aug 16 06:58:48 PM PDT 24 43763612 ps
T1462 /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.1091012421 Aug 16 06:51:52 PM PDT 24 Aug 16 06:52:17 PM PDT 24 254788201 ps
T1463 /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.80278025 Aug 16 06:56:12 PM PDT 24 Aug 16 06:56:28 PM PDT 24 337209276 ps
T1464 /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.626945808 Aug 16 06:47:12 PM PDT 24 Aug 16 06:47:19 PM PDT 24 47246167 ps
T657 /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.3229979392 Aug 16 06:58:37 PM PDT 24 Aug 16 07:03:40 PM PDT 24 2683541344 ps
T1465 /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.570745515 Aug 16 06:57:11 PM PDT 24 Aug 16 06:57:27 PM PDT 24 329200872 ps
T1466 /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.1232447140 Aug 16 06:58:05 PM PDT 24 Aug 16 06:59:36 PM PDT 24 8930579885 ps
T1467 /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.1564956613 Aug 16 06:55:08 PM PDT 24 Aug 16 07:02:04 PM PDT 24 26360017195 ps
T829 /workspace/coverage/cover_reg_top/81.xbar_stress_all.610332744 Aug 16 06:56:01 PM PDT 24 Aug 16 06:59:49 PM PDT 24 6255384623 ps
T815 /workspace/coverage/cover_reg_top/53.xbar_access_same_device.1549689492 Aug 16 06:52:10 PM PDT 24 Aug 16 06:53:24 PM PDT 24 1050724246 ps
T826 /workspace/coverage/cover_reg_top/55.xbar_stress_all.3058125659 Aug 16 06:52:14 PM PDT 24 Aug 16 06:56:32 PM PDT 24 3236753235 ps
T792 /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.925551765 Aug 16 06:58:04 PM PDT 24 Aug 16 07:01:14 PM PDT 24 552873285 ps
T1468 /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.3689925098 Aug 16 06:44:57 PM PDT 24 Aug 16 06:45:14 PM PDT 24 409536453 ps
T1469 /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.1422280402 Aug 16 06:48:02 PM PDT 24 Aug 16 06:49:35 PM PDT 24 5692523911 ps
T391 /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.1193030750 Aug 16 06:43:01 PM PDT 24 Aug 16 08:24:34 PM PDT 24 39275898944 ps
T1470 /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.389571189 Aug 16 06:51:46 PM PDT 24 Aug 16 06:52:42 PM PDT 24 3325708590 ps
T793 /workspace/coverage/cover_reg_top/46.xbar_stress_all.1823566947 Aug 16 06:50:44 PM PDT 24 Aug 16 06:57:31 PM PDT 24 10889552440 ps
T1471 /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.2592030025 Aug 16 06:46:21 PM PDT 24 Aug 16 06:46:42 PM PDT 24 197612914 ps
T499 /workspace/coverage/cover_reg_top/62.xbar_stress_all.195757497 Aug 16 06:53:29 PM PDT 24 Aug 16 07:03:19 PM PDT 24 13919601949 ps
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T1553 /workspace/coverage/cover_reg_top/35.xbar_smoke.1312172584 Aug 16 06:48:55 PM PDT 24 Aug 16 06:49:06 PM PDT 24 233369835 ps
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T1558 /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.2505125330 Aug 16 06:56:41 PM PDT 24 Aug 16 06:58:45 PM PDT 24 7074903684 ps
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