| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.02 | 95.41 | 93.69 | 95.42 | 94.52 | 97.53 | 99.58 |
| T2767 | /workspace/coverage/cover_reg_top/39.xbar_smoke.565807183 | Aug 17 06:50:38 PM PDT 24 | Aug 17 06:50:49 PM PDT 24 | 241336735 ps | ||
| T2768 | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.692632806 | Aug 17 06:48:10 PM PDT 24 | Aug 17 06:49:23 PM PDT 24 | 6905962207 ps | ||
| T2769 | /workspace/coverage/cover_reg_top/62.xbar_same_source.2942201866 | Aug 17 06:53:32 PM PDT 24 | Aug 17 06:54:07 PM PDT 24 | 461339462 ps | ||
| T2770 | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2037039037 | Aug 17 06:48:07 PM PDT 24 | Aug 17 06:48:12 PM PDT 24 | 19315090 ps | ||
| T2771 | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.3331502229 | Aug 17 06:52:02 PM PDT 24 | Aug 17 07:07:16 PM PDT 24 | 50561911173 ps | ||
| T2772 | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3640000997 | Aug 17 06:47:48 PM PDT 24 | Aug 17 06:48:29 PM PDT 24 | 482865034 ps | ||
| T2773 | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2340922749 | Aug 17 06:47:49 PM PDT 24 | Aug 17 06:48:36 PM PDT 24 | 520313529 ps | ||
| T2774 | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.20361143 | Aug 17 06:52:18 PM PDT 24 | Aug 17 06:52:40 PM PDT 24 | 260648294 ps | ||
| T2775 | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.254226335 | Aug 17 06:53:25 PM PDT 24 | Aug 17 06:57:59 PM PDT 24 | 3618467862 ps | ||
| T689 | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3931883308 | Aug 17 06:48:59 PM PDT 24 | Aug 17 06:52:34 PM PDT 24 | 3058360096 ps | ||
| T2776 | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3157366728 | Aug 17 06:52:54 PM PDT 24 | Aug 17 06:53:24 PM PDT 24 | 722114934 ps | ||
| T2777 | /workspace/coverage/cover_reg_top/1.xbar_random.105486955 | Aug 17 06:47:34 PM PDT 24 | Aug 17 06:47:45 PM PDT 24 | 106550883 ps | ||
| T2778 | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2807891305 | Aug 17 06:52:24 PM PDT 24 | Aug 17 07:33:26 PM PDT 24 | 136330051536 ps | ||
| T2779 | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.744351757 | Aug 17 06:50:25 PM PDT 24 | Aug 17 06:54:04 PM PDT 24 | 13807511989 ps | ||
| T2780 | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3981638351 | Aug 17 06:54:46 PM PDT 24 | Aug 17 06:55:51 PM PDT 24 | 898211923 ps | ||
| T2781 | /workspace/coverage/cover_reg_top/74.xbar_random.4278128766 | Aug 17 06:54:53 PM PDT 24 | Aug 17 06:56:01 PM PDT 24 | 1957214515 ps | ||
| T2782 | /workspace/coverage/cover_reg_top/33.xbar_same_source.3271745906 | Aug 17 06:50:03 PM PDT 24 | Aug 17 06:51:25 PM PDT 24 | 2650141019 ps | ||
| T2783 | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1711569572 | Aug 17 06:48:09 PM PDT 24 | Aug 17 06:59:00 PM PDT 24 | 38690162887 ps | ||
| T2784 | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2408493475 | Aug 17 06:48:04 PM PDT 24 | Aug 17 07:01:42 PM PDT 24 | 16972572571 ps | ||
| T2785 | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2441222451 | Aug 17 06:52:20 PM PDT 24 | Aug 17 06:53:31 PM PDT 24 | 1094558585 ps | ||
| T2786 | /workspace/coverage/cover_reg_top/45.xbar_stress_all.1491169869 | Aug 17 06:51:23 PM PDT 24 | Aug 17 06:58:01 PM PDT 24 | 10553092300 ps | ||
| T2787 | /workspace/coverage/cover_reg_top/1.chip_csr_rw.79521497 | Aug 17 06:47:36 PM PDT 24 | Aug 17 06:56:25 PM PDT 24 | 5833663682 ps | ||
| T2788 | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.438488615 | Aug 17 06:55:09 PM PDT 24 | Aug 17 06:56:43 PM PDT 24 | 5842021051 ps | ||
| T2789 | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3152296386 | Aug 17 06:54:50 PM PDT 24 | Aug 17 06:55:58 PM PDT 24 | 767712603 ps | ||
| T2790 | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.4035945407 | Aug 17 06:57:46 PM PDT 24 | Aug 17 07:13:51 PM PDT 24 | 90167667513 ps | ||
| T2791 | /workspace/coverage/cover_reg_top/59.xbar_smoke.3215496302 | Aug 17 06:53:02 PM PDT 24 | Aug 17 06:53:12 PM PDT 24 | 252878220 ps | ||
| T2792 | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2076901022 | Aug 17 06:48:19 PM PDT 24 | Aug 17 06:56:22 PM PDT 24 | 6131020675 ps | ||
| T2793 | /workspace/coverage/cover_reg_top/6.xbar_same_source.3759922606 | Aug 17 06:47:43 PM PDT 24 | Aug 17 06:47:58 PM PDT 24 | 436334953 ps | ||
| T2794 | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.980691409 | Aug 17 06:51:01 PM PDT 24 | Aug 17 07:01:03 PM PDT 24 | 35148945537 ps | ||
| T2795 | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.961735064 | Aug 17 06:52:17 PM PDT 24 | Aug 17 06:52:23 PM PDT 24 | 39446263 ps | ||
| T2796 | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2672908248 | Aug 17 06:53:50 PM PDT 24 | Aug 17 06:54:23 PM PDT 24 | 722703711 ps | ||
| T2797 | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3460363415 | Aug 17 06:47:39 PM PDT 24 | Aug 17 06:47:46 PM PDT 24 | 60369660 ps | ||
| T2798 | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.873761709 | Aug 17 06:56:30 PM PDT 24 | Aug 17 06:57:33 PM PDT 24 | 168643627 ps | ||
| T2799 | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2319847351 | Aug 17 06:49:44 PM PDT 24 | Aug 17 06:54:34 PM PDT 24 | 7598524636 ps | ||
| T2800 | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3118618912 | Aug 17 06:51:00 PM PDT 24 | Aug 17 06:58:00 PM PDT 24 | 5339323992 ps | ||
| T2801 | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1661884435 | Aug 17 06:49:00 PM PDT 24 | Aug 17 06:53:03 PM PDT 24 | 3709309033 ps | ||
| T2802 | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2322121025 | Aug 17 06:50:35 PM PDT 24 | Aug 17 06:52:17 PM PDT 24 | 336672669 ps | ||
| T2803 | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2805175341 | Aug 17 06:48:55 PM PDT 24 | Aug 17 06:49:32 PM PDT 24 | 385523918 ps | ||
| T2804 | /workspace/coverage/cover_reg_top/66.xbar_smoke.1992277035 | Aug 17 06:53:53 PM PDT 24 | Aug 17 06:53:59 PM PDT 24 | 42298505 ps | ||
| T2805 | /workspace/coverage/cover_reg_top/34.xbar_smoke.4084614010 | Aug 17 06:50:13 PM PDT 24 | Aug 17 06:50:21 PM PDT 24 | 166940143 ps | ||
| T2806 | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2701890697 | Aug 17 06:48:05 PM PDT 24 | Aug 17 06:56:22 PM PDT 24 | 6691954175 ps | ||
| T2807 | /workspace/coverage/cover_reg_top/27.xbar_same_source.2659572169 | Aug 17 06:49:21 PM PDT 24 | Aug 17 06:49:32 PM PDT 24 | 122210850 ps | ||
| T2808 | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.374609383 | Aug 17 06:51:00 PM PDT 24 | Aug 17 06:51:21 PM PDT 24 | 521010981 ps | ||
| T2809 | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2603078808 | Aug 17 06:52:11 PM PDT 24 | Aug 17 07:08:12 PM PDT 24 | 56988460510 ps | ||
| T2810 | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1518266327 | Aug 17 06:57:51 PM PDT 24 | Aug 17 07:03:10 PM PDT 24 | 1272988854 ps | ||
| T2811 | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1321796647 | Aug 17 06:49:15 PM PDT 24 | Aug 17 06:49:47 PM PDT 24 | 832363685 ps | ||
| T2812 | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3207737191 | Aug 17 06:57:40 PM PDT 24 | Aug 17 07:10:00 PM PDT 24 | 7486638207 ps | ||
| T2813 | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3057370140 | Aug 17 06:47:55 PM PDT 24 | Aug 17 07:58:13 PM PDT 24 | 32394350535 ps | ||
| T2814 | /workspace/coverage/cover_reg_top/60.xbar_same_source.1747725353 | Aug 17 06:53:16 PM PDT 24 | Aug 17 06:53:52 PM PDT 24 | 456974220 ps | ||
| T2815 | /workspace/coverage/cover_reg_top/7.xbar_same_source.2389532664 | Aug 17 06:48:09 PM PDT 24 | Aug 17 06:48:36 PM PDT 24 | 371076653 ps | ||
| T2816 | /workspace/coverage/cover_reg_top/62.xbar_smoke.468056693 | Aug 17 06:53:24 PM PDT 24 | Aug 17 06:53:33 PM PDT 24 | 190193337 ps | ||
| T2817 | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1274400865 | Aug 17 06:55:58 PM PDT 24 | Aug 17 07:12:02 PM PDT 24 | 57089927291 ps | ||
| T2818 | /workspace/coverage/cover_reg_top/77.xbar_random.1899654734 | Aug 17 06:55:16 PM PDT 24 | Aug 17 06:55:30 PM PDT 24 | 147089595 ps | ||
| T2819 | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.958116064 | Aug 17 06:56:28 PM PDT 24 | Aug 17 07:06:53 PM PDT 24 | 57980872369 ps | ||
| T2820 | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2156926091 | Aug 17 06:55:21 PM PDT 24 | Aug 17 06:56:58 PM PDT 24 | 1260097265 ps | ||
| T2821 | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.2251179923 | Aug 17 06:53:49 PM PDT 24 | Aug 17 06:54:09 PM PDT 24 | 409663090 ps | ||
| T2822 | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1703526834 | Aug 17 06:56:30 PM PDT 24 | Aug 17 06:56:36 PM PDT 24 | 48205463 ps | ||
| T2823 | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2428272505 | Aug 17 06:54:40 PM PDT 24 | Aug 17 06:54:49 PM PDT 24 | 66774664 ps | ||
| T2824 | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1016820076 | Aug 17 06:49:28 PM PDT 24 | Aug 17 06:52:46 PM PDT 24 | 11588527645 ps | ||
| T2825 | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.2952918831 | Aug 17 06:52:30 PM PDT 24 | Aug 17 06:54:25 PM PDT 24 | 3061587628 ps | ||
| T2826 | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3208489743 | Aug 17 06:56:01 PM PDT 24 | Aug 17 06:59:18 PM PDT 24 | 503500145 ps | ||
| T2827 | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.4267703507 | Aug 17 06:55:40 PM PDT 24 | Aug 17 07:28:05 PM PDT 24 | 118156549837 ps | ||
| T2828 | /workspace/coverage/cover_reg_top/8.xbar_error_random.3167946567 | Aug 17 06:47:48 PM PDT 24 | Aug 17 06:48:08 PM PDT 24 | 570320695 ps | ||
| T2829 | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.1239235549 | Aug 17 06:56:20 PM PDT 24 | Aug 17 06:57:18 PM PDT 24 | 5739547249 ps | ||
| T2830 | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2154623927 | Aug 17 06:47:38 PM PDT 24 | Aug 17 06:49:11 PM PDT 24 | 9476050736 ps | ||
| T2831 | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2319133693 | Aug 17 06:49:55 PM PDT 24 | Aug 17 06:50:19 PM PDT 24 | 341037025 ps | ||
| T2832 | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1356946930 | Aug 17 06:48:14 PM PDT 24 | Aug 17 06:48:21 PM PDT 24 | 49792084 ps | ||
| T2833 | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2491239494 | Aug 17 06:51:07 PM PDT 24 | Aug 17 06:51:48 PM PDT 24 | 3865200362 ps | ||
| T2834 | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1344035083 | Aug 17 06:51:18 PM PDT 24 | Aug 17 06:52:30 PM PDT 24 | 7143750659 ps | ||
| T2835 | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2769504456 | Aug 17 06:48:05 PM PDT 24 | Aug 17 06:56:18 PM PDT 24 | 30915916766 ps | ||
| T2836 | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1358355484 | Aug 17 06:52:27 PM PDT 24 | Aug 17 06:53:58 PM PDT 24 | 5250857194 ps | ||
| T2837 | /workspace/coverage/cover_reg_top/7.xbar_smoke.3076821971 | Aug 17 06:47:41 PM PDT 24 | Aug 17 06:47:47 PM PDT 24 | 47348117 ps | ||
| T2838 | /workspace/coverage/cover_reg_top/12.xbar_smoke.1788377252 | Aug 17 06:47:46 PM PDT 24 | Aug 17 06:47:55 PM PDT 24 | 209578288 ps | ||
| T2839 | /workspace/coverage/cover_reg_top/61.xbar_error_random.84407629 | Aug 17 06:53:23 PM PDT 24 | Aug 17 06:54:54 PM PDT 24 | 2540825236 ps | ||
| T2840 | /workspace/coverage/cover_reg_top/96.xbar_error_random.4168517207 | Aug 17 06:57:31 PM PDT 24 | Aug 17 06:58:18 PM PDT 24 | 1351554891 ps | ||
| T2841 | /workspace/coverage/cover_reg_top/88.xbar_same_source.4032780590 | Aug 17 06:56:32 PM PDT 24 | Aug 17 06:56:58 PM PDT 24 | 342892590 ps | ||
| T2842 | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1288346768 | Aug 17 06:49:49 PM PDT 24 | Aug 17 06:51:02 PM PDT 24 | 1839443505 ps | ||
| T2843 | /workspace/coverage/cover_reg_top/45.xbar_same_source.547876011 | Aug 17 06:51:21 PM PDT 24 | Aug 17 06:51:50 PM PDT 24 | 371188771 ps | ||
| T2844 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1321098414 | Aug 17 06:52:50 PM PDT 24 | Aug 17 06:59:43 PM PDT 24 | 5984219040 ps | ||
| T2845 | /workspace/coverage/cover_reg_top/22.xbar_random.1008629965 | Aug 17 06:48:51 PM PDT 24 | Aug 17 06:49:14 PM PDT 24 | 563336128 ps | ||
| T2846 | /workspace/coverage/cover_reg_top/63.xbar_same_source.2745196302 | Aug 17 06:53:39 PM PDT 24 | Aug 17 06:54:07 PM PDT 24 | 426128624 ps | ||
| T2847 | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3718851002 | Aug 17 06:53:08 PM PDT 24 | Aug 17 06:53:20 PM PDT 24 | 98289533 ps | ||
| T2848 | /workspace/coverage/cover_reg_top/16.xbar_random.1808275895 | Aug 17 06:48:02 PM PDT 24 | Aug 17 06:48:22 PM PDT 24 | 530383019 ps | ||
| T2849 | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.788840276 | Aug 17 06:53:58 PM PDT 24 | Aug 17 06:54:17 PM PDT 24 | 177113443 ps | ||
| T2850 | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1805511646 | Aug 17 06:48:59 PM PDT 24 | Aug 17 06:59:53 PM PDT 24 | 57432685417 ps | ||
| T2851 | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1801869857 | Aug 17 06:54:26 PM PDT 24 | Aug 17 06:55:44 PM PDT 24 | 960042550 ps | ||
| T2852 | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1491490607 | Aug 17 06:49:01 PM PDT 24 | Aug 17 06:49:51 PM PDT 24 | 1237838081 ps | ||
| T2853 | /workspace/coverage/cover_reg_top/75.xbar_stress_all.553933655 | Aug 17 06:55:16 PM PDT 24 | Aug 17 06:59:39 PM PDT 24 | 7654817268 ps | ||
| T2854 | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3962700683 | Aug 17 06:50:44 PM PDT 24 | Aug 17 06:52:15 PM PDT 24 | 2549956548 ps | ||
| T2855 | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.994196310 | Aug 17 06:55:31 PM PDT 24 | Aug 17 06:59:09 PM PDT 24 | 3092753664 ps | ||
| T2856 | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3465574751 | Aug 17 06:49:37 PM PDT 24 | Aug 17 07:16:45 PM PDT 24 | 90007728084 ps | ||
| T2857 | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.1509194486 | Aug 17 06:54:18 PM PDT 24 | Aug 17 06:54:31 PM PDT 24 | 113075052 ps | ||
| T2858 | /workspace/coverage/cover_reg_top/64.xbar_error_random.862719201 | Aug 17 06:53:44 PM PDT 24 | Aug 17 06:54:10 PM PDT 24 | 731804898 ps | ||
| T2859 | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3575208020 | Aug 17 06:55:13 PM PDT 24 | Aug 17 06:55:29 PM PDT 24 | 192711868 ps | ||
| T2860 | /workspace/coverage/cover_reg_top/44.xbar_random.2355470568 | Aug 17 06:51:17 PM PDT 24 | Aug 17 06:51:42 PM PDT 24 | 631076427 ps | ||
| T2861 | /workspace/coverage/cover_reg_top/25.xbar_smoke.716439123 | Aug 17 06:49:04 PM PDT 24 | Aug 17 06:49:13 PM PDT 24 | 194076633 ps | ||
| T2862 | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3602746817 | Aug 17 06:47:41 PM PDT 24 | Aug 17 07:15:14 PM PDT 24 | 15280957107 ps | ||
| T2863 | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2185557276 | Aug 17 06:52:37 PM PDT 24 | Aug 17 06:52:44 PM PDT 24 | 52626627 ps | ||
| T2864 | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3659597840 | Aug 17 06:49:13 PM PDT 24 | Aug 17 06:49:20 PM PDT 24 | 43286143 ps | ||
| T2865 | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1616250810 | Aug 17 06:49:00 PM PDT 24 | Aug 17 06:51:31 PM PDT 24 | 3205876060 ps | ||
| T2866 | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2393597324 | Aug 17 06:47:40 PM PDT 24 | Aug 17 06:50:52 PM PDT 24 | 5208142003 ps | ||
| T2867 | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1433046731 | Aug 17 06:52:55 PM PDT 24 | Aug 17 06:56:20 PM PDT 24 | 18391485738 ps | ||
| T2868 | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1546735760 | Aug 17 06:47:32 PM PDT 24 | Aug 17 06:48:36 PM PDT 24 | 4107422772 ps | ||
| T2869 | /workspace/coverage/cover_reg_top/35.xbar_stress_all.1090082007 | Aug 17 06:50:14 PM PDT 24 | Aug 17 06:53:09 PM PDT 24 | 2164904497 ps | ||
| T2870 | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.709928608 | Aug 17 06:53:22 PM PDT 24 | Aug 17 06:54:51 PM PDT 24 | 5388841021 ps | ||
| T2871 | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.4149536606 | Aug 17 06:48:14 PM PDT 24 | Aug 17 06:51:49 PM PDT 24 | 21894317605 ps | ||
| T2872 | /workspace/coverage/cover_reg_top/19.xbar_smoke.4288916579 | Aug 17 06:48:19 PM PDT 24 | Aug 17 06:48:27 PM PDT 24 | 142007806 ps | ||
| T2873 | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.552075115 | Aug 17 06:50:09 PM PDT 24 | Aug 17 06:50:56 PM PDT 24 | 477447137 ps | ||
| T2874 | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2934618670 | Aug 17 06:52:40 PM PDT 24 | Aug 17 06:59:50 PM PDT 24 | 5747796702 ps | ||
| T2875 | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.983212133 | Aug 17 06:48:54 PM PDT 24 | Aug 17 07:00:49 PM PDT 24 | 42013966074 ps | ||
| T2876 | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2448747532 | Aug 17 06:56:05 PM PDT 24 | Aug 17 06:57:28 PM PDT 24 | 8335454706 ps | ||
| T2877 | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.920534931 | Aug 17 06:51:52 PM PDT 24 | Aug 17 06:52:06 PM PDT 24 | 273200038 ps | ||
| T2878 | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2642836835 | Aug 17 06:56:27 PM PDT 24 | Aug 17 06:57:58 PM PDT 24 | 5709344052 ps | ||
| T2879 | /workspace/coverage/cover_reg_top/70.xbar_smoke.3300676136 | Aug 17 06:54:30 PM PDT 24 | Aug 17 06:54:40 PM PDT 24 | 211684714 ps | ||
| T612 | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.322751486 | Aug 17 06:51:06 PM PDT 24 | Aug 17 06:56:20 PM PDT 24 | 9295462831 ps | ||
| T2880 | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.4022643453 | Aug 17 06:52:08 PM PDT 24 | Aug 17 06:54:08 PM PDT 24 | 2982954544 ps | ||
| T869 | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3832285921 | Aug 17 06:51:36 PM PDT 24 | Aug 17 06:56:03 PM PDT 24 | 927166785 ps | ||
| T2881 | /workspace/coverage/cover_reg_top/29.xbar_error_random.192960309 | Aug 17 06:49:34 PM PDT 24 | Aug 17 06:50:06 PM PDT 24 | 944092851 ps | ||
| T2882 | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2952060993 | Aug 17 06:53:25 PM PDT 24 | Aug 17 06:53:59 PM PDT 24 | 324397670 ps | ||
| T2883 | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.143288441 | Aug 17 06:47:58 PM PDT 24 | Aug 17 06:49:48 PM PDT 24 | 271085088 ps | ||
| T2884 | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.4073387531 | Aug 17 06:56:45 PM PDT 24 | Aug 17 07:09:11 PM PDT 24 | 9401008387 ps | ||
| T687 | /workspace/coverage/cover_reg_top/8.chip_tl_errors.31887538 | Aug 17 06:47:44 PM PDT 24 | Aug 17 06:52:39 PM PDT 24 | 4319407800 ps | ||
| T2885 | /workspace/coverage/cover_reg_top/3.xbar_random.3447241653 | Aug 17 06:47:30 PM PDT 24 | Aug 17 06:48:15 PM PDT 24 | 522753266 ps | ||
| T2886 | /workspace/coverage/cover_reg_top/36.xbar_random.1638531681 | Aug 17 06:50:26 PM PDT 24 | Aug 17 06:50:36 PM PDT 24 | 77831494 ps | ||
| T2887 | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.594723290 | Aug 17 06:47:30 PM PDT 24 | Aug 17 06:48:05 PM PDT 24 | 283947090 ps | ||
| T2888 | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3874990649 | Aug 17 06:54:31 PM PDT 24 | Aug 17 06:54:59 PM PDT 24 | 585800330 ps | ||
| T2889 | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.163380687 | Aug 17 06:53:31 PM PDT 24 | Aug 17 06:53:49 PM PDT 24 | 393959914 ps | ||
| T2890 | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1309732896 | Aug 17 06:56:06 PM PDT 24 | Aug 17 06:57:43 PM PDT 24 | 9636050267 ps | ||
| T2891 | /workspace/coverage/cover_reg_top/63.xbar_random.7640291 | Aug 17 06:53:42 PM PDT 24 | Aug 17 06:54:49 PM PDT 24 | 2091629936 ps | ||
| T2892 | /workspace/coverage/cover_reg_top/6.xbar_smoke.1098015101 | Aug 17 06:47:50 PM PDT 24 | Aug 17 06:48:00 PM PDT 24 | 213892685 ps | ||
| T2893 | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2702232057 | Aug 17 06:51:09 PM PDT 24 | Aug 17 06:51:46 PM PDT 24 | 334885216 ps | ||
| T2894 | /workspace/coverage/cover_reg_top/41.xbar_same_source.1231630225 | Aug 17 06:51:02 PM PDT 24 | Aug 17 06:51:15 PM PDT 24 | 135026642 ps | ||
| T2895 | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.2636697115 | Aug 17 06:55:35 PM PDT 24 | Aug 17 06:56:08 PM PDT 24 | 337431442 ps | ||
| T2896 | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2048021893 | Aug 17 06:52:56 PM PDT 24 | Aug 17 06:54:27 PM PDT 24 | 8714239410 ps | ||
| T2897 | /workspace/coverage/cover_reg_top/5.xbar_error_random.1443403784 | Aug 17 06:47:34 PM PDT 24 | Aug 17 06:48:35 PM PDT 24 | 2030896878 ps | ||
| T2898 | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2365422454 | Aug 17 06:50:32 PM PDT 24 | Aug 17 07:03:36 PM PDT 24 | 48659398707 ps | ||
| T2899 | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1136428926 | Aug 17 06:51:43 PM PDT 24 | Aug 17 06:52:23 PM PDT 24 | 983529038 ps | ||
| T2900 | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.912542326 | Aug 17 06:57:52 PM PDT 24 | Aug 17 07:00:09 PM PDT 24 | 3485553868 ps | ||
| T2901 | /workspace/coverage/cover_reg_top/57.xbar_random.3933805331 | Aug 17 06:52:54 PM PDT 24 | Aug 17 06:53:01 PM PDT 24 | 81377561 ps | ||
| T2902 | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2476461370 | Aug 17 06:53:44 PM PDT 24 | Aug 17 07:00:56 PM PDT 24 | 11264649520 ps | ||
| T2903 | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1999555716 | Aug 17 06:55:42 PM PDT 24 | Aug 17 06:55:49 PM PDT 24 | 52922488 ps | ||
| T2904 | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.174496645 | Aug 17 06:49:54 PM PDT 24 | Aug 17 06:51:09 PM PDT 24 | 1835972531 ps | ||
| T2905 | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2750252840 | Aug 17 06:48:44 PM PDT 24 | Aug 17 06:50:47 PM PDT 24 | 7276288433 ps | ||
| T2906 | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.340980838 | Aug 17 06:48:04 PM PDT 24 | Aug 17 06:48:45 PM PDT 24 | 1056167180 ps | ||
| T2907 | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1100407166 | Aug 17 06:54:46 PM PDT 24 | Aug 17 06:55:29 PM PDT 24 | 527271849 ps | ||
| T2908 | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3614911806 | Aug 17 06:47:51 PM PDT 24 | Aug 17 06:49:29 PM PDT 24 | 6349987813 ps | ||
| T2909 | /workspace/coverage/cover_reg_top/66.xbar_error_random.492782013 | Aug 17 06:53:57 PM PDT 24 | Aug 17 06:54:18 PM PDT 24 | 609495667 ps | ||
| T2910 | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2316546131 | Aug 17 06:50:53 PM PDT 24 | Aug 17 06:50:59 PM PDT 24 | 44687653 ps | ||
| T2911 | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2001183364 | Aug 17 06:47:50 PM PDT 24 | Aug 17 06:53:11 PM PDT 24 | 3754382500 ps | ||
| T2912 | /workspace/coverage/cover_reg_top/72.xbar_random.4082024598 | Aug 17 06:54:50 PM PDT 24 | Aug 17 06:55:23 PM PDT 24 | 372265126 ps | ||
| T2913 | /workspace/coverage/cover_reg_top/1.xbar_error_random.2080095668 | Aug 17 06:47:36 PM PDT 24 | Aug 17 06:47:55 PM PDT 24 | 507537047 ps | ||
| T2914 | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.554194669 | Aug 17 06:54:33 PM PDT 24 | Aug 17 07:30:49 PM PDT 24 | 118035911556 ps | ||
| T2915 | /workspace/coverage/cover_reg_top/15.xbar_same_source.1196498947 | Aug 17 06:48:10 PM PDT 24 | Aug 17 06:49:25 PM PDT 24 | 2403019980 ps | ||
| T2916 | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.360521629 | Aug 17 06:57:32 PM PDT 24 | Aug 17 06:58:15 PM PDT 24 | 595227369 ps | ||
| T615 | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1854080199 | Aug 17 06:52:48 PM PDT 24 | Aug 17 06:57:45 PM PDT 24 | 1179497921 ps | ||
| T2917 | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.350905132 | Aug 17 06:57:20 PM PDT 24 | Aug 17 07:00:22 PM PDT 24 | 5176566778 ps | ||
| T2918 | /workspace/coverage/cover_reg_top/42.xbar_smoke.3391210909 | Aug 17 06:51:17 PM PDT 24 | Aug 17 06:51:25 PM PDT 24 | 135419645 ps | ||
| T2919 | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1294534350 | Aug 17 06:48:05 PM PDT 24 | Aug 17 06:48:56 PM PDT 24 | 3199197100 ps | ||
| T2920 | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2662223984 | Aug 17 06:54:25 PM PDT 24 | Aug 17 06:55:05 PM PDT 24 | 898501777 ps | ||
| T2921 | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.2538335638 | Aug 17 06:47:47 PM PDT 24 | Aug 17 06:48:17 PM PDT 24 | 331086453 ps | ||
| T2922 | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3144410951 | Aug 17 06:55:14 PM PDT 24 | Aug 17 06:55:21 PM PDT 24 | 36944874 ps | ||
| T2923 | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3107744244 | Aug 17 06:49:29 PM PDT 24 | Aug 17 06:49:35 PM PDT 24 | 52786308 ps | ||
| T2924 | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2166230945 | Aug 17 06:55:50 PM PDT 24 | Aug 17 07:06:57 PM PDT 24 | 72197822746 ps | ||
| T2925 | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.480432814 | Aug 17 06:54:33 PM PDT 24 | Aug 17 06:55:29 PM PDT 24 | 783056971 ps | ||
| T2926 | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1921661059 | Aug 17 06:47:44 PM PDT 24 | Aug 17 07:30:29 PM PDT 24 | 133056738556 ps | ||
| T2927 | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1479828295 | Aug 17 06:47:54 PM PDT 24 | Aug 17 06:48:54 PM PDT 24 | 260277447 ps | ||
| T2928 | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3873754673 | Aug 17 06:57:43 PM PDT 24 | Aug 17 06:59:12 PM PDT 24 | 8881858378 ps | ||
| T2929 | /workspace/coverage/cover_reg_top/99.xbar_smoke.2875559257 | Aug 17 06:57:57 PM PDT 24 | Aug 17 06:58:05 PM PDT 24 | 53607908 ps | ||
| T2930 | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.189493337 | Aug 17 06:52:32 PM PDT 24 | Aug 17 06:52:50 PM PDT 24 | 149486887 ps | ||
| T2931 | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.791128953 | Aug 17 06:53:31 PM PDT 24 | Aug 17 06:59:03 PM PDT 24 | 8055661926 ps | ||
| T728 | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1595123363 | Aug 17 06:47:59 PM PDT 24 | Aug 17 06:55:09 PM PDT 24 | 6117446519 ps | ||
| T2932 | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3810497445 | Aug 17 06:47:32 PM PDT 24 | Aug 17 06:47:39 PM PDT 24 | 54112752 ps | ||
| T2933 | /workspace/coverage/cover_reg_top/73.xbar_same_source.3599976217 | Aug 17 06:54:57 PM PDT 24 | Aug 17 06:55:31 PM PDT 24 | 476648487 ps | ||
| T2934 | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3330072190 | Aug 17 06:49:16 PM PDT 24 | Aug 17 07:02:19 PM PDT 24 | 72637540055 ps | ||
| T2935 | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3227884721 | Aug 17 06:51:37 PM PDT 24 | Aug 17 06:51:57 PM PDT 24 | 406916166 ps | ||
| T2936 | /workspace/coverage/cover_reg_top/77.xbar_same_source.3809071959 | Aug 17 06:55:14 PM PDT 24 | Aug 17 06:55:34 PM PDT 24 | 675630349 ps | ||
| T28 | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2875197593 | Aug 17 07:31:12 PM PDT 24 | Aug 17 07:37:07 PM PDT 24 | 5478291107 ps | ||
| T29 | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2519792807 | Aug 17 07:31:23 PM PDT 24 | Aug 17 07:36:05 PM PDT 24 | 4296091032 ps | ||
| T30 | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.180490848 | Aug 17 07:31:12 PM PDT 24 | Aug 17 07:35:59 PM PDT 24 | 4022688436 ps | ||
| T33 | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.964000122 | Aug 17 07:31:14 PM PDT 24 | Aug 17 07:35:37 PM PDT 24 | 4878408787 ps | ||
| T189 | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.647858988 | Aug 17 07:31:00 PM PDT 24 | Aug 17 07:35:03 PM PDT 24 | 4597336730 ps | ||
| T190 | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3921074240 | Aug 17 07:31:12 PM PDT 24 | Aug 17 07:34:19 PM PDT 24 | 3780867874 ps | ||
| T191 | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3774935257 | Aug 17 07:31:11 PM PDT 24 | Aug 17 07:36:08 PM PDT 24 | 4585609360 ps | ||
| T192 | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3261889369 | Aug 17 07:31:25 PM PDT 24 | Aug 17 07:34:59 PM PDT 24 | 5200985352 ps | ||
| T194 | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3690291162 | Aug 17 07:31:01 PM PDT 24 | Aug 17 07:37:32 PM PDT 24 | 5697378156 ps | ||
| T193 | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2221629467 | Aug 17 07:31:26 PM PDT 24 | Aug 17 07:36:53 PM PDT 24 | 4917183092 ps |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2536795900 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 14037729789 ps |
| CPU time | 1210.5 seconds |
| Started | Aug 17 07:23:46 PM PDT 24 |
| Finished | Aug 17 07:43:57 PM PDT 24 |
| Peak memory | 612112 kb |
| Host | smart-0973740a-5a0e-4887-bd04-7fdbc9e84715 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2536795900 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2536795900 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_rw.2376180421 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 4906827706 ps |
| CPU time | 353.23 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 06:54:00 PM PDT 24 |
| Peak memory | 597376 kb |
| Host | smart-4c225059-bf05-4c8a-8f6c-a174a7023e4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376180421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_csr_rw.2376180421 |
| Directory | /workspace/17.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device_slow_rsp.3780665304 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 87858733037 ps |
| CPU time | 1696.46 seconds |
| Started | Aug 17 06:50:57 PM PDT 24 |
| Finished | Aug 17 07:19:13 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-e704b155-9b12-4b7a-ab08-e6e4b9ad7b82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780665304 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_ device_slow_rsp.3780665304 |
| Directory | /workspace/40.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_0.1052881397 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 6692500360 ps |
| CPU time | 980.76 seconds |
| Started | Aug 17 07:23:49 PM PDT 24 |
| Finished | Aug 17 07:40:10 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-b0112314-af65-4b25-884f-f19f7ffe5917 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052881397 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_0.1052881397 |
| Directory | /workspace/2.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_virus.2301790302 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 5830033200 ps |
| CPU time | 1357.83 seconds |
| Started | Aug 17 07:31:46 PM PDT 24 |
| Finished | Aug 17 07:54:24 PM PDT 24 |
| Peak memory | 625820 kb |
| Host | smart-bbe8dea4-3158-4709-8db8-05a9a82f38d9 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=2301790302 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_virus.2301790302 |
| Directory | /workspace/2.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_reset_error.4175929110 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1318361409 ps |
| CPU time | 247.24 seconds |
| Started | Aug 17 06:56:58 PM PDT 24 |
| Finished | Aug 17 07:01:06 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-0bc5a24f-ef60-4521-b21a-c9871d62b341 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175929110 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_al l_with_reset_error.4175929110 |
| Directory | /workspace/90.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device_slow_rsp.2624286265 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 116991387703 ps |
| CPU time | 1925.21 seconds |
| Started | Aug 17 06:50:13 PM PDT 24 |
| Finished | Aug 17 07:22:19 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-1b13dd50-a65f-400a-abfb-e42a00c9b504 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624286265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_ device_slow_rsp.2624286265 |
| Directory | /workspace/33.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.2519792807 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 4296091032 ps |
| CPU time | 282.13 seconds |
| Started | Aug 17 07:31:23 PM PDT 24 |
| Finished | Aug 17 07:36:05 PM PDT 24 |
| Peak memory | 650616 kb |
| Host | smart-1c20a319-6cb8-4274-b976-0604150cd658 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519792807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 6.chip_padctrl_attributes.2519792807 |
| Directory | /workspace/6.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.1103132384 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 8987314916 ps |
| CPU time | 2088.37 seconds |
| Started | Aug 17 07:13:58 PM PDT 24 |
| Finished | Aug 17 07:48:47 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-b38e1a8b-b236-4953-bbd1-3044b6ad4b52 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110313 2384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_aes.1103132384 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device_slow_rsp.2522754083 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 127810554828 ps |
| CPU time | 2445.37 seconds |
| Started | Aug 17 06:54:37 PM PDT 24 |
| Finished | Aug 17 07:35:23 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-eb0f8f7f-489a-4113-bbcf-baf49e835f65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522754083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_ device_slow_rsp.2522754083 |
| Directory | /workspace/71.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_self_hash.631317007 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 25501601928 ps |
| CPU time | 5549.64 seconds |
| Started | Aug 17 07:13:32 PM PDT 24 |
| Finished | Aug 17 08:46:02 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-ea1b9376-4ce9-4d69-a36a-c2c25be853a1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631317007 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_self_hash.631317007 |
| Directory | /workspace/0.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.1268459266 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 49525343154 ps |
| CPU time | 4883.85 seconds |
| Started | Aug 17 07:20:16 PM PDT 24 |
| Finished | Aug 17 08:41:41 PM PDT 24 |
| Peak memory | 624232 kb |
| Host | smart-a6676ddf-32d8-42bb-9768-fcc215b12ed4 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268459266 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chi p_sw_lc_walkthrough_prod.1268459266 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.744288096 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 3054490267 ps |
| CPU time | 308.36 seconds |
| Started | Aug 17 07:05:08 PM PDT 24 |
| Finished | Aug 17 07:10:17 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-3531310f-4512-4c89-969c-d151e74cc60f |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7442 88096 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_mio_dio_val.744288096 |
| Directory | /workspace/0.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_reset_error.3438058315 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 14876751788 ps |
| CPU time | 754 seconds |
| Started | Aug 17 06:57:04 PM PDT 24 |
| Finished | Aug 17 07:09:38 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-e5c04ac1-c6f6-4145-9b3e-3eafa147c9e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438058315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_al l_with_reset_error.3438058315 |
| Directory | /workspace/91.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device_slow_rsp.2410870449 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 71370342379 ps |
| CPU time | 1249.58 seconds |
| Started | Aug 17 06:55:13 PM PDT 24 |
| Finished | Aug 17 07:16:03 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-522edcfb-6cc1-4e0c-b77d-4b0ac344c64c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410870449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_ device_slow_rsp.2410870449 |
| Directory | /workspace/76.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device_slow_rsp.630693004 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 120641008023 ps |
| CPU time | 2148.77 seconds |
| Started | Aug 17 06:51:21 PM PDT 24 |
| Finished | Aug 17 07:27:10 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-ce6ca2c4-847a-4f05-8f60-fcdc1fd83d81 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630693004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_d evice_slow_rsp.630693004 |
| Directory | /workspace/45.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4261417475 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 3481469832 ps |
| CPU time | 254.66 seconds |
| Started | Aug 17 07:07:49 PM PDT 24 |
| Finished | Aug 17 07:12:04 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-ea77546f-45f3-4d33-a5b7-5c7773a4f2b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=4261417475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_address_translation.4261417475 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3233584783 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 7416975288 ps |
| CPU time | 446.44 seconds |
| Started | Aug 17 07:26:00 PM PDT 24 |
| Finished | Aug 17 07:33:27 PM PDT 24 |
| Peak memory | 610940 kb |
| Host | smart-6d723541-8159-4141-aa7d-507ea1e8a493 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233584783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3233584783 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_mem_rw_with_rand_reset.202691975 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 10193682980 ps |
| CPU time | 839.53 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 07:01:56 PM PDT 24 |
| Peak memory | 646472 kb |
| Host | smart-29330295-8d86-4d78-8560-212d5769bdd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202691975 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 15.chip_csr_mem_rw_with_rand_reset.202691975 |
| Directory | /workspace/15.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_rand_reset.3225332040 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 4923801340 ps |
| CPU time | 597.71 seconds |
| Started | Aug 17 06:52:04 PM PDT 24 |
| Finished | Aug 17 07:02:02 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-16eb4109-c5c2-43e9-b435-1b9da368930a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225332040 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_rand_reset.3225332040 |
| Directory | /workspace/50.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_20.563562802 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 4654051242 ps |
| CPU time | 778.56 seconds |
| Started | Aug 17 07:25:34 PM PDT 24 |
| Finished | Aug 17 07:38:32 PM PDT 24 |
| Peak memory | 609796 kb |
| Host | smart-246e4862-3b1a-4bf3-8fad-1cda6ac5e572 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563562802 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_plic_all_irqs_20.563562802 |
| Directory | /workspace/2.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333714150 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 4095987968 ps |
| CPU time | 391.92 seconds |
| Started | Aug 17 07:34:29 PM PDT 24 |
| Finished | Aug 17 07:41:01 PM PDT 24 |
| Peak memory | 649224 kb |
| Host | smart-c77e1e7d-eb66-4082-8851-e03ac780e07e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333714150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3333714150 |
| Directory | /workspace/60.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_test.309146927 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2615064888 ps |
| CPU time | 287.19 seconds |
| Started | Aug 17 07:12:07 PM PDT 24 |
| Finished | Aug 17 07:16:54 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-60a1e624-bb4d-4aeb-8833-f672d34eccab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309146927 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 1.chip_sw_alert_test.309146927 |
| Directory | /workspace/1.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device_slow_rsp.380875569 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 86064207575 ps |
| CPU time | 1436.76 seconds |
| Started | Aug 17 06:47:29 PM PDT 24 |
| Finished | Aug 17 07:11:26 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-4289b2eb-e05c-445b-8221-a62a868d9236 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380875569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_de vice_slow_rsp.380875569 |
| Directory | /workspace/3.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_rma_unlocked.3619033627 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 42756656258 ps |
| CPU time | 4670.23 seconds |
| Started | Aug 17 07:05:33 PM PDT 24 |
| Finished | Aug 17 08:23:24 PM PDT 24 |
| Peak memory | 621324 kb |
| Host | smart-3f119b19-69ee-44a8-a3a9-2eddb7f8d60c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3619033627 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_rma_unlocked.3619033627 |
| Directory | /workspace/0.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_random.2081958047 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 533249388 ps |
| CPU time | 17.77 seconds |
| Started | Aug 17 06:51:09 PM PDT 24 |
| Finished | Aug 17 06:51:27 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-e5aac594-9dbf-401f-8c4e-41c7d51cbc54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081958047 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_random.2081958047 |
| Directory | /workspace/43.xbar_error_random/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_10.2061412059 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 3353099352 ps |
| CPU time | 546.48 seconds |
| Started | Aug 17 07:06:40 PM PDT 24 |
| Finished | Aug 17 07:15:47 PM PDT 24 |
| Peak memory | 609492 kb |
| Host | smart-3823ebbb-346e-4ff5-8cd1-64f58b549898 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061412059 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_10.2061412059 |
| Directory | /workspace/0.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_tl_errors.3419760826 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 4799851736 ps |
| CPU time | 437.14 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:55:08 PM PDT 24 |
| Peak memory | 604024 kb |
| Host | smart-bfcc0395-7a4c-4659-837c-7dd55108f33d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419760826 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_tl_errors.3419760826 |
| Directory | /workspace/14.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.2769736527 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 4256244278 ps |
| CPU time | 588.51 seconds |
| Started | Aug 17 07:06:38 PM PDT 24 |
| Finished | Aug 17 07:16:27 PM PDT 24 |
| Peak memory | 611084 kb |
| Host | smart-1a0b0969-b08d-436b-a003-342022b02394 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769736527 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw _sram_ctrl_scrambled_access.2769736527 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio.447061239 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 4060255348 ps |
| CPU time | 422.55 seconds |
| Started | Aug 17 07:11:28 PM PDT 24 |
| Finished | Aug 17 07:18:31 PM PDT 24 |
| Peak memory | 610512 kb |
| Host | smart-c4fb75eb-4614-4cab-a96c-c550a86e7876 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=447061239 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.chip_sw_gpio.447061239 |
| Directory | /workspace/1.chip_sw_gpio/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device_slow_rsp.1055286992 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 84535530812 ps |
| CPU time | 1571.23 seconds |
| Started | Aug 17 06:53:27 PM PDT 24 |
| Finished | Aug 17 07:19:38 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-5ffa6e04-6b70-4e87-980a-a2078553ed27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055286992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_ device_slow_rsp.1055286992 |
| Directory | /workspace/61.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_large_delays.4048307746 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 71047237605 ps |
| CPU time | 715.12 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 07:00:00 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-59a86fc8-7e78-4849-bca9-013fb72a90c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048307746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_large_delays.4048307746 |
| Directory | /workspace/9.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3352331357 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 2907390288 ps |
| CPU time | 343.38 seconds |
| Started | Aug 17 07:15:24 PM PDT 24 |
| Finished | Aug 17 07:21:07 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-68546b55-c0ad-4d48-83e1-e006a64debfb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352 331357 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_mio_dio_val.3352331357 |
| Directory | /workspace/1.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.3383497059 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 28559527200 ps |
| CPU time | 3913.62 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 07:53:21 PM PDT 24 |
| Peak memory | 593500 kb |
| Host | smart-dad370a7-841e-4abb-aa81-4f056ecdab75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383497059 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 18.chip_same_csr_outstanding.3383497059 |
| Directory | /workspace/18.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4071432941 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 5452428480 ps |
| CPU time | 483.54 seconds |
| Started | Aug 17 07:08:14 PM PDT 24 |
| Finished | Aug 17 07:16:18 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-59ef6a7c-c3b0-41a3-8997-17516fd19f1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40714329 41 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.4071432941 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_rma.1979412028 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 11357367017 ps |
| CPU time | 2205.13 seconds |
| Started | Aug 17 07:13:29 PM PDT 24 |
| Finished | Aug 17 07:50:16 PM PDT 24 |
| Peak memory | 624788 kb |
| Host | smart-c5b93076-51ef-48c7-bf7a-1490c4f5270c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794 12028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_rma.1979412028 |
| Directory | /workspace/0.rom_e2e_jtag_debug_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.3351795022 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 11777202064 ps |
| CPU time | 2569.17 seconds |
| Started | Aug 17 07:14:20 PM PDT 24 |
| Finished | Aug 17 07:57:09 PM PDT 24 |
| Peak memory | 610912 kb |
| Host | smart-cd087f22-83ac-469d-859d-8534532a66f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351795022 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency.3351795022 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_entropy.1755515773 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 3909339716 ps |
| CPU time | 399.54 seconds |
| Started | Aug 17 07:14:31 PM PDT 24 |
| Finished | Aug 17 07:21:10 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-2945b570-f6ce-4f4b-86a3-c84aef28eedd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1755515773 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_entropy.1755515773 |
| Directory | /workspace/1.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1673521649 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 4899770252 ps |
| CPU time | 385.19 seconds |
| Started | Aug 17 07:15:01 PM PDT 24 |
| Finished | Aug 17 07:21:27 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-9051c3c0-e1b2-43a5-8292-627a33fac77a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16 73521649 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_lc_rw_en.1673521649 |
| Directory | /workspace/1.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_retention.2777643513 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 3656267672 ps |
| CPU time | 329.5 seconds |
| Started | Aug 17 07:19:00 PM PDT 24 |
| Finished | Aug 17 07:24:29 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-7f8aa9a4-6fdb-4426-b96c-768f19173dd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777643513 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_retention.2777643513 |
| Directory | /workspace/2.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_tl_errors.1791881923 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 4886124424 ps |
| CPU time | 354.43 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:53:40 PM PDT 24 |
| Peak memory | 603932 kb |
| Host | smart-adabae42-2817-40c0-ab62-51039836260c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791881923 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_tl_errors.1791881923 |
| Directory | /workspace/5.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1951031364 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 5341655204 ps |
| CPU time | 523.07 seconds |
| Started | Aug 17 07:08:55 PM PDT 24 |
| Finished | Aug 17 07:17:39 PM PDT 24 |
| Peak memory | 611528 kb |
| Host | smart-759f2a5f-cf54-43b4-9e89-0058fafc30cc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1951031364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_escalation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_escalation.1951031364 |
| Directory | /workspace/0.chip_sw_otp_ctrl_escalation/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.3484321677 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 9093643937 ps |
| CPU time | 1065.71 seconds |
| Started | Aug 17 06:57:27 PM PDT 24 |
| Finished | Aug 17 07:15:13 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-5c1917ea-0319-4cc6-91eb-9714b17fc237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484321677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all _with_rand_reset.3484321677 |
| Directory | /workspace/95.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2873501006 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 23661001720 ps |
| CPU time | 1775.7 seconds |
| Started | Aug 17 07:22:31 PM PDT 24 |
| Finished | Aug 17 07:52:07 PM PDT 24 |
| Peak memory | 614588 kb |
| Host | smart-5237c3a7-4e3f-4322-ad24-9dbf8350891d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28735010 06 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_reset.2873501006 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_rand_reset.562270205 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 20301712293 ps |
| CPU time | 927.79 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 07:06:28 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-8848820c-d947-41b9-a8f7-8cc7d5063942 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562270205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_ with_rand_reset.562270205 |
| Directory | /workspace/42.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.573093126 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 3019255621 ps |
| CPU time | 294.14 seconds |
| Started | Aug 17 07:18:42 PM PDT 24 |
| Finished | Aug 17 07:23:36 PM PDT 24 |
| Peak memory | 610480 kb |
| Host | smart-558ccad3-a9e5-40f0-b0c8-8ec6b569ea4d |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_mio_dio_val_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5730 93126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_mio_dio_val_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_mio_dio_val.573093126 |
| Directory | /workspace/2.chip_sw_sleep_pin_mio_dio_val/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_rma_unlocked.428692315 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 43419829010 ps |
| CPU time | 4941.82 seconds |
| Started | Aug 17 07:10:09 PM PDT 24 |
| Finished | Aug 17 08:32:32 PM PDT 24 |
| Peak memory | 620384 kb |
| Host | smart-33f3b965-7499-4518-a4d7-301572b8b512 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=428692315 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_rma_unlocked.428692315 |
| Directory | /workspace/1.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/46.chip_sw_all_escalation_resets.1005373677 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 5871547976 ps |
| CPU time | 702.62 seconds |
| Started | Aug 17 07:34:14 PM PDT 24 |
| Finished | Aug 17 07:45:56 PM PDT 24 |
| Peak memory | 651272 kb |
| Host | smart-238fb2ae-3179-4cc8-9a85-2057400f8002 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1005373677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw_all_escalation_resets.1005373677 |
| Directory | /workspace/46.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_all_escalation_resets.3327521939 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 4782402260 ps |
| CPU time | 672.23 seconds |
| Started | Aug 17 07:29:56 PM PDT 24 |
| Finished | Aug 17 07:41:08 PM PDT 24 |
| Peak memory | 650608 kb |
| Host | smart-8b1df930-dd2d-4882-b626-82db3842783d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3327521939 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_all_escalation_resets.3327521939 |
| Directory | /workspace/9.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.3743576987 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 4283268376 ps |
| CPU time | 698.49 seconds |
| Started | Aug 17 07:29:51 PM PDT 24 |
| Finished | Aug 17 07:41:30 PM PDT 24 |
| Peak memory | 625152 kb |
| Host | smart-2e1564aa-32ae-4d1f-9920-38f1f6ea9850 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3743576987 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_uart_rand_baudrate.3743576987 |
| Directory | /workspace/5.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2775500023 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 5358768524 ps |
| CPU time | 445.16 seconds |
| Started | Aug 17 07:22:39 PM PDT 24 |
| Finished | Aug 17 07:30:04 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-1d8b1268-df50-4e4c-97c4-491b7f5b7687 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775500023 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_rstmgr_cpu_info.2775500023 |
| Directory | /workspace/2.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.3130807236 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 2987162584 ps |
| CPU time | 138.71 seconds |
| Started | Aug 17 07:08:08 PM PDT 24 |
| Finished | Aug 17 07:10:29 PM PDT 24 |
| Peak memory | 620752 kb |
| Host | smart-72cb0b77-4ba9-4097-b20d-c1cb70627895 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStTestLocked0 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3130807236 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_test_locked0_to_scrap.3130807236 |
| Directory | /workspace/0.chip_sw_lc_ctrl_test_locked0_to_scrap/latest |
| Test location | /workspace/coverage/default/63.chip_sw_all_escalation_resets.1135087748 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 6201256168 ps |
| CPU time | 603.27 seconds |
| Started | Aug 17 07:37:15 PM PDT 24 |
| Finished | Aug 17 07:47:19 PM PDT 24 |
| Peak memory | 650588 kb |
| Host | smart-07bed141-bdbd-49fb-bb08-f21976dc2fb9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1135087748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_sw_all_escalation_resets.1135087748 |
| Directory | /workspace/63.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/3.chip_sw_all_escalation_resets.961375599 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 4321494632 ps |
| CPU time | 620.33 seconds |
| Started | Aug 17 07:28:01 PM PDT 24 |
| Finished | Aug 17 07:38:22 PM PDT 24 |
| Peak memory | 650576 kb |
| Host | smart-f480a5d2-d57d-4c58-b25d-fd614a63b420 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 961375599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_all_escalation_resets.961375599 |
| Directory | /workspace/3.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_rand_reset.2188087224 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 15985468918 ps |
| CPU time | 777.66 seconds |
| Started | Aug 17 06:52:30 PM PDT 24 |
| Finished | Aug 17 07:05:28 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-2477d57e-ec45-45e6-942f-1a57944055d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188087224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all _with_rand_reset.2188087224 |
| Directory | /workspace/53.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_rma.3358582567 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 9092355642 ps |
| CPU time | 896.76 seconds |
| Started | Aug 17 07:25:26 PM PDT 24 |
| Finished | Aug 17 07:40:23 PM PDT 24 |
| Peak memory | 633992 kb |
| Host | smart-f4be4009-0153-46ac-8ae7-5bb5b81f9733 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358582567 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_rma.3358582567 |
| Directory | /workspace/2.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_data_integrity_escalation.926362558 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 5500395648 ps |
| CPU time | 819.86 seconds |
| Started | Aug 17 07:10:38 PM PDT 24 |
| Finished | Aug 17 07:24:18 PM PDT 24 |
| Peak memory | 611436 kb |
| Host | smart-cf9eec70-2650-4608-887e-8af3200d5d5b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=926362558 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_data_integrity_escalation.926362558 |
| Directory | /workspace/1.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1838298982 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 5928806900 ps |
| CPU time | 658.76 seconds |
| Started | Aug 17 07:11:03 PM PDT 24 |
| Finished | Aug 17 07:22:02 PM PDT 24 |
| Peak memory | 610088 kb |
| Host | smart-348ecd1c-4922-4102-aa0d-d618ec5bf33f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18382989 82 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_alert.1838298982 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/21.chip_tl_errors.3795466751 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 3645892084 ps |
| CPU time | 306.2 seconds |
| Started | Aug 17 06:48:52 PM PDT 24 |
| Finished | Aug 17 06:53:58 PM PDT 24 |
| Peak memory | 603856 kb |
| Host | smart-1467b430-5e49-405f-9677-46fa30d5f223 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795466751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.chip_tl_errors.3795466751 |
| Directory | /workspace/21.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_hw_reset.3727413070 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 7491326459 ps |
| CPU time | 382.2 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 06:54:18 PM PDT 24 |
| Peak memory | 664288 kb |
| Host | smart-0156e990-eee0-4e72-b054-f0a718f165a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727413070 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_hw_r eset.3727413070 |
| Directory | /workspace/3.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1805391497 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 7328500792 ps |
| CPU time | 905.55 seconds |
| Started | Aug 17 07:08:25 PM PDT 24 |
| Finished | Aug 17 07:23:32 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-098ae5a8-b770-47ac-b41d-cc9e0769bad4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805391497 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_execution_main.1805391497 |
| Directory | /workspace/0.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_wake.3883211567 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 3535470784 ps |
| CPU time | 288.12 seconds |
| Started | Aug 17 07:13:41 PM PDT 24 |
| Finished | Aug 17 07:18:29 PM PDT 24 |
| Peak memory | 610852 kb |
| Host | smart-ec5239ac-4940-457b-8712-b1c05eac76a9 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883211567 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_wake.3883211567 |
| Directory | /workspace/1.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pin_wake.3776108894 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 6120984122 ps |
| CPU time | 560.38 seconds |
| Started | Aug 17 07:19:37 PM PDT 24 |
| Finished | Aug 17 07:28:57 PM PDT 24 |
| Peak memory | 611472 kb |
| Host | smart-1353db03-3610-4e62-be04-ea44760318dd |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776108894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep_pin_wake.3776108894 |
| Directory | /workspace/2.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1137925420 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 3884544259 ps |
| CPU time | 382.07 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 07:04:03 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-d20b50bb-513c-4ae8-9699-98a4e4b8e2ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137925420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all _with_rand_reset.1137925420 |
| Directory | /workspace/97.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pinmux_sleep_retention.2001896236 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 4086951101 ps |
| CPU time | 337.54 seconds |
| Started | Aug 17 07:06:33 PM PDT 24 |
| Finished | Aug 17 07:12:11 PM PDT 24 |
| Peak memory | 618740 kb |
| Host | smart-fc2a7db7-3bc6-4ec0-9f6f-9fccffe93b02 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001896236 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pinmux_sleep_retention.2001896236 |
| Directory | /workspace/0.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.35417885 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 9519123024 ps |
| CPU time | 1545.55 seconds |
| Started | Aug 17 07:30:11 PM PDT 24 |
| Finished | Aug 17 07:55:57 PM PDT 24 |
| Peak memory | 623840 kb |
| Host | smart-54c9df6c-ea21-44d8-82ae-cd533afa6e01 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35417885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_bau drate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_a lt_clk_freq.35417885 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_dpi.4037418851 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 11570196360 ps |
| CPU time | 2700.96 seconds |
| Started | Aug 17 07:05:36 PM PDT 24 |
| Finished | Aug 17 07:50:39 PM PDT 24 |
| Peak memory | 610948 kb |
| Host | smart-2ac6e80d-3e8f-45e4-bad4-b1d4b626ce45 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=usbdev_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4037418851 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_dpi.4037418851 |
| Directory | /workspace/0.chip_sw_usbdev_dpi/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_error.3368572404 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 9951494456 ps |
| CPU time | 404.07 seconds |
| Started | Aug 17 06:55:41 PM PDT 24 |
| Finished | Aug 17 07:02:25 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-77015c8c-a731-4ddf-8ba4-5cb2ad3bed6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368572404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all_with_error.3368572404 |
| Directory | /workspace/80.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_0.3349809230 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 5846233312 ps |
| CPU time | 1383.72 seconds |
| Started | Aug 17 07:07:59 PM PDT 24 |
| Finished | Aug 17 07:31:03 PM PDT 24 |
| Peak memory | 609816 kb |
| Host | smart-a6fabbc8-1a07-4994-9646-a406b2b619e9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349809230 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_plic_all_irqs_0.3349809230 |
| Directory | /workspace/0.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/cover_reg_top/20.chip_tl_errors.2324920505 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 4172754960 ps |
| CPU time | 288.04 seconds |
| Started | Aug 17 06:48:34 PM PDT 24 |
| Finished | Aug 17 06:53:22 PM PDT 24 |
| Peak memory | 603852 kb |
| Host | smart-708ff136-ceba-46a7-ad8a-806bf1c5f831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324920505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.chip_tl_errors.2324920505 |
| Directory | /workspace/20.chip_tl_errors/latest |
| Test location | /workspace/coverage/default/1.chip_sw_inject_scramble_seed.3612869683 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 65632333816 ps |
| CPU time | 10840.8 seconds |
| Started | Aug 17 07:10:37 PM PDT 24 |
| Finished | Aug 17 10:11:20 PM PDT 24 |
| Peak memory | 625520 kb |
| Host | smart-16104340-225f-4430-a614-76f2ad27e2b7 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=3612869683 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_inject_scramble_seed.3612869683 |
| Directory | /workspace/1.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device_slow_rsp.2616213417 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 83385097791 ps |
| CPU time | 1483.07 seconds |
| Started | Aug 17 06:49:28 PM PDT 24 |
| Finished | Aug 17 07:14:12 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-fc40c498-bcde-4097-ab99-a1377f23347b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616213417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_ device_slow_rsp.2616213417 |
| Directory | /workspace/28.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2377337521 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 44574217500 ps |
| CPU time | 4321.72 seconds |
| Started | Aug 17 07:20:57 PM PDT 24 |
| Finished | Aug 17 08:32:59 PM PDT 24 |
| Peak memory | 620696 kb |
| Host | smart-1597f77b-eb1e-4c88-a006-a72e1de50ac9 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=flash_rma_unlocked_test:0:test_in_ rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2377337521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_rma_unlocked_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_rma_unlocked.2377337521 |
| Directory | /workspace/2.chip_sw_flash_rma_unlocked/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_20.2947213377 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 4622912880 ps |
| CPU time | 822.54 seconds |
| Started | Aug 17 07:14:30 PM PDT 24 |
| Finished | Aug 17 07:28:12 PM PDT 24 |
| Peak memory | 609764 kb |
| Host | smart-f23191cd-e4f8-4f86-b90a-ea5f9d6cf22f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947213377 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_20.2947213377 |
| Directory | /workspace/1.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_rst_inputs.1990980194 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 19423376190 ps |
| CPU time | 2636.2 seconds |
| Started | Aug 17 07:07:19 PM PDT 24 |
| Finished | Aug 17 07:51:17 PM PDT 24 |
| Peak memory | 611688 kb |
| Host | smart-35719ff4-81d7-4dc1-95b7-063a5763a428 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990980194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_rst_inputs.1990980194 |
| Directory | /workspace/0.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1810688948 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 14503843420 ps |
| CPU time | 3902.63 seconds |
| Started | Aug 17 07:13:21 PM PDT 24 |
| Finished | Aug 17 08:18:24 PM PDT 24 |
| Peak memory | 611076 kb |
| Host | smart-8bb541f4-3eee-428e-9d06-ea8ee8984d28 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810688948 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1810688948 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_rand_reset.1068396343 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 18736711445 ps |
| CPU time | 949.24 seconds |
| Started | Aug 17 06:47:38 PM PDT 24 |
| Finished | Aug 17 07:03:28 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-a929898a-4d0e-4d4f-a0b0-e2eb274b5898 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068396343 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_ with_rand_reset.1068396343 |
| Directory | /workspace/5.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_0.3480323607 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 6088328772 ps |
| CPU time | 1315.33 seconds |
| Started | Aug 17 07:14:46 PM PDT 24 |
| Finished | Aug 17 07:36:42 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-43e1a893-3a8c-4a5e-9c7b-96959d1b91de |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_0:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480323607 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_plic_all_irqs_0.3480323607 |
| Directory | /workspace/1.chip_plic_all_irqs_0/latest |
| Test location | /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.110569182 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4455853504 ps |
| CPU time | 473.38 seconds |
| Started | Aug 17 07:10:57 PM PDT 24 |
| Finished | Aug 17 07:18:50 PM PDT 24 |
| Peak memory | 624836 kb |
| Host | smart-703681cf-48a4-43d0-8f69-d8ec143b4109 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1 10569182 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_ndm_reset_req.110569182 |
| Directory | /workspace/0.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.824479562 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 4562452028 ps |
| CPU time | 426.57 seconds |
| Started | Aug 17 07:27:31 PM PDT 24 |
| Finished | Aug 17 07:34:37 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-d090e948-9e80-44ce-bef4-f84acd8829ff |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82447956 2 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_sensor_ctrl_alert.824479562 |
| Directory | /workspace/3.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4033834848 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 6309165512 ps |
| CPU time | 648.22 seconds |
| Started | Aug 17 07:29:34 PM PDT 24 |
| Finished | Aug 17 07:40:23 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-d57e0320-bc89-43d4-b917-d7dc21638df5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40338348 48 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_sensor_ctrl_alert.4033834848 |
| Directory | /workspace/4.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_rw.142611476 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 6211100374 ps |
| CPU time | 517.48 seconds |
| Started | Aug 17 06:48:10 PM PDT 24 |
| Finished | Aug 17 06:56:47 PM PDT 24 |
| Peak memory | 598804 kb |
| Host | smart-08e87508-df43-4abe-b5d2-73dddfe67a2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142611476 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_csr_rw.142611476 |
| Directory | /workspace/13.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_rand_reset.166502729 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 7386227410 ps |
| CPU time | 915.41 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 07:11:16 PM PDT 24 |
| Peak memory | 576588 kb |
| Host | smart-5ef24747-b841-4d21-b2a5-15d082604def |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166502729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_ with_rand_reset.166502729 |
| Directory | /workspace/83.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.3290495346 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 4564352070 ps |
| CPU time | 684.39 seconds |
| Started | Aug 17 07:06:31 PM PDT 24 |
| Finished | Aug 17 07:17:56 PM PDT 24 |
| Peak memory | 623520 kb |
| Host | smart-233f6b94-de13-4d73-a825-06f03b66ebd8 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290495346 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx2.3290495346 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3868089673 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2787286889 ps |
| CPU time | 104.37 seconds |
| Started | Aug 17 07:07:50 PM PDT 24 |
| Finished | Aug 17 07:09:35 PM PDT 24 |
| Peak memory | 622724 kb |
| Host | smart-6b73085e-2a37-45a4-9444-0920da7b450b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3868089673 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_vendor_test_csr_access.3868089673 |
| Directory | /workspace/0.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2891175305 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 3518032478 ps |
| CPU time | 518.11 seconds |
| Started | Aug 17 07:05:06 PM PDT 24 |
| Finished | Aug 17 07:13:45 PM PDT 24 |
| Peak memory | 609472 kb |
| Host | smart-1ec87226-2256-40a6-837d-9a8bd87ddffc |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_aon_pullup_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289117 5305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_aon_pullup.2891175305 |
| Directory | /workspace/0.chip_sw_usbdev_aon_pullup/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_tl_errors.4010559849 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 4213720566 ps |
| CPU time | 224.22 seconds |
| Started | Aug 17 06:48:12 PM PDT 24 |
| Finished | Aug 17 06:51:57 PM PDT 24 |
| Peak memory | 603908 kb |
| Host | smart-02819aca-16ee-484e-8fb0-98b59cb75e1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010559849 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_tl_errors.4010559849 |
| Directory | /workspace/18.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all.675024568 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 4493388516 ps |
| CPU time | 387.92 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:55:29 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-cfbd0e08-35cc-4ef8-b997-0cbdba5fbf11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675024568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all.675024568 |
| Directory | /workspace/22.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_reset_error.3280683090 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 9650515334 ps |
| CPU time | 444.33 seconds |
| Started | Aug 17 06:49:14 PM PDT 24 |
| Finished | Aug 17 06:56:39 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-e5d9e864-8667-4d28-812f-9af0445c514f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3280683090 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_al l_with_reset_error.3280683090 |
| Directory | /workspace/25.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_reset_error.1148044299 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 643107485 ps |
| CPU time | 197.76 seconds |
| Started | Aug 17 06:54:38 PM PDT 24 |
| Finished | Aug 17 06:57:56 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-a73ae28d-3efb-4988-a1ad-1b9b6b11c52b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148044299 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_al l_with_reset_error.1148044299 |
| Directory | /workspace/71.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.259912819 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 4081760950 ps |
| CPU time | 672.24 seconds |
| Started | Aug 17 07:12:05 PM PDT 24 |
| Finished | Aug 17 07:23:18 PM PDT 24 |
| Peak memory | 609532 kb |
| Host | smart-4c12115d-05f3-411d-ad47-1c72d7ad1da3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=259912819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en.259912819 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/68.chip_sw_all_escalation_resets.1862804518 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 4288525100 ps |
| CPU time | 508.96 seconds |
| Started | Aug 17 07:35:46 PM PDT 24 |
| Finished | Aug 17 07:44:16 PM PDT 24 |
| Peak memory | 650312 kb |
| Host | smart-3bebfb1f-32f7-4a89-81f1-d4919aa389ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1862804518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_sw_all_escalation_resets.1862804518 |
| Directory | /workspace/68.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.997687252 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 23127273550 ps |
| CPU time | 1868.75 seconds |
| Started | Aug 17 07:15:18 PM PDT 24 |
| Finished | Aug 17 07:46:27 PM PDT 24 |
| Peak memory | 611056 kb |
| Host | smart-b0ae5c95-f0cd-4ce0-a752-47e7011f21b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=997687252 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init_reduced_freq.997687252 |
| Directory | /workspace/1.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1626192496 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 12696648682 ps |
| CPU time | 822.76 seconds |
| Started | Aug 17 07:17:54 PM PDT 24 |
| Finished | Aug 17 07:31:37 PM PDT 24 |
| Peak memory | 625428 kb |
| Host | smart-84bd62ef-695b-4bbf-b5d2-cf797f7c110e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626192496 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_transition.1626192496 |
| Directory | /workspace/1.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_plic_all_irqs_10.2415545563 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 3536609208 ps |
| CPU time | 530.91 seconds |
| Started | Aug 17 07:25:37 PM PDT 24 |
| Finished | Aug 17 07:34:28 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-ddf3693c-469f-4d75-9c41-7edb71f09320 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415545563 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_plic_all_irqs_10.2415545563 |
| Directory | /workspace/2.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device.639165557 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 1029564765 ps |
| CPU time | 79.24 seconds |
| Started | Aug 17 06:57:18 PM PDT 24 |
| Finished | Aug 17 06:58:37 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-d5599a15-4c17-4982-b641-9e6a0a16104f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639165557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_device. 639165557 |
| Directory | /workspace/94.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2528156664 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 4044188160 ps |
| CPU time | 577.77 seconds |
| Started | Aug 17 07:09:25 PM PDT 24 |
| Finished | Aug 17 07:19:03 PM PDT 24 |
| Peak memory | 613948 kb |
| Host | smart-07d2d056-3e5f-4a70-a113-5f4ef2b4becc |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528156664 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2528156664 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_rand_reset.3022238669 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 12321404789 ps |
| CPU time | 625.32 seconds |
| Started | Aug 17 06:53:24 PM PDT 24 |
| Finished | Aug 17 07:03:50 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-1fdfcce8-c362-42db-8fbf-904c7a7e692d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022238669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all _with_rand_reset.3022238669 |
| Directory | /workspace/61.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx.2624168317 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 3921226232 ps |
| CPU time | 652.74 seconds |
| Started | Aug 17 07:04:54 PM PDT 24 |
| Finished | Aug 17 07:15:47 PM PDT 24 |
| Peak memory | 620364 kb |
| Host | smart-38425458-3679-4d05-bc73-f3689174f48f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624168317 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx.2624168317 |
| Directory | /workspace/0.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_all_escalation_resets.2920841388 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 4757978692 ps |
| CPU time | 589.63 seconds |
| Started | Aug 17 07:19:08 PM PDT 24 |
| Finished | Aug 17 07:28:58 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-bf6c8b53-dfbc-4d1c-8af9-1b221f575ca0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2920841388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_all_escalation_resets.2920841388 |
| Directory | /workspace/2.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_plic_all_irqs_20.1419942717 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 5443212140 ps |
| CPU time | 914.14 seconds |
| Started | Aug 17 07:10:38 PM PDT 24 |
| Finished | Aug 17 07:25:53 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-3d4289e1-ef68-4c26-8b1f-53c1f51c65ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_20:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419942717 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_plic_all_irqs_20.1419942717 |
| Directory | /workspace/0.chip_plic_all_irqs_20/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.647858988 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 4597336730 ps |
| CPU time | 242.98 seconds |
| Started | Aug 17 07:31:00 PM PDT 24 |
| Finished | Aug 17 07:35:03 PM PDT 24 |
| Peak memory | 657916 kb |
| Host | smart-9ab34a26-9dc0-4d32-81ea-0ed9d7ce2491 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=647858988 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 0.chip_padctrl_attributes.647858988 |
| Directory | /workspace/0.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/default/35.chip_sw_all_escalation_resets.247131785 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 5457217752 ps |
| CPU time | 615.01 seconds |
| Started | Aug 17 07:33:11 PM PDT 24 |
| Finished | Aug 17 07:43:26 PM PDT 24 |
| Peak memory | 650636 kb |
| Host | smart-3265ba4d-106e-4889-8c3c-947efa71c02c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 247131785 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_sw_all_escalation_resets.247131785 |
| Directory | /workspace/35.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.3375884628 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2377848400 ps |
| CPU time | 125.44 seconds |
| Started | Aug 17 07:18:15 PM PDT 24 |
| Finished | Aug 17 07:20:20 PM PDT 24 |
| Peak memory | 622712 kb |
| Host | smart-025c8d21-f8d2-4ac0-a232-24c739369258 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375884628 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_vendor_test_csr_access.3375884628 |
| Directory | /workspace/1.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.3007173809 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 13922412200 ps |
| CPU time | 1880.93 seconds |
| Started | Aug 17 07:08:05 PM PDT 24 |
| Finished | Aug 17 07:39:27 PM PDT 24 |
| Peak memory | 611548 kb |
| Host | smart-1a2bea73-89ce-4117-b27b-c6020a15300e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3007173809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_alert_info.3007173809 |
| Directory | /workspace/0.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_hw_reset.2547494354 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 6836372376 ps |
| CPU time | 372.44 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 06:53:46 PM PDT 24 |
| Peak memory | 663460 kb |
| Host | smart-1256d869-10f9-4424-b9e4-b9617fcabd20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547494354 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_hw_r eset.2547494354 |
| Directory | /workspace/1.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all.2097084766 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 8010075600 ps |
| CPU time | 290.58 seconds |
| Started | Aug 17 06:57:14 PM PDT 24 |
| Finished | Aug 17 07:02:05 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-b82e3813-17f7-45ac-a3d7-016037dd08d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097084766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all.2097084766 |
| Directory | /workspace/93.xbar_stress_all/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2884132336 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 7653684632 ps |
| CPU time | 1844.04 seconds |
| Started | Aug 17 07:15:32 PM PDT 24 |
| Finished | Aug 17 07:46:16 PM PDT 24 |
| Peak memory | 610188 kb |
| Host | smart-0a50fe6f-4a47-4c76-a54f-222e0ac8a301 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=2884132336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_csrng.2884132336 |
| Directory | /workspace/0.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/33.chip_sw_all_escalation_resets.3081493981 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 4466325000 ps |
| CPU time | 538.89 seconds |
| Started | Aug 17 07:33:51 PM PDT 24 |
| Finished | Aug 17 07:42:50 PM PDT 24 |
| Peak memory | 650568 kb |
| Host | smart-21f5a3d1-068a-4193-9d6b-8362c143d857 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3081493981 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_sw_all_escalation_resets.3081493981 |
| Directory | /workspace/33.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/0.chip_sw_plic_sw_irq.978939230 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2852870142 ps |
| CPU time | 301.63 seconds |
| Started | Aug 17 07:10:49 PM PDT 24 |
| Finished | Aug 17 07:15:51 PM PDT 24 |
| Peak memory | 609296 kb |
| Host | smart-9c825fe7-80f0-4cd8-9bd9-d6adccb729b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978939230 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_plic_sw_irq.978939230 |
| Directory | /workspace/0.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.3998223420 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 5311605787 ps |
| CPU time | 635.51 seconds |
| Started | Aug 17 07:10:31 PM PDT 24 |
| Finished | Aug 17 07:21:07 PM PDT 24 |
| Peak memory | 624972 kb |
| Host | smart-b3d9361d-ce02-4c0d-8fdd-eb3f06f2792e |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998223420 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_escalation_reset.3998223420 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_tl_errors.2283241230 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3209613707 ps |
| CPU time | 164.08 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 06:50:17 PM PDT 24 |
| Peak memory | 603880 kb |
| Host | smart-e443d535-2084-4d1d-80ef-6496be649c32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2283241230 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_tl_errors.2283241230 |
| Directory | /workspace/0.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_mem_rw_with_rand_reset.1595123363 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 6117446519 ps |
| CPU time | 429.89 seconds |
| Started | Aug 17 06:47:59 PM PDT 24 |
| Finished | Aug 17 06:55:09 PM PDT 24 |
| Peak memory | 639700 kb |
| Host | smart-4df895bf-cc56-4bfe-9269-fbabd497f300 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595123363 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 12.chip_csr_mem_rw_with_rand_reset.1595123363 |
| Directory | /workspace/12.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_reset_error.346083520 |
| Short name | T1535 |
| Test name | |
| Test status | |
| Simulation time | 5249323556 ps |
| CPU time | 548.18 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 06:57:20 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-32803b81-5945-4750-99b9-6d075b7ebe8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346083520 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_reset_error.346083520 |
| Directory | /workspace/18.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1581280201 |
| Short name | T2223 |
| Test name | |
| Test status | |
| Simulation time | 17903162088 ps |
| CPU time | 871.36 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 07:03:32 PM PDT 24 |
| Peak memory | 580216 kb |
| Host | smart-4fee65df-843c-4346-add6-c1b7b66b8cd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581280201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_al l_with_reset_error.1581280201 |
| Directory | /workspace/23.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4949883 |
| Short name | T1269 |
| Test name | |
| Test status | |
| Simulation time | 3359941136 ps |
| CPU time | 384.26 seconds |
| Started | Aug 17 07:09:32 PM PDT 24 |
| Finished | Aug 17 07:15:56 PM PDT 24 |
| Peak memory | 649280 kb |
| Host | smart-380da401-c0fc-4df9-a412-a80c16239945 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4949883 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_e scalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_a lert_handler_lpg_sleep_mode_alerts.4949883 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/0.chip_sw_all_escalation_resets.2813903891 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 4983229588 ps |
| CPU time | 643.91 seconds |
| Started | Aug 17 07:05:23 PM PDT 24 |
| Finished | Aug 17 07:16:07 PM PDT 24 |
| Peak memory | 647580 kb |
| Host | smart-f0627160-aa08-4d0a-85b8-c4e308926822 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2813903891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_all_escalation_resets.2813903891 |
| Directory | /workspace/0.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.2353668243 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 3083342140 ps |
| CPU time | 380.78 seconds |
| Started | Aug 17 07:11:50 PM PDT 24 |
| Finished | Aug 17 07:18:11 PM PDT 24 |
| Peak memory | 649272 kb |
| Host | smart-130b8011-c6f8-4ffb-adae-4a072836a484 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353668243 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_s w_alert_handler_lpg_sleep_mode_alerts.2353668243 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/1.chip_sw_all_escalation_resets.1769799688 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 5624837416 ps |
| CPU time | 768.82 seconds |
| Started | Aug 17 07:12:12 PM PDT 24 |
| Finished | Aug 17 07:25:01 PM PDT 24 |
| Peak memory | 650828 kb |
| Host | smart-f6365b91-519c-4be7-b627-4b76c2d49a21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1769799688 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_all_escalation_resets.1769799688 |
| Directory | /workspace/1.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/10.chip_sw_all_escalation_resets.990033173 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 6043680296 ps |
| CPU time | 685.94 seconds |
| Started | Aug 17 07:30:34 PM PDT 24 |
| Finished | Aug 17 07:42:01 PM PDT 24 |
| Peak memory | 650760 kb |
| Host | smart-e267e394-3925-4665-9ad5-d1e0cd56354f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 990033173 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_all_escalation_resets.990033173 |
| Directory | /workspace/10.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2135906242 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 3816064856 ps |
| CPU time | 375.67 seconds |
| Started | Aug 17 07:32:33 PM PDT 24 |
| Finished | Aug 17 07:38:49 PM PDT 24 |
| Peak memory | 649172 kb |
| Host | smart-171baa71-c131-4f05-a8bc-8b7c6ef6412e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135906242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2135906242 |
| Directory | /workspace/11.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/11.chip_sw_all_escalation_resets.3150695126 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 4579002584 ps |
| CPU time | 672.17 seconds |
| Started | Aug 17 07:30:23 PM PDT 24 |
| Finished | Aug 17 07:41:35 PM PDT 24 |
| Peak memory | 650612 kb |
| Host | smart-047cb2f9-285c-4118-83e4-3ce23b0610b3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3150695126 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_all_escalation_resets.3150695126 |
| Directory | /workspace/11.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/12.chip_sw_all_escalation_resets.2014071856 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 5817050212 ps |
| CPU time | 625.47 seconds |
| Started | Aug 17 07:32:52 PM PDT 24 |
| Finished | Aug 17 07:43:18 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-bee9647f-2c31-4f44-87e0-7d223eb722c5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2014071856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_all_escalation_resets.2014071856 |
| Directory | /workspace/12.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.3599563810 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 3740926470 ps |
| CPU time | 354.55 seconds |
| Started | Aug 17 07:32:21 PM PDT 24 |
| Finished | Aug 17 07:38:16 PM PDT 24 |
| Peak memory | 649628 kb |
| Host | smart-c3790517-a091-46cb-b748-31d306de105a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599563810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3599563810 |
| Directory | /workspace/13.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/13.chip_sw_all_escalation_resets.893793121 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 6055015336 ps |
| CPU time | 904.03 seconds |
| Started | Aug 17 07:30:36 PM PDT 24 |
| Finished | Aug 17 07:45:40 PM PDT 24 |
| Peak memory | 650588 kb |
| Host | smart-ddfed8cd-fbda-4c6e-b6f6-1b26451b2fde |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 893793121 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_all_escalation_resets.893793121 |
| Directory | /workspace/13.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.1617482390 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 3736922592 ps |
| CPU time | 463.46 seconds |
| Started | Aug 17 07:32:04 PM PDT 24 |
| Finished | Aug 17 07:39:48 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-32102dde-9050-407b-b404-477cf522c73c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617482390 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1617482390 |
| Directory | /workspace/14.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/14.chip_sw_all_escalation_resets.1437889707 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 6496973600 ps |
| CPU time | 682.94 seconds |
| Started | Aug 17 07:31:54 PM PDT 24 |
| Finished | Aug 17 07:43:17 PM PDT 24 |
| Peak memory | 650660 kb |
| Host | smart-6bf0132f-078b-4262-a084-21c4ac340a40 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1437889707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_all_escalation_resets.1437889707 |
| Directory | /workspace/14.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2034913160 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 3494296110 ps |
| CPU time | 321.71 seconds |
| Started | Aug 17 07:32:12 PM PDT 24 |
| Finished | Aug 17 07:37:34 PM PDT 24 |
| Peak memory | 649612 kb |
| Host | smart-6bd4995b-c185-430a-9b5d-760a425bdb70 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034913160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2034913160 |
| Directory | /workspace/16.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/16.chip_sw_all_escalation_resets.454834746 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 4978691248 ps |
| CPU time | 604.37 seconds |
| Started | Aug 17 07:33:57 PM PDT 24 |
| Finished | Aug 17 07:44:01 PM PDT 24 |
| Peak memory | 650556 kb |
| Host | smart-d8d597a7-8584-48d2-be8e-398228b2c232 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 454834746 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_all_escalation_resets.454834746 |
| Directory | /workspace/16.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/18.chip_sw_all_escalation_resets.295228608 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 4882321940 ps |
| CPU time | 562.46 seconds |
| Started | Aug 17 07:33:50 PM PDT 24 |
| Finished | Aug 17 07:43:12 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-5bc048fa-ca83-443c-8c73-63c1484cb471 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 295228608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_all_escalation_resets.295228608 |
| Directory | /workspace/18.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538374277 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 3741111600 ps |
| CPU time | 499.25 seconds |
| Started | Aug 17 07:32:36 PM PDT 24 |
| Finished | Aug 17 07:40:55 PM PDT 24 |
| Peak memory | 649520 kb |
| Host | smart-cb745b85-d044-44b8-89fd-22cf013db3bd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538374277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1538374277 |
| Directory | /workspace/20.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/20.chip_sw_all_escalation_resets.175063776 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 6088491776 ps |
| CPU time | 714.97 seconds |
| Started | Aug 17 07:33:03 PM PDT 24 |
| Finished | Aug 17 07:44:58 PM PDT 24 |
| Peak memory | 650928 kb |
| Host | smart-ae0217b6-9c3a-4859-b700-fac36fb7f7c1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 175063776 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.chip_sw_all_escalation_resets.175063776 |
| Directory | /workspace/20.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/21.chip_sw_all_escalation_resets.2107607942 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 6179532252 ps |
| CPU time | 645.65 seconds |
| Started | Aug 17 07:33:34 PM PDT 24 |
| Finished | Aug 17 07:44:20 PM PDT 24 |
| Peak memory | 650612 kb |
| Host | smart-c87a9412-6aa5-403a-a199-75a310bf5134 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2107607942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_sw_all_escalation_resets.2107607942 |
| Directory | /workspace/21.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1208462223 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 3623605200 ps |
| CPU time | 334.11 seconds |
| Started | Aug 17 07:31:27 PM PDT 24 |
| Finished | Aug 17 07:37:01 PM PDT 24 |
| Peak memory | 649496 kb |
| Host | smart-97de9975-e4a7-4dc8-a68b-fac074035cff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208462223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1208462223 |
| Directory | /workspace/22.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/22.chip_sw_all_escalation_resets.2051194470 |
| Short name | T1171 |
| Test name | |
| Test status | |
| Simulation time | 4948993800 ps |
| CPU time | 554.24 seconds |
| Started | Aug 17 07:32:43 PM PDT 24 |
| Finished | Aug 17 07:41:57 PM PDT 24 |
| Peak memory | 649300 kb |
| Host | smart-90a8b780-fdae-441f-ba7a-3c0bc481ebda |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2051194470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.chip_sw_all_escalation_resets.2051194470 |
| Directory | /workspace/22.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/23.chip_sw_all_escalation_resets.4040688611 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 4952642356 ps |
| CPU time | 599.41 seconds |
| Started | Aug 17 07:32:16 PM PDT 24 |
| Finished | Aug 17 07:42:16 PM PDT 24 |
| Peak memory | 650448 kb |
| Host | smart-21889310-9f26-4d95-b35e-2400c2749bb6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4040688611 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_sw_all_escalation_resets.4040688611 |
| Directory | /workspace/23.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/24.chip_sw_all_escalation_resets.3386310764 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 5933206210 ps |
| CPU time | 655.74 seconds |
| Started | Aug 17 07:32:38 PM PDT 24 |
| Finished | Aug 17 07:43:34 PM PDT 24 |
| Peak memory | 650392 kb |
| Host | smart-5a08c86f-f0c3-4d67-9bc5-9d39e8aa2a77 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3386310764 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_sw_all_escalation_resets.3386310764 |
| Directory | /workspace/24.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115622011 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 2995866264 ps |
| CPU time | 380.6 seconds |
| Started | Aug 17 07:32:04 PM PDT 24 |
| Finished | Aug 17 07:38:25 PM PDT 24 |
| Peak memory | 648508 kb |
| Host | smart-fd7562ed-224b-4a4f-a036-9a3ac9f2e09f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115622011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1115622011 |
| Directory | /workspace/25.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3664962175 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 3873823788 ps |
| CPU time | 380.84 seconds |
| Started | Aug 17 07:33:03 PM PDT 24 |
| Finished | Aug 17 07:39:24 PM PDT 24 |
| Peak memory | 649752 kb |
| Host | smart-8ab26567-7d63-47f9-ba84-c295f2820507 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664962175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3664962175 |
| Directory | /workspace/26.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.1871038595 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 3926371480 ps |
| CPU time | 359.63 seconds |
| Started | Aug 17 07:35:04 PM PDT 24 |
| Finished | Aug 17 07:41:05 PM PDT 24 |
| Peak memory | 649296 kb |
| Host | smart-acceffbd-4c8f-4cc7-a37a-782403418ee5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871038595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1871038595 |
| Directory | /workspace/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/27.chip_sw_all_escalation_resets.74542998 |
| Short name | T1347 |
| Test name | |
| Test status | |
| Simulation time | 4947974516 ps |
| CPU time | 466.44 seconds |
| Started | Aug 17 07:35:26 PM PDT 24 |
| Finished | Aug 17 07:43:13 PM PDT 24 |
| Peak memory | 649164 kb |
| Host | smart-2610912e-50c0-4614-b83d-7c9368586277 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 74542998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.chip_sw_all_escalation_resets.74542998 |
| Directory | /workspace/27.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1347815979 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3735271800 ps |
| CPU time | 501.06 seconds |
| Started | Aug 17 07:33:20 PM PDT 24 |
| Finished | Aug 17 07:41:42 PM PDT 24 |
| Peak memory | 649680 kb |
| Host | smart-2ea4bb10-fc49-48ad-9cc6-3514fa3cf171 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347815979 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1347815979 |
| Directory | /workspace/28.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/29.chip_sw_all_escalation_resets.3528051264 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 5448600640 ps |
| CPU time | 548.92 seconds |
| Started | Aug 17 07:32:58 PM PDT 24 |
| Finished | Aug 17 07:42:07 PM PDT 24 |
| Peak memory | 650688 kb |
| Host | smart-b8fdd175-1857-4b74-990c-a32b6c84c3d3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3528051264 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_sw_all_escalation_resets.3528051264 |
| Directory | /workspace/29.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1107699067 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 3451637176 ps |
| CPU time | 311.81 seconds |
| Started | Aug 17 07:35:17 PM PDT 24 |
| Finished | Aug 17 07:40:29 PM PDT 24 |
| Peak memory | 648280 kb |
| Host | smart-e3693112-fdb6-403e-84e9-b588595e3b0e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107699067 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1107699067 |
| Directory | /workspace/31.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_all_escalation_resets.421417772 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 4879913832 ps |
| CPU time | 717.73 seconds |
| Started | Aug 17 07:33:57 PM PDT 24 |
| Finished | Aug 17 07:45:55 PM PDT 24 |
| Peak memory | 650632 kb |
| Host | smart-b2894fe7-c432-4f66-ab4d-fff56d112bfe |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 421417772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_sw_all_escalation_resets.421417772 |
| Directory | /workspace/34.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325551934 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 4065201620 ps |
| CPU time | 398.48 seconds |
| Started | Aug 17 07:32:41 PM PDT 24 |
| Finished | Aug 17 07:39:19 PM PDT 24 |
| Peak memory | 649636 kb |
| Host | smart-ea35acce-d71a-438d-b6d9-44303f4ec564 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325551934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2325551934 |
| Directory | /workspace/36.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/36.chip_sw_all_escalation_resets.2289522778 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 4199503456 ps |
| CPU time | 498.29 seconds |
| Started | Aug 17 07:33:14 PM PDT 24 |
| Finished | Aug 17 07:41:32 PM PDT 24 |
| Peak memory | 650272 kb |
| Host | smart-0401765b-16a9-4152-a936-008d21474a43 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2289522778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.chip_sw_all_escalation_resets.2289522778 |
| Directory | /workspace/36.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.3681299786 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 4328824660 ps |
| CPU time | 440.21 seconds |
| Started | Aug 17 07:34:14 PM PDT 24 |
| Finished | Aug 17 07:41:34 PM PDT 24 |
| Peak memory | 649940 kb |
| Host | smart-f8628a99-2787-4351-9235-90ea314a6601 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681299786 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3681299786 |
| Directory | /workspace/37.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/37.chip_sw_all_escalation_resets.390945012 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 6126036824 ps |
| CPU time | 549.72 seconds |
| Started | Aug 17 07:35:59 PM PDT 24 |
| Finished | Aug 17 07:45:09 PM PDT 24 |
| Peak memory | 650608 kb |
| Host | smart-ce13fa70-fe15-4ccb-a706-db5580b3220f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 390945012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.chip_sw_all_escalation_resets.390945012 |
| Directory | /workspace/37.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.3353971258 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2994276230 ps |
| CPU time | 400.71 seconds |
| Started | Aug 17 07:30:18 PM PDT 24 |
| Finished | Aug 17 07:36:59 PM PDT 24 |
| Peak memory | 649216 kb |
| Host | smart-27898fa0-c0af-4a35-8a51-da5ee4b52167 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353971258 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_s w_alert_handler_lpg_sleep_mode_alerts.3353971258 |
| Directory | /workspace/4.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.849593276 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 3741974260 ps |
| CPU time | 385.92 seconds |
| Started | Aug 17 07:33:47 PM PDT 24 |
| Finished | Aug 17 07:40:13 PM PDT 24 |
| Peak memory | 646432 kb |
| Host | smart-e8ad1854-11e9-4d19-a432-0b7872583adc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849593276 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_s w_alert_handler_lpg_sleep_mode_alerts.849593276 |
| Directory | /workspace/40.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2393702221 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 3764606864 ps |
| CPU time | 413.66 seconds |
| Started | Aug 17 07:34:06 PM PDT 24 |
| Finished | Aug 17 07:41:00 PM PDT 24 |
| Peak memory | 649656 kb |
| Host | smart-e4ae822f-8dbd-41a3-9abe-04d1240cef73 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393702221 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2393702221 |
| Directory | /workspace/42.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/42.chip_sw_all_escalation_resets.261392524 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 5660121550 ps |
| CPU time | 741.94 seconds |
| Started | Aug 17 07:33:54 PM PDT 24 |
| Finished | Aug 17 07:46:16 PM PDT 24 |
| Peak memory | 650708 kb |
| Host | smart-cc9430ad-a702-4784-8258-8c25a9299384 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 261392524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.chip_sw_all_escalation_resets.261392524 |
| Directory | /workspace/42.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_all_escalation_resets.2066010830 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 6017141466 ps |
| CPU time | 783.67 seconds |
| Started | Aug 17 07:33:41 PM PDT 24 |
| Finished | Aug 17 07:46:45 PM PDT 24 |
| Peak memory | 650596 kb |
| Host | smart-02bb155e-6fd4-46b7-a296-5f23422f7686 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2066010830 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_sw_all_escalation_resets.2066010830 |
| Directory | /workspace/43.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3626754585 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 3606070600 ps |
| CPU time | 447.79 seconds |
| Started | Aug 17 07:35:12 PM PDT 24 |
| Finished | Aug 17 07:42:40 PM PDT 24 |
| Peak memory | 649812 kb |
| Host | smart-16292b5c-3448-4524-a3c0-2b4a80684d58 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626754585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3626754585 |
| Directory | /workspace/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/47.chip_sw_all_escalation_resets.2627059667 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 5058155012 ps |
| CPU time | 687.64 seconds |
| Started | Aug 17 07:34:03 PM PDT 24 |
| Finished | Aug 17 07:45:30 PM PDT 24 |
| Peak memory | 650444 kb |
| Host | smart-7498f1c4-04ac-44b3-a718-a919a08688ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2627059667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.chip_sw_all_escalation_resets.2627059667 |
| Directory | /workspace/47.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/48.chip_sw_all_escalation_resets.3382855967 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 5689411560 ps |
| CPU time | 576.84 seconds |
| Started | Aug 17 07:34:13 PM PDT 24 |
| Finished | Aug 17 07:43:50 PM PDT 24 |
| Peak memory | 650768 kb |
| Host | smart-ac7969b0-db48-408f-86e8-53b8fa4f32d1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3382855967 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_sw_all_escalation_resets.3382855967 |
| Directory | /workspace/48.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909677937 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 3534513628 ps |
| CPU time | 301.92 seconds |
| Started | Aug 17 07:33:59 PM PDT 24 |
| Finished | Aug 17 07:39:01 PM PDT 24 |
| Peak memory | 649780 kb |
| Host | smart-2079e785-688e-48d4-9546-83790d775ea5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909677937 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2909677937 |
| Directory | /workspace/49.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/49.chip_sw_all_escalation_resets.2598349751 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 5893030698 ps |
| CPU time | 663.98 seconds |
| Started | Aug 17 07:33:26 PM PDT 24 |
| Finished | Aug 17 07:44:30 PM PDT 24 |
| Peak memory | 650656 kb |
| Host | smart-575b4ba7-e9be-4d06-b29b-99e3e5bb84e8 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2598349751 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.chip_sw_all_escalation_resets.2598349751 |
| Directory | /workspace/49.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/5.chip_sw_all_escalation_resets.2508484135 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 5187411168 ps |
| CPU time | 437.13 seconds |
| Started | Aug 17 07:34:53 PM PDT 24 |
| Finished | Aug 17 07:42:10 PM PDT 24 |
| Peak memory | 650672 kb |
| Host | smart-220bd0c7-98f2-4555-9fba-8fdfc3e94c21 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2508484135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_all_escalation_resets.2508484135 |
| Directory | /workspace/5.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_all_escalation_resets.209904167 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 4395448000 ps |
| CPU time | 406.66 seconds |
| Started | Aug 17 07:35:24 PM PDT 24 |
| Finished | Aug 17 07:42:11 PM PDT 24 |
| Peak memory | 650508 kb |
| Host | smart-ccbd0613-09cc-45cb-8def-02b5eb77e642 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 209904167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_sw_all_escalation_resets.209904167 |
| Directory | /workspace/52.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2184645461 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 3230581152 ps |
| CPU time | 384.02 seconds |
| Started | Aug 17 07:33:52 PM PDT 24 |
| Finished | Aug 17 07:40:16 PM PDT 24 |
| Peak memory | 649948 kb |
| Host | smart-374005b7-f5a9-47ef-a135-94fc0cfd86ac |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184645461 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 53.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2184645461 |
| Directory | /workspace/53.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/55.chip_sw_all_escalation_resets.2046463891 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 5107238320 ps |
| CPU time | 818.9 seconds |
| Started | Aug 17 07:36:33 PM PDT 24 |
| Finished | Aug 17 07:50:12 PM PDT 24 |
| Peak memory | 650640 kb |
| Host | smart-9cecb3c1-45bb-498c-8ab7-e1b93a3daeb9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2046463891 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 55.chip_sw_all_escalation_resets.2046463891 |
| Directory | /workspace/55.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.162290383 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 3925016096 ps |
| CPU time | 352.76 seconds |
| Started | Aug 17 07:36:20 PM PDT 24 |
| Finished | Aug 17 07:42:13 PM PDT 24 |
| Peak memory | 649488 kb |
| Host | smart-1135dede-4fe7-4967-84c7-5f3a1cbcbd36 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=162290383 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_s w_alert_handler_lpg_sleep_mode_alerts.162290383 |
| Directory | /workspace/59.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/59.chip_sw_all_escalation_resets.3818538073 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 5136133120 ps |
| CPU time | 517.76 seconds |
| Started | Aug 17 07:36:21 PM PDT 24 |
| Finished | Aug 17 07:44:59 PM PDT 24 |
| Peak memory | 650984 kb |
| Host | smart-bcd00633-2d53-4df3-aea8-9bc01efa7f22 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3818538073 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 59.chip_sw_all_escalation_resets.3818538073 |
| Directory | /workspace/59.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_all_escalation_resets.69576999 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 5177886236 ps |
| CPU time | 661.46 seconds |
| Started | Aug 17 07:30:24 PM PDT 24 |
| Finished | Aug 17 07:41:26 PM PDT 24 |
| Peak memory | 651184 kb |
| Host | smart-65ae1823-d698-4925-95e1-73a22d9b7cef |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 69576999 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_all_escalation_resets.69576999 |
| Directory | /workspace/6.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.403610505 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 3368242538 ps |
| CPU time | 318.1 seconds |
| Started | Aug 17 07:35:22 PM PDT 24 |
| Finished | Aug 17 07:40:41 PM PDT 24 |
| Peak memory | 650044 kb |
| Host | smart-b67c1ca1-fdc0-4c8e-8de9-c9acbc80ef93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403610505 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_s w_alert_handler_lpg_sleep_mode_alerts.403610505 |
| Directory | /workspace/62.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/62.chip_sw_all_escalation_resets.3820406273 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 5972857846 ps |
| CPU time | 661.7 seconds |
| Started | Aug 17 07:36:40 PM PDT 24 |
| Finished | Aug 17 07:47:42 PM PDT 24 |
| Peak memory | 650656 kb |
| Host | smart-ed575be2-d38d-4571-bd8d-362792b8307e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3820406273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 62.chip_sw_all_escalation_resets.3820406273 |
| Directory | /workspace/62.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1103327217 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 3506128736 ps |
| CPU time | 419.01 seconds |
| Started | Aug 17 07:36:41 PM PDT 24 |
| Finished | Aug 17 07:43:40 PM PDT 24 |
| Peak memory | 649260 kb |
| Host | smart-8401df78-13af-4286-b106-c4b8d74c59a0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103327217 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1103327217 |
| Directory | /workspace/66.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1975495072 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 3269895100 ps |
| CPU time | 344.76 seconds |
| Started | Aug 17 07:37:30 PM PDT 24 |
| Finished | Aug 17 07:43:15 PM PDT 24 |
| Peak memory | 649652 kb |
| Host | smart-91597452-3aba-4660-9fd6-a329c16c8edd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975495072 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 68.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1975495072 |
| Directory | /workspace/68.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/73.chip_sw_all_escalation_resets.1749103392 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 6082222600 ps |
| CPU time | 572.4 seconds |
| Started | Aug 17 07:35:58 PM PDT 24 |
| Finished | Aug 17 07:45:31 PM PDT 24 |
| Peak memory | 650556 kb |
| Host | smart-35516203-5837-465b-bca1-fe5778258e53 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1749103392 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_sw_all_escalation_resets.1749103392 |
| Directory | /workspace/73.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_all_escalation_resets.1196388720 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 5466780312 ps |
| CPU time | 543.45 seconds |
| Started | Aug 17 07:36:53 PM PDT 24 |
| Finished | Aug 17 07:45:57 PM PDT 24 |
| Peak memory | 650952 kb |
| Host | smart-f3bb603e-9c01-4e75-b266-637444e44dca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1196388720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_sw_all_escalation_resets.1196388720 |
| Directory | /workspace/78.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.470110278 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 3737026260 ps |
| CPU time | 429.7 seconds |
| Started | Aug 17 07:37:59 PM PDT 24 |
| Finished | Aug 17 07:45:08 PM PDT 24 |
| Peak memory | 649608 kb |
| Host | smart-55ccc687-cb1d-43ee-ba03-2004313b1836 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470110278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_s w_alert_handler_lpg_sleep_mode_alerts.470110278 |
| Directory | /workspace/80.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/80.chip_sw_all_escalation_resets.3193046376 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 4091198740 ps |
| CPU time | 473.02 seconds |
| Started | Aug 17 07:39:11 PM PDT 24 |
| Finished | Aug 17 07:47:04 PM PDT 24 |
| Peak memory | 650476 kb |
| Host | smart-c377bab5-1fe8-4114-87ed-d844bd95252f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3193046376 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 80.chip_sw_all_escalation_resets.3193046376 |
| Directory | /workspace/80.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776887421 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 3068569696 ps |
| CPU time | 377.79 seconds |
| Started | Aug 17 07:37:14 PM PDT 24 |
| Finished | Aug 17 07:43:32 PM PDT 24 |
| Peak memory | 649512 kb |
| Host | smart-65de902e-9542-498c-8f27-4122bcbe3608 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776887421 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1776887421 |
| Directory | /workspace/83.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/84.chip_sw_all_escalation_resets.2514333895 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 5014257214 ps |
| CPU time | 443.94 seconds |
| Started | Aug 17 07:37:53 PM PDT 24 |
| Finished | Aug 17 07:45:17 PM PDT 24 |
| Peak memory | 650260 kb |
| Host | smart-6493aa56-f98d-4891-9fff-e2fdde2eaeb7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2514333895 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_sw_all_escalation_resets.2514333895 |
| Directory | /workspace/84.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.765763457 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 4579548300 ps |
| CPU time | 310.76 seconds |
| Started | Aug 17 07:39:58 PM PDT 24 |
| Finished | Aug 17 07:45:09 PM PDT 24 |
| Peak memory | 649848 kb |
| Host | smart-230a1b28-797b-489d-8f56-59caf9d8e4e8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765763457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_s w_alert_handler_lpg_sleep_mode_alerts.765763457 |
| Directory | /workspace/86.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/87.chip_sw_all_escalation_resets.3995112562 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 5443817284 ps |
| CPU time | 566.49 seconds |
| Started | Aug 17 07:38:22 PM PDT 24 |
| Finished | Aug 17 07:47:49 PM PDT 24 |
| Peak memory | 650844 kb |
| Host | smart-a89adf7e-0288-4ba7-a86a-89af2836918b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3995112562 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_sw_all_escalation_resets.3995112562 |
| Directory | /workspace/87.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/88.chip_sw_all_escalation_resets.2686852898 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 5718827132 ps |
| CPU time | 751.78 seconds |
| Started | Aug 17 07:37:10 PM PDT 24 |
| Finished | Aug 17 07:49:42 PM PDT 24 |
| Peak memory | 650720 kb |
| Host | smart-3a523c99-627a-462f-bee3-58d83016134c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2686852898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 88.chip_sw_all_escalation_resets.2686852898 |
| Directory | /workspace/88.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device.918909460 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 2655529196 ps |
| CPU time | 106.2 seconds |
| Started | Aug 17 06:53:38 PM PDT 24 |
| Finished | Aug 17 06:55:24 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-ce96c3fa-e697-4631-9353-41bd87a7a926 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918909460 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_device. 918909460 |
| Directory | /workspace/63.xbar_access_same_device/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3982754438 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 3390424622 ps |
| CPU time | 690.01 seconds |
| Started | Aug 17 07:09:04 PM PDT 24 |
| Finished | Aug 17 07:20:34 PM PDT 24 |
| Peak memory | 609504 kb |
| Host | smart-c6cc08e3-364b-4d0a-aa6f-8f05d6c5a52d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982754438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops.3982754438 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio.651461202 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 3532341150 ps |
| CPU time | 489.23 seconds |
| Started | Aug 17 07:05:23 PM PDT 24 |
| Finished | Aug 17 07:13:32 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-569dce3a-d817-449b-a96f-ff360a9e4ac4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651461202 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.chip_sw_gpio.651461202 |
| Directory | /workspace/0.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_lowpower_cancel.2327846070 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 3853369320 ps |
| CPU time | 471.43 seconds |
| Started | Aug 17 07:10:07 PM PDT 24 |
| Finished | Aug 17 07:17:59 PM PDT 24 |
| Peak memory | 610544 kb |
| Host | smart-56cfa16b-c899-4f09-98e2-2052d1d9360e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327846070 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_pwrmgr_lowpower_cancel.2327846070 |
| Directory | /workspace/0.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.2621897566 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 6092978040 ps |
| CPU time | 381.29 seconds |
| Started | Aug 17 07:06:14 PM PDT 24 |
| Finished | Aug 17 07:12:35 PM PDT 24 |
| Peak memory | 611604 kb |
| Host | smart-2b78c0eb-3740-4393-ad9f-d7fe7a771547 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=2621897566 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.2621897566 |
| Directory | /workspace/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio.876671518 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 4306705640 ps |
| CPU time | 568.06 seconds |
| Started | Aug 17 07:20:48 PM PDT 24 |
| Finished | Aug 17 07:30:17 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-72e9ca5b-11ef-49a1-818d-7d7be1b81c1e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876671518 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_gpio_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.chip_sw_gpio.876671518 |
| Directory | /workspace/2.chip_sw_gpio/latest |
| Test location | /workspace/coverage/default/50.chip_sw_all_escalation_resets.1785419207 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 5411103484 ps |
| CPU time | 685.19 seconds |
| Started | Aug 17 07:34:13 PM PDT 24 |
| Finished | Aug 17 07:45:39 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-f83ad894-531b-485d-99c9-4b85276bdaa2 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1785419207 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_sw_all_escalation_resets.1785419207 |
| Directory | /workspace/50.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_same_csr_outstanding.3953630139 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 16489869116 ps |
| CPU time | 2110.28 seconds |
| Started | Aug 17 06:48:18 PM PDT 24 |
| Finished | Aug 17 07:23:28 PM PDT 24 |
| Peak memory | 593340 kb |
| Host | smart-3bb0db6e-95b0-4ebd-81f7-17e875bbf213 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953630139 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 19.chip_same_csr_outstanding.3953630139 |
| Directory | /workspace/19.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2774480180 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 14334758760 ps |
| CPU time | 5091.63 seconds |
| Started | Aug 17 07:07:11 PM PDT 24 |
| Finished | Aug 17 08:32:04 PM PDT 24 |
| Peak memory | 610556 kb |
| Host | smart-96af8af6-d3f8-430c-8d72-9d2d3e5d2e2a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27744 80180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_otbn.2774480180 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2009081526 |
| Short name | T1345 |
| Test name | |
| Test status | |
| Simulation time | 7276639395 ps |
| CPU time | 694.28 seconds |
| Started | Aug 17 07:06:35 PM PDT 24 |
| Finished | Aug 17 07:18:10 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-a1452ab2-91b1-4fd8-a9cb-4126f2dfce78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009081526 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_full_aon_reset.2009081526 |
| Directory | /workspace/0.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1359244189 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2730605648 ps |
| CPU time | 277.56 seconds |
| Started | Aug 17 07:09:46 PM PDT 24 |
| Finished | Aug 17 07:14:25 PM PDT 24 |
| Peak memory | 613552 kb |
| Host | smart-0ddaceeb-35ae-4b8c-a5a6-384192962473 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359244189 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_inputs.1359244189 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2401861253 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 24899463808 ps |
| CPU time | 1633.76 seconds |
| Started | Aug 17 07:08:24 PM PDT 24 |
| Finished | Aug 17 07:35:38 PM PDT 24 |
| Peak memory | 611664 kb |
| Host | smart-823c7999-6627-4fa7-83b6-9b4c89e98d34 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2401861253 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2401861253 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_tl_errors.2871753011 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3899584690 ps |
| CPU time | 260.27 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 06:51:53 PM PDT 24 |
| Peak memory | 603820 kb |
| Host | smart-d5888612-4be3-4924-8e3c-126598b09629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871753011 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_tl_errors.2871753011 |
| Directory | /workspace/1.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all.811910739 |
| Short name | T2452 |
| Test name | |
| Test status | |
| Simulation time | 2324365154 ps |
| CPU time | 164.99 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:50:48 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-cbeb07f0-4e6f-487f-a347-b5b273ec320b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811910739 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all.811910739 |
| Directory | /workspace/13.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device_slow_rsp.1465398104 |
| Short name | T2447 |
| Test name | |
| Test status | |
| Simulation time | 121685872283 ps |
| CPU time | 2233.16 seconds |
| Started | Aug 17 06:48:00 PM PDT 24 |
| Finished | Aug 17 07:25:13 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-997d1256-d530-48cb-8e99-17b9a275c265 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465398104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_ device_slow_rsp.1465398104 |
| Directory | /workspace/15.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device_slow_rsp.1343950971 |
| Short name | T2089 |
| Test name | |
| Test status | |
| Simulation time | 136322265480 ps |
| CPU time | 2587.81 seconds |
| Started | Aug 17 06:48:52 PM PDT 24 |
| Finished | Aug 17 07:32:00 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-f3dafc61-0afe-4f62-931c-44c364cc0ac3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343950971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_ device_slow_rsp.1343950971 |
| Directory | /workspace/21.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_error.2398345995 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2355280206 ps |
| CPU time | 186.65 seconds |
| Started | Aug 17 06:55:30 PM PDT 24 |
| Finished | Aug 17 06:58:37 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-ee50674d-f94f-448b-92bf-72365aa70c2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398345995 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_with_error.2398345995 |
| Directory | /workspace/78.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.3291653538 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 4776910792 ps |
| CPU time | 962.84 seconds |
| Started | Aug 17 07:06:04 PM PDT 24 |
| Finished | Aug 17 07:22:08 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-d64e1724-3b3a-4493-9132-fff743678e97 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291653538 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx2.3291653538 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pattgen_ios.418664139 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 2799524262 ps |
| CPU time | 235.6 seconds |
| Started | Aug 17 07:13:40 PM PDT 24 |
| Finished | Aug 17 07:17:36 PM PDT 24 |
| Peak memory | 610564 kb |
| Host | smart-c5e6e37b-b640-47e1-b9c8-fcc1d90c94b0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418664139 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pattgen_ios.418664139 |
| Directory | /workspace/1.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_lowpower_cancel.1665760267 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 3897715040 ps |
| CPU time | 452.43 seconds |
| Started | Aug 17 07:26:13 PM PDT 24 |
| Finished | Aug 17 07:33:46 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-77319fb0-a2e4-4f08-a303-eea3039127d4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665760267 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_pwrmgr_lowpower_cancel.1665760267 |
| Directory | /workspace/2.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2447803298 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 19945545508 ps |
| CPU time | 515.67 seconds |
| Started | Aug 17 07:08:54 PM PDT 24 |
| Finished | Aug 17 07:17:31 PM PDT 24 |
| Peak memory | 619428 kb |
| Host | smart-286bfbd4-68b1-4530-ad8f-61e5cc453d2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2447803298 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2447803298 |
| Directory | /workspace/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.2257414984 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 3096859104 ps |
| CPU time | 266.33 seconds |
| Started | Aug 17 07:05:24 PM PDT 24 |
| Finished | Aug 17 07:09:51 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-7796b79b-9797-4d04-875d-d923e0245bec |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257414984 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_spi_host_tx_rx.2257414984 |
| Directory | /workspace/0.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_rv_dm_lc_disabled.1152240705 |
| Short name | T1925 |
| Test name | |
| Test status | |
| Simulation time | 13647357894 ps |
| CPU time | 547.17 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:56:38 PM PDT 24 |
| Peak memory | 591184 kb |
| Host | smart-0d9c5da3-bc40-4fd9-973f-d5a3e4d36ad0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152240705 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_rv_dm_lc_disabled.1152240705 |
| Directory | /workspace/0.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_hw_reset.3326582886 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 4708871816 ps |
| CPU time | 268.49 seconds |
| Started | Aug 17 06:47:28 PM PDT 24 |
| Finished | Aug 17 06:51:57 PM PDT 24 |
| Peak memory | 662572 kb |
| Host | smart-e45ae932-eba6-44e8-b381-d7a7f6bb4075 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326582886 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_hw_r eset.3326582886 |
| Directory | /workspace/2.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.3121176905 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4933874452 ps |
| CPU time | 943.54 seconds |
| Started | Aug 17 07:08:35 PM PDT 24 |
| Finished | Aug 17 07:24:19 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-82310993-2494-409b-8bb0-55b0cdd682dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3121176905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_clkoff.3121176905 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1008273200 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 13307756371 ps |
| CPU time | 1120.27 seconds |
| Started | Aug 17 07:12:32 PM PDT 24 |
| Finished | Aug 17 07:31:13 PM PDT 24 |
| Peak memory | 625472 kb |
| Host | smart-eca01fda-4366-45d4-9fc8-9e3db19ced4b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=1008273200 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_external_clk_src_for_lc.1008273200 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1649898943 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 4093234200 ps |
| CPU time | 428.67 seconds |
| Started | Aug 17 07:09:52 PM PDT 24 |
| Finished | Aug 17 07:17:01 PM PDT 24 |
| Peak memory | 611384 kb |
| Host | smart-15c3383a-263b-48f0-9a5d-0885fe63fb64 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1649898943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_program_error.1649898943 |
| Directory | /workspace/0.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2671977538 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 47129974733 ps |
| CPU time | 5002.74 seconds |
| Started | Aug 17 07:06:33 PM PDT 24 |
| Finished | Aug 17 08:29:57 PM PDT 24 |
| Peak memory | 625024 kb |
| Host | smart-fa82bf1e-2037-411c-9060-117a3e061de3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671977538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_rma.2671977538 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3753536472 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 24732751127 ps |
| CPU time | 3697.45 seconds |
| Started | Aug 17 07:10:27 PM PDT 24 |
| Finished | Aug 17 08:12:05 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-1bc6fc59-6ac3-47f9-9050-ef532f5de549 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753536472 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.3753536472 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3027207419 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 7569715618 ps |
| CPU time | 538.92 seconds |
| Started | Aug 17 07:06:53 PM PDT 24 |
| Finished | Aug 17 07:15:52 PM PDT 24 |
| Peak memory | 617060 kb |
| Host | smart-4a6b31a5-5f10-446b-9b80-e53a48b641b5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3027207419 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3027207419 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1611787943 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 2457101165 ps |
| CPU time | 299.46 seconds |
| Started | Aug 17 07:22:57 PM PDT 24 |
| Finished | Aug 17 07:27:57 PM PDT 24 |
| Peak memory | 623448 kb |
| Host | smart-f48d9f4b-ec7f-4717-be42-790925d02110 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_csr_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611787943 -assert nopost proc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_csr_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_vendor_test_csr_access.1611787943 |
| Directory | /workspace/2.chip_sw_otp_ctrl_vendor_test_csr_access/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_tl_errors.77741650 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 3800262140 ps |
| CPU time | 225.3 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 603816 kb |
| Host | smart-175391e7-0e17-4bf4-b7ce-01c2cef8bea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77741650 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_tl_errors.77741650 |
| Directory | /workspace/10.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_reset_error.4180564015 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 13201820278 ps |
| CPU time | 597.24 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:57:30 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-447ec7cc-663f-4a76-9b46-0e9f522c6427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180564015 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all _with_reset_error.4180564015 |
| Directory | /workspace/2.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_error.2510854585 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 13859406993 ps |
| CPU time | 522.59 seconds |
| Started | Aug 17 06:49:43 PM PDT 24 |
| Finished | Aug 17 06:58:26 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-84bfdf6a-6f60-47b7-894d-b0b421a44586 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2510854585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all_with_error.2510854585 |
| Directory | /workspace/30.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2530078326 |
| Short name | T1457 |
| Test name | |
| Test status | |
| Simulation time | 811232683 ps |
| CPU time | 72.1 seconds |
| Started | Aug 17 06:50:15 PM PDT 24 |
| Finished | Aug 17 06:51:27 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-91871db0-f7cc-4b3c-a900-0b8d9e527a69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2530078326 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all_with_error.2530078326 |
| Directory | /workspace/34.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_error.322751486 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 9295462831 ps |
| CPU time | 314.04 seconds |
| Started | Aug 17 06:51:06 PM PDT 24 |
| Finished | Aug 17 06:56:20 PM PDT 24 |
| Peak memory | 576012 kb |
| Host | smart-a6d506b7-d385-469e-b38c-f421a0cfef1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=322751486 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all_with_error.322751486 |
| Directory | /workspace/43.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_error.3236511590 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 14456142836 ps |
| CPU time | 521.38 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 07:01:28 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-1a0a024c-cf11-4f74-84f6-3e0b8bbf5e06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236511590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all_with_error.3236511590 |
| Directory | /workspace/55.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_reset_error.1854080199 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 1179497921 ps |
| CPU time | 297.28 seconds |
| Started | Aug 17 06:52:48 PM PDT 24 |
| Finished | Aug 17 06:57:45 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-2e5cfafb-7be5-4b8a-9314-248c7524cbd3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854080199 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_al l_with_reset_error.1854080199 |
| Directory | /workspace/56.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_error.1262958954 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 3978030830 ps |
| CPU time | 245.84 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:59:55 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-1e5b61c8-1ece-4470-a3ca-70f24ad996d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262958954 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all_with_error.1262958954 |
| Directory | /workspace/81.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_reset_error.1264829764 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 3526091288 ps |
| CPU time | 379.98 seconds |
| Started | Aug 17 06:56:10 PM PDT 24 |
| Finished | Aug 17 07:02:30 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-501a01d3-17ac-429a-87a1-8cb0b34af0f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264829764 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_al l_with_reset_error.1264829764 |
| Directory | /workspace/84.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_error.3312455253 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 7262399815 ps |
| CPU time | 227.61 seconds |
| Started | Aug 17 06:57:31 PM PDT 24 |
| Finished | Aug 17 07:01:19 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-0e567cfb-3fd7-49e1-a6b8-9d8af6da5884 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3312455253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_with_error.3312455253 |
| Directory | /workspace/96.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.3800360393 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 3255922618 ps |
| CPU time | 314.27 seconds |
| Started | Aug 17 07:10:26 PM PDT 24 |
| Finished | Aug 17 07:15:40 PM PDT 24 |
| Peak memory | 609992 kb |
| Host | smart-b66bdd26-1215-4cad-8b6e-0610907b5fb1 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800360393 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en_reduced_freq.3800360393 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.50507073 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 5253948744 ps |
| CPU time | 1045.73 seconds |
| Started | Aug 17 07:06:01 PM PDT 24 |
| Finished | Aug 17 07:23:28 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-451ca7d1-a649-4174-b4b3-f97cdf593b0c |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50507073 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa ult.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx.50507073 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1907786416 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 4762786734 ps |
| CPU time | 888.26 seconds |
| Started | Aug 17 07:05:27 PM PDT 24 |
| Finished | Aug 17 07:20:15 PM PDT 24 |
| Peak memory | 609672 kb |
| Host | smart-9d79ad1e-2347-4b9d-9b03-9c88b025aab4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19077 86416 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_nmi_irq.1907786416 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_plic_all_irqs_10.4150621040 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 3671378560 ps |
| CPU time | 692.4 seconds |
| Started | Aug 17 07:15:03 PM PDT 24 |
| Finished | Aug 17 07:26:36 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-5fcdfa5b-6b6c-43b5-8cbf-62b704a3e70a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_all_irqs_test_10:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4150621040 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_plic_all_irqs_10.4150621040 |
| Directory | /workspace/1.chip_plic_all_irqs_10/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3595989887 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 4281258050 ps |
| CPU time | 682.21 seconds |
| Started | Aug 17 07:10:34 PM PDT 24 |
| Finished | Aug 17 07:21:56 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-cfd7f78d-3760-4fd0-8f37-00316604a67d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595989887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops.3595989887 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.1663438445 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 3639046144 ps |
| CPU time | 513.18 seconds |
| Started | Aug 17 07:20:35 PM PDT 24 |
| Finished | Aug 17 07:29:09 PM PDT 24 |
| Peak memory | 611476 kb |
| Host | smart-0b72ddea-6732-4a94-8dc3-687f04d20603 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663438445 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_i2c_device_tx_rx.1663438445 |
| Directory | /workspace/2.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3005503281 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 11171472890 ps |
| CPU time | 1508.64 seconds |
| Started | Aug 17 07:22:22 PM PDT 24 |
| Finished | Aug 17 07:47:31 PM PDT 24 |
| Peak memory | 611504 kb |
| Host | smart-820c6ef3-c4e8-45ad-804c-9ab1dc1dc488 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=3005503281 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_alert_info.3005503281 |
| Directory | /workspace/2.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_irq.2652663820 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 4103756544 ps |
| CPU time | 404.23 seconds |
| Started | Aug 17 07:08:34 PM PDT 24 |
| Finished | Aug 17 07:15:19 PM PDT 24 |
| Peak memory | 610436 kb |
| Host | smart-525abeac-b71e-46a9-b899-7352b7ff898e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652663820 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_irq.2652663820 |
| Directory | /workspace/0.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_boot_mode.490261027 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 2939744928 ps |
| CPU time | 673.08 seconds |
| Started | Aug 17 07:08:56 PM PDT 24 |
| Finished | Aug 17 07:20:10 PM PDT 24 |
| Peak memory | 610648 kb |
| Host | smart-f3ae404a-7fe2-4049-b0b9-8d96396ef0d9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490261027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_b oot_mode.490261027 |
| Directory | /workspace/0.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1195621945 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2931885368 ps |
| CPU time | 242.75 seconds |
| Started | Aug 17 07:06:32 PM PDT 24 |
| Finished | Aug 17 07:10:35 PM PDT 24 |
| Peak memory | 639356 kb |
| Host | smart-46f00509-33b2-4d68-8fcd-e75b93b364a8 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195621945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_lockstep_glitch.1195621945 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.4249608191 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 93266633627 ps |
| CPU time | 13233.6 seconds |
| Started | Aug 17 07:17:57 PM PDT 24 |
| Finished | Aug 17 10:58:33 PM PDT 24 |
| Peak memory | 610936 kb |
| Host | smart-137c765e-5644-4d24-8fc9-43288ac613d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=4249608191 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_edn_concurrency_reduced_freq.4249608191 |
| Directory | /workspace/1.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_fuse_en_sw_app_read_test.1648213818 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 4537244084 ps |
| CPU time | 350.17 seconds |
| Started | Aug 17 07:06:52 PM PDT 24 |
| Finished | Aug 17 07:12:42 PM PDT 24 |
| Peak memory | 610452 kb |
| Host | smart-edc388ef-3844-494f-891a-fb46fcad05c7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16482 13818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_fuse_en_sw_app_read_test.1648213818 |
| Directory | /workspace/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1874760926 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 23743228816 ps |
| CPU time | 5632.58 seconds |
| Started | Aug 17 07:14:46 PM PDT 24 |
| Finished | Aug 17 08:48:39 PM PDT 24 |
| Peak memory | 611248 kb |
| Host | smart-f91ebf6d-0268-4d8c-80e1-26f1af28ce0c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1874760926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.1874760926 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_aliasing.3001716153 |
| Short name | T2236 |
| Test name | |
| Test status | |
| Simulation time | 67563712300 ps |
| CPU time | 9863.98 seconds |
| Started | Aug 17 06:47:14 PM PDT 24 |
| Finished | Aug 17 09:31:40 PM PDT 24 |
| Peak memory | 634872 kb |
| Host | smart-3ecc7261-be48-4e4e-8840-c735a9b0735d |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001716153 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 0.chip_csr_aliasing.3001716153 |
| Directory | /workspace/0.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_bit_bash.1890275503 |
| Short name | T1928 |
| Test name | |
| Test status | |
| Simulation time | 43957282474 ps |
| CPU time | 4393.04 seconds |
| Started | Aug 17 06:47:15 PM PDT 24 |
| Finished | Aug 17 08:00:29 PM PDT 24 |
| Peak memory | 598748 kb |
| Host | smart-cef13e72-64d5-4aae-9200-d80dd0ef5c38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1890275503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 0.chip_csr_bit_bash.1890275503 |
| Directory | /workspace/0.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.3703302119 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 7494344657 ps |
| CPU time | 372.18 seconds |
| Started | Aug 17 06:47:27 PM PDT 24 |
| Finished | Aug 17 06:53:40 PM PDT 24 |
| Peak memory | 662664 kb |
| Host | smart-66a074c8-16d6-43b2-a79f-778809c5585e |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703302119 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_ common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_hw_r eset.3703302119 |
| Directory | /workspace/0.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_mem_rw_with_rand_reset.2059547865 |
| Short name | T1755 |
| Test name | |
| Test status | |
| Simulation time | 8611504370 ps |
| CPU time | 854.72 seconds |
| Started | Aug 17 06:47:18 PM PDT 24 |
| Finished | Aug 17 07:01:33 PM PDT 24 |
| Peak memory | 653080 kb |
| Host | smart-276a4d9f-5c1b-4e90-b911-58d61d6d61c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059547865 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 0.chip_csr_mem_rw_with_rand_reset.2059547865 |
| Directory | /workspace/0.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_csr_rw.2847247442 |
| Short name | T1876 |
| Test name | |
| Test status | |
| Simulation time | 6187900270 ps |
| CPU time | 587.7 seconds |
| Started | Aug 17 06:47:27 PM PDT 24 |
| Finished | Aug 17 06:57:15 PM PDT 24 |
| Peak memory | 599336 kb |
| Host | smart-5fb95c34-ceb5-4676-95cd-b8b18e1bd657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847247442 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_csr_rw.2847247442 |
| Directory | /workspace/0.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_prim_tl_access.2676307457 |
| Short name | T1717 |
| Test name | |
| Test status | |
| Simulation time | 4405572258 ps |
| CPU time | 120.41 seconds |
| Started | Aug 17 06:47:29 PM PDT 24 |
| Finished | Aug 17 06:49:29 PM PDT 24 |
| Peak memory | 589468 kb |
| Host | smart-f2f20da8-296a-464e-bb57-e0af961145b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676307457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.chip_prim_tl_access.2676307457 |
| Directory | /workspace/0.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/0.chip_same_csr_outstanding.1685876724 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 14630989665 ps |
| CPU time | 1807.55 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 07:17:39 PM PDT 24 |
| Peak memory | 593392 kb |
| Host | smart-3120c884-b849-4f46-99cd-be6a6ddc1b9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685876724 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 0.chip_same_csr_outstanding.1685876724 |
| Directory | /workspace/0.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device.2122805826 |
| Short name | T2175 |
| Test name | |
| Test status | |
| Simulation time | 3432937093 ps |
| CPU time | 133.32 seconds |
| Started | Aug 17 06:47:27 PM PDT 24 |
| Finished | Aug 17 06:49:41 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-f52beed0-3457-45cb-916a-ad88345c14f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122805826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_device. 2122805826 |
| Directory | /workspace/0.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_access_same_device_slow_rsp.2993422540 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 96896629352 ps |
| CPU time | 1769.48 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 07:17:04 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-589d4793-8875-4e2f-aa37-3be594bc8f8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993422540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_access_same_d evice_slow_rsp.2993422540 |
| Directory | /workspace/0.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_and_unmapped_addr.425562348 |
| Short name | T2102 |
| Test name | |
| Test status | |
| Simulation time | 225371916 ps |
| CPU time | 10.54 seconds |
| Started | Aug 17 06:47:35 PM PDT 24 |
| Finished | Aug 17 06:47:46 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-d6eaa747-7cb0-4042-8ee5-76d2ecb19417 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425562348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_and_unmapped_addr. 425562348 |
| Directory | /workspace/0.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_error_random.1626068531 |
| Short name | T1727 |
| Test name | |
| Test status | |
| Simulation time | 1233348813 ps |
| CPU time | 40.57 seconds |
| Started | Aug 17 06:47:35 PM PDT 24 |
| Finished | Aug 17 06:48:15 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-8ee49b18-cd2c-4b40-80f6-f04590d42577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626068531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_error_random.1626068531 |
| Directory | /workspace/0.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random.3617849871 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 502974331 ps |
| CPU time | 39.1 seconds |
| Started | Aug 17 06:47:27 PM PDT 24 |
| Finished | Aug 17 06:48:06 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-f1aaefdc-981e-4e91-95cf-7c87d3cebb04 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617849871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random.3617849871 |
| Directory | /workspace/0.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_large_delays.625209162 |
| Short name | T1531 |
| Test name | |
| Test status | |
| Simulation time | 79235250497 ps |
| CPU time | 773.16 seconds |
| Started | Aug 17 06:47:26 PM PDT 24 |
| Finished | Aug 17 07:00:19 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-672fb825-2ae0-40df-8c51-2c14ed18cbfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=625209162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_large_delays.625209162 |
| Directory | /workspace/0.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_slow_rsp.1546735760 |
| Short name | T2868 |
| Test name | |
| Test status | |
| Simulation time | 4107422772 ps |
| CPU time | 63.9 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 06:48:36 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-3b6f0d6b-dd3f-4c89-a5f4-567fe173f247 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546735760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_slow_rsp.1546735760 |
| Directory | /workspace/0.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_random_zero_delays.1466154020 |
| Short name | T1973 |
| Test name | |
| Test status | |
| Simulation time | 300386781 ps |
| CPU time | 22.68 seconds |
| Started | Aug 17 06:47:24 PM PDT 24 |
| Finished | Aug 17 06:47:47 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-fe31596d-3fb4-4cb1-b90c-2fcd05156a1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1466154020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_random_zero_dela ys.1466154020 |
| Directory | /workspace/0.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_same_source.560180642 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 71662893 ps |
| CPU time | 7.68 seconds |
| Started | Aug 17 06:47:24 PM PDT 24 |
| Finished | Aug 17 06:47:32 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-5f8e34f0-7734-40af-ad21-1acdfa36dd97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560180642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_same_source.560180642 |
| Directory | /workspace/0.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke.2927652791 |
| Short name | T2257 |
| Test name | |
| Test status | |
| Simulation time | 40783208 ps |
| CPU time | 5.46 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:47:38 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-7e6dcb23-6e7b-4cd5-ac91-df4614c8b523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927652791 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke.2927652791 |
| Directory | /workspace/0.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_large_delays.2016415493 |
| Short name | T1472 |
| Test name | |
| Test status | |
| Simulation time | 6619131677 ps |
| CPU time | 67 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 06:48:41 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-f95a19d5-e7e5-481d-a2fa-12d757482748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016415493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_large_delays.2016415493 |
| Directory | /workspace/0.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.2889934309 |
| Short name | T2143 |
| Test name | |
| Test status | |
| Simulation time | 3946343456 ps |
| CPU time | 69.07 seconds |
| Started | Aug 17 06:47:15 PM PDT 24 |
| Finished | Aug 17 06:48:24 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-2ec1272b-2fe8-4f23-9516-d8435e4410e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889934309 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_slow_rsp.2889934309 |
| Directory | /workspace/0.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.3597842443 |
| Short name | T2704 |
| Test name | |
| Test status | |
| Simulation time | 41691457 ps |
| CPU time | 5.87 seconds |
| Started | Aug 17 06:47:20 PM PDT 24 |
| Finished | Aug 17 06:47:26 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-823107f0-719d-420f-a31a-b9e2a544bc91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597842443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_smoke_zero_delays .3597842443 |
| Directory | /workspace/0.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all.1432001462 |
| Short name | T2666 |
| Test name | |
| Test status | |
| Simulation time | 18159806224 ps |
| CPU time | 613.08 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 06:57:43 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-62251edb-f735-4df6-a3b9-904bc5444c99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432001462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all.1432001462 |
| Directory | /workspace/0.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_error.3571772283 |
| Short name | T2568 |
| Test name | |
| Test status | |
| Simulation time | 4052967351 ps |
| CPU time | 128.09 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:49:52 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-69a58307-406b-4ab0-9579-e6ecf4a30b3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571772283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_with_error.3571772283 |
| Directory | /workspace/0.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_rand_reset.2250084764 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 368219556 ps |
| CPU time | 129.79 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:49:53 PM PDT 24 |
| Peak memory | 576212 kb |
| Host | smart-69549757-2b54-4052-99a2-996c66dab012 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250084764 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all_ with_rand_reset.2250084764 |
| Directory | /workspace/0.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_stress_all_with_reset_error.4221244408 |
| Short name | T2300 |
| Test name | |
| Test status | |
| Simulation time | 1303102372 ps |
| CPU time | 237.98 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:51:29 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-7da7e794-7a83-4da5-9add-70a4546567f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4221244408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_stress_all _with_reset_error.4221244408 |
| Directory | /workspace/0.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/0.xbar_unmapped_addr.3324543258 |
| Short name | T1450 |
| Test name | |
| Test status | |
| Simulation time | 232814916 ps |
| CPU time | 24.42 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:47:58 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-d1ee29c5-0c29-4eae-b03f-0f3f39c29d82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3324543258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.xbar_unmapped_addr.3324543258 |
| Directory | /workspace/0.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_aliasing.850663971 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 44315328560 ps |
| CPU time | 6380.87 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 08:33:53 PM PDT 24 |
| Peak memory | 598032 kb |
| Host | smart-a1034b90-b9b8-4825-808e-962ff5f328dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850663971 -assert nopostproc +UVM_TESTNAME=chip_b ase_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/n ull -cm_name 1.chip_csr_aliasing.850663971 |
| Directory | /workspace/1.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_bit_bash.2843671510 |
| Short name | T1422 |
| Test name | |
| Test status | |
| Simulation time | 11856325130 ps |
| CPU time | 1384.94 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 07:10:36 PM PDT 24 |
| Peak memory | 597700 kb |
| Host | smart-906c1fc1-f751-4747-a984-e3271aacf9ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843671510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 1.chip_csr_bit_bash.2843671510 |
| Directory | /workspace/1.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_mem_rw_with_rand_reset.2213302048 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 8099449970 ps |
| CPU time | 487.48 seconds |
| Started | Aug 17 06:47:25 PM PDT 24 |
| Finished | Aug 17 06:55:33 PM PDT 24 |
| Peak memory | 638696 kb |
| Host | smart-7fd3b3fb-2674-4f7f-853a-1a6995125b0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2213302048 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 1.chip_csr_mem_rw_with_rand_reset.2213302048 |
| Directory | /workspace/1.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_csr_rw.79521497 |
| Short name | T2787 |
| Test name | |
| Test status | |
| Simulation time | 5833663682 ps |
| CPU time | 529.07 seconds |
| Started | Aug 17 06:47:36 PM PDT 24 |
| Finished | Aug 17 06:56:25 PM PDT 24 |
| Peak memory | 599048 kb |
| Host | smart-964e3408-7d79-4dd5-a9c6-00a93634c57f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79521497 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_csr_rw.79521497 |
| Directory | /workspace/1.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_prim_tl_access.4210212559 |
| Short name | T2752 |
| Test name | |
| Test status | |
| Simulation time | 6921868670 ps |
| CPU time | 350.22 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 06:53:25 PM PDT 24 |
| Peak memory | 589460 kb |
| Host | smart-e3b0f594-4f29-4fdc-810f-792a8bb945ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4210212559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_prim_tl_access.4210212559 |
| Directory | /workspace/1.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_rv_dm_lc_disabled.2358830370 |
| Short name | T1916 |
| Test name | |
| Test status | |
| Simulation time | 14106913630 ps |
| CPU time | 468.11 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:55:19 PM PDT 24 |
| Peak memory | 591180 kb |
| Host | smart-d201b6ce-4fbb-45af-ab95-5d9d3458bafd |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358830370 -assert nopostproc +UVM_TESTNAME=chip_base_t est +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_lc_disabled.2358830370 |
| Directory | /workspace/1.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/1.chip_same_csr_outstanding.8347940 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 17037669407 ps |
| CPU time | 1631.36 seconds |
| Started | Aug 17 06:47:29 PM PDT 24 |
| Finished | Aug 17 07:14:40 PM PDT 24 |
| Peak memory | 593340 kb |
| Host | smart-1e6155cd-b6dd-42f8-ab46-610e4845862c |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8347940 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_ log /dev/null -cm_name 1.chip_same_csr_outstanding.8347940 |
| Directory | /workspace/1.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device.3781596602 |
| Short name | T2347 |
| Test name | |
| Test status | |
| Simulation time | 1841075574 ps |
| CPU time | 86.19 seconds |
| Started | Aug 17 06:47:27 PM PDT 24 |
| Finished | Aug 17 06:48:53 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-8d130d0f-439d-481b-9e81-c675fb6f3a95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781596602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_device. 3781596602 |
| Directory | /workspace/1.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_access_same_device_slow_rsp.384244872 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 102316350391 ps |
| CPU time | 1828.97 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 07:18:01 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-e71e8eb6-f4ad-4dcc-b0b0-2a50f2c3f4d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384244872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_access_same_de vice_slow_rsp.384244872 |
| Directory | /workspace/1.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_and_unmapped_addr.1801802153 |
| Short name | T1351 |
| Test name | |
| Test status | |
| Simulation time | 60948397 ps |
| CPU time | 5.24 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:47:36 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-c497e5a4-654c-47c2-ae73-3d653380df09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801802153 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_and_unmapped_addr .1801802153 |
| Directory | /workspace/1.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_error_random.2080095668 |
| Short name | T2913 |
| Test name | |
| Test status | |
| Simulation time | 507537047 ps |
| CPU time | 18.43 seconds |
| Started | Aug 17 06:47:36 PM PDT 24 |
| Finished | Aug 17 06:47:55 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c958b426-e043-4567-bc16-7687d2c893fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080095668 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_error_random.2080095668 |
| Directory | /workspace/1.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random.105486955 |
| Short name | T2777 |
| Test name | |
| Test status | |
| Simulation time | 106550883 ps |
| CPU time | 10.96 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 06:47:45 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-c7eb77d3-b4b2-46e4-aec7-b1c44bc12ef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=105486955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random.105486955 |
| Directory | /workspace/1.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_large_delays.2352759092 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 75378804081 ps |
| CPU time | 733.75 seconds |
| Started | Aug 17 06:47:29 PM PDT 24 |
| Finished | Aug 17 06:59:43 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-23606ee0-1cbb-4670-8bde-66b43127517c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352759092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_large_delays.2352759092 |
| Directory | /workspace/1.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_slow_rsp.2655598715 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 44329103101 ps |
| CPU time | 669.27 seconds |
| Started | Aug 17 06:47:29 PM PDT 24 |
| Finished | Aug 17 06:58:39 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-61cdb6f8-e3d1-4424-9135-15e06917c211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655598715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_slow_rsp.2655598715 |
| Directory | /workspace/1.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_random_zero_delays.3471520567 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 309133337 ps |
| CPU time | 27.01 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:47:58 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-b25e00b3-8b28-48fb-97ff-77e591399f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471520567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_random_zero_dela ys.3471520567 |
| Directory | /workspace/1.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_same_source.1044679930 |
| Short name | T1935 |
| Test name | |
| Test status | |
| Simulation time | 331018722 ps |
| CPU time | 24.93 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:47:56 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-212b807f-288b-40e7-90b0-94f5680fd600 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044679930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_same_source.1044679930 |
| Directory | /workspace/1.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke.851963550 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 44233844 ps |
| CPU time | 6.23 seconds |
| Started | Aug 17 06:47:35 PM PDT 24 |
| Finished | Aug 17 06:47:41 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-a5385ecf-0a35-40d1-99b6-48880a8cb2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851963550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke.851963550 |
| Directory | /workspace/1.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3423954903 |
| Short name | T1695 |
| Test name | |
| Test status | |
| Simulation time | 7452760855 ps |
| CPU time | 77.02 seconds |
| Started | Aug 17 06:47:37 PM PDT 24 |
| Finished | Aug 17 06:48:54 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-ad9ca502-aa91-43b9-bd42-2efc3f224e01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423954903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_large_delays.3423954903 |
| Directory | /workspace/1.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_slow_rsp.440753967 |
| Short name | T1371 |
| Test name | |
| Test status | |
| Simulation time | 4205066455 ps |
| CPU time | 69.73 seconds |
| Started | Aug 17 06:47:37 PM PDT 24 |
| Finished | Aug 17 06:48:47 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-2b910b89-d8ad-4da5-939d-3d031dc7cd2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440753967 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_slow_rsp.440753967 |
| Directory | /workspace/1.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_smoke_zero_delays.334201446 |
| Short name | T1433 |
| Test name | |
| Test status | |
| Simulation time | 47062741 ps |
| CPU time | 6.69 seconds |
| Started | Aug 17 06:47:27 PM PDT 24 |
| Finished | Aug 17 06:47:34 PM PDT 24 |
| Peak memory | 574080 kb |
| Host | smart-f3e0e411-004b-4a6a-aec9-792868b0d554 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334201446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_smoke_zero_delays. 334201446 |
| Directory | /workspace/1.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all.505640098 |
| Short name | T1487 |
| Test name | |
| Test status | |
| Simulation time | 1869190643 ps |
| CPU time | 64.37 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 06:48:37 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a64da531-7a45-4106-b32a-54c8d5af64c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505640098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all.505640098 |
| Directory | /workspace/1.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_error.76739295 |
| Short name | T2111 |
| Test name | |
| Test status | |
| Simulation time | 4612008374 ps |
| CPU time | 146.59 seconds |
| Started | Aug 17 06:47:26 PM PDT 24 |
| Finished | Aug 17 06:49:52 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-c2face03-9fde-493f-b37c-86c850f972d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76739295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_with_error.76739295 |
| Directory | /workspace/1.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_rand_reset.622804819 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2834748006 ps |
| CPU time | 116.49 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:49:28 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-830ef1a8-881e-4468-aaab-b8f466ebd0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622804819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all_w ith_rand_reset.622804819 |
| Directory | /workspace/1.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_stress_all_with_reset_error.4039867920 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 7883655340 ps |
| CPU time | 759.47 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 07:00:10 PM PDT 24 |
| Peak memory | 595956 kb |
| Host | smart-609dd9af-27f8-47c1-902e-c460c8c5da0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039867920 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_stress_all _with_reset_error.4039867920 |
| Directory | /workspace/1.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/1.xbar_unmapped_addr.594723290 |
| Short name | T2887 |
| Test name | |
| Test status | |
| Simulation time | 283947090 ps |
| CPU time | 35.19 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 06:48:05 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-4ed19804-3416-4042-a9b3-1656d8ea3d11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594723290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.xbar_unmapped_addr.594723290 |
| Directory | /workspace/1.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_mem_rw_with_rand_reset.1113051540 |
| Short name | T1893 |
| Test name | |
| Test status | |
| Simulation time | 11869742482 ps |
| CPU time | 725.64 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:59:56 PM PDT 24 |
| Peak memory | 642120 kb |
| Host | smart-cf1ab494-0403-4d9e-a203-0228d6b38317 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113051540 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 10.chip_csr_mem_rw_with_rand_reset.1113051540 |
| Directory | /workspace/10.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_csr_rw.3207351733 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 4130206300 ps |
| CPU time | 265.54 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:52:18 PM PDT 24 |
| Peak memory | 597784 kb |
| Host | smart-6950b99c-9d11-40a3-a24e-c2c4339a8dc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207351733 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.chip_csr_rw.3207351733 |
| Directory | /workspace/10.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/10.chip_same_csr_outstanding.3057370140 |
| Short name | T2813 |
| Test name | |
| Test status | |
| Simulation time | 32394350535 ps |
| CPU time | 4217.07 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 07:58:13 PM PDT 24 |
| Peak memory | 593356 kb |
| Host | smart-4d0623fa-a0cd-4b5f-97f9-891e50f38f6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057370140 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 10.chip_same_csr_outstanding.3057370140 |
| Directory | /workspace/10.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device.560356336 |
| Short name | T2013 |
| Test name | |
| Test status | |
| Simulation time | 1844820156 ps |
| CPU time | 70.95 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 06:49:06 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-c608d5a6-6266-495e-9a1e-7d2ce4fb0c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560356336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_device. 560356336 |
| Directory | /workspace/10.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_access_same_device_slow_rsp.209510513 |
| Short name | T1873 |
| Test name | |
| Test status | |
| Simulation time | 19073911081 ps |
| CPU time | 313.14 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:52:59 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-b5b39a99-50fd-4a8f-aa5d-1e7ce6d045d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=209510513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_access_same_d evice_slow_rsp.209510513 |
| Directory | /workspace/10.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_and_unmapped_addr.959533895 |
| Short name | T1560 |
| Test name | |
| Test status | |
| Simulation time | 1212735881 ps |
| CPU time | 47.88 seconds |
| Started | Aug 17 06:47:59 PM PDT 24 |
| Finished | Aug 17 06:48:47 PM PDT 24 |
| Peak memory | 575412 kb |
| Host | smart-20d5895a-e1f7-483e-be18-4544978efb3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959533895 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_and_unmapped_addr .959533895 |
| Directory | /workspace/10.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_error_random.1206604300 |
| Short name | T1744 |
| Test name | |
| Test status | |
| Simulation time | 246891728 ps |
| CPU time | 22.78 seconds |
| Started | Aug 17 06:48:01 PM PDT 24 |
| Finished | Aug 17 06:48:24 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-fddcf42e-b16a-4175-a758-c8b348a318ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206604300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_error_random.1206604300 |
| Directory | /workspace/10.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random.2591902747 |
| Short name | T2005 |
| Test name | |
| Test status | |
| Simulation time | 409344247 ps |
| CPU time | 35.82 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:48:27 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-a949ab52-4023-452f-929b-14545f142fd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591902747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random.2591902747 |
| Directory | /workspace/10.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_large_delays.3591551891 |
| Short name | T1829 |
| Test name | |
| Test status | |
| Simulation time | 99916416753 ps |
| CPU time | 909.96 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 07:02:57 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-27931f48-591b-4f78-8168-4271181a4093 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591551891 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_large_delays.3591551891 |
| Directory | /workspace/10.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1547774311 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 12453478959 ps |
| CPU time | 208.07 seconds |
| Started | Aug 17 06:47:46 PM PDT 24 |
| Finished | Aug 17 06:51:14 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-347a8911-b0c8-4489-8500-d65098262732 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547774311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_slow_rsp.1547774311 |
| Directory | /workspace/10.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_random_zero_delays.2321115196 |
| Short name | T2535 |
| Test name | |
| Test status | |
| Simulation time | 175685438 ps |
| CPU time | 17.45 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:48:06 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-691f5e11-9a7e-4faa-876c-f05b938bac29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321115196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_random_zero_del ays.2321115196 |
| Directory | /workspace/10.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_same_source.3369924713 |
| Short name | T2045 |
| Test name | |
| Test status | |
| Simulation time | 571296972 ps |
| CPU time | 38.49 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:28 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-17c1cf79-1595-4ef7-9a18-21f8848ab50f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369924713 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_same_source.3369924713 |
| Directory | /workspace/10.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke.2109476649 |
| Short name | T2638 |
| Test name | |
| Test status | |
| Simulation time | 215679695 ps |
| CPU time | 8.99 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:14 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-082e79c6-401c-443e-828c-d747f1ba7e9b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109476649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke.2109476649 |
| Directory | /workspace/10.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.2553066364 |
| Short name | T1771 |
| Test name | |
| Test status | |
| Simulation time | 11443994075 ps |
| CPU time | 109.99 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:49:39 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-380f10d2-4bd2-4468-8673-7695947ac7f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553066364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_large_delays.2553066364 |
| Directory | /workspace/10.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_slow_rsp.179693749 |
| Short name | T1793 |
| Test name | |
| Test status | |
| Simulation time | 6024225063 ps |
| CPU time | 95.56 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:49:25 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-b69d2612-ffb0-4d20-b91e-777f4964115a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179693749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_slow_rsp.179693749 |
| Directory | /workspace/10.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_smoke_zero_delays.905608668 |
| Short name | T2456 |
| Test name | |
| Test status | |
| Simulation time | 47757985 ps |
| CPU time | 6.72 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:47:59 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-2d6635fe-0d7d-4d33-83c9-7233b4e22dad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=905608668 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_smoke_zero_delays .905608668 |
| Directory | /workspace/10.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all.2599458265 |
| Short name | T1844 |
| Test name | |
| Test status | |
| Simulation time | 9962915370 ps |
| CPU time | 355.75 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:53:45 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-e8888ade-2327-4ce6-8bec-2ce72e0f7174 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2599458265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all.2599458265 |
| Directory | /workspace/10.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_error.156557621 |
| Short name | T2401 |
| Test name | |
| Test status | |
| Simulation time | 13699614335 ps |
| CPU time | 482.74 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:55:51 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-7126d54e-17f8-4819-9f94-12caa53afb91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=156557621 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all_with_error.156557621 |
| Directory | /workspace/10.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_rand_reset.1660425905 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 416577455 ps |
| CPU time | 102.75 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:49:30 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-66030465-0b01-4318-9a0d-48e48b9dfab9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660425905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_all _with_rand_reset.1660425905 |
| Directory | /workspace/10.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_stress_all_with_reset_error.1350399638 |
| Short name | T2500 |
| Test name | |
| Test status | |
| Simulation time | 87978311 ps |
| CPU time | 22.17 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:48:14 PM PDT 24 |
| Peak memory | 573592 kb |
| Host | smart-9d7d4e04-4b9a-484c-ab0e-88d3cc97aecc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350399638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_stress_al l_with_reset_error.1350399638 |
| Directory | /workspace/10.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/10.xbar_unmapped_addr.1568918480 |
| Short name | T2317 |
| Test name | |
| Test status | |
| Simulation time | 342276896 ps |
| CPU time | 16.87 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:48:13 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-4e8a7f9e-b128-4b9d-914a-56214259d1a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568918480 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.xbar_unmapped_addr.1568918480 |
| Directory | /workspace/10.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_mem_rw_with_rand_reset.1247807270 |
| Short name | T2109 |
| Test name | |
| Test status | |
| Simulation time | 11016427440 ps |
| CPU time | 831.39 seconds |
| Started | Aug 17 06:47:57 PM PDT 24 |
| Finished | Aug 17 07:01:49 PM PDT 24 |
| Peak memory | 652936 kb |
| Host | smart-db08bca9-33be-448f-9298-2008c0f5b5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247807270 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 11.chip_csr_mem_rw_with_rand_reset.1247807270 |
| Directory | /workspace/11.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_csr_rw.2679440864 |
| Short name | T1885 |
| Test name | |
| Test status | |
| Simulation time | 4110676758 ps |
| CPU time | 269.48 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 06:52:25 PM PDT 24 |
| Peak memory | 597460 kb |
| Host | smart-06fa7f7e-449a-4f57-ad01-1ed8a628fc9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679440864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_csr_rw.2679440864 |
| Directory | /workspace/11.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_same_csr_outstanding.489851921 |
| Short name | T2180 |
| Test name | |
| Test status | |
| Simulation time | 34623926071 ps |
| CPU time | 3888.94 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 07:52:41 PM PDT 24 |
| Peak memory | 593688 kb |
| Host | smart-bb1b4176-f06d-4347-9aa3-33ab4303316e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489851921 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 11.chip_same_csr_outstanding.489851921 |
| Directory | /workspace/11.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/11.chip_tl_errors.1732813957 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 4265715060 ps |
| CPU time | 268.47 seconds |
| Started | Aug 17 06:47:41 PM PDT 24 |
| Finished | Aug 17 06:52:09 PM PDT 24 |
| Peak memory | 596844 kb |
| Host | smart-12af34ee-0533-4540-9a53-baab5c6984dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732813957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.chip_tl_errors.1732813957 |
| Directory | /workspace/11.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device.3470031773 |
| Short name | T2294 |
| Test name | |
| Test status | |
| Simulation time | 23512275 ps |
| CPU time | 9.59 seconds |
| Started | Aug 17 06:48:06 PM PDT 24 |
| Finished | Aug 17 06:48:15 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-e6f728b7-2567-4bc8-b2d7-ac51999351a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470031773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_device .3470031773 |
| Directory | /workspace/11.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_access_same_device_slow_rsp.3531043154 |
| Short name | T1447 |
| Test name | |
| Test status | |
| Simulation time | 13445449811 ps |
| CPU time | 214.17 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:51:36 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-f7aaa968-a0e9-4f32-afc8-e89282e3cc4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531043154 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_access_same_ device_slow_rsp.3531043154 |
| Directory | /workspace/11.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_and_unmapped_addr.1361106812 |
| Short name | T2720 |
| Test name | |
| Test status | |
| Simulation time | 99509193 ps |
| CPU time | 11.8 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:17 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d6773436-e758-48f7-8a35-adc08d4d29af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361106812 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_and_unmapped_add r.1361106812 |
| Directory | /workspace/11.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_error_random.2914092419 |
| Short name | T1761 |
| Test name | |
| Test status | |
| Simulation time | 705424447 ps |
| CPU time | 24.09 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:29 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-be2b4e2c-f503-4ea9-b137-0ce547f53867 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914092419 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_error_random.2914092419 |
| Directory | /workspace/11.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random.3605197869 |
| Short name | T2299 |
| Test name | |
| Test status | |
| Simulation time | 1847401069 ps |
| CPU time | 55.16 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:48:42 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-0ebcff2f-0787-489f-b59a-e1a4d6858747 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605197869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random.3605197869 |
| Directory | /workspace/11.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_large_delays.3534519161 |
| Short name | T1781 |
| Test name | |
| Test status | |
| Simulation time | 15919624210 ps |
| CPU time | 167.31 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:50:34 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-65d65f7e-89c9-4420-a774-532d1c22a1fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3534519161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_large_delays.3534519161 |
| Directory | /workspace/11.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_slow_rsp.88424031 |
| Short name | T2484 |
| Test name | |
| Test status | |
| Simulation time | 42119189365 ps |
| CPU time | 699.23 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:59:44 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-661694d6-56f8-4faa-b846-b31c498ece18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88424031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_slow_rsp.88424031 |
| Directory | /workspace/11.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_random_zero_delays.2340922749 |
| Short name | T2773 |
| Test name | |
| Test status | |
| Simulation time | 520313529 ps |
| CPU time | 46.54 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:48:36 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-8c0e8d2b-1115-43af-baf9-d1372ba4069d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340922749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_random_zero_del ays.2340922749 |
| Directory | /workspace/11.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_same_source.4167797201 |
| Short name | T1575 |
| Test name | |
| Test status | |
| Simulation time | 117995442 ps |
| CPU time | 11.59 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:48:14 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-3db019ea-1f50-40f3-8e06-69610be1c23b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167797201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_same_source.4167797201 |
| Directory | /workspace/11.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke.3693859219 |
| Short name | T2611 |
| Test name | |
| Test status | |
| Simulation time | 168568012 ps |
| CPU time | 8.54 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:47:59 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-15d1370e-63c6-4c5e-9db7-dd20b9a2ccdc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693859219 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke.3693859219 |
| Directory | /workspace/11.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_large_delays.2892073218 |
| Short name | T1832 |
| Test name | |
| Test status | |
| Simulation time | 7698373124 ps |
| CPU time | 76.79 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:49:01 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-91f4c11b-3cbd-4b0f-a71b-f0a2bf3f5ae1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892073218 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_large_delays.2892073218 |
| Directory | /workspace/11.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_slow_rsp.1671145446 |
| Short name | T1359 |
| Test name | |
| Test status | |
| Simulation time | 5519600793 ps |
| CPU time | 94.48 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:49:22 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-0214dc2e-12b8-450c-9de9-e98a84102234 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1671145446 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_slow_rsp.1671145446 |
| Directory | /workspace/11.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_smoke_zero_delays.310934523 |
| Short name | T1451 |
| Test name | |
| Test status | |
| Simulation time | 50147405 ps |
| CPU time | 6.08 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:48:00 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-302d26b0-b13c-4c17-b1de-95e5ad25b51b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310934523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_smoke_zero_delays .310934523 |
| Directory | /workspace/11.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all.2073888690 |
| Short name | T1834 |
| Test name | |
| Test status | |
| Simulation time | 359097598 ps |
| CPU time | 33.24 seconds |
| Started | Aug 17 06:47:59 PM PDT 24 |
| Finished | Aug 17 06:48:32 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-57b38c59-1e19-45c1-959a-b42831871f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073888690 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all.2073888690 |
| Directory | /workspace/11.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_error.641749841 |
| Short name | T1568 |
| Test name | |
| Test status | |
| Simulation time | 14252892368 ps |
| CPU time | 538 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:56:51 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-a3fd8fa3-87be-4e0f-a07a-64963b9097d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641749841 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all_with_error.641749841 |
| Directory | /workspace/11.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_rand_reset.2408493475 |
| Short name | T2784 |
| Test name | |
| Test status | |
| Simulation time | 16972572571 ps |
| CPU time | 817.47 seconds |
| Started | Aug 17 06:48:04 PM PDT 24 |
| Finished | Aug 17 07:01:42 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-29310db5-ae4e-4f84-9cbb-e59c7553be00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408493475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_all _with_rand_reset.2408493475 |
| Directory | /workspace/11.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.2660273687 |
| Short name | T1678 |
| Test name | |
| Test status | |
| Simulation time | 947090235 ps |
| CPU time | 243.2 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:52:08 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-4d68ee2a-c92b-475b-bfc8-5f00ccdff217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660273687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_stress_al l_with_reset_error.2660273687 |
| Directory | /workspace/11.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/11.xbar_unmapped_addr.2807177332 |
| Short name | T2608 |
| Test name | |
| Test status | |
| Simulation time | 247809556 ps |
| CPU time | 27.77 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:33 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-5302512e-7af3-47e7-9ca9-8fc2b7893f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807177332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.xbar_unmapped_addr.2807177332 |
| Directory | /workspace/11.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_csr_rw.1674300398 |
| Short name | T2355 |
| Test name | |
| Test status | |
| Simulation time | 4333798167 ps |
| CPU time | 315.13 seconds |
| Started | Aug 17 06:47:54 PM PDT 24 |
| Finished | Aug 17 06:53:09 PM PDT 24 |
| Peak memory | 598740 kb |
| Host | smart-55cecea3-253f-4490-9b51-ffe03378b8b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1674300398 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_csr_rw.1674300398 |
| Directory | /workspace/12.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_same_csr_outstanding.2127231820 |
| Short name | T2684 |
| Test name | |
| Test status | |
| Simulation time | 16162494144 ps |
| CPU time | 2244.16 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 07:25:12 PM PDT 24 |
| Peak memory | 593260 kb |
| Host | smart-02e03f25-0149-439f-984a-7d0274b4b8a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127231820 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 12.chip_same_csr_outstanding.2127231820 |
| Directory | /workspace/12.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/12.chip_tl_errors.1570548879 |
| Short name | T2176 |
| Test name | |
| Test status | |
| Simulation time | 3199442050 ps |
| CPU time | 119.47 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 06:49:55 PM PDT 24 |
| Peak memory | 603796 kb |
| Host | smart-0b192a69-9b9b-4b2e-aa6f-72f64a5a9f16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570548879 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.chip_tl_errors.1570548879 |
| Directory | /workspace/12.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device.739826104 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2868479134 ps |
| CPU time | 112.78 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:49:58 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-f81bb7c6-8cad-406a-97a5-5b177dd951d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739826104 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_device. 739826104 |
| Directory | /workspace/12.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_access_same_device_slow_rsp.2424580795 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 143713043267 ps |
| CPU time | 2580.13 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 07:30:53 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-f6f84257-5770-40b7-a8f1-fd25aeb6dcb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424580795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_access_same_ device_slow_rsp.2424580795 |
| Directory | /workspace/12.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_and_unmapped_addr.555963620 |
| Short name | T1475 |
| Test name | |
| Test status | |
| Simulation time | 418517333 ps |
| CPU time | 16.79 seconds |
| Started | Aug 17 06:48:04 PM PDT 24 |
| Finished | Aug 17 06:48:21 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-2518f878-2009-47e1-9824-2460bf5ca72c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555963620 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_and_unmapped_addr .555963620 |
| Directory | /workspace/12.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_error_random.1664152732 |
| Short name | T2702 |
| Test name | |
| Test status | |
| Simulation time | 1940368945 ps |
| CPU time | 67.38 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:48:58 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-2148c436-8621-428a-9056-a79495f0d281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664152732 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_error_random.1664152732 |
| Directory | /workspace/12.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random.639935336 |
| Short name | T1810 |
| Test name | |
| Test status | |
| Simulation time | 2329620835 ps |
| CPU time | 79.51 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:49:11 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-7ffc52da-d9d2-420f-89b3-ef1c53825a3e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639935336 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random.639935336 |
| Directory | /workspace/12.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_large_delays.3236280796 |
| Short name | T1995 |
| Test name | |
| Test status | |
| Simulation time | 5936909651 ps |
| CPU time | 60.29 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:48:53 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-f54bd95a-636f-4265-97ca-bc4c9038a620 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236280796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_large_delays.3236280796 |
| Directory | /workspace/12.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_slow_rsp.1530263825 |
| Short name | T1647 |
| Test name | |
| Test status | |
| Simulation time | 50916054312 ps |
| CPU time | 798.83 seconds |
| Started | Aug 17 06:47:58 PM PDT 24 |
| Finished | Aug 17 07:01:17 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-e7341f93-228b-4925-8d0e-a22c431346ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530263825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_slow_rsp.1530263825 |
| Directory | /workspace/12.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.3797976345 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 381610740 ps |
| CPU time | 36.9 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:27 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-5dc88b6e-6fb2-44fd-848c-a22f3ba3a158 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3797976345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_random_zero_del ays.3797976345 |
| Directory | /workspace/12.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_same_source.785526408 |
| Short name | T1493 |
| Test name | |
| Test status | |
| Simulation time | 77770045 ps |
| CPU time | 8.69 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:48:01 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-1e27d6e5-4e98-4740-b7a9-d56928c7a7ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785526408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_same_source.785526408 |
| Directory | /workspace/12.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke.1788377252 |
| Short name | T2838 |
| Test name | |
| Test status | |
| Simulation time | 209578288 ps |
| CPU time | 9.05 seconds |
| Started | Aug 17 06:47:46 PM PDT 24 |
| Finished | Aug 17 06:47:55 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-35c86163-5bda-4a50-a724-d1e87a9c0b15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788377252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke.1788377252 |
| Directory | /workspace/12.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_large_delays.854471163 |
| Short name | T1489 |
| Test name | |
| Test status | |
| Simulation time | 7383675797 ps |
| CPU time | 78.27 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:49:11 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-f8fe9578-fa34-4a25-8486-d469a45ce321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854471163 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_large_delays.854471163 |
| Directory | /workspace/12.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_slow_rsp.2096015395 |
| Short name | T1608 |
| Test name | |
| Test status | |
| Simulation time | 5508917303 ps |
| CPU time | 95.77 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:49:32 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-c3ba7d86-f92d-4876-8fde-67b48f4474b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096015395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_slow_rsp.2096015395 |
| Directory | /workspace/12.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_smoke_zero_delays.1839841375 |
| Short name | T1879 |
| Test name | |
| Test status | |
| Simulation time | 47708180 ps |
| CPU time | 6.64 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:47:52 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-a9e8c474-72e2-4add-b1f9-8c726c0146ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839841375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_smoke_zero_delay s.1839841375 |
| Directory | /workspace/12.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all.2192398306 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 13333089607 ps |
| CPU time | 496.93 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:56:13 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-21b40ce6-3080-4498-8571-0e759977a9e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2192398306 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all.2192398306 |
| Directory | /workspace/12.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_error.788152392 |
| Short name | T2511 |
| Test name | |
| Test status | |
| Simulation time | 1534262711 ps |
| CPU time | 100.97 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:49:24 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-2f4abee1-f560-4ecb-944d-62c1fab535bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788152392 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all_with_error.788152392 |
| Directory | /workspace/12.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_rand_reset.2107153615 |
| Short name | T2292 |
| Test name | |
| Test status | |
| Simulation time | 3357013743 ps |
| CPU time | 342.64 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:53:34 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-49c4005c-aa30-4d57-a521-b7db46e8f400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107153615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_all _with_rand_reset.2107153615 |
| Directory | /workspace/12.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_stress_all_with_reset_error.2866593673 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 2911547821 ps |
| CPU time | 245.06 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:51:55 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-4e97a023-8611-4abe-8798-d1521fc62467 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866593673 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_stress_al l_with_reset_error.2866593673 |
| Directory | /workspace/12.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/12.xbar_unmapped_addr.2733751472 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 1398337941 ps |
| CPU time | 54.81 seconds |
| Started | Aug 17 06:47:54 PM PDT 24 |
| Finished | Aug 17 06:48:49 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-92171ea5-bbb5-4e9c-84aa-d7ae8f6f4c0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733751472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.xbar_unmapped_addr.2733751472 |
| Directory | /workspace/12.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_csr_mem_rw_with_rand_reset.4176414119 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 7413027336 ps |
| CPU time | 419.68 seconds |
| Started | Aug 17 06:48:01 PM PDT 24 |
| Finished | Aug 17 06:55:00 PM PDT 24 |
| Peak memory | 638736 kb |
| Host | smart-44c6f923-3645-4de5-a218-11d238ff401f |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176414119 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 13.chip_csr_mem_rw_with_rand_reset.4176414119 |
| Directory | /workspace/13.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_same_csr_outstanding.212716366 |
| Short name | T2662 |
| Test name | |
| Test status | |
| Simulation time | 27904637665 ps |
| CPU time | 3979.11 seconds |
| Started | Aug 17 06:47:59 PM PDT 24 |
| Finished | Aug 17 07:54:19 PM PDT 24 |
| Peak memory | 593432 kb |
| Host | smart-e3af5356-bf63-46dd-a46b-7202388205f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212716366 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 13.chip_same_csr_outstanding.212716366 |
| Directory | /workspace/13.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/13.chip_tl_errors.2001183364 |
| Short name | T2911 |
| Test name | |
| Test status | |
| Simulation time | 3754382500 ps |
| CPU time | 320.71 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:53:11 PM PDT 24 |
| Peak memory | 603916 kb |
| Host | smart-ddcc463f-d842-4de2-a2cb-9c456f0594bc |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001183364 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.chip_tl_errors.2001183364 |
| Directory | /workspace/13.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device.450930647 |
| Short name | T2549 |
| Test name | |
| Test status | |
| Simulation time | 757520978 ps |
| CPU time | 55.35 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:49:01 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-9078bd75-b2a0-49f3-967f-54d3e4b30c37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450930647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_device. 450930647 |
| Directory | /workspace/13.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_access_same_device_slow_rsp.3656792955 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 14853411186 ps |
| CPU time | 222.85 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:51:36 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-edc8e8fb-3803-4ff1-b683-42b41d3c746d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656792955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_access_same_ device_slow_rsp.3656792955 |
| Directory | /workspace/13.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_and_unmapped_addr.3175110842 |
| Short name | T1629 |
| Test name | |
| Test status | |
| Simulation time | 35969412 ps |
| CPU time | 6.32 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:47:56 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-48e7c99a-3ea4-4c09-9275-bccdc11d5afc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175110842 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_and_unmapped_add r.3175110842 |
| Directory | /workspace/13.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_error_random.3591143200 |
| Short name | T2279 |
| Test name | |
| Test status | |
| Simulation time | 1431901230 ps |
| CPU time | 44.35 seconds |
| Started | Aug 17 06:48:00 PM PDT 24 |
| Finished | Aug 17 06:48:45 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-80a151b9-f0cf-48db-b6cd-810a69885684 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591143200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_error_random.3591143200 |
| Directory | /workspace/13.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random.2759761642 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 2188809728 ps |
| CPU time | 77.72 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 06:49:13 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-dbe086d4-15f9-46ea-b94d-19d5d75fdf1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759761642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random.2759761642 |
| Directory | /workspace/13.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_large_delays.2236879585 |
| Short name | T1559 |
| Test name | |
| Test status | |
| Simulation time | 4453291247 ps |
| CPU time | 45.05 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:48:47 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-b3f1c2ec-c158-4425-817c-fd9d58d13f94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236879585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_large_delays.2236879585 |
| Directory | /workspace/13.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_slow_rsp.2683628519 |
| Short name | T2007 |
| Test name | |
| Test status | |
| Simulation time | 3697371507 ps |
| CPU time | 60.35 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 06:49:08 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-12d9b4b6-dc48-46d9-87f6-1ed3af5df3fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683628519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_slow_rsp.2683628519 |
| Directory | /workspace/13.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.3596560204 |
| Short name | T2427 |
| Test name | |
| Test status | |
| Simulation time | 187372316 ps |
| CPU time | 17.61 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:07 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-5106ef3b-eceb-4014-8000-38439ea6d10e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596560204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_random_zero_del ays.3596560204 |
| Directory | /workspace/13.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_same_source.1803532224 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 573208899 ps |
| CPU time | 38.23 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:43 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-3adbc1d0-abcd-47ac-8ded-57b5281e9a85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803532224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_same_source.1803532224 |
| Directory | /workspace/13.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke.3374471568 |
| Short name | T2217 |
| Test name | |
| Test status | |
| Simulation time | 50497863 ps |
| CPU time | 7 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:48:03 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-f5213013-0b88-4225-9b73-e11bcfbdc0cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374471568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke.3374471568 |
| Directory | /workspace/13.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3399653537 |
| Short name | T1609 |
| Test name | |
| Test status | |
| Simulation time | 7209560158 ps |
| CPU time | 76.94 seconds |
| Started | Aug 17 06:48:08 PM PDT 24 |
| Finished | Aug 17 06:49:25 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-8b29a1d4-ceeb-40a9-b697-964bf4ca4633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399653537 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_large_delays.3399653537 |
| Directory | /workspace/13.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_slow_rsp.130033566 |
| Short name | T1507 |
| Test name | |
| Test status | |
| Simulation time | 5423586317 ps |
| CPU time | 82.68 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:49:16 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-bd40005d-7804-4cd8-af31-4e41006c86c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130033566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_slow_rsp.130033566 |
| Directory | /workspace/13.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.2701715571 |
| Short name | T2632 |
| Test name | |
| Test status | |
| Simulation time | 50032179 ps |
| CPU time | 7.06 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:48:09 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-b813bcc0-40a8-4868-be9d-81c8bee696ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701715571 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_smoke_zero_delay s.2701715571 |
| Directory | /workspace/13.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_error.4062894424 |
| Short name | T1731 |
| Test name | |
| Test status | |
| Simulation time | 9434339147 ps |
| CPU time | 323.28 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:53:29 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-2fb236db-8bad-4d44-90f2-c4ce386c3f09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062894424 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all_with_error.4062894424 |
| Directory | /workspace/13.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_rand_reset.3703197379 |
| Short name | T2545 |
| Test name | |
| Test status | |
| Simulation time | 17802921955 ps |
| CPU time | 912.13 seconds |
| Started | Aug 17 06:48:00 PM PDT 24 |
| Finished | Aug 17 07:03:12 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-49e1502d-906b-4951-8963-d0553d394503 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703197379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_all _with_rand_reset.3703197379 |
| Directory | /workspace/13.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1479828295 |
| Short name | T2927 |
| Test name | |
| Test status | |
| Simulation time | 260277447 ps |
| CPU time | 59.24 seconds |
| Started | Aug 17 06:47:54 PM PDT 24 |
| Finished | Aug 17 06:48:54 PM PDT 24 |
| Peak memory | 576104 kb |
| Host | smart-11e595eb-9935-41b7-877c-34cbe9470273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479828295 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_stress_al l_with_reset_error.1479828295 |
| Directory | /workspace/13.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/13.xbar_unmapped_addr.1825387279 |
| Short name | T2170 |
| Test name | |
| Test status | |
| Simulation time | 362459225 ps |
| CPU time | 40.03 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 06:48:51 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-d2781155-02cc-4b24-b93c-fa04c50adc15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825387279 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.xbar_unmapped_addr.1825387279 |
| Directory | /workspace/13.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_mem_rw_with_rand_reset.2701890697 |
| Short name | T2806 |
| Test name | |
| Test status | |
| Simulation time | 6691954175 ps |
| CPU time | 496.29 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:56:22 PM PDT 24 |
| Peak memory | 638300 kb |
| Host | smart-75f4f8a9-468b-436e-87aa-41f719140e12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701890697 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 14.chip_csr_mem_rw_with_rand_reset.2701890697 |
| Directory | /workspace/14.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_csr_rw.1806162608 |
| Short name | T1984 |
| Test name | |
| Test status | |
| Simulation time | 4317472720 ps |
| CPU time | 318.26 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 06:53:26 PM PDT 24 |
| Peak memory | 597516 kb |
| Host | smart-61295394-63da-4b9d-8cbf-f58e27a19a4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806162608 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.chip_csr_rw.1806162608 |
| Directory | /workspace/14.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/14.chip_same_csr_outstanding.672165892 |
| Short name | T2239 |
| Test name | |
| Test status | |
| Simulation time | 29031424652 ps |
| CPU time | 3779.3 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 07:51:02 PM PDT 24 |
| Peak memory | 593068 kb |
| Host | smart-65a9f247-d495-44f9-b2e4-48063ba7c3cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672165892 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 14.chip_same_csr_outstanding.672165892 |
| Directory | /workspace/14.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device.15842066 |
| Short name | T1686 |
| Test name | |
| Test status | |
| Simulation time | 892051782 ps |
| CPU time | 35.18 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:48:28 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-e8e58924-299d-4283-96d7-cda22ffe0b46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15842066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_device.15842066 |
| Directory | /workspace/14.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_access_same_device_slow_rsp.1052598320 |
| Short name | T1708 |
| Test name | |
| Test status | |
| Simulation time | 37975731023 ps |
| CPU time | 660.08 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:59:05 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-ab548c8f-e60d-4195-a87f-22d2a03955a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052598320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_access_same_ device_slow_rsp.1052598320 |
| Directory | /workspace/14.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.768997396 |
| Short name | T1627 |
| Test name | |
| Test status | |
| Simulation time | 167626989 ps |
| CPU time | 9.03 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:48:01 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-f4b241b6-5e1c-4850-ada5-c4ed8e1e504a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768997396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_and_unmapped_addr .768997396 |
| Directory | /workspace/14.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_error_random.4082847232 |
| Short name | T2336 |
| Test name | |
| Test status | |
| Simulation time | 1176353852 ps |
| CPU time | 38.55 seconds |
| Started | Aug 17 06:48:06 PM PDT 24 |
| Finished | Aug 17 06:48:45 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-c5c31b21-96ca-4853-845e-d4d3b13a8ae6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082847232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_error_random.4082847232 |
| Directory | /workspace/14.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random.2951878814 |
| Short name | T2592 |
| Test name | |
| Test status | |
| Simulation time | 449503345 ps |
| CPU time | 39.92 seconds |
| Started | Aug 17 06:48:09 PM PDT 24 |
| Finished | Aug 17 06:48:49 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-98f01c4f-a07c-4a44-9683-7263652e6e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951878814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random.2951878814 |
| Directory | /workspace/14.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_large_delays.670102132 |
| Short name | T1645 |
| Test name | |
| Test status | |
| Simulation time | 87339323822 ps |
| CPU time | 1025.99 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 07:04:57 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-f6e98b09-b834-40d4-b0ab-78a6851c6fa6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670102132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_large_delays.670102132 |
| Directory | /workspace/14.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_slow_rsp.2769504456 |
| Short name | T2835 |
| Test name | |
| Test status | |
| Simulation time | 30915916766 ps |
| CPU time | 492.46 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:56:18 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-d2a0fcd5-908a-4aac-bd99-d2cadb5bd77d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769504456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_slow_rsp.2769504456 |
| Directory | /workspace/14.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.359902536 |
| Short name | T2384 |
| Test name | |
| Test status | |
| Simulation time | 68627269 ps |
| CPU time | 9.41 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:48:12 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-7767db35-4165-4b28-9ed8-5d8fa681b18c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359902536 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_random_zero_dela ys.359902536 |
| Directory | /workspace/14.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_same_source.472351479 |
| Short name | T2630 |
| Test name | |
| Test status | |
| Simulation time | 2073882964 ps |
| CPU time | 62 seconds |
| Started | Aug 17 06:48:04 PM PDT 24 |
| Finished | Aug 17 06:49:07 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-dd85f4b1-250f-43f3-9be3-8fcf92a82c12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472351479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_same_source.472351479 |
| Directory | /workspace/14.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke.3965005961 |
| Short name | T1803 |
| Test name | |
| Test status | |
| Simulation time | 140580119 ps |
| CPU time | 7.71 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:47:59 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-9122c1f6-9663-4a59-b8f7-b7ce9485a964 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965005961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke.3965005961 |
| Directory | /workspace/14.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_large_delays.3014911373 |
| Short name | T1410 |
| Test name | |
| Test status | |
| Simulation time | 10349801401 ps |
| CPU time | 105.83 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:49:50 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-90a6351f-ac93-430a-8735-39d2873c82e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3014911373 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_large_delays.3014911373 |
| Directory | /workspace/14.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_slow_rsp.1294534350 |
| Short name | T2919 |
| Test name | |
| Test status | |
| Simulation time | 3199197100 ps |
| CPU time | 50.46 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:56 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-655d79b1-37d9-4eb9-a1e2-79fc58221bee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294534350 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_slow_rsp.1294534350 |
| Directory | /workspace/14.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.121924917 |
| Short name | T1782 |
| Test name | |
| Test status | |
| Simulation time | 40525129 ps |
| CPU time | 5.48 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:47:58 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-5da869c5-c056-4a89-b61b-d0a3a71cc65d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=121924917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_smoke_zero_delays .121924917 |
| Directory | /workspace/14.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all.2738843889 |
| Short name | T1658 |
| Test name | |
| Test status | |
| Simulation time | 9496543751 ps |
| CPU time | 321.18 seconds |
| Started | Aug 17 06:48:00 PM PDT 24 |
| Finished | Aug 17 06:53:22 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5f0ccf98-1d22-4438-84ac-34f7ef84281c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738843889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all.2738843889 |
| Directory | /workspace/14.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_error.1837913670 |
| Short name | T1944 |
| Test name | |
| Test status | |
| Simulation time | 1183358477 ps |
| CPU time | 75.06 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:49:05 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-d02397c5-d7ec-47d3-ac2b-51fd0ad6eb45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837913670 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all_with_error.1837913670 |
| Directory | /workspace/14.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.3803489919 |
| Short name | T1570 |
| Test name | |
| Test status | |
| Simulation time | 267704507 ps |
| CPU time | 97.73 seconds |
| Started | Aug 17 06:47:53 PM PDT 24 |
| Finished | Aug 17 06:49:30 PM PDT 24 |
| Peak memory | 576264 kb |
| Host | smart-30290bc9-9af6-40be-9348-6c278adb2beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803489919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_all _with_rand_reset.3803489919 |
| Directory | /workspace/14.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_stress_all_with_reset_error.3375145905 |
| Short name | T1510 |
| Test name | |
| Test status | |
| Simulation time | 303919340 ps |
| CPU time | 82.22 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:49:25 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-bf6881a8-1513-4575-a958-9f51aae32b58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375145905 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_stress_al l_with_reset_error.3375145905 |
| Directory | /workspace/14.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/14.xbar_unmapped_addr.1929805849 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 334162074 ps |
| CPU time | 40.21 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:48:31 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-a0f0862a-8d20-4e27-af0b-45d6b527d794 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929805849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.xbar_unmapped_addr.1929805849 |
| Directory | /workspace/14.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_csr_rw.634115869 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 5646418956 ps |
| CPU time | 594.87 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:57:58 PM PDT 24 |
| Peak memory | 598912 kb |
| Host | smart-d51e21b4-37da-4cdb-8b84-0bfeb6b08cdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634115869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_csr_rw.634115869 |
| Directory | /workspace/15.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_same_csr_outstanding.3126825900 |
| Short name | T2167 |
| Test name | |
| Test status | |
| Simulation time | 13967860500 ps |
| CPU time | 2007.04 seconds |
| Started | Aug 17 06:47:58 PM PDT 24 |
| Finished | Aug 17 07:21:25 PM PDT 24 |
| Peak memory | 593276 kb |
| Host | smart-91d591f5-8659-4031-ae20-2090ce57142b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126825900 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 15.chip_same_csr_outstanding.3126825900 |
| Directory | /workspace/15.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/15.chip_tl_errors.3742785760 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 3707079420 ps |
| CPU time | 252.03 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 06:52:19 PM PDT 24 |
| Peak memory | 603912 kb |
| Host | smart-a333ab1d-47be-4b56-8b5b-466641e13127 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742785760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.chip_tl_errors.3742785760 |
| Directory | /workspace/15.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_access_same_device.4169021929 |
| Short name | T2727 |
| Test name | |
| Test status | |
| Simulation time | 2362455781 ps |
| CPU time | 84.59 seconds |
| Started | Aug 17 06:48:17 PM PDT 24 |
| Finished | Aug 17 06:49:42 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-bc06fad2-b681-4ef6-a0e6-3845684b1ea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169021929 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_access_same_device .4169021929 |
| Directory | /workspace/15.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_and_unmapped_addr.2037039037 |
| Short name | T2770 |
| Test name | |
| Test status | |
| Simulation time | 19315090 ps |
| CPU time | 4.92 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 06:48:12 PM PDT 24 |
| Peak memory | 573416 kb |
| Host | smart-cde79930-a628-4a4e-8d6c-e3063707a869 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037039037 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_and_unmapped_add r.2037039037 |
| Directory | /workspace/15.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_error_random.4125641250 |
| Short name | T1823 |
| Test name | |
| Test status | |
| Simulation time | 791557677 ps |
| CPU time | 27.21 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:48:29 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-5250b5d3-c99c-4499-a98e-caae90bffd13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125641250 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_error_random.4125641250 |
| Directory | /workspace/15.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random.1132674444 |
| Short name | T2122 |
| Test name | |
| Test status | |
| Simulation time | 1620434021 ps |
| CPU time | 62.27 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:49:04 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-51d1c670-6f3b-49ec-8c77-f46d2681664a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1132674444 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random.1132674444 |
| Directory | /workspace/15.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_large_delays.3376095358 |
| Short name | T1977 |
| Test name | |
| Test status | |
| Simulation time | 107310868344 ps |
| CPU time | 1165.77 seconds |
| Started | Aug 17 06:48:08 PM PDT 24 |
| Finished | Aug 17 07:07:34 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-0bf277ea-1691-4ca8-b54f-669906719d9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376095358 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_large_delays.3376095358 |
| Directory | /workspace/15.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_slow_rsp.1711569572 |
| Short name | T2783 |
| Test name | |
| Test status | |
| Simulation time | 38690162887 ps |
| CPU time | 651.06 seconds |
| Started | Aug 17 06:48:09 PM PDT 24 |
| Finished | Aug 17 06:59:00 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-a4e2a53e-7dcd-4839-bcf7-e71183a8e216 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1711569572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_slow_rsp.1711569572 |
| Directory | /workspace/15.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_random_zero_delays.1393454882 |
| Short name | T2419 |
| Test name | |
| Test status | |
| Simulation time | 614586509 ps |
| CPU time | 45.3 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 06:48:40 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-414ca485-de76-4fc2-b923-e481b6ed0046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1393454882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_random_zero_del ays.1393454882 |
| Directory | /workspace/15.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_same_source.1196498947 |
| Short name | T2915 |
| Test name | |
| Test status | |
| Simulation time | 2403019980 ps |
| CPU time | 74.57 seconds |
| Started | Aug 17 06:48:10 PM PDT 24 |
| Finished | Aug 17 06:49:25 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-1d785d0a-ffa5-4210-bc06-9e27b07abdf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196498947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_same_source.1196498947 |
| Directory | /workspace/15.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke.3186805133 |
| Short name | T2612 |
| Test name | |
| Test status | |
| Simulation time | 205253009 ps |
| CPU time | 8.42 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:48:12 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-87eddee2-0545-44a4-9a59-d781bc259f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186805133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke.3186805133 |
| Directory | /workspace/15.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_large_delays.692632806 |
| Short name | T2768 |
| Test name | |
| Test status | |
| Simulation time | 6905962207 ps |
| CPU time | 72.92 seconds |
| Started | Aug 17 06:48:10 PM PDT 24 |
| Finished | Aug 17 06:49:23 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-3a2b8e7c-5e47-4ad0-af05-f5162b54743b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692632806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_large_delays.692632806 |
| Directory | /workspace/15.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_slow_rsp.1374864477 |
| Short name | T2108 |
| Test name | |
| Test status | |
| Simulation time | 5530683939 ps |
| CPU time | 85.52 seconds |
| Started | Aug 17 06:48:10 PM PDT 24 |
| Finished | Aug 17 06:49:36 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-cc3d7dbe-a6b8-4675-808c-b9c8fb5eb645 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374864477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_slow_rsp.1374864477 |
| Directory | /workspace/15.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.267987719 |
| Short name | T1716 |
| Test name | |
| Test status | |
| Simulation time | 56310009 ps |
| CPU time | 6.32 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:11 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-de173226-05be-41e7-a657-09ec179e0b0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267987719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_smoke_zero_delays .267987719 |
| Directory | /workspace/15.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all.3090614943 |
| Short name | T2729 |
| Test name | |
| Test status | |
| Simulation time | 2673562935 ps |
| CPU time | 204.15 seconds |
| Started | Aug 17 06:47:59 PM PDT 24 |
| Finished | Aug 17 06:51:23 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-977b6901-7f28-44f7-83cf-1f3761b89046 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090614943 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all.3090614943 |
| Directory | /workspace/15.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_error.97074142 |
| Short name | T1456 |
| Test name | |
| Test status | |
| Simulation time | 578871137 ps |
| CPU time | 43.28 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:49 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-dbca0b6f-9a2a-4593-b5ca-ee6e962dbe2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97074142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all_with_error.97074142 |
| Directory | /workspace/15.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1405118098 |
| Short name | T2224 |
| Test name | |
| Test status | |
| Simulation time | 4851065335 ps |
| CPU time | 188.04 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 06:51:19 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-6524ad22-8674-4d31-a967-115d88ed7bf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1405118098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_rand_reset.1405118098 |
| Directory | /workspace/15.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_stress_all_with_reset_error.143288441 |
| Short name | T2883 |
| Test name | |
| Test status | |
| Simulation time | 271085088 ps |
| CPU time | 110.01 seconds |
| Started | Aug 17 06:47:58 PM PDT 24 |
| Finished | Aug 17 06:49:48 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-c291cec4-bfee-4d51-b778-a6f43b6e6d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=143288441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_stress_all _with_reset_error.143288441 |
| Directory | /workspace/15.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2928516700 |
| Short name | T2149 |
| Test name | |
| Test status | |
| Simulation time | 129712560 ps |
| CPU time | 16.11 seconds |
| Started | Aug 17 06:48:01 PM PDT 24 |
| Finished | Aug 17 06:48:17 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-e055c580-d158-4a3c-bbcb-1b10a9c564f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928516700 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.xbar_unmapped_addr.2928516700 |
| Directory | /workspace/15.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_mem_rw_with_rand_reset.4086234272 |
| Short name | T1656 |
| Test name | |
| Test status | |
| Simulation time | 11362758925 ps |
| CPU time | 860.22 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 07:02:22 PM PDT 24 |
| Peak memory | 646816 kb |
| Host | smart-05af51ca-9fb3-4511-a374-4b55a67d4710 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086234272 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 16.chip_csr_mem_rw_with_rand_reset.4086234272 |
| Directory | /workspace/16.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_csr_rw.3451794479 |
| Short name | T1756 |
| Test name | |
| Test status | |
| Simulation time | 5506219186 ps |
| CPU time | 482.85 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:56:06 PM PDT 24 |
| Peak memory | 598752 kb |
| Host | smart-d8084102-2981-4f88-a9ec-cf6aecead1de |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451794479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_csr_rw.3451794479 |
| Directory | /workspace/16.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_same_csr_outstanding.284159785 |
| Short name | T2681 |
| Test name | |
| Test status | |
| Simulation time | 14916790482 ps |
| CPU time | 2420.93 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 07:28:23 PM PDT 24 |
| Peak memory | 593388 kb |
| Host | smart-4166f6fe-5aad-478a-b4ad-f3971240fb08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284159785 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -c m_log /dev/null -cm_name 16.chip_same_csr_outstanding.284159785 |
| Directory | /workspace/16.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/16.chip_tl_errors.1155596741 |
| Short name | T2453 |
| Test name | |
| Test status | |
| Simulation time | 3551903425 ps |
| CPU time | 160.97 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:50:44 PM PDT 24 |
| Peak memory | 598092 kb |
| Host | smart-32e73d48-d38a-48df-8443-a2b2af913501 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155596741 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.chip_tl_errors.1155596741 |
| Directory | /workspace/16.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device.888197669 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 3525749860 ps |
| CPU time | 150.92 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:50:34 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-afa1023a-d5c7-42a3-88e4-fc9f19e6bdab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=888197669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_device. 888197669 |
| Directory | /workspace/16.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_access_same_device_slow_rsp.2211534389 |
| Short name | T1812 |
| Test name | |
| Test status | |
| Simulation time | 25941254993 ps |
| CPU time | 434.37 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:55:18 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-252e9b48-ee2b-48d3-81bf-4cbd91e1e204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211534389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_access_same_ device_slow_rsp.2211534389 |
| Directory | /workspace/16.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.3479907488 |
| Short name | T1556 |
| Test name | |
| Test status | |
| Simulation time | 55960105 ps |
| CPU time | 5.92 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:48:08 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-384bff60-1fbf-40d7-9b1e-630fc83d5a06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479907488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_and_unmapped_add r.3479907488 |
| Directory | /workspace/16.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_error_random.1743528659 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2616145638 ps |
| CPU time | 94.95 seconds |
| Started | Aug 17 06:48:00 PM PDT 24 |
| Finished | Aug 17 06:49:35 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-f9a416a8-b022-4cf6-86ed-bfd6839bdae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743528659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_error_random.1743528659 |
| Directory | /workspace/16.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random.1808275895 |
| Short name | T2848 |
| Test name | |
| Test status | |
| Simulation time | 530383019 ps |
| CPU time | 19 seconds |
| Started | Aug 17 06:48:02 PM PDT 24 |
| Finished | Aug 17 06:48:22 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-44704c7f-4ca5-476c-96b2-570f97ecd817 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808275895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random.1808275895 |
| Directory | /workspace/16.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_large_delays.2396639959 |
| Short name | T1983 |
| Test name | |
| Test status | |
| Simulation time | 76167239132 ps |
| CPU time | 793.39 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 07:01:24 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-105c792c-61ad-4e1e-aa37-a2ae674ac238 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2396639959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_large_delays.2396639959 |
| Directory | /workspace/16.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_slow_rsp.3108562543 |
| Short name | T2049 |
| Test name | |
| Test status | |
| Simulation time | 55910934879 ps |
| CPU time | 935.31 seconds |
| Started | Aug 17 06:48:00 PM PDT 24 |
| Finished | Aug 17 07:03:35 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-3dfcdb22-dc05-4160-b4d5-b18729ca6f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108562543 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_slow_rsp.3108562543 |
| Directory | /workspace/16.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_random_zero_delays.3657847680 |
| Short name | T2382 |
| Test name | |
| Test status | |
| Simulation time | 140406013 ps |
| CPU time | 13.18 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:48:16 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-73297e5b-8434-411f-a5ed-872831262b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657847680 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_random_zero_del ays.3657847680 |
| Directory | /workspace/16.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_same_source.1627809136 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2522465617 ps |
| CPU time | 70.35 seconds |
| Started | Aug 17 06:48:01 PM PDT 24 |
| Finished | Aug 17 06:49:11 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-5db2209f-fdb4-4ac4-b70d-c54efe5bc4bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627809136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_same_source.1627809136 |
| Directory | /workspace/16.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke.3990431945 |
| Short name | T2686 |
| Test name | |
| Test status | |
| Simulation time | 59684454 ps |
| CPU time | 6.76 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:48:12 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-4f4dc840-9a92-44fe-bfd5-59db040651a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3990431945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke.3990431945 |
| Directory | /workspace/16.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_large_delays.567093045 |
| Short name | T1569 |
| Test name | |
| Test status | |
| Simulation time | 6896101051 ps |
| CPU time | 70.85 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 06:49:21 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-b25cb4fa-12e9-41e6-b267-752ddfa96e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567093045 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_large_delays.567093045 |
| Directory | /workspace/16.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_slow_rsp.3816721483 |
| Short name | T2442 |
| Test name | |
| Test status | |
| Simulation time | 6144864254 ps |
| CPU time | 103.27 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 06:49:50 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-79bfc7fc-140e-4adf-8375-020ee5235388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816721483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_slow_rsp.3816721483 |
| Directory | /workspace/16.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_smoke_zero_delays.2342308448 |
| Short name | T1372 |
| Test name | |
| Test status | |
| Simulation time | 47609489 ps |
| CPU time | 6.4 seconds |
| Started | Aug 17 06:48:10 PM PDT 24 |
| Finished | Aug 17 06:48:16 PM PDT 24 |
| Peak memory | 573404 kb |
| Host | smart-2701a12c-969e-4562-a14d-a282976bbe7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342308448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_smoke_zero_delay s.2342308448 |
| Directory | /workspace/16.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all.677674970 |
| Short name | T2454 |
| Test name | |
| Test status | |
| Simulation time | 2851980313 ps |
| CPU time | 239.16 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:52:03 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-849a2dcd-a18c-4957-a242-76089bdfbde6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677674970 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all.677674970 |
| Directory | /workspace/16.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_error.3152187336 |
| Short name | T1952 |
| Test name | |
| Test status | |
| Simulation time | 1755851747 ps |
| CPU time | 126.34 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:50:10 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-13e59f2d-3bc5-4f25-8011-c0e81b815d97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152187336 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_with_error.3152187336 |
| Directory | /workspace/16.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_rand_reset.583267884 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 590056334 ps |
| CPU time | 207.1 seconds |
| Started | Aug 17 06:48:08 PM PDT 24 |
| Finished | Aug 17 06:51:35 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-edfaf2e5-ded3-4b69-893d-d428f6fbb8ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583267884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_all_ with_rand_reset.583267884 |
| Directory | /workspace/16.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_stress_all_with_reset_error.2958649981 |
| Short name | T1401 |
| Test name | |
| Test status | |
| Simulation time | 2734811086 ps |
| CPU time | 125.03 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:50:08 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-33ccea4c-c8ef-40c5-86a0-51229ef09e40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958649981 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_stress_al l_with_reset_error.2958649981 |
| Directory | /workspace/16.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/16.xbar_unmapped_addr.3219082295 |
| Short name | T2430 |
| Test name | |
| Test status | |
| Simulation time | 27314477 ps |
| CPU time | 5.79 seconds |
| Started | Aug 17 06:48:10 PM PDT 24 |
| Finished | Aug 17 06:48:15 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-39dd0c17-84f6-4d5d-aef9-7ee567666f15 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219082295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.xbar_unmapped_addr.3219082295 |
| Directory | /workspace/16.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_csr_mem_rw_with_rand_reset.4211469968 |
| Short name | T2404 |
| Test name | |
| Test status | |
| Simulation time | 11209392906 ps |
| CPU time | 817.47 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 07:02:04 PM PDT 24 |
| Peak memory | 645380 kb |
| Host | smart-d5e6c470-1098-4c21-91a3-75b6427723d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4211469968 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 17.chip_csr_mem_rw_with_rand_reset.4211469968 |
| Directory | /workspace/17.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_same_csr_outstanding.1739427040 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 30431127272 ps |
| CPU time | 4083.14 seconds |
| Started | Aug 17 06:48:18 PM PDT 24 |
| Finished | Aug 17 07:56:21 PM PDT 24 |
| Peak memory | 593780 kb |
| Host | smart-f5316d8e-5eb9-40f3-9675-9905cc9b6bbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1739427040 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 17.chip_same_csr_outstanding.1739427040 |
| Directory | /workspace/17.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/17.chip_tl_errors.1403688348 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3150050335 ps |
| CPU time | 150.61 seconds |
| Started | Aug 17 06:48:17 PM PDT 24 |
| Finished | Aug 17 06:50:48 PM PDT 24 |
| Peak memory | 603940 kb |
| Host | smart-b7e67b54-5c4c-4f82-bdf7-2500386358ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1403688348 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.chip_tl_errors.1403688348 |
| Directory | /workspace/17.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device.824062002 |
| Short name | T1796 |
| Test name | |
| Test status | |
| Simulation time | 442264130 ps |
| CPU time | 38.41 seconds |
| Started | Aug 17 06:48:04 PM PDT 24 |
| Finished | Aug 17 06:48:42 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-b3e0d63f-31f0-46c0-ab06-98a7ff5b9c68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824062002 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_device. 824062002 |
| Directory | /workspace/17.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_access_same_device_slow_rsp.3641200547 |
| Short name | T2737 |
| Test name | |
| Test status | |
| Simulation time | 149915938083 ps |
| CPU time | 2849.04 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 07:35:35 PM PDT 24 |
| Peak memory | 575852 kb |
| Host | smart-ff75338b-b792-410e-9e8d-9396b7b28a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3641200547 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_access_same_ device_slow_rsp.3641200547 |
| Directory | /workspace/17.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_and_unmapped_addr.1737934840 |
| Short name | T1816 |
| Test name | |
| Test status | |
| Simulation time | 1378056005 ps |
| CPU time | 50.3 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 06:49:17 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-74fea2b6-736e-4920-84f1-6be2a4e8bf58 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737934840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_and_unmapped_add r.1737934840 |
| Directory | /workspace/17.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_error_random.3722811897 |
| Short name | T2726 |
| Test name | |
| Test status | |
| Simulation time | 107340414 ps |
| CPU time | 10.43 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 06:48:37 PM PDT 24 |
| Peak memory | 575208 kb |
| Host | smart-89ed5eea-33be-469e-9125-c857b4d6bfd9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722811897 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_error_random.3722811897 |
| Directory | /workspace/17.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random.3214083621 |
| Short name | T1901 |
| Test name | |
| Test status | |
| Simulation time | 1959332034 ps |
| CPU time | 65.65 seconds |
| Started | Aug 17 06:48:14 PM PDT 24 |
| Finished | Aug 17 06:49:19 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-f1da8179-7da9-4583-89d4-bce2613aa643 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214083621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random.3214083621 |
| Directory | /workspace/17.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_large_delays.429796755 |
| Short name | T1751 |
| Test name | |
| Test status | |
| Simulation time | 65481242146 ps |
| CPU time | 738.1 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 07:00:29 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-aef78caa-a805-4ad9-b68d-6be90a16132d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=429796755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_large_delays.429796755 |
| Directory | /workspace/17.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_slow_rsp.1821585405 |
| Short name | T1662 |
| Test name | |
| Test status | |
| Simulation time | 27925659409 ps |
| CPU time | 459.44 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 06:56:06 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-83dfb8b3-a8d9-4a6f-85f2-b4d859f46ab0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821585405 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_slow_rsp.1821585405 |
| Directory | /workspace/17.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_random_zero_delays.312984759 |
| Short name | T1484 |
| Test name | |
| Test status | |
| Simulation time | 92363167 ps |
| CPU time | 9.75 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 06:48:36 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-f441ea9a-4eae-4e7d-88f8-65240e478c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312984759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_random_zero_dela ys.312984759 |
| Directory | /workspace/17.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_same_source.2537730834 |
| Short name | T2115 |
| Test name | |
| Test status | |
| Simulation time | 296421639 ps |
| CPU time | 19.42 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 06:48:31 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-165d2bbf-c8fe-4a47-ae67-36f5a5f20b3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537730834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_same_source.2537730834 |
| Directory | /workspace/17.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke.2333931926 |
| Short name | T1847 |
| Test name | |
| Test status | |
| Simulation time | 218555555 ps |
| CPU time | 8.56 seconds |
| Started | Aug 17 06:48:13 PM PDT 24 |
| Finished | Aug 17 06:48:22 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-2345cc92-23c6-4495-9977-5ee5ce9fbbf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2333931926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke.2333931926 |
| Directory | /workspace/17.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_large_delays.1626834022 |
| Short name | T2413 |
| Test name | |
| Test status | |
| Simulation time | 8469875528 ps |
| CPU time | 82.6 seconds |
| Started | Aug 17 06:48:13 PM PDT 24 |
| Finished | Aug 17 06:49:36 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-8bf8d21f-cf5b-4407-8089-de180ec5f664 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626834022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_large_delays.1626834022 |
| Directory | /workspace/17.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_slow_rsp.1438527401 |
| Short name | T2571 |
| Test name | |
| Test status | |
| Simulation time | 4957277443 ps |
| CPU time | 82.87 seconds |
| Started | Aug 17 06:48:07 PM PDT 24 |
| Finished | Aug 17 06:49:30 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-89d5943e-e63c-4ba0-b782-05ef08ed891f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438527401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_slow_rsp.1438527401 |
| Directory | /workspace/17.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_smoke_zero_delays.1292263566 |
| Short name | T2394 |
| Test name | |
| Test status | |
| Simulation time | 49956367 ps |
| CPU time | 6.17 seconds |
| Started | Aug 17 06:48:06 PM PDT 24 |
| Finished | Aug 17 06:48:13 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-dad3514e-886e-4dac-bbb5-32f9a423f6af |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292263566 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_smoke_zero_delay s.1292263566 |
| Directory | /workspace/17.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all.478986439 |
| Short name | T1835 |
| Test name | |
| Test status | |
| Simulation time | 2251242214 ps |
| CPU time | 84.1 seconds |
| Started | Aug 17 06:48:05 PM PDT 24 |
| Finished | Aug 17 06:49:29 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-1d3ba4ea-f8f7-4602-ac87-0cc35e7bf5cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478986439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all.478986439 |
| Directory | /workspace/17.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_error.2649580142 |
| Short name | T1611 |
| Test name | |
| Test status | |
| Simulation time | 823244185 ps |
| CPU time | 64.99 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 06:49:32 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-0a40716d-0b46-439c-92b2-e5fb7b3ab603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649580142 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all_with_error.2649580142 |
| Directory | /workspace/17.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_rand_reset.1941172357 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 2654664787 ps |
| CPU time | 278.17 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:52:42 PM PDT 24 |
| Peak memory | 576368 kb |
| Host | smart-84f74a36-7262-43f0-a0ca-5520ab205e22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941172357 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_all _with_rand_reset.1941172357 |
| Directory | /workspace/17.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_stress_all_with_reset_error.2173975848 |
| Short name | T2540 |
| Test name | |
| Test status | |
| Simulation time | 401556696 ps |
| CPU time | 115.23 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 06:50:22 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-7e3930dc-347c-40f8-9204-1ab6688e1d52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173975848 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_stress_al l_with_reset_error.2173975848 |
| Directory | /workspace/17.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/17.xbar_unmapped_addr.340980838 |
| Short name | T2906 |
| Test name | |
| Test status | |
| Simulation time | 1056167180 ps |
| CPU time | 40.88 seconds |
| Started | Aug 17 06:48:04 PM PDT 24 |
| Finished | Aug 17 06:48:45 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-613a9cf0-2eea-42b0-9bec-3e325a11635a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340980838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.xbar_unmapped_addr.340980838 |
| Directory | /workspace/17.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_mem_rw_with_rand_reset.2076901022 |
| Short name | T2792 |
| Test name | |
| Test status | |
| Simulation time | 6131020675 ps |
| CPU time | 483.04 seconds |
| Started | Aug 17 06:48:19 PM PDT 24 |
| Finished | Aug 17 06:56:22 PM PDT 24 |
| Peak memory | 646496 kb |
| Host | smart-1b5800de-b77b-4b0e-8ff8-07a31ff96e1c |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076901022 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 18.chip_csr_mem_rw_with_rand_reset.2076901022 |
| Directory | /workspace/18.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.chip_csr_rw.1207672818 |
| Short name | T2708 |
| Test name | |
| Test status | |
| Simulation time | 6133230182 ps |
| CPU time | 691.24 seconds |
| Started | Aug 17 06:48:18 PM PDT 24 |
| Finished | Aug 17 06:59:50 PM PDT 24 |
| Peak memory | 598528 kb |
| Host | smart-4669f205-95c9-4e08-98c3-4b83ad044fb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207672818 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.chip_csr_rw.1207672818 |
| Directory | /workspace/18.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device.3920362992 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 602744236 ps |
| CPU time | 47.77 seconds |
| Started | Aug 17 06:48:12 PM PDT 24 |
| Finished | Aug 17 06:49:00 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-e20ba93a-835a-488e-b62d-779b8433d682 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920362992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_device .3920362992 |
| Directory | /workspace/18.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_access_same_device_slow_rsp.1289914742 |
| Short name | T2284 |
| Test name | |
| Test status | |
| Simulation time | 111808762044 ps |
| CPU time | 2006.84 seconds |
| Started | Aug 17 06:48:14 PM PDT 24 |
| Finished | Aug 17 07:21:42 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-9085ef8d-acbb-458d-a44d-4180c249092b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289914742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_access_same_ device_slow_rsp.1289914742 |
| Directory | /workspace/18.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.3368564488 |
| Short name | T2512 |
| Test name | |
| Test status | |
| Simulation time | 118108253 ps |
| CPU time | 13.61 seconds |
| Started | Aug 17 06:48:29 PM PDT 24 |
| Finished | Aug 17 06:48:43 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-0f0eaa88-3761-46ba-977c-7c450d09a548 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368564488 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_and_unmapped_add r.3368564488 |
| Directory | /workspace/18.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_error_random.3311992996 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 134923737 ps |
| CPU time | 12.96 seconds |
| Started | Aug 17 06:48:13 PM PDT 24 |
| Finished | Aug 17 06:48:26 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-1cd92a0d-8c9b-43fd-89f8-dac945c692ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311992996 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_error_random.3311992996 |
| Directory | /workspace/18.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random.1129191493 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 587331855 ps |
| CPU time | 22.11 seconds |
| Started | Aug 17 06:48:15 PM PDT 24 |
| Finished | Aug 17 06:48:37 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-06285059-dbaf-4adb-bb91-93891a5658ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129191493 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random.1129191493 |
| Directory | /workspace/18.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_large_delays.4149536606 |
| Short name | T2871 |
| Test name | |
| Test status | |
| Simulation time | 21894317605 ps |
| CPU time | 215.3 seconds |
| Started | Aug 17 06:48:14 PM PDT 24 |
| Finished | Aug 17 06:51:49 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-edbf88f7-4b52-4da7-b668-4ccb543a40d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149536606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_large_delays.4149536606 |
| Directory | /workspace/18.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_slow_rsp.1471429551 |
| Short name | T2341 |
| Test name | |
| Test status | |
| Simulation time | 19019022278 ps |
| CPU time | 314.42 seconds |
| Started | Aug 17 06:48:16 PM PDT 24 |
| Finished | Aug 17 06:53:30 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-5a1acf60-3136-493d-bd91-97190e8d347a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471429551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_slow_rsp.1471429551 |
| Directory | /workspace/18.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_random_zero_delays.3765124789 |
| Short name | T1486 |
| Test name | |
| Test status | |
| Simulation time | 354876858 ps |
| CPU time | 33.23 seconds |
| Started | Aug 17 06:48:16 PM PDT 24 |
| Finished | Aug 17 06:48:49 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-2db4751b-2ccf-4fcd-b8c1-8293f49d956c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765124789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_random_zero_del ays.3765124789 |
| Directory | /workspace/18.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_same_source.2660601232 |
| Short name | T2068 |
| Test name | |
| Test status | |
| Simulation time | 158173288 ps |
| CPU time | 13.36 seconds |
| Started | Aug 17 06:48:16 PM PDT 24 |
| Finished | Aug 17 06:48:29 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-738d018a-197a-4734-b3f1-df329bc59cb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660601232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_same_source.2660601232 |
| Directory | /workspace/18.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke.333763013 |
| Short name | T2202 |
| Test name | |
| Test status | |
| Simulation time | 214124567 ps |
| CPU time | 9.51 seconds |
| Started | Aug 17 06:48:19 PM PDT 24 |
| Finished | Aug 17 06:48:29 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-3a37ba82-5801-426c-be82-9a112f0fd73e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=333763013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke.333763013 |
| Directory | /workspace/18.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_large_delays.4182298382 |
| Short name | T2323 |
| Test name | |
| Test status | |
| Simulation time | 8585469573 ps |
| CPU time | 91 seconds |
| Started | Aug 17 06:48:16 PM PDT 24 |
| Finished | Aug 17 06:49:47 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-f7dde7c7-76be-4af4-8b02-607842866e5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182298382 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_large_delays.4182298382 |
| Directory | /workspace/18.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_slow_rsp.1955518094 |
| Short name | T1470 |
| Test name | |
| Test status | |
| Simulation time | 4246084910 ps |
| CPU time | 68.86 seconds |
| Started | Aug 17 06:48:15 PM PDT 24 |
| Finished | Aug 17 06:49:24 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-f013ccb2-bd9a-4a80-bca7-97f518b4c830 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955518094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_slow_rsp.1955518094 |
| Directory | /workspace/18.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_smoke_zero_delays.1356946930 |
| Short name | T2832 |
| Test name | |
| Test status | |
| Simulation time | 49792084 ps |
| CPU time | 6.65 seconds |
| Started | Aug 17 06:48:14 PM PDT 24 |
| Finished | Aug 17 06:48:21 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-6d772fcd-0b0d-46bc-a676-c34ebc762669 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1356946930 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_smoke_zero_delay s.1356946930 |
| Directory | /workspace/18.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all.583060697 |
| Short name | T2352 |
| Test name | |
| Test status | |
| Simulation time | 9455195714 ps |
| CPU time | 335.6 seconds |
| Started | Aug 17 06:48:13 PM PDT 24 |
| Finished | Aug 17 06:53:49 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-d9fae46c-e7d3-434b-802a-09200e63e108 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583060697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all.583060697 |
| Directory | /workspace/18.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_error.1773734871 |
| Short name | T2001 |
| Test name | |
| Test status | |
| Simulation time | 13295223258 ps |
| CPU time | 446.28 seconds |
| Started | Aug 17 06:48:11 PM PDT 24 |
| Finished | Aug 17 06:55:38 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-ff6e0fb3-dbb2-48e1-8cda-983726e2faee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773734871 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all_with_error.1773734871 |
| Directory | /workspace/18.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_stress_all_with_rand_reset.1946480756 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 409409505 ps |
| CPU time | 141.99 seconds |
| Started | Aug 17 06:48:13 PM PDT 24 |
| Finished | Aug 17 06:50:35 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-c70b85ec-8073-4858-b93e-663a0b401e59 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946480756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_stress_all _with_rand_reset.1946480756 |
| Directory | /workspace/18.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/18.xbar_unmapped_addr.3954223348 |
| Short name | T1943 |
| Test name | |
| Test status | |
| Simulation time | 209487305 ps |
| CPU time | 25.33 seconds |
| Started | Aug 17 06:48:13 PM PDT 24 |
| Finished | Aug 17 06:48:38 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-d2170ad4-49bc-4e55-bb97-87b634df41dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954223348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.xbar_unmapped_addr.3954223348 |
| Directory | /workspace/18.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_mem_rw_with_rand_reset.4065746209 |
| Short name | T2358 |
| Test name | |
| Test status | |
| Simulation time | 5708883098 ps |
| CPU time | 471.26 seconds |
| Started | Aug 17 06:48:36 PM PDT 24 |
| Finished | Aug 17 06:56:28 PM PDT 24 |
| Peak memory | 638272 kb |
| Host | smart-60ac835e-154a-40c5-8a00-6ba0925dfafb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4065746209 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 19.chip_csr_mem_rw_with_rand_reset.4065746209 |
| Directory | /workspace/19.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_csr_rw.2091608422 |
| Short name | T2547 |
| Test name | |
| Test status | |
| Simulation time | 3927643674 ps |
| CPU time | 307.56 seconds |
| Started | Aug 17 06:48:35 PM PDT 24 |
| Finished | Aug 17 06:53:43 PM PDT 24 |
| Peak memory | 598000 kb |
| Host | smart-dd51cdf0-6577-4923-887c-65c54a50e734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091608422 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_csr_rw.2091608422 |
| Directory | /workspace/19.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/19.chip_tl_errors.2595041006 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 3838829314 ps |
| CPU time | 212.92 seconds |
| Started | Aug 17 06:48:21 PM PDT 24 |
| Finished | Aug 17 06:51:54 PM PDT 24 |
| Peak memory | 603904 kb |
| Host | smart-5361d838-4b7a-4c62-826e-0e3bb7f0e553 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595041006 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.chip_tl_errors.2595041006 |
| Directory | /workspace/19.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device.1493597068 |
| Short name | T1770 |
| Test name | |
| Test status | |
| Simulation time | 1176982096 ps |
| CPU time | 47.12 seconds |
| Started | Aug 17 06:48:28 PM PDT 24 |
| Finished | Aug 17 06:49:16 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-7d06c6bf-6283-4ed0-bc95-b3ed2d6bfe3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493597068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_device .1493597068 |
| Directory | /workspace/19.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_access_same_device_slow_rsp.3862593999 |
| Short name | T2631 |
| Test name | |
| Test status | |
| Simulation time | 71043497522 ps |
| CPU time | 1258.87 seconds |
| Started | Aug 17 06:48:24 PM PDT 24 |
| Finished | Aug 17 07:09:23 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-113547ba-db09-4139-878c-fae4c0f03ac7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862593999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_access_same_ device_slow_rsp.3862593999 |
| Directory | /workspace/19.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_and_unmapped_addr.2168365517 |
| Short name | T1634 |
| Test name | |
| Test status | |
| Simulation time | 81919097 ps |
| CPU time | 6.26 seconds |
| Started | Aug 17 06:48:39 PM PDT 24 |
| Finished | Aug 17 06:48:46 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-f401a8c1-0dfe-4753-b338-7b1dcf885ff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168365517 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_and_unmapped_add r.2168365517 |
| Directory | /workspace/19.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_error_random.587896440 |
| Short name | T1815 |
| Test name | |
| Test status | |
| Simulation time | 2712754750 ps |
| CPU time | 99.52 seconds |
| Started | Aug 17 06:48:28 PM PDT 24 |
| Finished | Aug 17 06:50:08 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-b718113a-0c4e-4911-8efc-d4b9b51237e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=587896440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_error_random.587896440 |
| Directory | /workspace/19.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random.467861689 |
| Short name | T1813 |
| Test name | |
| Test status | |
| Simulation time | 947326999 ps |
| CPU time | 33.13 seconds |
| Started | Aug 17 06:48:22 PM PDT 24 |
| Finished | Aug 17 06:48:55 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-47bdd15f-57e4-4a0a-ac45-4ec4af5fd2b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=467861689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random.467861689 |
| Directory | /workspace/19.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_large_delays.3968951722 |
| Short name | T2683 |
| Test name | |
| Test status | |
| Simulation time | 46916187164 ps |
| CPU time | 528.1 seconds |
| Started | Aug 17 06:48:30 PM PDT 24 |
| Finished | Aug 17 06:57:18 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-5d3d39a2-b909-4dad-b1a1-070a60630c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968951722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_large_delays.3968951722 |
| Directory | /workspace/19.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.1279315019 |
| Short name | T2433 |
| Test name | |
| Test status | |
| Simulation time | 61530699393 ps |
| CPU time | 1131.12 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 07:07:17 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-535abf66-d7b1-461f-9856-7bdf0fc51737 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279315019 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_slow_rsp.1279315019 |
| Directory | /workspace/19.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_random_zero_delays.3030552111 |
| Short name | T2268 |
| Test name | |
| Test status | |
| Simulation time | 483498269 ps |
| CPU time | 44.27 seconds |
| Started | Aug 17 06:48:25 PM PDT 24 |
| Finished | Aug 17 06:49:09 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-0a944ec1-48bd-45a7-8cb8-8abe2e87ce6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030552111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_random_zero_del ays.3030552111 |
| Directory | /workspace/19.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_same_source.457682658 |
| Short name | T2470 |
| Test name | |
| Test status | |
| Simulation time | 568181493 ps |
| CPU time | 17.9 seconds |
| Started | Aug 17 06:48:26 PM PDT 24 |
| Finished | Aug 17 06:48:43 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-a135c06e-50f4-4017-a741-9e77854be67f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457682658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_same_source.457682658 |
| Directory | /workspace/19.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke.4288916579 |
| Short name | T2872 |
| Test name | |
| Test status | |
| Simulation time | 142007806 ps |
| CPU time | 7.86 seconds |
| Started | Aug 17 06:48:19 PM PDT 24 |
| Finished | Aug 17 06:48:27 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-0f5d2377-7783-4996-a85c-4965e92deb45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288916579 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke.4288916579 |
| Directory | /workspace/19.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_large_delays.1996004232 |
| Short name | T2133 |
| Test name | |
| Test status | |
| Simulation time | 8944354050 ps |
| CPU time | 94.44 seconds |
| Started | Aug 17 06:48:17 PM PDT 24 |
| Finished | Aug 17 06:49:52 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-a9fe1016-e1b2-4a34-bb72-0d4038a58bd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996004232 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_large_delays.1996004232 |
| Directory | /workspace/19.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.3198088116 |
| Short name | T1659 |
| Test name | |
| Test status | |
| Simulation time | 4387545715 ps |
| CPU time | 81.74 seconds |
| Started | Aug 17 06:48:23 PM PDT 24 |
| Finished | Aug 17 06:49:45 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-735a687d-530c-4935-8439-f6af1d1fe179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3198088116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_slow_rsp.3198088116 |
| Directory | /workspace/19.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_smoke_zero_delays.3461744575 |
| Short name | T1561 |
| Test name | |
| Test status | |
| Simulation time | 51351954 ps |
| CPU time | 6.58 seconds |
| Started | Aug 17 06:48:18 PM PDT 24 |
| Finished | Aug 17 06:48:25 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-313d2e8e-67f4-4f88-8cab-d7c33a2f3073 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461744575 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_smoke_zero_delay s.3461744575 |
| Directory | /workspace/19.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all.1838363174 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 1528944121 ps |
| CPU time | 121.76 seconds |
| Started | Aug 17 06:48:35 PM PDT 24 |
| Finished | Aug 17 06:50:37 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-a8651d13-ebf7-4a01-ab32-0eac7459c758 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1838363174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all.1838363174 |
| Directory | /workspace/19.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_error.88890694 |
| Short name | T1861 |
| Test name | |
| Test status | |
| Simulation time | 854760800 ps |
| CPU time | 66.12 seconds |
| Started | Aug 17 06:48:35 PM PDT 24 |
| Finished | Aug 17 06:49:41 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a16f1b1c-1cef-496e-93d8-c9d7a1d91af4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88890694 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all_with_error.88890694 |
| Directory | /workspace/19.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_rand_reset.1126751615 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 532447775 ps |
| CPU time | 179.59 seconds |
| Started | Aug 17 06:48:37 PM PDT 24 |
| Finished | Aug 17 06:51:36 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-57078267-6e18-44ba-8909-e09e1edd3fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126751615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_all _with_rand_reset.1126751615 |
| Directory | /workspace/19.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_stress_all_with_reset_error.3877009562 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 743592656 ps |
| CPU time | 75.51 seconds |
| Started | Aug 17 06:48:37 PM PDT 24 |
| Finished | Aug 17 06:49:53 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-6917ce90-fec2-4faa-b879-5dbe0e8bd871 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3877009562 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_stress_al l_with_reset_error.3877009562 |
| Directory | /workspace/19.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/19.xbar_unmapped_addr.391665558 |
| Short name | T1665 |
| Test name | |
| Test status | |
| Simulation time | 891490853 ps |
| CPU time | 39.69 seconds |
| Started | Aug 17 06:48:25 PM PDT 24 |
| Finished | Aug 17 06:49:05 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-14c1d238-961a-467e-899c-351a5654d9b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391665558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.xbar_unmapped_addr.391665558 |
| Directory | /workspace/19.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_aliasing.3376475988 |
| Short name | T1979 |
| Test name | |
| Test status | |
| Simulation time | 38093216084 ps |
| CPU time | 5923.64 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 08:26:15 PM PDT 24 |
| Peak memory | 596628 kb |
| Host | smart-e5bd6acc-550a-4227-a92a-085955105133 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376475988 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 2.chip_csr_aliasing.3376475988 |
| Directory | /workspace/2.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.1025682676 |
| Short name | T2731 |
| Test name | |
| Test status | |
| Simulation time | 6972594113 ps |
| CPU time | 677.24 seconds |
| Started | Aug 17 06:47:28 PM PDT 24 |
| Finished | Aug 17 06:58:46 PM PDT 24 |
| Peak memory | 597680 kb |
| Host | smart-de35e6ff-b6a1-466a-bf6c-01ac12ff28e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025682676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 2.chip_csr_bit_bash.1025682676 |
| Directory | /workspace/2.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_mem_rw_with_rand_reset.4074647071 |
| Short name | T1741 |
| Test name | |
| Test status | |
| Simulation time | 12660225802 ps |
| CPU time | 861.23 seconds |
| Started | Aug 17 06:47:36 PM PDT 24 |
| Finished | Aug 17 07:01:58 PM PDT 24 |
| Peak memory | 652584 kb |
| Host | smart-af6e1a14-193d-4ba2-954b-75e69c7ae10b |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074647071 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 2.chip_csr_mem_rw_with_rand_reset.4074647071 |
| Directory | /workspace/2.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_csr_rw.881858543 |
| Short name | T1667 |
| Test name | |
| Test status | |
| Simulation time | 3871664724 ps |
| CPU time | 316.12 seconds |
| Started | Aug 17 06:47:38 PM PDT 24 |
| Finished | Aug 17 06:52:54 PM PDT 24 |
| Peak memory | 597720 kb |
| Host | smart-6e27d7de-ef03-48d5-9cb8-5351a108f8c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881858543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_csr_rw.881858543 |
| Directory | /workspace/2.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_prim_tl_access.2374980311 |
| Short name | T2665 |
| Test name | |
| Test status | |
| Simulation time | 3923193525 ps |
| CPU time | 135.2 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 06:49:46 PM PDT 24 |
| Peak memory | 589472 kb |
| Host | smart-dc6acb51-a972-4da5-b4e0-782d3d4a77c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374980311 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_prim_tl_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_prim_tl_access.2374980311 |
| Directory | /workspace/2.chip_prim_tl_access/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.166814798 |
| Short name | T2330 |
| Test name | |
| Test status | |
| Simulation time | 16570486161 ps |
| CPU time | 586.05 seconds |
| Started | Aug 17 06:47:28 PM PDT 24 |
| Finished | Aug 17 06:57:14 PM PDT 24 |
| Peak memory | 591192 kb |
| Host | smart-5ec4657c-13f9-4cc7-8068-ca8548671367 |
| User | root |
| Command | /workspace/cover_reg_top/simv +en_scb=0 +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSIT Y=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166814798 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_rv_dm_lc_disabled_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log / dev/null -cm_name 2.chip_rv_dm_lc_disabled.166814798 |
| Directory | /workspace/2.chip_rv_dm_lc_disabled/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_same_csr_outstanding.2516555976 |
| Short name | T2169 |
| Test name | |
| Test status | |
| Simulation time | 15725796941 ps |
| CPU time | 2546.41 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 07:29:57 PM PDT 24 |
| Peak memory | 593064 kb |
| Host | smart-79a992a2-cfba-4bbd-ae6d-30d585840f7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516555976 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 2.chip_same_csr_outstanding.2516555976 |
| Directory | /workspace/2.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/2.chip_tl_errors.3013788591 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 3379805764 ps |
| CPU time | 79.39 seconds |
| Started | Aug 17 06:47:28 PM PDT 24 |
| Finished | Aug 17 06:48:47 PM PDT 24 |
| Peak memory | 603920 kb |
| Host | smart-0bc4da88-3230-479e-b49c-9172363f4e85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013788591 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.chip_tl_errors.3013788591 |
| Directory | /workspace/2.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device.3874096936 |
| Short name | T2650 |
| Test name | |
| Test status | |
| Simulation time | 412801472 ps |
| CPU time | 31.78 seconds |
| Started | Aug 17 06:47:24 PM PDT 24 |
| Finished | Aug 17 06:47:55 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-a90adfbb-6f5e-4b73-8995-e4a853fd2ad9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874096936 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_device. 3874096936 |
| Directory | /workspace/2.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_access_same_device_slow_rsp.3983670205 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 57675546887 ps |
| CPU time | 948.74 seconds |
| Started | Aug 17 06:47:37 PM PDT 24 |
| Finished | Aug 17 07:03:26 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-a0df2224-7985-4132-9591-1f8066c582ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983670205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_access_same_d evice_slow_rsp.3983670205 |
| Directory | /workspace/2.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_and_unmapped_addr.2624006253 |
| Short name | T1415 |
| Test name | |
| Test status | |
| Simulation time | 778759966 ps |
| CPU time | 29.16 seconds |
| Started | Aug 17 06:47:25 PM PDT 24 |
| Finished | Aug 17 06:47:54 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-02d5b998-080e-46eb-a3e5-4c51815807cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624006253 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_and_unmapped_addr .2624006253 |
| Directory | /workspace/2.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_error_random.1136106585 |
| Short name | T1643 |
| Test name | |
| Test status | |
| Simulation time | 512716698 ps |
| CPU time | 18.22 seconds |
| Started | Aug 17 06:47:26 PM PDT 24 |
| Finished | Aug 17 06:47:44 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-07e0d4c6-f1dd-4f1e-9395-f20c024d7602 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136106585 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_error_random.1136106585 |
| Directory | /workspace/2.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random.1304063614 |
| Short name | T2080 |
| Test name | |
| Test status | |
| Simulation time | 244493575 ps |
| CPU time | 21.95 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:47:53 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-5362a98d-8aa7-422c-91af-ecf84a4d57d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304063614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random.1304063614 |
| Directory | /workspace/2.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_large_delays.2624625784 |
| Short name | T1527 |
| Test name | |
| Test status | |
| Simulation time | 117717649580 ps |
| CPU time | 1333.03 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 07:09:43 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-2e995411-3493-4479-a4b3-5286569ad6c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624625784 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_large_delays.2624625784 |
| Directory | /workspace/2.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_slow_rsp.2428758685 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 43376388043 ps |
| CPU time | 729.55 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:59:40 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-429a2678-edee-463a-ac30-f8597a865505 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428758685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_slow_rsp.2428758685 |
| Directory | /workspace/2.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_random_zero_delays.1664715421 |
| Short name | T1949 |
| Test name | |
| Test status | |
| Simulation time | 209381594 ps |
| CPU time | 18.08 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:47:51 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-50696acc-2079-4fe6-97ad-392e880bbbf7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664715421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_random_zero_dela ys.1664715421 |
| Directory | /workspace/2.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_same_source.3541477092 |
| Short name | T2238 |
| Test name | |
| Test status | |
| Simulation time | 1811729028 ps |
| CPU time | 49.29 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:48:22 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-36bbd8cb-ac57-4eed-a408-daaebf4533ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541477092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_same_source.3541477092 |
| Directory | /workspace/2.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke.3677307070 |
| Short name | T2381 |
| Test name | |
| Test status | |
| Simulation time | 207270203 ps |
| CPU time | 8.57 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 06:47:38 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-f2e1fc81-4300-4e14-93c0-1ca33bf1edd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677307070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke.3677307070 |
| Directory | /workspace/2.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_large_delays.645893327 |
| Short name | T1963 |
| Test name | |
| Test status | |
| Simulation time | 9388983587 ps |
| CPU time | 105.32 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 06:49:15 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-2fdddf18-ab47-46ea-a4de-1023b36e91ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645893327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_large_delays.645893327 |
| Directory | /workspace/2.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_slow_rsp.2884641657 |
| Short name | T1624 |
| Test name | |
| Test status | |
| Simulation time | 4735973919 ps |
| CPU time | 69.63 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:48:42 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-daf8654c-73d7-4f07-98e0-238c4bc538b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884641657 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_slow_rsp.2884641657 |
| Directory | /workspace/2.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_smoke_zero_delays.3810497445 |
| Short name | T2932 |
| Test name | |
| Test status | |
| Simulation time | 54112752 ps |
| CPU time | 6.44 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 06:47:39 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-df22e7e9-77bf-4ae5-abbe-4cca90d63ebd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810497445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_smoke_zero_delays .3810497445 |
| Directory | /workspace/2.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all.3041218505 |
| Short name | T2700 |
| Test name | |
| Test status | |
| Simulation time | 4107887494 ps |
| CPU time | 349.71 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:53:21 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-d54e0ebe-40e2-4099-97fb-7ffc06efd733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041218505 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all.3041218505 |
| Directory | /workspace/2.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_error.811707440 |
| Short name | T2566 |
| Test name | |
| Test status | |
| Simulation time | 3976224924 ps |
| CPU time | 153.17 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 06:50:07 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-b50fa23f-3bc9-4b2d-9489-2f24e2858ffe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811707440 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_with_error.811707440 |
| Directory | /workspace/2.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_stress_all_with_rand_reset.361283958 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 792189073 ps |
| CPU time | 269.87 seconds |
| Started | Aug 17 06:47:28 PM PDT 24 |
| Finished | Aug 17 06:51:58 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-49fe1466-1204-4c59-a2ff-20d32358189d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361283958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_stress_all_w ith_rand_reset.361283958 |
| Directory | /workspace/2.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/2.xbar_unmapped_addr.3959835676 |
| Short name | T2582 |
| Test name | |
| Test status | |
| Simulation time | 578251848 ps |
| CPU time | 24.75 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:47:58 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-b37f33b9-d07d-46a4-b97b-c17c8d8f5355 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3959835676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.xbar_unmapped_addr.3959835676 |
| Directory | /workspace/2.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device.2282326412 |
| Short name | T2734 |
| Test name | |
| Test status | |
| Simulation time | 511327727 ps |
| CPU time | 21.42 seconds |
| Started | Aug 17 06:48:46 PM PDT 24 |
| Finished | Aug 17 06:49:07 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-6576763c-7b66-4062-afbc-f92c99e78442 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282326412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_device .2282326412 |
| Directory | /workspace/20.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_access_same_device_slow_rsp.797878910 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 48668787133 ps |
| CPU time | 808.76 seconds |
| Started | Aug 17 06:48:52 PM PDT 24 |
| Finished | Aug 17 07:02:21 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-e7c278fc-74e9-443c-97f9-4ca94758b384 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797878910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_access_same_d evice_slow_rsp.797878910 |
| Directory | /workspace/20.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.2162149541 |
| Short name | T2032 |
| Test name | |
| Test status | |
| Simulation time | 128149698 ps |
| CPU time | 14.92 seconds |
| Started | Aug 17 06:48:44 PM PDT 24 |
| Finished | Aug 17 06:48:59 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-aa65e1cd-df94-4795-bec0-52453fee2725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162149541 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_and_unmapped_add r.2162149541 |
| Directory | /workspace/20.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_error_random.4261738269 |
| Short name | T1871 |
| Test name | |
| Test status | |
| Simulation time | 641531533 ps |
| CPU time | 23.71 seconds |
| Started | Aug 17 06:48:43 PM PDT 24 |
| Finished | Aug 17 06:49:07 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-df2408c6-7040-4200-9e0f-73a370127f54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261738269 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_error_random.4261738269 |
| Directory | /workspace/20.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random.3902838054 |
| Short name | T1554 |
| Test name | |
| Test status | |
| Simulation time | 2110614410 ps |
| CPU time | 77.49 seconds |
| Started | Aug 17 06:48:44 PM PDT 24 |
| Finished | Aug 17 06:50:02 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-dbc476cb-70eb-438e-a4e0-3885120356df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3902838054 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random.3902838054 |
| Directory | /workspace/20.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_large_delays.3743868024 |
| Short name | T1382 |
| Test name | |
| Test status | |
| Simulation time | 60037731098 ps |
| CPU time | 646.95 seconds |
| Started | Aug 17 06:48:44 PM PDT 24 |
| Finished | Aug 17 06:59:32 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-a71ce8d8-ccec-450e-be4a-7561152c1b2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743868024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_large_delays.3743868024 |
| Directory | /workspace/20.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_slow_rsp.388870864 |
| Short name | T2402 |
| Test name | |
| Test status | |
| Simulation time | 33037535993 ps |
| CPU time | 541.63 seconds |
| Started | Aug 17 06:48:48 PM PDT 24 |
| Finished | Aug 17 06:57:50 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-7012dc12-032b-4f7e-be4e-f10dfbc67b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388870864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_slow_rsp.388870864 |
| Directory | /workspace/20.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_random_zero_delays.904259053 |
| Short name | T2649 |
| Test name | |
| Test status | |
| Simulation time | 291883201 ps |
| CPU time | 24.3 seconds |
| Started | Aug 17 06:48:47 PM PDT 24 |
| Finished | Aug 17 06:49:11 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-5b28d42d-e2ce-4464-8ff8-53747e32e321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904259053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_random_zero_dela ys.904259053 |
| Directory | /workspace/20.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_same_source.3568714142 |
| Short name | T2517 |
| Test name | |
| Test status | |
| Simulation time | 196624268 ps |
| CPU time | 14.65 seconds |
| Started | Aug 17 06:48:46 PM PDT 24 |
| Finished | Aug 17 06:49:00 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-221939bf-62c2-4f39-a051-8bb08ec1a49c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568714142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_same_source.3568714142 |
| Directory | /workspace/20.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke.2018334067 |
| Short name | T2675 |
| Test name | |
| Test status | |
| Simulation time | 255810513 ps |
| CPU time | 9.33 seconds |
| Started | Aug 17 06:48:35 PM PDT 24 |
| Finished | Aug 17 06:48:45 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-3654d918-d7a2-4dfb-be78-c0b3606c31f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018334067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke.2018334067 |
| Directory | /workspace/20.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_large_delays.443453039 |
| Short name | T2537 |
| Test name | |
| Test status | |
| Simulation time | 8221175997 ps |
| CPU time | 84.65 seconds |
| Started | Aug 17 06:48:43 PM PDT 24 |
| Finished | Aug 17 06:50:07 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-665cdd02-caef-47a4-8419-d7db71396953 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=443453039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_large_delays.443453039 |
| Directory | /workspace/20.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_slow_rsp.3023176404 |
| Short name | T2710 |
| Test name | |
| Test status | |
| Simulation time | 6528729308 ps |
| CPU time | 110.79 seconds |
| Started | Aug 17 06:48:46 PM PDT 24 |
| Finished | Aug 17 06:50:37 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-4aa570e2-d0e2-4fb1-a79a-b99d8e77074a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023176404 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_slow_rsp.3023176404 |
| Directory | /workspace/20.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3915755485 |
| Short name | T2348 |
| Test name | |
| Test status | |
| Simulation time | 55910893 ps |
| CPU time | 6.25 seconds |
| Started | Aug 17 06:48:39 PM PDT 24 |
| Finished | Aug 17 06:48:46 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-1df1f7a3-f080-42b5-a6a9-6205254a60e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915755485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_smoke_zero_delay s.3915755485 |
| Directory | /workspace/20.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all.3853342570 |
| Short name | T2253 |
| Test name | |
| Test status | |
| Simulation time | 8150789606 ps |
| CPU time | 299.45 seconds |
| Started | Aug 17 06:48:48 PM PDT 24 |
| Finished | Aug 17 06:53:48 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-66b2c646-fb04-462c-9034-5cf0a2c4cd35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853342570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all.3853342570 |
| Directory | /workspace/20.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_error.274764384 |
| Short name | T1737 |
| Test name | |
| Test status | |
| Simulation time | 6414142 ps |
| CPU time | 3.88 seconds |
| Started | Aug 17 06:48:43 PM PDT 24 |
| Finished | Aug 17 06:48:47 PM PDT 24 |
| Peak memory | 565632 kb |
| Host | smart-d674a4fa-4491-485f-85f5-08df0debe607 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=274764384 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all_with_error.274764384 |
| Directory | /workspace/20.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_rand_reset.2254604128 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 975898512 ps |
| CPU time | 130.5 seconds |
| Started | Aug 17 06:48:46 PM PDT 24 |
| Finished | Aug 17 06:50:56 PM PDT 24 |
| Peak memory | 576168 kb |
| Host | smart-96801dfe-cd36-49da-8908-9f266570179e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254604128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_all _with_rand_reset.2254604128 |
| Directory | /workspace/20.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_stress_all_with_reset_error.3616731324 |
| Short name | T1924 |
| Test name | |
| Test status | |
| Simulation time | 10145283 ps |
| CPU time | 9.27 seconds |
| Started | Aug 17 06:48:44 PM PDT 24 |
| Finished | Aug 17 06:48:53 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-85cd12a1-de55-419e-a532-54d3b3585a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616731324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_stress_al l_with_reset_error.3616731324 |
| Directory | /workspace/20.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/20.xbar_unmapped_addr.1790770850 |
| Short name | T1896 |
| Test name | |
| Test status | |
| Simulation time | 1050948501 ps |
| CPU time | 43.82 seconds |
| Started | Aug 17 06:48:42 PM PDT 24 |
| Finished | Aug 17 06:49:26 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-fbf536b2-550f-41f8-b857-225f0f3e9c55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790770850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.xbar_unmapped_addr.1790770850 |
| Directory | /workspace/20.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_access_same_device.3443924004 |
| Short name | T1964 |
| Test name | |
| Test status | |
| Simulation time | 1631753565 ps |
| CPU time | 58.16 seconds |
| Started | Aug 17 06:48:56 PM PDT 24 |
| Finished | Aug 17 06:49:54 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-13f6a62e-dffb-4118-b84f-9c80a4e7163e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3443924004 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_access_same_device .3443924004 |
| Directory | /workspace/21.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_and_unmapped_addr.2638487825 |
| Short name | T1432 |
| Test name | |
| Test status | |
| Simulation time | 1087652299 ps |
| CPU time | 42.85 seconds |
| Started | Aug 17 06:48:55 PM PDT 24 |
| Finished | Aug 17 06:49:38 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-810fea4a-2920-4906-8891-30ec8c6bc6f5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638487825 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_and_unmapped_add r.2638487825 |
| Directory | /workspace/21.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_error_random.3032238886 |
| Short name | T2192 |
| Test name | |
| Test status | |
| Simulation time | 2388947228 ps |
| CPU time | 82.87 seconds |
| Started | Aug 17 06:48:55 PM PDT 24 |
| Finished | Aug 17 06:50:18 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-68b4e2dc-576a-4c66-87dc-beab93f06563 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032238886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_error_random.3032238886 |
| Directory | /workspace/21.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random.2746052289 |
| Short name | T1580 |
| Test name | |
| Test status | |
| Simulation time | 64550244 ps |
| CPU time | 8.02 seconds |
| Started | Aug 17 06:48:46 PM PDT 24 |
| Finished | Aug 17 06:48:54 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-7301e7e0-9faa-4ddb-8355-12d3e946eb02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746052289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random.2746052289 |
| Directory | /workspace/21.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_large_delays.3121168753 |
| Short name | T1421 |
| Test name | |
| Test status | |
| Simulation time | 35357034485 ps |
| CPU time | 353.95 seconds |
| Started | Aug 17 06:48:50 PM PDT 24 |
| Finished | Aug 17 06:54:44 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-eed51ad5-df06-4a61-b4fb-63f65be9f206 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121168753 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_large_delays.3121168753 |
| Directory | /workspace/21.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_slow_rsp.983212133 |
| Short name | T2875 |
| Test name | |
| Test status | |
| Simulation time | 42013966074 ps |
| CPU time | 714.85 seconds |
| Started | Aug 17 06:48:54 PM PDT 24 |
| Finished | Aug 17 07:00:49 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-387ab4dc-7cc3-4712-8757-00affa41006a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983212133 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_slow_rsp.983212133 |
| Directory | /workspace/21.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_random_zero_delays.3153592844 |
| Short name | T2056 |
| Test name | |
| Test status | |
| Simulation time | 408195576 ps |
| CPU time | 39.43 seconds |
| Started | Aug 17 06:48:56 PM PDT 24 |
| Finished | Aug 17 06:49:36 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-e31d5f25-e8f8-4afc-a1a7-42d3d43235e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153592844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_random_zero_del ays.3153592844 |
| Directory | /workspace/21.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_same_source.213421339 |
| Short name | T2177 |
| Test name | |
| Test status | |
| Simulation time | 57243328 ps |
| CPU time | 7.31 seconds |
| Started | Aug 17 06:48:52 PM PDT 24 |
| Finished | Aug 17 06:49:00 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-3800ec7f-01f9-4a06-a820-17acfec3f251 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213421339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_same_source.213421339 |
| Directory | /workspace/21.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke.1456953017 |
| Short name | T2471 |
| Test name | |
| Test status | |
| Simulation time | 173577652 ps |
| CPU time | 8.07 seconds |
| Started | Aug 17 06:48:44 PM PDT 24 |
| Finished | Aug 17 06:48:52 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-1601531d-cae8-4610-976f-d261b514b399 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456953017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke.1456953017 |
| Directory | /workspace/21.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_large_delays.291379216 |
| Short name | T1807 |
| Test name | |
| Test status | |
| Simulation time | 7436752480 ps |
| CPU time | 76.13 seconds |
| Started | Aug 17 06:48:45 PM PDT 24 |
| Finished | Aug 17 06:50:01 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-ca9c0465-5d35-44a8-a18b-00aec62fecc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291379216 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_large_delays.291379216 |
| Directory | /workspace/21.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_slow_rsp.2750252840 |
| Short name | T2905 |
| Test name | |
| Test status | |
| Simulation time | 7276288433 ps |
| CPU time | 122.96 seconds |
| Started | Aug 17 06:48:44 PM PDT 24 |
| Finished | Aug 17 06:50:47 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-834296f9-dff0-42a3-9d12-00a88e50c19a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750252840 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_slow_rsp.2750252840 |
| Directory | /workspace/21.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.2927634281 |
| Short name | T1819 |
| Test name | |
| Test status | |
| Simulation time | 43684421 ps |
| CPU time | 6.01 seconds |
| Started | Aug 17 06:48:43 PM PDT 24 |
| Finished | Aug 17 06:48:49 PM PDT 24 |
| Peak memory | 573368 kb |
| Host | smart-f80463a3-befa-41d2-a9ab-fbea156e2291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927634281 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_smoke_zero_delay s.2927634281 |
| Directory | /workspace/21.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all.188341475 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 1333189357 ps |
| CPU time | 112.15 seconds |
| Started | Aug 17 06:48:52 PM PDT 24 |
| Finished | Aug 17 06:50:44 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-009e67d9-e852-417b-82d7-5621eae7e577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188341475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all.188341475 |
| Directory | /workspace/21.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_error.1520601652 |
| Short name | T2459 |
| Test name | |
| Test status | |
| Simulation time | 6525510529 ps |
| CPU time | 301.01 seconds |
| Started | Aug 17 06:48:53 PM PDT 24 |
| Finished | Aug 17 06:53:54 PM PDT 24 |
| Peak memory | 575748 kb |
| Host | smart-05437b0f-5b7f-4397-bc8f-9ff6015ca73d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520601652 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all_with_error.1520601652 |
| Directory | /workspace/21.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_rand_reset.3366646091 |
| Short name | T2418 |
| Test name | |
| Test status | |
| Simulation time | 2110559598 ps |
| CPU time | 260.34 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:53:20 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-6edb9922-b723-467e-b407-9f8ef33c43bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366646091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_rand_reset.3366646091 |
| Directory | /workspace/21.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_stress_all_with_reset_error.116078235 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 217719217 ps |
| CPU time | 63.99 seconds |
| Started | Aug 17 06:48:55 PM PDT 24 |
| Finished | Aug 17 06:49:59 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-a41149d7-40c1-4cc6-b71c-fc43821d7e68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116078235 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_stress_all _with_reset_error.116078235 |
| Directory | /workspace/21.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/21.xbar_unmapped_addr.840810947 |
| Short name | T1972 |
| Test name | |
| Test status | |
| Simulation time | 510184374 ps |
| CPU time | 23.39 seconds |
| Started | Aug 17 06:48:51 PM PDT 24 |
| Finished | Aug 17 06:49:15 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-5f5fc4a5-c37d-4557-8a2f-f7f1f155117d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840810947 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.xbar_unmapped_addr.840810947 |
| Directory | /workspace/21.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.chip_tl_errors.3294065296 |
| Short name | T2286 |
| Test name | |
| Test status | |
| Simulation time | 5287511495 ps |
| CPU time | 416.15 seconds |
| Started | Aug 17 06:48:51 PM PDT 24 |
| Finished | Aug 17 06:55:47 PM PDT 24 |
| Peak memory | 603840 kb |
| Host | smart-51921c99-7654-4ee5-a3b1-40b448497a48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294065296 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.chip_tl_errors.3294065296 |
| Directory | /workspace/22.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device.3600212013 |
| Short name | T1913 |
| Test name | |
| Test status | |
| Simulation time | 571224695 ps |
| CPU time | 23.69 seconds |
| Started | Aug 17 06:48:58 PM PDT 24 |
| Finished | Aug 17 06:49:22 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-fe71c8db-4194-44f7-9f5c-81a2bcfe88d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600212013 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_device .3600212013 |
| Directory | /workspace/22.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_access_same_device_slow_rsp.4120582608 |
| Short name | T2678 |
| Test name | |
| Test status | |
| Simulation time | 96560931452 ps |
| CPU time | 1719.32 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 07:17:41 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-2a8ca2d4-dec7-4caf-88e7-8bd7fa7a132d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120582608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_access_same_ device_slow_rsp.4120582608 |
| Directory | /workspace/22.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_and_unmapped_addr.1491490607 |
| Short name | T2852 |
| Test name | |
| Test status | |
| Simulation time | 1237838081 ps |
| CPU time | 50 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:49:51 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-ef2d22c0-2fa1-46e6-b47e-84ea7ac380dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491490607 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_and_unmapped_add r.1491490607 |
| Directory | /workspace/22.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_error_random.507033208 |
| Short name | T2199 |
| Test name | |
| Test status | |
| Simulation time | 711465924 ps |
| CPU time | 25.18 seconds |
| Started | Aug 17 06:48:58 PM PDT 24 |
| Finished | Aug 17 06:49:23 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-b150baf1-ea9c-4514-9d96-024262b6980d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507033208 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_error_random.507033208 |
| Directory | /workspace/22.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random.1008629965 |
| Short name | T2845 |
| Test name | |
| Test status | |
| Simulation time | 563336128 ps |
| CPU time | 23.49 seconds |
| Started | Aug 17 06:48:51 PM PDT 24 |
| Finished | Aug 17 06:49:14 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-799de5ce-ce91-4fbd-a09e-ea0cfc86a729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008629965 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random.1008629965 |
| Directory | /workspace/22.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_large_delays.1188733500 |
| Short name | T2755 |
| Test name | |
| Test status | |
| Simulation time | 57055936986 ps |
| CPU time | 578.66 seconds |
| Started | Aug 17 06:48:51 PM PDT 24 |
| Finished | Aug 17 06:58:30 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-840eb97d-058c-4edf-8e31-b9dd39af7666 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188733500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_large_delays.1188733500 |
| Directory | /workspace/22.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_slow_rsp.2448491607 |
| Short name | T2461 |
| Test name | |
| Test status | |
| Simulation time | 57806314397 ps |
| CPU time | 963.77 seconds |
| Started | Aug 17 06:48:58 PM PDT 24 |
| Finished | Aug 17 07:05:02 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-46fae597-1b72-40b3-903b-1b0cf08e50bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448491607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_slow_rsp.2448491607 |
| Directory | /workspace/22.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2805175341 |
| Short name | T2803 |
| Test name | |
| Test status | |
| Simulation time | 385523918 ps |
| CPU time | 36.5 seconds |
| Started | Aug 17 06:48:55 PM PDT 24 |
| Finished | Aug 17 06:49:32 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-1c66446b-805b-4706-bf2a-58958e3e0313 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805175341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_random_zero_del ays.2805175341 |
| Directory | /workspace/22.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_same_source.448237698 |
| Short name | T2738 |
| Test name | |
| Test status | |
| Simulation time | 598845690 ps |
| CPU time | 18.82 seconds |
| Started | Aug 17 06:49:02 PM PDT 24 |
| Finished | Aug 17 06:49:21 PM PDT 24 |
| Peak memory | 575752 kb |
| Host | smart-61671535-a1d0-4247-b8e2-08d4f77d7ba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448237698 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_same_source.448237698 |
| Directory | /workspace/22.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke.2120961080 |
| Short name | T1530 |
| Test name | |
| Test status | |
| Simulation time | 235195795 ps |
| CPU time | 10.44 seconds |
| Started | Aug 17 06:48:52 PM PDT 24 |
| Finished | Aug 17 06:49:03 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-c5a66987-2501-4a9e-8134-c4049acfbe74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120961080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke.2120961080 |
| Directory | /workspace/22.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_large_delays.293494966 |
| Short name | T1889 |
| Test name | |
| Test status | |
| Simulation time | 10409937948 ps |
| CPU time | 105.43 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:50:45 PM PDT 24 |
| Peak memory | 574196 kb |
| Host | smart-b3a661db-a76e-47f4-bdc9-3a2ee09dca7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293494966 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_large_delays.293494966 |
| Directory | /workspace/22.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_slow_rsp.3980182205 |
| Short name | T2022 |
| Test name | |
| Test status | |
| Simulation time | 4088296994 ps |
| CPU time | 69.16 seconds |
| Started | Aug 17 06:48:50 PM PDT 24 |
| Finished | Aug 17 06:49:59 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-3938f767-8878-4958-8e73-8d9cbff88a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980182205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_slow_rsp.3980182205 |
| Directory | /workspace/22.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.4034065624 |
| Short name | T2711 |
| Test name | |
| Test status | |
| Simulation time | 38479335 ps |
| CPU time | 5.57 seconds |
| Started | Aug 17 06:48:53 PM PDT 24 |
| Finished | Aug 17 06:48:58 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-6f6947b9-0dc4-4f38-8b07-0840384c95a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034065624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_smoke_zero_delay s.4034065624 |
| Directory | /workspace/22.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_error.1661884435 |
| Short name | T2801 |
| Test name | |
| Test status | |
| Simulation time | 3709309033 ps |
| CPU time | 243.57 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:53:03 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-d78ee142-6767-4455-8a61-18b2070e11a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661884435 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all_with_error.1661884435 |
| Directory | /workspace/22.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_rand_reset.1210612328 |
| Short name | T1558 |
| Test name | |
| Test status | |
| Simulation time | 368393970 ps |
| CPU time | 131.38 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:51:12 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-52040a67-baba-4043-84ca-95db00edf875 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210612328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_all _with_rand_reset.1210612328 |
| Directory | /workspace/22.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_stress_all_with_reset_error.3815103413 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 258091744 ps |
| CPU time | 61.81 seconds |
| Started | Aug 17 06:49:02 PM PDT 24 |
| Finished | Aug 17 06:50:04 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-00326854-9be8-4318-b4c9-56b1bc0b2ccf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815103413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_stress_al l_with_reset_error.3815103413 |
| Directory | /workspace/22.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/22.xbar_unmapped_addr.1896478289 |
| Short name | T1850 |
| Test name | |
| Test status | |
| Simulation time | 1427953302 ps |
| CPU time | 54.29 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:49:55 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-bd79843b-925c-45cc-80a4-1f76b4ed5985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896478289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.xbar_unmapped_addr.1896478289 |
| Directory | /workspace/22.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.chip_tl_errors.1616250810 |
| Short name | T2865 |
| Test name | |
| Test status | |
| Simulation time | 3205876060 ps |
| CPU time | 150.18 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:51:31 PM PDT 24 |
| Peak memory | 603792 kb |
| Host | smart-2081cf81-3106-4357-8e39-64024a84de6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616250810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.chip_tl_errors.1616250810 |
| Directory | /workspace/23.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device.1045499551 |
| Short name | T2035 |
| Test name | |
| Test status | |
| Simulation time | 444500553 ps |
| CPU time | 32.42 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:49:33 PM PDT 24 |
| Peak memory | 575380 kb |
| Host | smart-421b55b3-de40-46f8-b099-f3f6a509e00d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045499551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_device .1045499551 |
| Directory | /workspace/23.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_access_same_device_slow_rsp.1064542073 |
| Short name | T2399 |
| Test name | |
| Test status | |
| Simulation time | 112033048690 ps |
| CPU time | 2027.5 seconds |
| Started | Aug 17 06:49:06 PM PDT 24 |
| Finished | Aug 17 07:22:53 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-10a69bf2-bcae-488a-a32f-6923733f9220 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064542073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_access_same_ device_slow_rsp.1064542073 |
| Directory | /workspace/23.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_and_unmapped_addr.2011896404 |
| Short name | T2362 |
| Test name | |
| Test status | |
| Simulation time | 77897562 ps |
| CPU time | 10.32 seconds |
| Started | Aug 17 06:48:58 PM PDT 24 |
| Finished | Aug 17 06:49:09 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-3048c9f9-cf0b-4482-8032-0a35c5962c25 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2011896404 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_and_unmapped_add r.2011896404 |
| Directory | /workspace/23.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_error_random.3478407216 |
| Short name | T1784 |
| Test name | |
| Test status | |
| Simulation time | 2407771223 ps |
| CPU time | 80.12 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:50:21 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-3ed9d4c7-8f20-41ed-a0ee-50cd3ca3cf68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478407216 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_error_random.3478407216 |
| Directory | /workspace/23.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random.952014999 |
| Short name | T1446 |
| Test name | |
| Test status | |
| Simulation time | 1430323550 ps |
| CPU time | 47.92 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:49:48 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-6e51ad59-6cae-4592-a1ef-e5b6994e46c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952014999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random.952014999 |
| Directory | /workspace/23.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_large_delays.4069644574 |
| Short name | T2593 |
| Test name | |
| Test status | |
| Simulation time | 110484002415 ps |
| CPU time | 1155.55 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 07:08:17 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-3c9bc7f8-f246-484c-bfe7-206148394aab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069644574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_large_delays.4069644574 |
| Directory | /workspace/23.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3231191679 |
| Short name | T1825 |
| Test name | |
| Test status | |
| Simulation time | 41468959158 ps |
| CPU time | 666.12 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 07:00:07 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-bd31d3ff-5660-4e9c-abe4-7fc8807adcf9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231191679 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_slow_rsp.3231191679 |
| Directory | /workspace/23.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_random_zero_delays.550842498 |
| Short name | T2724 |
| Test name | |
| Test status | |
| Simulation time | 196522488 ps |
| CPU time | 20.42 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:49:21 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-9f40d204-ddcd-4a2d-bb0c-045e30c9f74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550842498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_random_zero_dela ys.550842498 |
| Directory | /workspace/23.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_same_source.2952349457 |
| Short name | T2074 |
| Test name | |
| Test status | |
| Simulation time | 203405751 ps |
| CPU time | 17.76 seconds |
| Started | Aug 17 06:48:58 PM PDT 24 |
| Finished | Aug 17 06:49:16 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-7e7533fd-64af-47f8-aea3-845026a09bcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952349457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_same_source.2952349457 |
| Directory | /workspace/23.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke.3462476513 |
| Short name | T1427 |
| Test name | |
| Test status | |
| Simulation time | 48238720 ps |
| CPU time | 6.14 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:49:07 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-49aa4453-226d-4a17-abc0-7885f0f5628b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462476513 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke.3462476513 |
| Directory | /workspace/23.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_large_delays.4046270179 |
| Short name | T2499 |
| Test name | |
| Test status | |
| Simulation time | 6831668994 ps |
| CPU time | 72.02 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:50:13 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-d6ec999f-1a05-4904-90cf-47f19232d2f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4046270179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_large_delays.4046270179 |
| Directory | /workspace/23.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_slow_rsp.354426106 |
| Short name | T2482 |
| Test name | |
| Test status | |
| Simulation time | 3774883601 ps |
| CPU time | 61.28 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:50:03 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-af7f9f98-ec87-41df-9cb0-380a54f68f4a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354426106 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_slow_rsp.354426106 |
| Directory | /workspace/23.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_smoke_zero_delays.1084140356 |
| Short name | T1428 |
| Test name | |
| Test status | |
| Simulation time | 43475668 ps |
| CPU time | 5.64 seconds |
| Started | Aug 17 06:49:06 PM PDT 24 |
| Finished | Aug 17 06:49:11 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-dda9a707-e802-448a-825f-2c83e89b1f01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084140356 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_smoke_zero_delay s.1084140356 |
| Directory | /workspace/23.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all.2184974656 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 3341789019 ps |
| CPU time | 118.34 seconds |
| Started | Aug 17 06:49:04 PM PDT 24 |
| Finished | Aug 17 06:51:02 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-1e3e0d24-ecb2-4c4b-8efa-0f2fbe3a0fad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184974656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all.2184974656 |
| Directory | /workspace/23.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_error.3749298594 |
| Short name | T2159 |
| Test name | |
| Test status | |
| Simulation time | 9093048375 ps |
| CPU time | 332.16 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:54:32 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e8252d09-d970-4305-87f1-0bad27221034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3749298594 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all_with_error.3749298594 |
| Directory | /workspace/23.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.2023982716 |
| Short name | T2371 |
| Test name | |
| Test status | |
| Simulation time | 6400924684 ps |
| CPU time | 282.9 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:53:44 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-39d9b0ad-1cde-450b-b2bf-1b8e9b0d46bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023982716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_stress_all _with_rand_reset.2023982716 |
| Directory | /workspace/23.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.4168730950 |
| Short name | T2123 |
| Test name | |
| Test status | |
| Simulation time | 188026056 ps |
| CPU time | 22.9 seconds |
| Started | Aug 17 06:48:58 PM PDT 24 |
| Finished | Aug 17 06:49:21 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-75e579e3-85bb-4d8b-8d79-1b99779f9d0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168730950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.xbar_unmapped_addr.4168730950 |
| Directory | /workspace/23.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.chip_tl_errors.3931883308 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3058360096 ps |
| CPU time | 214.96 seconds |
| Started | Aug 17 06:48:59 PM PDT 24 |
| Finished | Aug 17 06:52:34 PM PDT 24 |
| Peak memory | 603916 kb |
| Host | smart-4e03f970-f234-4d41-bfed-561ee2fea05d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931883308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.chip_tl_errors.3931883308 |
| Directory | /workspace/24.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device.2077795656 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 466667146 ps |
| CPU time | 39.73 seconds |
| Started | Aug 17 06:49:07 PM PDT 24 |
| Finished | Aug 17 06:49:47 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-6bada5e4-4243-44ec-a4d8-0456c4acc37f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077795656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_device .2077795656 |
| Directory | /workspace/24.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1021188921 |
| Short name | T1912 |
| Test name | |
| Test status | |
| Simulation time | 108525533751 ps |
| CPU time | 1961.19 seconds |
| Started | Aug 17 06:49:07 PM PDT 24 |
| Finished | Aug 17 07:21:49 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-d3492f7e-5243-44ea-be15-947fbf75f1bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021188921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_access_same_ device_slow_rsp.1021188921 |
| Directory | /workspace/24.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.2331556945 |
| Short name | T1544 |
| Test name | |
| Test status | |
| Simulation time | 1141023274 ps |
| CPU time | 39.03 seconds |
| Started | Aug 17 06:49:09 PM PDT 24 |
| Finished | Aug 17 06:49:48 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-de70f916-e3cf-4b91-9343-7b8470b948bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331556945 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_and_unmapped_add r.2331556945 |
| Directory | /workspace/24.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_error_random.2472246997 |
| Short name | T1600 |
| Test name | |
| Test status | |
| Simulation time | 423774326 ps |
| CPU time | 15.32 seconds |
| Started | Aug 17 06:49:06 PM PDT 24 |
| Finished | Aug 17 06:49:21 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-f119c37a-05c4-481e-82ba-9f4a696eb733 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472246997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_error_random.2472246997 |
| Directory | /workspace/24.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random.2677547595 |
| Short name | T2428 |
| Test name | |
| Test status | |
| Simulation time | 594774790 ps |
| CPU time | 23.54 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:49:24 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-de645cc9-272e-40e9-8f9e-235b4ef284f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677547595 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random.2677547595 |
| Directory | /workspace/24.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_large_delays.1805511646 |
| Short name | T2850 |
| Test name | |
| Test status | |
| Simulation time | 57432685417 ps |
| CPU time | 654.21 seconds |
| Started | Aug 17 06:48:59 PM PDT 24 |
| Finished | Aug 17 06:59:53 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-cdf3fed0-a56c-4234-9162-af31be88eedf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805511646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_large_delays.1805511646 |
| Directory | /workspace/24.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_slow_rsp.4187336702 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 31917393087 ps |
| CPU time | 527.06 seconds |
| Started | Aug 17 06:49:01 PM PDT 24 |
| Finished | Aug 17 06:57:48 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-12f3b3de-b93d-48dc-939a-1da6e7c7606b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187336702 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_slow_rsp.4187336702 |
| Directory | /workspace/24.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_random_zero_delays.205130910 |
| Short name | T1648 |
| Test name | |
| Test status | |
| Simulation time | 67498644 ps |
| CPU time | 8.08 seconds |
| Started | Aug 17 06:49:04 PM PDT 24 |
| Finished | Aug 17 06:49:12 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-e551b8b7-e5c7-4945-8303-d9ed24ab1e16 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205130910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_random_zero_dela ys.205130910 |
| Directory | /workspace/24.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_same_source.4177342983 |
| Short name | T2728 |
| Test name | |
| Test status | |
| Simulation time | 1142808027 ps |
| CPU time | 30.97 seconds |
| Started | Aug 17 06:49:05 PM PDT 24 |
| Finished | Aug 17 06:49:36 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-f3c39129-df59-46a5-8b93-f84dd816d343 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177342983 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_same_source.4177342983 |
| Directory | /workspace/24.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke.1998345466 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 49822428 ps |
| CPU time | 6.83 seconds |
| Started | Aug 17 06:49:00 PM PDT 24 |
| Finished | Aug 17 06:49:07 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-bf05cdbd-ee80-4016-bd93-c957feb10b70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998345466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke.1998345466 |
| Directory | /workspace/24.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.536421164 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 7801763353 ps |
| CPU time | 77.02 seconds |
| Started | Aug 17 06:48:59 PM PDT 24 |
| Finished | Aug 17 06:50:16 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-481ceed1-dab6-4277-a247-60df55ab34d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536421164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_large_delays.536421164 |
| Directory | /workspace/24.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_slow_rsp.4157995174 |
| Short name | T1676 |
| Test name | |
| Test status | |
| Simulation time | 4763679478 ps |
| CPU time | 81.52 seconds |
| Started | Aug 17 06:48:58 PM PDT 24 |
| Finished | Aug 17 06:50:20 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-9ca9a310-7e6e-4661-b4d0-7adfa5d0b786 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157995174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_slow_rsp.4157995174 |
| Directory | /workspace/24.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_smoke_zero_delays.1933327798 |
| Short name | T1380 |
| Test name | |
| Test status | |
| Simulation time | 50993052 ps |
| CPU time | 6.29 seconds |
| Started | Aug 17 06:49:02 PM PDT 24 |
| Finished | Aug 17 06:49:08 PM PDT 24 |
| Peak memory | 574020 kb |
| Host | smart-3290b2fa-f4c1-4131-b302-d62bce59e894 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1933327798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_smoke_zero_delay s.1933327798 |
| Directory | /workspace/24.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all.4126127235 |
| Short name | T1822 |
| Test name | |
| Test status | |
| Simulation time | 2841912456 ps |
| CPU time | 239.84 seconds |
| Started | Aug 17 06:49:06 PM PDT 24 |
| Finished | Aug 17 06:53:06 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-7611dbae-2b23-4fe3-a2bd-0897e1bb55b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126127235 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all.4126127235 |
| Directory | /workspace/24.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_error.3562906827 |
| Short name | T2715 |
| Test name | |
| Test status | |
| Simulation time | 3698013165 ps |
| CPU time | 114.4 seconds |
| Started | Aug 17 06:49:13 PM PDT 24 |
| Finished | Aug 17 06:51:08 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-354b18f4-7563-4269-8239-7dfb94cb925f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562906827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_with_error.3562906827 |
| Directory | /workspace/24.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.701432985 |
| Short name | T2696 |
| Test name | |
| Test status | |
| Simulation time | 2592759353 ps |
| CPU time | 435.43 seconds |
| Started | Aug 17 06:49:13 PM PDT 24 |
| Finished | Aug 17 06:56:29 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-0877a261-fca0-47d6-81e1-4d6cc017c67d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701432985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_all_ with_rand_reset.701432985 |
| Directory | /workspace/24.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_stress_all_with_reset_error.3690525042 |
| Short name | T1376 |
| Test name | |
| Test status | |
| Simulation time | 182297364 ps |
| CPU time | 47.22 seconds |
| Started | Aug 17 06:49:14 PM PDT 24 |
| Finished | Aug 17 06:50:01 PM PDT 24 |
| Peak memory | 576004 kb |
| Host | smart-5620f45f-b6c6-4798-b016-d98807c20582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690525042 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_stress_al l_with_reset_error.3690525042 |
| Directory | /workspace/24.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/24.xbar_unmapped_addr.1721189850 |
| Short name | T1502 |
| Test name | |
| Test status | |
| Simulation time | 831040291 ps |
| CPU time | 31.65 seconds |
| Started | Aug 17 06:49:04 PM PDT 24 |
| Finished | Aug 17 06:49:36 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-42309170-b846-4970-b392-27d721a799cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721189850 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.xbar_unmapped_addr.1721189850 |
| Directory | /workspace/24.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.chip_tl_errors.1176066998 |
| Short name | T2529 |
| Test name | |
| Test status | |
| Simulation time | 3163503254 ps |
| CPU time | 184.53 seconds |
| Started | Aug 17 06:49:13 PM PDT 24 |
| Finished | Aug 17 06:52:18 PM PDT 24 |
| Peak memory | 603928 kb |
| Host | smart-246fd782-fef0-4bb9-9245-d4e3d248cac5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176066998 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.chip_tl_errors.1176066998 |
| Directory | /workspace/25.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device.4073144551 |
| Short name | T1416 |
| Test name | |
| Test status | |
| Simulation time | 525356028 ps |
| CPU time | 54.39 seconds |
| Started | Aug 17 06:49:07 PM PDT 24 |
| Finished | Aug 17 06:50:02 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-40087e71-94ed-43e2-82fe-a2c5898a722a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073144551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_device .4073144551 |
| Directory | /workspace/25.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_access_same_device_slow_rsp.789952558 |
| Short name | T2207 |
| Test name | |
| Test status | |
| Simulation time | 62843093515 ps |
| CPU time | 1137.28 seconds |
| Started | Aug 17 06:49:04 PM PDT 24 |
| Finished | Aug 17 07:08:01 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-9c5a174f-686a-46b9-997c-9d7485edaf72 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789952558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_access_same_d evice_slow_rsp.789952558 |
| Directory | /workspace/25.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_and_unmapped_addr.318899100 |
| Short name | T1562 |
| Test name | |
| Test status | |
| Simulation time | 945394100 ps |
| CPU time | 36.45 seconds |
| Started | Aug 17 06:49:17 PM PDT 24 |
| Finished | Aug 17 06:49:54 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-8791c9fd-cdf8-4fc0-8461-2765e8012358 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318899100 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_and_unmapped_addr .318899100 |
| Directory | /workspace/25.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_error_random.2615022927 |
| Short name | T1899 |
| Test name | |
| Test status | |
| Simulation time | 2614590053 ps |
| CPU time | 83.09 seconds |
| Started | Aug 17 06:49:16 PM PDT 24 |
| Finished | Aug 17 06:50:39 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-7dcaaa3e-cb72-4e98-a4a6-649fe32cb9f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615022927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_error_random.2615022927 |
| Directory | /workspace/25.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random.2423615240 |
| Short name | T2307 |
| Test name | |
| Test status | |
| Simulation time | 576363298 ps |
| CPU time | 24.58 seconds |
| Started | Aug 17 06:49:06 PM PDT 24 |
| Finished | Aug 17 06:49:31 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-5051b787-9523-4b03-8745-84d9490b7a51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2423615240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random.2423615240 |
| Directory | /workspace/25.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_large_delays.3852460859 |
| Short name | T1641 |
| Test name | |
| Test status | |
| Simulation time | 93127583901 ps |
| CPU time | 990.55 seconds |
| Started | Aug 17 06:49:15 PM PDT 24 |
| Finished | Aug 17 07:05:46 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-e95306ed-f06f-465f-874f-5ecfa3b4bb40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852460859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_large_delays.3852460859 |
| Directory | /workspace/25.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_slow_rsp.1713322825 |
| Short name | T2304 |
| Test name | |
| Test status | |
| Simulation time | 38071046719 ps |
| CPU time | 635.02 seconds |
| Started | Aug 17 06:49:05 PM PDT 24 |
| Finished | Aug 17 06:59:40 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-bf25e16d-ed67-48ed-87b8-986d88ca07f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713322825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_slow_rsp.1713322825 |
| Directory | /workspace/25.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_random_zero_delays.131096280 |
| Short name | T1577 |
| Test name | |
| Test status | |
| Simulation time | 350778393 ps |
| CPU time | 34.14 seconds |
| Started | Aug 17 06:49:06 PM PDT 24 |
| Finished | Aug 17 06:49:40 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-015b289e-1ca4-4c90-9a99-0ec3845b79d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131096280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_random_zero_dela ys.131096280 |
| Directory | /workspace/25.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_same_source.2352283269 |
| Short name | T1711 |
| Test name | |
| Test status | |
| Simulation time | 151526378 ps |
| CPU time | 13.5 seconds |
| Started | Aug 17 06:49:15 PM PDT 24 |
| Finished | Aug 17 06:49:28 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-0ea0d205-8bad-4718-a25f-8e5f3d164a0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2352283269 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_same_source.2352283269 |
| Directory | /workspace/25.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke.716439123 |
| Short name | T2861 |
| Test name | |
| Test status | |
| Simulation time | 194076633 ps |
| CPU time | 9.15 seconds |
| Started | Aug 17 06:49:04 PM PDT 24 |
| Finished | Aug 17 06:49:13 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-e98ac744-1552-45e6-ad09-04c0f9845dde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716439123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke.716439123 |
| Directory | /workspace/25.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_large_delays.1904112770 |
| Short name | T1439 |
| Test name | |
| Test status | |
| Simulation time | 5150842763 ps |
| CPU time | 51.43 seconds |
| Started | Aug 17 06:49:04 PM PDT 24 |
| Finished | Aug 17 06:49:56 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-9cf9ca51-7ed4-408d-9bed-75a6b6965e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1904112770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_large_delays.1904112770 |
| Directory | /workspace/25.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_slow_rsp.351513203 |
| Short name | T2017 |
| Test name | |
| Test status | |
| Simulation time | 5547414274 ps |
| CPU time | 97.02 seconds |
| Started | Aug 17 06:49:09 PM PDT 24 |
| Finished | Aug 17 06:50:46 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-12c5dd9d-f6d1-4821-8e08-9fcfc51f1754 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351513203 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_slow_rsp.351513203 |
| Directory | /workspace/25.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_smoke_zero_delays.114372088 |
| Short name | T2692 |
| Test name | |
| Test status | |
| Simulation time | 55618412 ps |
| CPU time | 6.5 seconds |
| Started | Aug 17 06:49:09 PM PDT 24 |
| Finished | Aug 17 06:49:16 PM PDT 24 |
| Peak memory | 573388 kb |
| Host | smart-54611e4e-e9a9-4d46-9ba3-cb1b3ae8225f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114372088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_smoke_zero_delays .114372088 |
| Directory | /workspace/25.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all.821775961 |
| Short name | T2297 |
| Test name | |
| Test status | |
| Simulation time | 2173375285 ps |
| CPU time | 71.12 seconds |
| Started | Aug 17 06:49:15 PM PDT 24 |
| Finished | Aug 17 06:50:26 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-6a7ed6a3-0adb-4a48-80de-8cd8a48b6357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821775961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all.821775961 |
| Directory | /workspace/25.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_error.10644733 |
| Short name | T2121 |
| Test name | |
| Test status | |
| Simulation time | 9307708555 ps |
| CPU time | 312.03 seconds |
| Started | Aug 17 06:49:14 PM PDT 24 |
| Finished | Aug 17 06:54:26 PM PDT 24 |
| Peak memory | 576176 kb |
| Host | smart-843b204f-7294-473a-a61a-deda616f00b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10644733 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_with_error.10644733 |
| Directory | /workspace/25.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_stress_all_with_rand_reset.552822085 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 394846258 ps |
| CPU time | 147.56 seconds |
| Started | Aug 17 06:49:15 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 576276 kb |
| Host | smart-45bece8a-55c6-433c-bf2d-6d1027716015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552822085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_stress_all_ with_rand_reset.552822085 |
| Directory | /workspace/25.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/25.xbar_unmapped_addr.1321796647 |
| Short name | T2811 |
| Test name | |
| Test status | |
| Simulation time | 832363685 ps |
| CPU time | 31.48 seconds |
| Started | Aug 17 06:49:15 PM PDT 24 |
| Finished | Aug 17 06:49:47 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6ce0ef67-a0aa-45b1-9ca0-efe269e449d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321796647 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.xbar_unmapped_addr.1321796647 |
| Directory | /workspace/25.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.chip_tl_errors.4180292470 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 4372167822 ps |
| CPU time | 268.59 seconds |
| Started | Aug 17 06:49:16 PM PDT 24 |
| Finished | Aug 17 06:53:44 PM PDT 24 |
| Peak memory | 603912 kb |
| Host | smart-00ee75d2-72cd-4532-a0d5-879497284011 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4180292470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.chip_tl_errors.4180292470 |
| Directory | /workspace/26.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device.2064526555 |
| Short name | T2465 |
| Test name | |
| Test status | |
| Simulation time | 3583748958 ps |
| CPU time | 129.87 seconds |
| Started | Aug 17 06:49:16 PM PDT 24 |
| Finished | Aug 17 06:51:26 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-d463b6c5-6a6d-4052-98fc-e819df8acc2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064526555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_device .2064526555 |
| Directory | /workspace/26.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_access_same_device_slow_rsp.3536241992 |
| Short name | T2481 |
| Test name | |
| Test status | |
| Simulation time | 127088807882 ps |
| CPU time | 2139.52 seconds |
| Started | Aug 17 06:49:14 PM PDT 24 |
| Finished | Aug 17 07:24:54 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-43b9ff7e-33a5-46a8-8e08-6d5f890e798a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536241992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_access_same_ device_slow_rsp.3536241992 |
| Directory | /workspace/26.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_and_unmapped_addr.3659597840 |
| Short name | T2864 |
| Test name | |
| Test status | |
| Simulation time | 43286143 ps |
| CPU time | 7.25 seconds |
| Started | Aug 17 06:49:13 PM PDT 24 |
| Finished | Aug 17 06:49:20 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-07b5ad56-4764-4056-b0ec-2b584d9e9917 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659597840 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_and_unmapped_add r.3659597840 |
| Directory | /workspace/26.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_error_random.3888010157 |
| Short name | T1354 |
| Test name | |
| Test status | |
| Simulation time | 416145741 ps |
| CPU time | 17.79 seconds |
| Started | Aug 17 06:49:19 PM PDT 24 |
| Finished | Aug 17 06:49:37 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-c84b0108-c8db-4324-b01a-9b87e167b272 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888010157 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_error_random.3888010157 |
| Directory | /workspace/26.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random.748749310 |
| Short name | T1613 |
| Test name | |
| Test status | |
| Simulation time | 883485122 ps |
| CPU time | 35.12 seconds |
| Started | Aug 17 06:49:14 PM PDT 24 |
| Finished | Aug 17 06:49:49 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-58ce2583-b011-4cef-b2b2-b19b3dee467f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=748749310 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random.748749310 |
| Directory | /workspace/26.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_large_delays.3330072190 |
| Short name | T2934 |
| Test name | |
| Test status | |
| Simulation time | 72637540055 ps |
| CPU time | 782.15 seconds |
| Started | Aug 17 06:49:16 PM PDT 24 |
| Finished | Aug 17 07:02:19 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-064668f1-590f-4023-add4-b2c298f522dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330072190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_large_delays.3330072190 |
| Directory | /workspace/26.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_slow_rsp.1089115137 |
| Short name | T2203 |
| Test name | |
| Test status | |
| Simulation time | 25120976934 ps |
| CPU time | 411.32 seconds |
| Started | Aug 17 06:49:16 PM PDT 24 |
| Finished | Aug 17 06:56:07 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-a9831edf-fcf7-4298-b36a-1e6b9782bb49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089115137 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_slow_rsp.1089115137 |
| Directory | /workspace/26.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_random_zero_delays.3499074587 |
| Short name | T1874 |
| Test name | |
| Test status | |
| Simulation time | 501092120 ps |
| CPU time | 41.98 seconds |
| Started | Aug 17 06:49:14 PM PDT 24 |
| Finished | Aug 17 06:49:56 PM PDT 24 |
| Peak memory | 575332 kb |
| Host | smart-36bb5c44-8d4f-4979-889d-4b9476d2aedb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499074587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_random_zero_del ays.3499074587 |
| Directory | /workspace/26.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_same_source.541582578 |
| Short name | T2221 |
| Test name | |
| Test status | |
| Simulation time | 1327292658 ps |
| CPU time | 43.19 seconds |
| Started | Aug 17 06:49:13 PM PDT 24 |
| Finished | Aug 17 06:49:57 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-7f2173d3-9239-4dbe-8210-0ea6a6a15ccb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541582578 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_same_source.541582578 |
| Directory | /workspace/26.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke.1912110913 |
| Short name | T2636 |
| Test name | |
| Test status | |
| Simulation time | 141018700 ps |
| CPU time | 8.56 seconds |
| Started | Aug 17 06:49:18 PM PDT 24 |
| Finished | Aug 17 06:49:26 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-14859ea1-7524-4800-b2c9-726eaa9b9cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912110913 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke.1912110913 |
| Directory | /workspace/26.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_large_delays.1365285964 |
| Short name | T1836 |
| Test name | |
| Test status | |
| Simulation time | 8623510065 ps |
| CPU time | 89 seconds |
| Started | Aug 17 06:49:17 PM PDT 24 |
| Finished | Aug 17 06:50:46 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-419ab446-3996-48c4-9049-4ed46ef0dce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1365285964 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_large_delays.1365285964 |
| Directory | /workspace/26.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_slow_rsp.405506127 |
| Short name | T1408 |
| Test name | |
| Test status | |
| Simulation time | 5578776431 ps |
| CPU time | 92.18 seconds |
| Started | Aug 17 06:49:13 PM PDT 24 |
| Finished | Aug 17 06:50:46 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-a1b45086-24fb-482d-a185-fa0a76ee2a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405506127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_slow_rsp.405506127 |
| Directory | /workspace/26.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_smoke_zero_delays.2146478365 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 48796674 ps |
| CPU time | 6.1 seconds |
| Started | Aug 17 06:49:17 PM PDT 24 |
| Finished | Aug 17 06:49:23 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-ecbc0bb5-5092-45c3-b56e-7fe05618394e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146478365 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_smoke_zero_delay s.2146478365 |
| Directory | /workspace/26.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all.1487289940 |
| Short name | T2458 |
| Test name | |
| Test status | |
| Simulation time | 644600435 ps |
| CPU time | 50.56 seconds |
| Started | Aug 17 06:49:24 PM PDT 24 |
| Finished | Aug 17 06:50:15 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-24ce5f80-6d70-45a9-a19a-9811853fea2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487289940 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all.1487289940 |
| Directory | /workspace/26.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_error.1716407224 |
| Short name | T2225 |
| Test name | |
| Test status | |
| Simulation time | 1639898798 ps |
| CPU time | 125.24 seconds |
| Started | Aug 17 06:49:23 PM PDT 24 |
| Finished | Aug 17 06:51:29 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-3b47c18d-6867-400d-9695-4f473af53734 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716407224 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all_with_error.1716407224 |
| Directory | /workspace/26.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_rand_reset.1715226898 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 3221067162 ps |
| CPU time | 286.98 seconds |
| Started | Aug 17 06:49:22 PM PDT 24 |
| Finished | Aug 17 06:54:09 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-1f14cd4e-3fac-4a0f-a535-41c5f66fe996 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1715226898 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_all _with_rand_reset.1715226898 |
| Directory | /workspace/26.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.3245204498 |
| Short name | T2602 |
| Test name | |
| Test status | |
| Simulation time | 291282069 ps |
| CPU time | 108.18 seconds |
| Started | Aug 17 06:49:20 PM PDT 24 |
| Finished | Aug 17 06:51:09 PM PDT 24 |
| Peak memory | 576236 kb |
| Host | smart-8b49ae16-370d-401b-9529-6c635e65b3c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245204498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_stress_al l_with_reset_error.3245204498 |
| Directory | /workspace/26.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/26.xbar_unmapped_addr.3689032461 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 454026804 ps |
| CPU time | 23.48 seconds |
| Started | Aug 17 06:49:13 PM PDT 24 |
| Finished | Aug 17 06:49:37 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-02796a08-d1c3-4ca1-8456-4ededb48e18d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689032461 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.xbar_unmapped_addr.3689032461 |
| Directory | /workspace/26.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.chip_tl_errors.47618292 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 3259813048 ps |
| CPU time | 246.52 seconds |
| Started | Aug 17 06:49:22 PM PDT 24 |
| Finished | Aug 17 06:53:28 PM PDT 24 |
| Peak memory | 603928 kb |
| Host | smart-380250a6-b2e4-47e2-bea8-85dfb467f502 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47618292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.chip_tl_errors.47618292 |
| Directory | /workspace/27.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device.3957455824 |
| Short name | T2273 |
| Test name | |
| Test status | |
| Simulation time | 235875023 ps |
| CPU time | 10.52 seconds |
| Started | Aug 17 06:49:22 PM PDT 24 |
| Finished | Aug 17 06:49:33 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-66eac9ad-7e70-4f68-91b0-f0550082ddb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957455824 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_device .3957455824 |
| Directory | /workspace/27.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_access_same_device_slow_rsp.2641031500 |
| Short name | T2016 |
| Test name | |
| Test status | |
| Simulation time | 89656180439 ps |
| CPU time | 1595.07 seconds |
| Started | Aug 17 06:49:23 PM PDT 24 |
| Finished | Aug 17 07:15:58 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-7db2506d-f1a1-4980-95c0-d48530a98d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641031500 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_access_same_ device_slow_rsp.2641031500 |
| Directory | /workspace/27.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_and_unmapped_addr.3472389879 |
| Short name | T1403 |
| Test name | |
| Test status | |
| Simulation time | 1105482182 ps |
| CPU time | 39.35 seconds |
| Started | Aug 17 06:49:20 PM PDT 24 |
| Finished | Aug 17 06:49:59 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-ca8a31b0-d222-4159-89f3-594d73549773 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472389879 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_and_unmapped_add r.3472389879 |
| Directory | /workspace/27.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_error_random.1568459123 |
| Short name | T1589 |
| Test name | |
| Test status | |
| Simulation time | 39688954 ps |
| CPU time | 6.16 seconds |
| Started | Aug 17 06:49:25 PM PDT 24 |
| Finished | Aug 17 06:49:31 PM PDT 24 |
| Peak memory | 573948 kb |
| Host | smart-af12a834-41ee-4103-a039-1e92624ae3e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568459123 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_error_random.1568459123 |
| Directory | /workspace/27.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random.1697759699 |
| Short name | T2070 |
| Test name | |
| Test status | |
| Simulation time | 174917402 ps |
| CPU time | 8.52 seconds |
| Started | Aug 17 06:49:28 PM PDT 24 |
| Finished | Aug 17 06:49:37 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-70ade6ec-e651-4dc0-835e-7e9b73e775f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697759699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random.1697759699 |
| Directory | /workspace/27.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_large_delays.562804168 |
| Short name | T1742 |
| Test name | |
| Test status | |
| Simulation time | 71742934405 ps |
| CPU time | 795.3 seconds |
| Started | Aug 17 06:49:29 PM PDT 24 |
| Finished | Aug 17 07:02:45 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-fc4acc39-4d38-410e-80c1-ba7a1a0ae637 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562804168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_large_delays.562804168 |
| Directory | /workspace/27.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_slow_rsp.2764760501 |
| Short name | T1429 |
| Test name | |
| Test status | |
| Simulation time | 26950639275 ps |
| CPU time | 451.26 seconds |
| Started | Aug 17 06:49:19 PM PDT 24 |
| Finished | Aug 17 06:56:50 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-3f7c68d9-7409-46a6-8819-5f8ebbff2a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764760501 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_slow_rsp.2764760501 |
| Directory | /workspace/27.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_random_zero_delays.2876407720 |
| Short name | T2144 |
| Test name | |
| Test status | |
| Simulation time | 423335122 ps |
| CPU time | 41.66 seconds |
| Started | Aug 17 06:49:19 PM PDT 24 |
| Finished | Aug 17 06:50:01 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-eaeb56df-67fe-4136-866e-b435a463a648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876407720 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_random_zero_del ays.2876407720 |
| Directory | /workspace/27.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_same_source.2659572169 |
| Short name | T2807 |
| Test name | |
| Test status | |
| Simulation time | 122210850 ps |
| CPU time | 11.29 seconds |
| Started | Aug 17 06:49:21 PM PDT 24 |
| Finished | Aug 17 06:49:32 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-b987c13d-4496-44ae-8f0d-bbff73c86751 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659572169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_same_source.2659572169 |
| Directory | /workspace/27.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke.1909849642 |
| Short name | T1894 |
| Test name | |
| Test status | |
| Simulation time | 49634682 ps |
| CPU time | 6.23 seconds |
| Started | Aug 17 06:49:21 PM PDT 24 |
| Finished | Aug 17 06:49:27 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-9aa36d7d-c256-487f-be28-a7d96a0254f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909849642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke.1909849642 |
| Directory | /workspace/27.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_large_delays.2546094400 |
| Short name | T1818 |
| Test name | |
| Test status | |
| Simulation time | 9918783229 ps |
| CPU time | 99.44 seconds |
| Started | Aug 17 06:49:22 PM PDT 24 |
| Finished | Aug 17 06:51:02 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-8b4b2817-1968-4300-a9fb-4d8d4879acb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546094400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_large_delays.2546094400 |
| Directory | /workspace/27.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.461752667 |
| Short name | T2081 |
| Test name | |
| Test status | |
| Simulation time | 5004316919 ps |
| CPU time | 86.17 seconds |
| Started | Aug 17 06:49:21 PM PDT 24 |
| Finished | Aug 17 06:50:47 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-a922cb68-15eb-4a17-83b9-ab0ce11ee679 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461752667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_slow_rsp.461752667 |
| Directory | /workspace/27.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_smoke_zero_delays.3107744244 |
| Short name | T2923 |
| Test name | |
| Test status | |
| Simulation time | 52786308 ps |
| CPU time | 5.96 seconds |
| Started | Aug 17 06:49:29 PM PDT 24 |
| Finished | Aug 17 06:49:35 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-677d597f-8b6e-4382-9bdc-25492b793ec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107744244 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_smoke_zero_delay s.3107744244 |
| Directory | /workspace/27.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all.2248861709 |
| Short name | T2679 |
| Test name | |
| Test status | |
| Simulation time | 3775338797 ps |
| CPU time | 281.5 seconds |
| Started | Aug 17 06:49:22 PM PDT 24 |
| Finished | Aug 17 06:54:03 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-a2bdd712-005d-43e3-89a6-50380b4e7853 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248861709 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all.2248861709 |
| Directory | /workspace/27.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.1034977283 |
| Short name | T2589 |
| Test name | |
| Test status | |
| Simulation time | 8818186908 ps |
| CPU time | 330.72 seconds |
| Started | Aug 17 06:49:31 PM PDT 24 |
| Finished | Aug 17 06:55:02 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-96f8c586-8593-46d4-b39e-0819f468a3c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034977283 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all_with_error.1034977283 |
| Directory | /workspace/27.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_rand_reset.3554755320 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 471731715 ps |
| CPU time | 154.73 seconds |
| Started | Aug 17 06:49:29 PM PDT 24 |
| Finished | Aug 17 06:52:04 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-49accf73-a96d-43fa-bd33-ec36486f00fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554755320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_all _with_rand_reset.3554755320 |
| Directory | /workspace/27.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_stress_all_with_reset_error.3744869305 |
| Short name | T2562 |
| Test name | |
| Test status | |
| Simulation time | 1369277697 ps |
| CPU time | 184.51 seconds |
| Started | Aug 17 06:49:30 PM PDT 24 |
| Finished | Aug 17 06:52:35 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-5c70a42b-06ac-4cda-bd12-badedf8264da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744869305 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_stress_al l_with_reset_error.3744869305 |
| Directory | /workspace/27.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/27.xbar_unmapped_addr.3779012845 |
| Short name | T2215 |
| Test name | |
| Test status | |
| Simulation time | 477934107 ps |
| CPU time | 21.25 seconds |
| Started | Aug 17 06:49:23 PM PDT 24 |
| Finished | Aug 17 06:49:45 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-b02b0e07-81b5-499e-a87a-b4124c9f5f40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779012845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.xbar_unmapped_addr.3779012845 |
| Directory | /workspace/27.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.chip_tl_errors.1858791078 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 3214709162 ps |
| CPU time | 213.27 seconds |
| Started | Aug 17 06:49:27 PM PDT 24 |
| Finished | Aug 17 06:53:01 PM PDT 24 |
| Peak memory | 603892 kb |
| Host | smart-bb0c5d27-c432-4acd-bded-57eb4b534667 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858791078 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.chip_tl_errors.1858791078 |
| Directory | /workspace/28.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_access_same_device.1212343320 |
| Short name | T2043 |
| Test name | |
| Test status | |
| Simulation time | 686683928 ps |
| CPU time | 43.99 seconds |
| Started | Aug 17 06:49:30 PM PDT 24 |
| Finished | Aug 17 06:50:14 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-d7d1c0a5-278c-4bb4-b161-e38ea5af0bc9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212343320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_access_same_device .1212343320 |
| Directory | /workspace/28.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_and_unmapped_addr.734902078 |
| Short name | T2388 |
| Test name | |
| Test status | |
| Simulation time | 108679769 ps |
| CPU time | 14.85 seconds |
| Started | Aug 17 06:49:31 PM PDT 24 |
| Finished | Aug 17 06:49:46 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-1cb4fe98-ebed-46c1-80b1-daeb209fb7d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734902078 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_and_unmapped_addr .734902078 |
| Directory | /workspace/28.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_error_random.689027406 |
| Short name | T1555 |
| Test name | |
| Test status | |
| Simulation time | 743668964 ps |
| CPU time | 25.07 seconds |
| Started | Aug 17 06:49:29 PM PDT 24 |
| Finished | Aug 17 06:49:54 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-b08304e8-96d7-4b23-8580-eb427459bdb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689027406 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_error_random.689027406 |
| Directory | /workspace/28.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random.1113440611 |
| Short name | T2044 |
| Test name | |
| Test status | |
| Simulation time | 59347225 ps |
| CPU time | 8.25 seconds |
| Started | Aug 17 06:49:31 PM PDT 24 |
| Finished | Aug 17 06:49:39 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-402544ee-f2df-4081-ba80-c61f5add779d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113440611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random.1113440611 |
| Directory | /workspace/28.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_large_delays.796361812 |
| Short name | T2758 |
| Test name | |
| Test status | |
| Simulation time | 3973619214 ps |
| CPU time | 43.85 seconds |
| Started | Aug 17 06:49:29 PM PDT 24 |
| Finished | Aug 17 06:50:13 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-1fe958ca-e962-4c5e-bf16-ea20475287bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796361812 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_large_delays.796361812 |
| Directory | /workspace/28.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_slow_rsp.1016820076 |
| Short name | T2824 |
| Test name | |
| Test status | |
| Simulation time | 11588527645 ps |
| CPU time | 198.48 seconds |
| Started | Aug 17 06:49:28 PM PDT 24 |
| Finished | Aug 17 06:52:46 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-a4596c88-c806-4852-ad6a-8d7217237b7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016820076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_slow_rsp.1016820076 |
| Directory | /workspace/28.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_random_zero_delays.1213618577 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 402310727 ps |
| CPU time | 35.48 seconds |
| Started | Aug 17 06:49:28 PM PDT 24 |
| Finished | Aug 17 06:50:03 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-77481b43-f410-4a29-b68c-670d0af66924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213618577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_random_zero_del ays.1213618577 |
| Directory | /workspace/28.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_same_source.579505213 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2082289174 ps |
| CPU time | 51.63 seconds |
| Started | Aug 17 06:49:30 PM PDT 24 |
| Finished | Aug 17 06:50:22 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-60f7d324-1fd9-42d6-ad48-1f3e5eb0f380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579505213 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_same_source.579505213 |
| Directory | /workspace/28.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke.4256504311 |
| Short name | T2740 |
| Test name | |
| Test status | |
| Simulation time | 176544394 ps |
| CPU time | 8.06 seconds |
| Started | Aug 17 06:49:27 PM PDT 24 |
| Finished | Aug 17 06:49:35 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-d9839708-96cf-4feb-a93a-a10815e2efda |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256504311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke.4256504311 |
| Directory | /workspace/28.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_large_delays.3773417996 |
| Short name | T2162 |
| Test name | |
| Test status | |
| Simulation time | 7536792208 ps |
| CPU time | 84.58 seconds |
| Started | Aug 17 06:49:27 PM PDT 24 |
| Finished | Aug 17 06:50:52 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-42b9ff63-d274-415e-a577-1f402fc86aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773417996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_large_delays.3773417996 |
| Directory | /workspace/28.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_slow_rsp.3133664408 |
| Short name | T2255 |
| Test name | |
| Test status | |
| Simulation time | 5414772548 ps |
| CPU time | 93.38 seconds |
| Started | Aug 17 06:49:29 PM PDT 24 |
| Finished | Aug 17 06:51:02 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-cdad153e-0a07-4ca0-bade-ad1b8a8caf75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133664408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_slow_rsp.3133664408 |
| Directory | /workspace/28.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_smoke_zero_delays.990214084 |
| Short name | T1595 |
| Test name | |
| Test status | |
| Simulation time | 54054711 ps |
| CPU time | 6.9 seconds |
| Started | Aug 17 06:49:28 PM PDT 24 |
| Finished | Aug 17 06:49:35 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-74d613c4-55e4-4535-9768-868bc6f2bea6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990214084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_smoke_zero_delays .990214084 |
| Directory | /workspace/28.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all.4057331131 |
| Short name | T2188 |
| Test name | |
| Test status | |
| Simulation time | 3252493260 ps |
| CPU time | 239.61 seconds |
| Started | Aug 17 06:49:28 PM PDT 24 |
| Finished | Aug 17 06:53:27 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-fe7b260e-2b5c-434a-8b8c-b543c4ad421e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057331131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all.4057331131 |
| Directory | /workspace/28.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_error.2078714719 |
| Short name | T2483 |
| Test name | |
| Test status | |
| Simulation time | 12772406593 ps |
| CPU time | 440.98 seconds |
| Started | Aug 17 06:49:36 PM PDT 24 |
| Finished | Aug 17 06:56:57 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-4371d979-19e9-4a21-b51d-10db9ccb0211 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078714719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all_with_error.2078714719 |
| Directory | /workspace/28.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_rand_reset.2891803619 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 102999455 ps |
| CPU time | 48.23 seconds |
| Started | Aug 17 06:49:35 PM PDT 24 |
| Finished | Aug 17 06:50:24 PM PDT 24 |
| Peak memory | 576144 kb |
| Host | smart-fb9d371c-1d89-4a27-aac8-4e9b7ea6e738 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2891803619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_all _with_rand_reset.2891803619 |
| Directory | /workspace/28.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_stress_all_with_reset_error.1496140127 |
| Short name | T2520 |
| Test name | |
| Test status | |
| Simulation time | 1810660158 ps |
| CPU time | 241.06 seconds |
| Started | Aug 17 06:49:36 PM PDT 24 |
| Finished | Aug 17 06:53:37 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-18dd6845-487d-4860-8fcf-586175526cba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496140127 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_stress_al l_with_reset_error.1496140127 |
| Directory | /workspace/28.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.3789386749 |
| Short name | T2648 |
| Test name | |
| Test status | |
| Simulation time | 81242074 ps |
| CPU time | 7.22 seconds |
| Started | Aug 17 06:49:28 PM PDT 24 |
| Finished | Aug 17 06:49:36 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-5031a58f-d91f-4ea1-93b6-600dfcdb726a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3789386749 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.xbar_unmapped_addr.3789386749 |
| Directory | /workspace/28.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.chip_tl_errors.3298768942 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 3529776912 ps |
| CPU time | 157.54 seconds |
| Started | Aug 17 06:49:36 PM PDT 24 |
| Finished | Aug 17 06:52:14 PM PDT 24 |
| Peak memory | 603888 kb |
| Host | smart-995f4b5f-84bc-4bbc-93ec-13f4a66b9149 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298768942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.chip_tl_errors.3298768942 |
| Directory | /workspace/29.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device.2752462486 |
| Short name | T2266 |
| Test name | |
| Test status | |
| Simulation time | 701981817 ps |
| CPU time | 50.86 seconds |
| Started | Aug 17 06:49:34 PM PDT 24 |
| Finished | Aug 17 06:50:25 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-37e02cf3-c726-4e98-ae7c-a9b8a9242e2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752462486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_device .2752462486 |
| Directory | /workspace/29.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.3465574751 |
| Short name | T2856 |
| Test name | |
| Test status | |
| Simulation time | 90007728084 ps |
| CPU time | 1628.16 seconds |
| Started | Aug 17 06:49:37 PM PDT 24 |
| Finished | Aug 17 07:16:45 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-5e0e57b5-4588-4ebb-9028-8964f23ff9f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3465574751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_access_same_ device_slow_rsp.3465574751 |
| Directory | /workspace/29.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_and_unmapped_addr.1253010771 |
| Short name | T2210 |
| Test name | |
| Test status | |
| Simulation time | 85651392 ps |
| CPU time | 6.96 seconds |
| Started | Aug 17 06:49:35 PM PDT 24 |
| Finished | Aug 17 06:49:42 PM PDT 24 |
| Peak memory | 573284 kb |
| Host | smart-8207b08b-4769-46cf-ad6e-4808e2062237 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253010771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_and_unmapped_add r.1253010771 |
| Directory | /workspace/29.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_error_random.192960309 |
| Short name | T2881 |
| Test name | |
| Test status | |
| Simulation time | 944092851 ps |
| CPU time | 31.77 seconds |
| Started | Aug 17 06:49:34 PM PDT 24 |
| Finished | Aug 17 06:50:06 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-c463486d-461d-4bbb-8443-a20b8dfcd91e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192960309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_error_random.192960309 |
| Directory | /workspace/29.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random.3057955058 |
| Short name | T2533 |
| Test name | |
| Test status | |
| Simulation time | 141689105 ps |
| CPU time | 15.27 seconds |
| Started | Aug 17 06:49:35 PM PDT 24 |
| Finished | Aug 17 06:49:50 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a2f950b0-b517-4c29-a49e-eb66f5671a18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057955058 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random.3057955058 |
| Directory | /workspace/29.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_large_delays.4194572596 |
| Short name | T2610 |
| Test name | |
| Test status | |
| Simulation time | 103025227157 ps |
| CPU time | 1134.75 seconds |
| Started | Aug 17 06:49:35 PM PDT 24 |
| Finished | Aug 17 07:08:30 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-e3d4c01e-43bc-42da-9aae-d6be1c01679c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194572596 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_large_delays.4194572596 |
| Directory | /workspace/29.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_slow_rsp.3474174300 |
| Short name | T2147 |
| Test name | |
| Test status | |
| Simulation time | 17388895686 ps |
| CPU time | 293.38 seconds |
| Started | Aug 17 06:49:35 PM PDT 24 |
| Finished | Aug 17 06:54:29 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-173305eb-bbcc-43ae-ae02-0370b1cde451 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474174300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_slow_rsp.3474174300 |
| Directory | /workspace/29.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_random_zero_delays.4260584375 |
| Short name | T2349 |
| Test name | |
| Test status | |
| Simulation time | 29262418 ps |
| CPU time | 5.62 seconds |
| Started | Aug 17 06:49:35 PM PDT 24 |
| Finished | Aug 17 06:49:40 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-e853590d-3b73-46cf-8c4c-2e68847b149b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260584375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_random_zero_del ays.4260584375 |
| Directory | /workspace/29.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_same_source.1825195604 |
| Short name | T1808 |
| Test name | |
| Test status | |
| Simulation time | 1126596321 ps |
| CPU time | 32.66 seconds |
| Started | Aug 17 06:49:37 PM PDT 24 |
| Finished | Aug 17 06:50:09 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-c9c2b08c-608c-4718-aaa1-21bfbcc16454 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1825195604 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_same_source.1825195604 |
| Directory | /workspace/29.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke.2574352179 |
| Short name | T2229 |
| Test name | |
| Test status | |
| Simulation time | 44450405 ps |
| CPU time | 6.2 seconds |
| Started | Aug 17 06:49:35 PM PDT 24 |
| Finished | Aug 17 06:49:41 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-66e616fd-458f-4bb5-80e6-730da813f72d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574352179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke.2574352179 |
| Directory | /workspace/29.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.3332839212 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 6814765672 ps |
| CPU time | 65.99 seconds |
| Started | Aug 17 06:49:37 PM PDT 24 |
| Finished | Aug 17 06:50:43 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-214a002f-6ccc-473c-a454-5e9b61b029de |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332839212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_large_delays.3332839212 |
| Directory | /workspace/29.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_slow_rsp.3790839691 |
| Short name | T1399 |
| Test name | |
| Test status | |
| Simulation time | 5025538021 ps |
| CPU time | 88.43 seconds |
| Started | Aug 17 06:49:37 PM PDT 24 |
| Finished | Aug 17 06:51:05 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-684b5b93-1147-4431-b7e0-54fd4ce2b61a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790839691 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_slow_rsp.3790839691 |
| Directory | /workspace/29.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.929029466 |
| Short name | T2334 |
| Test name | |
| Test status | |
| Simulation time | 37930521 ps |
| CPU time | 5.59 seconds |
| Started | Aug 17 06:49:36 PM PDT 24 |
| Finished | Aug 17 06:49:42 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-312a1a19-ca47-4215-87b3-e949e65c707c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=929029466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_smoke_zero_delays .929029466 |
| Directory | /workspace/29.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all.3189976313 |
| Short name | T2179 |
| Test name | |
| Test status | |
| Simulation time | 1749491317 ps |
| CPU time | 139.04 seconds |
| Started | Aug 17 06:49:34 PM PDT 24 |
| Finished | Aug 17 06:51:53 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-342b7dc6-708f-4fe5-af35-e84ba2c0943b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189976313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all.3189976313 |
| Directory | /workspace/29.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_error.4204960113 |
| Short name | T2440 |
| Test name | |
| Test status | |
| Simulation time | 3162794676 ps |
| CPU time | 108.94 seconds |
| Started | Aug 17 06:49:41 PM PDT 24 |
| Finished | Aug 17 06:51:30 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-4d058949-4a12-4108-9644-52be3839ca8a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204960113 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all_with_error.4204960113 |
| Directory | /workspace/29.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_rand_reset.4120861561 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2083822344 ps |
| CPU time | 351.95 seconds |
| Started | Aug 17 06:49:42 PM PDT 24 |
| Finished | Aug 17 06:55:34 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-310720cb-42db-41c4-9a06-9bf2c54faddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120861561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_all _with_rand_reset.4120861561 |
| Directory | /workspace/29.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_stress_all_with_reset_error.3546844783 |
| Short name | T1523 |
| Test name | |
| Test status | |
| Simulation time | 1413503112 ps |
| CPU time | 178.17 seconds |
| Started | Aug 17 06:49:42 PM PDT 24 |
| Finished | Aug 17 06:52:40 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-b123752a-70a0-4834-9948-d7058468eb0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546844783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_stress_al l_with_reset_error.3546844783 |
| Directory | /workspace/29.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/29.xbar_unmapped_addr.3379769026 |
| Short name | T1522 |
| Test name | |
| Test status | |
| Simulation time | 223473176 ps |
| CPU time | 26.04 seconds |
| Started | Aug 17 06:49:36 PM PDT 24 |
| Finished | Aug 17 06:50:02 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-81c32626-3389-4729-be72-18a2f3d7ad2d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3379769026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.xbar_unmapped_addr.3379769026 |
| Directory | /workspace/29.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_aliasing.1202121233 |
| Short name | T2275 |
| Test name | |
| Test status | |
| Simulation time | 37126122160 ps |
| CPU time | 5452.35 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 08:18:23 PM PDT 24 |
| Peak memory | 597704 kb |
| Host | smart-f5d985b3-22d8-411b-8985-6a636514f83e |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202121233 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 3.chip_csr_aliasing.1202121233 |
| Directory | /workspace/3.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_bit_bash.637154478 |
| Short name | T1509 |
| Test name | |
| Test status | |
| Simulation time | 12004805584 ps |
| CPU time | 1124.02 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 07:06:23 PM PDT 24 |
| Peak memory | 597668 kb |
| Host | smart-aebeffaa-8961-4c56-86d4-dbd7daa09f4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637154478 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_bit_bash.637154478 |
| Directory | /workspace/3.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_mem_rw_with_rand_reset.3204341280 |
| Short name | T1552 |
| Test name | |
| Test status | |
| Simulation time | 7293974800 ps |
| CPU time | 403.16 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:54:32 PM PDT 24 |
| Peak memory | 642820 kb |
| Host | smart-a60635ae-2160-47fd-b95a-e74b13afaf89 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204341280 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 3.chip_csr_mem_rw_with_rand_reset.3204341280 |
| Directory | /workspace/3.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_csr_rw.174847014 |
| Short name | T2518 |
| Test name | |
| Test status | |
| Simulation time | 4605314924 ps |
| CPU time | 299.23 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:52:47 PM PDT 24 |
| Peak memory | 598740 kb |
| Host | smart-fa776d9a-19a1-438e-9497-bb904b586129 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174847014 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_csr_rw.174847014 |
| Directory | /workspace/3.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.4061848950 |
| Short name | T1710 |
| Test name | |
| Test status | |
| Simulation time | 17109396983 ps |
| CPU time | 2143.72 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 07:23:15 PM PDT 24 |
| Peak memory | 593032 kb |
| Host | smart-13389f8d-78c6-4abc-b7c0-8c6302a4b861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4061848950 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 3.chip_same_csr_outstanding.4061848950 |
| Directory | /workspace/3.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/3.chip_tl_errors.2084970787 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 4168876361 ps |
| CPU time | 301.82 seconds |
| Started | Aug 17 06:47:36 PM PDT 24 |
| Finished | Aug 17 06:52:38 PM PDT 24 |
| Peak memory | 604040 kb |
| Host | smart-9a534239-fd6d-406c-bcee-6a119ba7392d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084970787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.chip_tl_errors.2084970787 |
| Directory | /workspace/3.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_access_same_device.3984307780 |
| Short name | T2497 |
| Test name | |
| Test status | |
| Simulation time | 2321593536 ps |
| CPU time | 93.66 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:49:06 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-fcc11632-e1db-406a-8dca-e0fda0d5b9f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984307780 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_access_same_device. 3984307780 |
| Directory | /workspace/3.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_and_unmapped_addr.1022316001 |
| Short name | T2460 |
| Test name | |
| Test status | |
| Simulation time | 511965125 ps |
| CPU time | 19.18 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:47:50 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-04cd3a6d-0b15-439b-bd76-a51c65a92ee6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022316001 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_and_unmapped_addr .1022316001 |
| Directory | /workspace/3.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_error_random.3384463783 |
| Short name | T1606 |
| Test name | |
| Test status | |
| Simulation time | 271323569 ps |
| CPU time | 19.91 seconds |
| Started | Aug 17 06:47:36 PM PDT 24 |
| Finished | Aug 17 06:47:55 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-b93f8c66-6db3-4165-a8bd-103b34b7f0d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384463783 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_error_random.3384463783 |
| Directory | /workspace/3.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random.3447241653 |
| Short name | T2885 |
| Test name | |
| Test status | |
| Simulation time | 522753266 ps |
| CPU time | 44.99 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 06:48:15 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-893c2cc3-7208-4c62-9d9a-6815450089a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3447241653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random.3447241653 |
| Directory | /workspace/3.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_large_delays.3227930116 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 87494670155 ps |
| CPU time | 833.9 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 07:01:40 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-a398edaa-f83d-430a-b045-22d0c41d9c0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227930116 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_large_delays.3227930116 |
| Directory | /workspace/3.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_slow_rsp.281652783 |
| Short name | T1956 |
| Test name | |
| Test status | |
| Simulation time | 37555289150 ps |
| CPU time | 611.74 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 06:57:44 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-a5b7ba0a-c215-4885-a209-42982259a0e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281652783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_slow_rsp.281652783 |
| Directory | /workspace/3.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_random_zero_delays.4235170725 |
| Short name | T2493 |
| Test name | |
| Test status | |
| Simulation time | 121998770 ps |
| CPU time | 12.01 seconds |
| Started | Aug 17 06:47:36 PM PDT 24 |
| Finished | Aug 17 06:47:48 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-94998448-5964-40e9-ba49-1c23f43b6acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235170725 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_random_zero_dela ys.4235170725 |
| Directory | /workspace/3.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_same_source.4024521955 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 132301236 ps |
| CPU time | 11 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:47:56 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c9a05481-52e2-427a-a9f1-3086281682ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024521955 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_same_source.4024521955 |
| Directory | /workspace/3.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke.2413584815 |
| Short name | T2320 |
| Test name | |
| Test status | |
| Simulation time | 169999864 ps |
| CPU time | 7.13 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:47:40 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-7ce62f41-2f06-4454-bafc-b174157ea25c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413584815 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke.2413584815 |
| Directory | /workspace/3.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_large_delays.797328481 |
| Short name | T1854 |
| Test name | |
| Test status | |
| Simulation time | 9648887537 ps |
| CPU time | 95.63 seconds |
| Started | Aug 17 06:47:38 PM PDT 24 |
| Finished | Aug 17 06:49:14 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-771643ff-0a47-45f6-b470-6a4675bf8921 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797328481 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_large_delays.797328481 |
| Directory | /workspace/3.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_slow_rsp.3059966601 |
| Short name | T2096 |
| Test name | |
| Test status | |
| Simulation time | 4270857284 ps |
| CPU time | 69.69 seconds |
| Started | Aug 17 06:47:32 PM PDT 24 |
| Finished | Aug 17 06:48:42 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-56863072-5cbf-4796-abee-cd1578ab4e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059966601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_slow_rsp.3059966601 |
| Directory | /workspace/3.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1115546056 |
| Short name | T2066 |
| Test name | |
| Test status | |
| Simulation time | 41310047 ps |
| CPU time | 5.84 seconds |
| Started | Aug 17 06:47:24 PM PDT 24 |
| Finished | Aug 17 06:47:30 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-2ee13fd2-067e-4da0-b472-b303a06e85e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115546056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_smoke_zero_delays .1115546056 |
| Directory | /workspace/3.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all.2393597324 |
| Short name | T2866 |
| Test name | |
| Test status | |
| Simulation time | 5208142003 ps |
| CPU time | 192.06 seconds |
| Started | Aug 17 06:47:40 PM PDT 24 |
| Finished | Aug 17 06:50:52 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-8327dfe5-6feb-43f8-ad80-7063c47d4d28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2393597324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all.2393597324 |
| Directory | /workspace/3.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_error.4167624232 |
| Short name | T2285 |
| Test name | |
| Test status | |
| Simulation time | 1459795031 ps |
| CPU time | 52.58 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:41 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-2d122b01-c2a2-4a62-b5e5-4c81ecc60c8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167624232 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_with_error.4167624232 |
| Directory | /workspace/3.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_rand_reset.2372975114 |
| Short name | T1499 |
| Test name | |
| Test status | |
| Simulation time | 1275975136 ps |
| CPU time | 274.48 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:52:26 PM PDT 24 |
| Peak memory | 576272 kb |
| Host | smart-8389eb15-8306-4c27-863e-40308655cbb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372975114 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_rand_reset.2372975114 |
| Directory | /workspace/3.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_stress_all_with_reset_error.810483166 |
| Short name | T2718 |
| Test name | |
| Test status | |
| Simulation time | 14064963759 ps |
| CPU time | 687.54 seconds |
| Started | Aug 17 06:47:27 PM PDT 24 |
| Finished | Aug 17 06:58:55 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-e6fc4129-d857-4a8e-b8e9-56fe3b22c94f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=810483166 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_stress_all_ with_reset_error.810483166 |
| Directory | /workspace/3.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/3.xbar_unmapped_addr.2603841642 |
| Short name | T2168 |
| Test name | |
| Test status | |
| Simulation time | 435044843 ps |
| CPU time | 20.85 seconds |
| Started | Aug 17 06:47:35 PM PDT 24 |
| Finished | Aug 17 06:47:56 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-49abb5f0-16d2-4598-ba7a-142b7c689be2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603841642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.xbar_unmapped_addr.2603841642 |
| Directory | /workspace/3.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device.857605992 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 901846837 ps |
| CPU time | 65.65 seconds |
| Started | Aug 17 06:49:41 PM PDT 24 |
| Finished | Aug 17 06:50:47 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-0d4da544-0d5b-4dae-9a0b-0d5ae6069249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857605992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_device. 857605992 |
| Directory | /workspace/30.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.1586672124 |
| Short name | T2400 |
| Test name | |
| Test status | |
| Simulation time | 142343490030 ps |
| CPU time | 2407.37 seconds |
| Started | Aug 17 06:49:41 PM PDT 24 |
| Finished | Aug 17 07:29:49 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-07db3b3b-f846-45e8-b737-b122794426e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586672124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_access_same_ device_slow_rsp.1586672124 |
| Directory | /workspace/30.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_and_unmapped_addr.2082212476 |
| Short name | T1501 |
| Test name | |
| Test status | |
| Simulation time | 414074623 ps |
| CPU time | 19.33 seconds |
| Started | Aug 17 06:49:41 PM PDT 24 |
| Finished | Aug 17 06:50:01 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-eb311820-6e20-421e-8504-ad56bb5a5ecd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082212476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_and_unmapped_add r.2082212476 |
| Directory | /workspace/30.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_error_random.558347837 |
| Short name | T2340 |
| Test name | |
| Test status | |
| Simulation time | 355455000 ps |
| CPU time | 28.24 seconds |
| Started | Aug 17 06:49:42 PM PDT 24 |
| Finished | Aug 17 06:50:10 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-925bdbda-14e5-45e1-814d-0dcebe142648 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558347837 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_error_random.558347837 |
| Directory | /workspace/30.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random.922667670 |
| Short name | T2156 |
| Test name | |
| Test status | |
| Simulation time | 2029257454 ps |
| CPU time | 72.14 seconds |
| Started | Aug 17 06:49:44 PM PDT 24 |
| Finished | Aug 17 06:50:56 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-7fd148d9-0532-4dda-a519-262d455789f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922667670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random.922667670 |
| Directory | /workspace/30.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_large_delays.2059000926 |
| Short name | T2432 |
| Test name | |
| Test status | |
| Simulation time | 74456085145 ps |
| CPU time | 859.35 seconds |
| Started | Aug 17 06:49:40 PM PDT 24 |
| Finished | Aug 17 07:03:59 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-ecbe771c-0b95-427e-b2fd-cfedba75c2c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059000926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_large_delays.2059000926 |
| Directory | /workspace/30.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_slow_rsp.1814954777 |
| Short name | T1419 |
| Test name | |
| Test status | |
| Simulation time | 13208452528 ps |
| CPU time | 234.5 seconds |
| Started | Aug 17 06:49:41 PM PDT 24 |
| Finished | Aug 17 06:53:36 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-a93e614a-931b-4af7-b76b-cf30eb8dff07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814954777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_slow_rsp.1814954777 |
| Directory | /workspace/30.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_random_zero_delays.430719400 |
| Short name | T1541 |
| Test name | |
| Test status | |
| Simulation time | 120606261 ps |
| CPU time | 12.2 seconds |
| Started | Aug 17 06:49:43 PM PDT 24 |
| Finished | Aug 17 06:49:55 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-fb929a29-0cbc-4c6a-a38a-ccb6d2952627 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430719400 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_random_zero_dela ys.430719400 |
| Directory | /workspace/30.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_same_source.3624402380 |
| Short name | T1476 |
| Test name | |
| Test status | |
| Simulation time | 1365880862 ps |
| CPU time | 41.07 seconds |
| Started | Aug 17 06:49:41 PM PDT 24 |
| Finished | Aug 17 06:50:22 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-6ae31c3c-9bc8-44fe-a2ce-83b3cc591604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624402380 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_same_source.3624402380 |
| Directory | /workspace/30.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke.1578194009 |
| Short name | T2158 |
| Test name | |
| Test status | |
| Simulation time | 192202608 ps |
| CPU time | 8.85 seconds |
| Started | Aug 17 06:49:44 PM PDT 24 |
| Finished | Aug 17 06:49:53 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-44752a95-26af-409d-949d-bf55196ae21f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578194009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke.1578194009 |
| Directory | /workspace/30.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_large_delays.1632205714 |
| Short name | T2293 |
| Test name | |
| Test status | |
| Simulation time | 10140164386 ps |
| CPU time | 110.54 seconds |
| Started | Aug 17 06:49:45 PM PDT 24 |
| Finished | Aug 17 06:51:35 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-038ccab6-0276-4f1d-a844-ff85cf2a25ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632205714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_large_delays.1632205714 |
| Directory | /workspace/30.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.3441569820 |
| Short name | T2395 |
| Test name | |
| Test status | |
| Simulation time | 6139421151 ps |
| CPU time | 102.03 seconds |
| Started | Aug 17 06:49:42 PM PDT 24 |
| Finished | Aug 17 06:51:24 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-79a13d1a-3dcc-4c47-8874-e08913020309 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441569820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_slow_rsp.3441569820 |
| Directory | /workspace/30.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_smoke_zero_delays.1083460299 |
| Short name | T1670 |
| Test name | |
| Test status | |
| Simulation time | 50294647 ps |
| CPU time | 6.68 seconds |
| Started | Aug 17 06:49:44 PM PDT 24 |
| Finished | Aug 17 06:49:50 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-d806e163-9ed2-4b9b-9ce3-3e25e0fad8be |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083460299 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_smoke_zero_delay s.1083460299 |
| Directory | /workspace/30.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all.2319847351 |
| Short name | T2799 |
| Test name | |
| Test status | |
| Simulation time | 7598524636 ps |
| CPU time | 290.14 seconds |
| Started | Aug 17 06:49:44 PM PDT 24 |
| Finished | Aug 17 06:54:34 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-fb1df54e-acaa-405d-b180-38ebe9a587c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319847351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all.2319847351 |
| Directory | /workspace/30.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_rand_reset.1529411424 |
| Short name | T2741 |
| Test name | |
| Test status | |
| Simulation time | 492588524 ps |
| CPU time | 179.72 seconds |
| Started | Aug 17 06:49:44 PM PDT 24 |
| Finished | Aug 17 06:52:43 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-0c4da4a4-96ec-4ee1-98a1-ca4501dff15f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529411424 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_all _with_rand_reset.1529411424 |
| Directory | /workspace/30.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_stress_all_with_reset_error.3393366064 |
| Short name | T2498 |
| Test name | |
| Test status | |
| Simulation time | 506402726 ps |
| CPU time | 74.08 seconds |
| Started | Aug 17 06:49:41 PM PDT 24 |
| Finished | Aug 17 06:50:55 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-082fb5a9-6674-482a-8aba-24f87b581f1b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393366064 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_stress_al l_with_reset_error.3393366064 |
| Directory | /workspace/30.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/30.xbar_unmapped_addr.3108055949 |
| Short name | T1740 |
| Test name | |
| Test status | |
| Simulation time | 728103970 ps |
| CPU time | 30.86 seconds |
| Started | Aug 17 06:49:42 PM PDT 24 |
| Finished | Aug 17 06:50:12 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-cceb702d-b02b-467d-a2c0-795adb0e62b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108055949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.xbar_unmapped_addr.3108055949 |
| Directory | /workspace/30.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device.1288346768 |
| Short name | T2842 |
| Test name | |
| Test status | |
| Simulation time | 1839443505 ps |
| CPU time | 73.43 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 06:51:02 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-e7204f0b-a0fa-4536-8530-a4ba88f965a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288346768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_device .1288346768 |
| Directory | /workspace/31.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_access_same_device_slow_rsp.203144659 |
| Short name | T2744 |
| Test name | |
| Test status | |
| Simulation time | 115887565223 ps |
| CPU time | 1897.96 seconds |
| Started | Aug 17 06:49:50 PM PDT 24 |
| Finished | Aug 17 07:21:28 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-fda44886-407f-4d13-805a-ac1402d8002e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203144659 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_access_same_d evice_slow_rsp.203144659 |
| Directory | /workspace/31.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_and_unmapped_addr.1937321574 |
| Short name | T1774 |
| Test name | |
| Test status | |
| Simulation time | 642266633 ps |
| CPU time | 25.85 seconds |
| Started | Aug 17 06:49:53 PM PDT 24 |
| Finished | Aug 17 06:50:19 PM PDT 24 |
| Peak memory | 575320 kb |
| Host | smart-25542b46-a9b3-42b6-a3db-9e5fb28f3bad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937321574 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_and_unmapped_add r.1937321574 |
| Directory | /workspace/31.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_error_random.1234822315 |
| Short name | T2668 |
| Test name | |
| Test status | |
| Simulation time | 472418035 ps |
| CPU time | 35.03 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 06:50:24 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-06cdee85-4ae3-48a8-bc10-b59a9b21f94e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234822315 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_error_random.1234822315 |
| Directory | /workspace/31.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random.1630179117 |
| Short name | T1497 |
| Test name | |
| Test status | |
| Simulation time | 686513374 ps |
| CPU time | 27.6 seconds |
| Started | Aug 17 06:49:48 PM PDT 24 |
| Finished | Aug 17 06:50:16 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-acba302f-164e-4a21-85b7-8ad88493fd09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630179117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random.1630179117 |
| Directory | /workspace/31.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_large_delays.3560855785 |
| Short name | T1860 |
| Test name | |
| Test status | |
| Simulation time | 68662785911 ps |
| CPU time | 801.83 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 07:03:11 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-d3739974-2058-407b-b6a5-ddc9d62a4c05 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560855785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_large_delays.3560855785 |
| Directory | /workspace/31.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_slow_rsp.2520923103 |
| Short name | T2383 |
| Test name | |
| Test status | |
| Simulation time | 5859492926 ps |
| CPU time | 99.4 seconds |
| Started | Aug 17 06:49:53 PM PDT 24 |
| Finished | Aug 17 06:51:33 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-b30814cf-dc9a-4455-b618-b8498889697a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520923103 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_slow_rsp.2520923103 |
| Directory | /workspace/31.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_random_zero_delays.3039344287 |
| Short name | T2690 |
| Test name | |
| Test status | |
| Simulation time | 381012064 ps |
| CPU time | 34.59 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 06:50:24 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-9ea5b036-d2ca-4abf-991c-9046a70ac552 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039344287 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_random_zero_del ays.3039344287 |
| Directory | /workspace/31.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_same_source.1010329333 |
| Short name | T2376 |
| Test name | |
| Test status | |
| Simulation time | 2351236107 ps |
| CPU time | 73.45 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 06:51:03 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-6c7337b5-2038-441c-aa2e-af7cf1d733eb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010329333 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_same_source.1010329333 |
| Directory | /workspace/31.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke.4259113025 |
| Short name | T2191 |
| Test name | |
| Test status | |
| Simulation time | 200099772 ps |
| CPU time | 8.41 seconds |
| Started | Aug 17 06:49:43 PM PDT 24 |
| Finished | Aug 17 06:49:51 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-12257645-9a79-46ca-aa46-c1894240cb53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259113025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke.4259113025 |
| Directory | /workspace/31.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_large_delays.391423601 |
| Short name | T1702 |
| Test name | |
| Test status | |
| Simulation time | 5454534873 ps |
| CPU time | 58.44 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 06:50:47 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-0cb34077-1c1a-4d93-98c9-27fbee5c05a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391423601 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_large_delays.391423601 |
| Directory | /workspace/31.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_slow_rsp.1007386479 |
| Short name | T2025 |
| Test name | |
| Test status | |
| Simulation time | 6317501608 ps |
| CPU time | 106.03 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 06:51:35 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-10f667f1-49a4-4309-8235-daf965da34b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007386479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_slow_rsp.1007386479 |
| Directory | /workspace/31.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1896348349 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 45531657 ps |
| CPU time | 6.69 seconds |
| Started | Aug 17 06:49:39 PM PDT 24 |
| Finished | Aug 17 06:49:46 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-fee4b199-a42a-4b68-be84-e96e77162388 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896348349 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_smoke_zero_delay s.1896348349 |
| Directory | /workspace/31.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all.547864117 |
| Short name | T2237 |
| Test name | |
| Test status | |
| Simulation time | 2502034235 ps |
| CPU time | 91.17 seconds |
| Started | Aug 17 06:49:53 PM PDT 24 |
| Finished | Aug 17 06:51:24 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-a7086530-095d-4cf6-9d0c-5030bc5b6120 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547864117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all.547864117 |
| Directory | /workspace/31.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_error.3909291092 |
| Short name | T2379 |
| Test name | |
| Test status | |
| Simulation time | 2469902532 ps |
| CPU time | 199.46 seconds |
| Started | Aug 17 06:49:50 PM PDT 24 |
| Finished | Aug 17 06:53:10 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-7603ffbb-14ca-4486-b9f2-a366ca5da0d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3909291092 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_with_error.3909291092 |
| Directory | /workspace/31.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_rand_reset.726753958 |
| Short name | T2059 |
| Test name | |
| Test status | |
| Simulation time | 15885643908 ps |
| CPU time | 766.42 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 07:02:36 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-7fc08dae-fb80-42f5-a084-d23cbcd40c80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726753958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all_ with_rand_reset.726753958 |
| Directory | /workspace/31.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.430010950 |
| Short name | T1903 |
| Test name | |
| Test status | |
| Simulation time | 1822202850 ps |
| CPU time | 288.63 seconds |
| Started | Aug 17 06:49:49 PM PDT 24 |
| Finished | Aug 17 06:54:37 PM PDT 24 |
| Peak memory | 576348 kb |
| Host | smart-f52feca0-d8e6-4a6c-a77b-c704e4b23572 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430010950 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_stress_all _with_reset_error.430010950 |
| Directory | /workspace/31.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/31.xbar_unmapped_addr.1374559570 |
| Short name | T2090 |
| Test name | |
| Test status | |
| Simulation time | 22941849 ps |
| CPU time | 5.54 seconds |
| Started | Aug 17 06:49:53 PM PDT 24 |
| Finished | Aug 17 06:49:59 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-cae31930-bea3-4416-a7f2-de647fe03cb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374559570 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.xbar_unmapped_addr.1374559570 |
| Directory | /workspace/31.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device.2319133693 |
| Short name | T2831 |
| Test name | |
| Test status | |
| Simulation time | 341037025 ps |
| CPU time | 24.13 seconds |
| Started | Aug 17 06:49:55 PM PDT 24 |
| Finished | Aug 17 06:50:19 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-a005bdb7-a820-43f5-ad1f-0155ea27c1d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319133693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_device .2319133693 |
| Directory | /workspace/32.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_access_same_device_slow_rsp.1266555338 |
| Short name | T1940 |
| Test name | |
| Test status | |
| Simulation time | 137792359096 ps |
| CPU time | 2538.9 seconds |
| Started | Aug 17 06:49:55 PM PDT 24 |
| Finished | Aug 17 07:32:14 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-69c7ee7c-dd9d-45ab-bae8-dae6f1e08e51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266555338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_access_same_ device_slow_rsp.1266555338 |
| Directory | /workspace/32.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_and_unmapped_addr.3263304086 |
| Short name | T1937 |
| Test name | |
| Test status | |
| Simulation time | 1333147695 ps |
| CPU time | 50.15 seconds |
| Started | Aug 17 06:49:59 PM PDT 24 |
| Finished | Aug 17 06:50:49 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-c0c0f4ba-6f16-4c0b-a954-cb1bf5b7fd29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263304086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_and_unmapped_add r.3263304086 |
| Directory | /workspace/32.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_error_random.2109975254 |
| Short name | T1821 |
| Test name | |
| Test status | |
| Simulation time | 967928688 ps |
| CPU time | 31.04 seconds |
| Started | Aug 17 06:50:05 PM PDT 24 |
| Finished | Aug 17 06:50:36 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-b322a153-1e8e-4f49-abe8-65ff4dfedfde |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109975254 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_error_random.2109975254 |
| Directory | /workspace/32.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random.4037787882 |
| Short name | T1809 |
| Test name | |
| Test status | |
| Simulation time | 116068466 ps |
| CPU time | 7.75 seconds |
| Started | Aug 17 06:49:55 PM PDT 24 |
| Finished | Aug 17 06:50:03 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-17e9f8c8-596f-4d55-8f98-3db2cfc9d067 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037787882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random.4037787882 |
| Directory | /workspace/32.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_large_delays.2741493260 |
| Short name | T2048 |
| Test name | |
| Test status | |
| Simulation time | 45246596332 ps |
| CPU time | 498 seconds |
| Started | Aug 17 06:49:58 PM PDT 24 |
| Finished | Aug 17 06:58:16 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-81b6dc65-03df-4d67-90ad-96ede8b9a604 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2741493260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_large_delays.2741493260 |
| Directory | /workspace/32.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.3904851705 |
| Short name | T1494 |
| Test name | |
| Test status | |
| Simulation time | 60645907845 ps |
| CPU time | 940.09 seconds |
| Started | Aug 17 06:50:05 PM PDT 24 |
| Finished | Aug 17 07:05:45 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-fb569047-6d88-41c4-bf6a-c19f1281ced2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3904851705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_slow_rsp.3904851705 |
| Directory | /workspace/32.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_random_zero_delays.286637156 |
| Short name | T2637 |
| Test name | |
| Test status | |
| Simulation time | 533983736 ps |
| CPU time | 48.32 seconds |
| Started | Aug 17 06:49:58 PM PDT 24 |
| Finished | Aug 17 06:50:46 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-2bfd0599-c998-4220-b12a-75f69efe5881 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286637156 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_random_zero_dela ys.286637156 |
| Directory | /workspace/32.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_same_source.2904869539 |
| Short name | T2040 |
| Test name | |
| Test status | |
| Simulation time | 1159912621 ps |
| CPU time | 30.51 seconds |
| Started | Aug 17 06:50:06 PM PDT 24 |
| Finished | Aug 17 06:50:36 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-4b088872-2380-414f-bb00-e851c5803ead |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904869539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_same_source.2904869539 |
| Directory | /workspace/32.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke.1860372748 |
| Short name | T1594 |
| Test name | |
| Test status | |
| Simulation time | 36935634 ps |
| CPU time | 5.43 seconds |
| Started | Aug 17 06:49:55 PM PDT 24 |
| Finished | Aug 17 06:50:00 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-65923432-70d7-44e7-8e82-06f2a99fb68a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860372748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke.1860372748 |
| Directory | /workspace/32.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.651589146 |
| Short name | T2408 |
| Test name | |
| Test status | |
| Simulation time | 8257143284 ps |
| CPU time | 86.03 seconds |
| Started | Aug 17 06:49:56 PM PDT 24 |
| Finished | Aug 17 06:51:22 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-47d31660-a4b6-4102-ad7b-964d55b0850f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651589146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_large_delays.651589146 |
| Directory | /workspace/32.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_slow_rsp.541049645 |
| Short name | T1652 |
| Test name | |
| Test status | |
| Simulation time | 5788721882 ps |
| CPU time | 99.41 seconds |
| Started | Aug 17 06:49:55 PM PDT 24 |
| Finished | Aug 17 06:51:35 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-159041c1-e8a6-45d2-81de-bfeefe8da018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541049645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_slow_rsp.541049645 |
| Directory | /workspace/32.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_smoke_zero_delays.3735010524 |
| Short name | T1905 |
| Test name | |
| Test status | |
| Simulation time | 54279595 ps |
| CPU time | 6.67 seconds |
| Started | Aug 17 06:50:05 PM PDT 24 |
| Finished | Aug 17 06:50:12 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-47fa6d99-4cf9-40e8-9c4a-1ffdad74cd18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3735010524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_smoke_zero_delay s.3735010524 |
| Directory | /workspace/32.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all.2728753989 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 11062272348 ps |
| CPU time | 433.43 seconds |
| Started | Aug 17 06:49:55 PM PDT 24 |
| Finished | Aug 17 06:57:08 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-6fced8a0-08a7-47d4-b05c-5807328cdc3a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728753989 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all.2728753989 |
| Directory | /workspace/32.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_error.174496645 |
| Short name | T2904 |
| Test name | |
| Test status | |
| Simulation time | 1835972531 ps |
| CPU time | 74.69 seconds |
| Started | Aug 17 06:49:54 PM PDT 24 |
| Finished | Aug 17 06:51:09 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-ab8446cd-ec93-4bb9-9040-a609adf7f7cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174496645 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all_with_error.174496645 |
| Directory | /workspace/32.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_rand_reset.2315595751 |
| Short name | T2594 |
| Test name | |
| Test status | |
| Simulation time | 4430633567 ps |
| CPU time | 549.95 seconds |
| Started | Aug 17 06:50:04 PM PDT 24 |
| Finished | Aug 17 06:59:14 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-cd61b7a3-7fa5-4fd4-be30-0d671034458a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315595751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_all _with_rand_reset.2315595751 |
| Directory | /workspace/32.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_stress_all_with_reset_error.2442730704 |
| Short name | T1999 |
| Test name | |
| Test status | |
| Simulation time | 314482521 ps |
| CPU time | 93.06 seconds |
| Started | Aug 17 06:50:02 PM PDT 24 |
| Finished | Aug 17 06:51:35 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-15676d9e-1429-4141-9c3a-d69d06c56bc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442730704 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_stress_al l_with_reset_error.2442730704 |
| Directory | /workspace/32.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/32.xbar_unmapped_addr.1652205420 |
| Short name | T2060 |
| Test name | |
| Test status | |
| Simulation time | 315160503 ps |
| CPU time | 15.39 seconds |
| Started | Aug 17 06:49:59 PM PDT 24 |
| Finished | Aug 17 06:50:15 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-48f4f266-28b5-4cbb-9836-4f5386d3c555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652205420 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.xbar_unmapped_addr.1652205420 |
| Directory | /workspace/32.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_access_same_device.476751789 |
| Short name | T1437 |
| Test name | |
| Test status | |
| Simulation time | 403324270 ps |
| CPU time | 15.31 seconds |
| Started | Aug 17 06:50:15 PM PDT 24 |
| Finished | Aug 17 06:50:30 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-a4f39e44-3c88-4eee-8a97-132b1bfc6d54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476751789 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_access_same_device. 476751789 |
| Directory | /workspace/33.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.3484442701 |
| Short name | T1730 |
| Test name | |
| Test status | |
| Simulation time | 80725840 ps |
| CPU time | 11.65 seconds |
| Started | Aug 17 06:50:01 PM PDT 24 |
| Finished | Aug 17 06:50:13 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-5fbc3a3b-6131-4119-9299-a688ec534476 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484442701 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_and_unmapped_add r.3484442701 |
| Directory | /workspace/33.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_error_random.1401598212 |
| Short name | T2026 |
| Test name | |
| Test status | |
| Simulation time | 336354147 ps |
| CPU time | 27.27 seconds |
| Started | Aug 17 06:50:02 PM PDT 24 |
| Finished | Aug 17 06:50:30 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-5edf901e-4a05-4820-912c-7e1b638277c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401598212 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_error_random.1401598212 |
| Directory | /workspace/33.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random.4119601740 |
| Short name | T1997 |
| Test name | |
| Test status | |
| Simulation time | 667331597 ps |
| CPU time | 23.54 seconds |
| Started | Aug 17 06:50:01 PM PDT 24 |
| Finished | Aug 17 06:50:25 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-e01dc8a3-6584-4f24-a0be-88524207f811 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119601740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random.4119601740 |
| Directory | /workspace/33.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_large_delays.3711581886 |
| Short name | T2010 |
| Test name | |
| Test status | |
| Simulation time | 19045032929 ps |
| CPU time | 186.79 seconds |
| Started | Aug 17 06:50:02 PM PDT 24 |
| Finished | Aug 17 06:53:09 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-bdacaee3-2266-4136-bcb7-73e69e2c5339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3711581886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_large_delays.3711581886 |
| Directory | /workspace/33.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_slow_rsp.2589769150 |
| Short name | T1675 |
| Test name | |
| Test status | |
| Simulation time | 60505781446 ps |
| CPU time | 986.09 seconds |
| Started | Aug 17 06:50:12 PM PDT 24 |
| Finished | Aug 17 07:06:38 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-c109bfbf-7a4a-4224-ab55-3c23518056d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2589769150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_slow_rsp.2589769150 |
| Directory | /workspace/33.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_random_zero_delays.3767686117 |
| Short name | T2344 |
| Test name | |
| Test status | |
| Simulation time | 312025494 ps |
| CPU time | 29.33 seconds |
| Started | Aug 17 06:50:00 PM PDT 24 |
| Finished | Aug 17 06:50:30 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-2e795ee4-b436-49b3-b1df-7935cbac20d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767686117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_random_zero_del ays.3767686117 |
| Directory | /workspace/33.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_same_source.3271745906 |
| Short name | T2782 |
| Test name | |
| Test status | |
| Simulation time | 2650141019 ps |
| CPU time | 82.32 seconds |
| Started | Aug 17 06:50:03 PM PDT 24 |
| Finished | Aug 17 06:51:25 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-9ce3a5d8-19e5-4beb-b003-d27d5e25f33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271745906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_same_source.3271745906 |
| Directory | /workspace/33.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke.3336442877 |
| Short name | T1704 |
| Test name | |
| Test status | |
| Simulation time | 56335298 ps |
| CPU time | 7.24 seconds |
| Started | Aug 17 06:50:01 PM PDT 24 |
| Finished | Aug 17 06:50:08 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-1facf1ce-df05-4cb5-ad39-e6f7d86987fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336442877 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke.3336442877 |
| Directory | /workspace/33.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3807375448 |
| Short name | T2644 |
| Test name | |
| Test status | |
| Simulation time | 9545859410 ps |
| CPU time | 105.33 seconds |
| Started | Aug 17 06:50:03 PM PDT 24 |
| Finished | Aug 17 06:51:48 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-fefe7594-b8c2-4caf-a24c-94a6857069dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807375448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_large_delays.3807375448 |
| Directory | /workspace/33.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.3660925873 |
| Short name | T2438 |
| Test name | |
| Test status | |
| Simulation time | 5305776823 ps |
| CPU time | 89.7 seconds |
| Started | Aug 17 06:50:02 PM PDT 24 |
| Finished | Aug 17 06:51:32 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-d7d4d1e0-094a-49f7-abff-32e66182dc2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660925873 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_slow_rsp.3660925873 |
| Directory | /workspace/33.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_smoke_zero_delays.1076779845 |
| Short name | T1706 |
| Test name | |
| Test status | |
| Simulation time | 50002370 ps |
| CPU time | 6.41 seconds |
| Started | Aug 17 06:50:01 PM PDT 24 |
| Finished | Aug 17 06:50:07 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-06226809-8207-4384-9dfa-0a8d7ee136a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1076779845 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_smoke_zero_delay s.1076779845 |
| Directory | /workspace/33.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all.1401889851 |
| Short name | T2361 |
| Test name | |
| Test status | |
| Simulation time | 3248409212 ps |
| CPU time | 118.39 seconds |
| Started | Aug 17 06:50:07 PM PDT 24 |
| Finished | Aug 17 06:52:05 PM PDT 24 |
| Peak memory | 575864 kb |
| Host | smart-17f9fb1c-438a-4060-b3c2-7226d84bf613 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401889851 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all.1401889851 |
| Directory | /workspace/33.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_error.3072519149 |
| Short name | T2707 |
| Test name | |
| Test status | |
| Simulation time | 2991217662 ps |
| CPU time | 234.3 seconds |
| Started | Aug 17 06:50:10 PM PDT 24 |
| Finished | Aug 17 06:54:05 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-0004a124-421e-49d3-ab55-81e7114c30fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072519149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all_with_error.3072519149 |
| Directory | /workspace/33.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_rand_reset.4252147435 |
| Short name | T2193 |
| Test name | |
| Test status | |
| Simulation time | 5993964039 ps |
| CPU time | 913.51 seconds |
| Started | Aug 17 06:50:08 PM PDT 24 |
| Finished | Aug 17 07:05:22 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-a6f12552-112c-4001-a68a-e1a774078371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252147435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_all _with_rand_reset.4252147435 |
| Directory | /workspace/33.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_stress_all_with_reset_error.2703395918 |
| Short name | T2164 |
| Test name | |
| Test status | |
| Simulation time | 2403866965 ps |
| CPU time | 367.5 seconds |
| Started | Aug 17 06:50:13 PM PDT 24 |
| Finished | Aug 17 06:56:21 PM PDT 24 |
| Peak memory | 576568 kb |
| Host | smart-931e59fa-88d0-42ba-8bb8-91ee92d9c7af |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703395918 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_stress_al l_with_reset_error.2703395918 |
| Directory | /workspace/33.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/33.xbar_unmapped_addr.3750778035 |
| Short name | T2289 |
| Test name | |
| Test status | |
| Simulation time | 346843623 ps |
| CPU time | 18.19 seconds |
| Started | Aug 17 06:50:02 PM PDT 24 |
| Finished | Aug 17 06:50:20 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-921c2939-246d-46e3-80bc-05b2e3261522 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750778035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.xbar_unmapped_addr.3750778035 |
| Directory | /workspace/33.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device.3124662755 |
| Short name | T1743 |
| Test name | |
| Test status | |
| Simulation time | 826093358 ps |
| CPU time | 58.72 seconds |
| Started | Aug 17 06:50:09 PM PDT 24 |
| Finished | Aug 17 06:51:08 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-b7f1b120-b254-4d8b-b186-b6057748938e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124662755 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_device .3124662755 |
| Directory | /workspace/34.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_access_same_device_slow_rsp.4208144976 |
| Short name | T2182 |
| Test name | |
| Test status | |
| Simulation time | 82799007297 ps |
| CPU time | 1568.92 seconds |
| Started | Aug 17 06:50:08 PM PDT 24 |
| Finished | Aug 17 07:16:17 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-e004f4dd-95d5-42fd-b51d-c8ab358d8555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208144976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_access_same_ device_slow_rsp.4208144976 |
| Directory | /workspace/34.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.4240749430 |
| Short name | T2661 |
| Test name | |
| Test status | |
| Simulation time | 1275957032 ps |
| CPU time | 46.48 seconds |
| Started | Aug 17 06:50:20 PM PDT 24 |
| Finished | Aug 17 06:51:07 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-3620415f-4b91-4014-86b0-1732ae26aa29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240749430 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_and_unmapped_add r.4240749430 |
| Directory | /workspace/34.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_error_random.3293823752 |
| Short name | T1496 |
| Test name | |
| Test status | |
| Simulation time | 618724180 ps |
| CPU time | 22.59 seconds |
| Started | Aug 17 06:50:09 PM PDT 24 |
| Finished | Aug 17 06:50:32 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-259dbcf5-7205-4524-8b5c-72bde0a40e80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293823752 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_error_random.3293823752 |
| Directory | /workspace/34.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random.1124680248 |
| Short name | T2698 |
| Test name | |
| Test status | |
| Simulation time | 1522772362 ps |
| CPU time | 57.18 seconds |
| Started | Aug 17 06:50:09 PM PDT 24 |
| Finished | Aug 17 06:51:06 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-47531f35-8222-4ec6-92ee-d9f950df14fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124680248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random.1124680248 |
| Directory | /workspace/34.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_large_delays.2849049979 |
| Short name | T2098 |
| Test name | |
| Test status | |
| Simulation time | 108778390109 ps |
| CPU time | 1121.7 seconds |
| Started | Aug 17 06:50:09 PM PDT 24 |
| Finished | Aug 17 07:08:51 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-7b42d497-7d3b-4365-9e75-a448ef825fac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849049979 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_large_delays.2849049979 |
| Directory | /workspace/34.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_slow_rsp.4269520722 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 46868143254 ps |
| CPU time | 853.77 seconds |
| Started | Aug 17 06:50:09 PM PDT 24 |
| Finished | Aug 17 07:04:23 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-afd4a237-f9cb-411f-8152-0753c4d9454e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269520722 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_slow_rsp.4269520722 |
| Directory | /workspace/34.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_random_zero_delays.552075115 |
| Short name | T2873 |
| Test name | |
| Test status | |
| Simulation time | 477447137 ps |
| CPU time | 46.83 seconds |
| Started | Aug 17 06:50:09 PM PDT 24 |
| Finished | Aug 17 06:50:56 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-775f247f-e7a1-487c-925a-34fe63af74f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552075115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_random_zero_dela ys.552075115 |
| Directory | /workspace/34.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_same_source.2880687135 |
| Short name | T2368 |
| Test name | |
| Test status | |
| Simulation time | 1874866856 ps |
| CPU time | 57.89 seconds |
| Started | Aug 17 06:50:08 PM PDT 24 |
| Finished | Aug 17 06:51:06 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-0a8b5d14-f131-488c-b38d-0a2df03f7e27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880687135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_same_source.2880687135 |
| Directory | /workspace/34.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke.4084614010 |
| Short name | T2805 |
| Test name | |
| Test status | |
| Simulation time | 166940143 ps |
| CPU time | 8.22 seconds |
| Started | Aug 17 06:50:13 PM PDT 24 |
| Finished | Aug 17 06:50:21 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-925679ea-1f54-477e-adba-40e589ab3b35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084614010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke.4084614010 |
| Directory | /workspace/34.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_large_delays.712103094 |
| Short name | T1728 |
| Test name | |
| Test status | |
| Simulation time | 8563512594 ps |
| CPU time | 83.02 seconds |
| Started | Aug 17 06:50:20 PM PDT 24 |
| Finished | Aug 17 06:51:43 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-0235c079-4679-4c02-955a-684e976ad3a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712103094 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_large_delays.712103094 |
| Directory | /workspace/34.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.3245347328 |
| Short name | T2673 |
| Test name | |
| Test status | |
| Simulation time | 4692259060 ps |
| CPU time | 77.99 seconds |
| Started | Aug 17 06:50:07 PM PDT 24 |
| Finished | Aug 17 06:51:25 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-153c958b-2419-4625-9d80-c0c901643865 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245347328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_slow_rsp.3245347328 |
| Directory | /workspace/34.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_smoke_zero_delays.2340560652 |
| Short name | T2277 |
| Test name | |
| Test status | |
| Simulation time | 44836614 ps |
| CPU time | 6.35 seconds |
| Started | Aug 17 06:50:12 PM PDT 24 |
| Finished | Aug 17 06:50:19 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-bfbd68c6-4147-4731-ad64-f283983bdc47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340560652 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_smoke_zero_delay s.2340560652 |
| Directory | /workspace/34.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all.1343896185 |
| Short name | T2295 |
| Test name | |
| Test status | |
| Simulation time | 5616340294 ps |
| CPU time | 186.33 seconds |
| Started | Aug 17 06:50:20 PM PDT 24 |
| Finished | Aug 17 06:53:27 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-fbef9421-8813-4ee2-bf7d-fa0f19938c46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343896185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all.1343896185 |
| Directory | /workspace/34.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.1045371666 |
| Short name | T1917 |
| Test name | |
| Test status | |
| Simulation time | 2716817734 ps |
| CPU time | 387.95 seconds |
| Started | Aug 17 06:50:10 PM PDT 24 |
| Finished | Aug 17 06:56:38 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-d9c06423-1fd7-467e-9bdf-8761d02bd924 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045371666 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_all _with_rand_reset.1045371666 |
| Directory | /workspace/34.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_stress_all_with_reset_error.1727601409 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 5989380777 ps |
| CPU time | 652.14 seconds |
| Started | Aug 17 06:50:15 PM PDT 24 |
| Finished | Aug 17 07:01:08 PM PDT 24 |
| Peak memory | 577436 kb |
| Host | smart-40b74523-2b90-4b42-8691-98855a10bf01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727601409 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_stress_al l_with_reset_error.1727601409 |
| Directory | /workspace/34.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/34.xbar_unmapped_addr.456843222 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 82757233 ps |
| CPU time | 11.83 seconds |
| Started | Aug 17 06:50:08 PM PDT 24 |
| Finished | Aug 17 06:50:20 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-f03196ad-c216-4e9c-9735-4ad0d5f69a74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456843222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.xbar_unmapped_addr.456843222 |
| Directory | /workspace/34.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device.1859729289 |
| Short name | T2473 |
| Test name | |
| Test status | |
| Simulation time | 1285096852 ps |
| CPU time | 50.86 seconds |
| Started | Aug 17 06:50:16 PM PDT 24 |
| Finished | Aug 17 06:51:06 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-ce73f470-0cf9-44a9-b026-94e03046c61b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859729289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_device .1859729289 |
| Directory | /workspace/35.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_access_same_device_slow_rsp.878407804 |
| Short name | T2475 |
| Test name | |
| Test status | |
| Simulation time | 81472709999 ps |
| CPU time | 1409.75 seconds |
| Started | Aug 17 06:50:14 PM PDT 24 |
| Finished | Aug 17 07:13:44 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-968945a3-2bea-4e94-924c-946069aa779a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878407804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_access_same_d evice_slow_rsp.878407804 |
| Directory | /workspace/35.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_and_unmapped_addr.1461164220 |
| Short name | T2468 |
| Test name | |
| Test status | |
| Simulation time | 115101619 ps |
| CPU time | 15.42 seconds |
| Started | Aug 17 06:50:16 PM PDT 24 |
| Finished | Aug 17 06:50:31 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-c9f355bc-b37a-413b-82bf-a0059f4a07a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461164220 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_and_unmapped_add r.1461164220 |
| Directory | /workspace/35.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_error_random.472593669 |
| Short name | T2614 |
| Test name | |
| Test status | |
| Simulation time | 961427514 ps |
| CPU time | 31.97 seconds |
| Started | Aug 17 06:50:13 PM PDT 24 |
| Finished | Aug 17 06:50:45 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-bb196a47-b38d-4892-9404-96efc17e981c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472593669 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_error_random.472593669 |
| Directory | /workspace/35.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random.2672331907 |
| Short name | T1588 |
| Test name | |
| Test status | |
| Simulation time | 751197803 ps |
| CPU time | 31.55 seconds |
| Started | Aug 17 06:50:14 PM PDT 24 |
| Finished | Aug 17 06:50:45 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-8656f10d-549f-492a-b86a-7c93b8de268e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672331907 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random.2672331907 |
| Directory | /workspace/35.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_large_delays.4102408765 |
| Short name | T1853 |
| Test name | |
| Test status | |
| Simulation time | 98817953735 ps |
| CPU time | 1111.24 seconds |
| Started | Aug 17 06:50:13 PM PDT 24 |
| Finished | Aug 17 07:08:44 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-1e8c0967-b536-4511-a401-c72b19a71e08 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102408765 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_large_delays.4102408765 |
| Directory | /workspace/35.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_slow_rsp.3757025761 |
| Short name | T2350 |
| Test name | |
| Test status | |
| Simulation time | 4414748611 ps |
| CPU time | 73.61 seconds |
| Started | Aug 17 06:50:12 PM PDT 24 |
| Finished | Aug 17 06:51:26 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-8e9459a6-dd58-4432-90a6-b4b66414e02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757025761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_slow_rsp.3757025761 |
| Directory | /workspace/35.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_random_zero_delays.2968979186 |
| Short name | T1468 |
| Test name | |
| Test status | |
| Simulation time | 280915860 ps |
| CPU time | 24.97 seconds |
| Started | Aug 17 06:50:12 PM PDT 24 |
| Finished | Aug 17 06:50:37 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-30af4b6c-3acd-4631-ad6f-292f1296041a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968979186 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_random_zero_del ays.2968979186 |
| Directory | /workspace/35.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_same_source.1060402498 |
| Short name | T1621 |
| Test name | |
| Test status | |
| Simulation time | 503499428 ps |
| CPU time | 32.19 seconds |
| Started | Aug 17 06:50:14 PM PDT 24 |
| Finished | Aug 17 06:50:46 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-06bf6c93-722f-42da-8309-800e8aa8beeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060402498 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_same_source.1060402498 |
| Directory | /workspace/35.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke.3388483206 |
| Short name | T1891 |
| Test name | |
| Test status | |
| Simulation time | 176860975 ps |
| CPU time | 8.09 seconds |
| Started | Aug 17 06:50:14 PM PDT 24 |
| Finished | Aug 17 06:50:22 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-175fa338-1a59-4d88-bb4b-ed2f9029f1a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388483206 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke.3388483206 |
| Directory | /workspace/35.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.247380272 |
| Short name | T1811 |
| Test name | |
| Test status | |
| Simulation time | 6407765271 ps |
| CPU time | 64.7 seconds |
| Started | Aug 17 06:50:14 PM PDT 24 |
| Finished | Aug 17 06:51:19 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-903e0d40-dcc7-455b-8239-c0d15e7ff378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=247380272 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_large_delays.247380272 |
| Directory | /workspace/35.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_slow_rsp.133745110 |
| Short name | T2305 |
| Test name | |
| Test status | |
| Simulation time | 5172315066 ps |
| CPU time | 90.77 seconds |
| Started | Aug 17 06:50:15 PM PDT 24 |
| Finished | Aug 17 06:51:45 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-97d596ef-c967-4bb2-9938-e91bcf37cb65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133745110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_slow_rsp.133745110 |
| Directory | /workspace/35.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_smoke_zero_delays.474574155 |
| Short name | T2751 |
| Test name | |
| Test status | |
| Simulation time | 40724068 ps |
| CPU time | 5.67 seconds |
| Started | Aug 17 06:50:13 PM PDT 24 |
| Finished | Aug 17 06:50:19 PM PDT 24 |
| Peak memory | 573416 kb |
| Host | smart-4749e506-77c3-468f-ac77-b6646816d42a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474574155 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_smoke_zero_delays .474574155 |
| Directory | /workspace/35.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all.1090082007 |
| Short name | T2869 |
| Test name | |
| Test status | |
| Simulation time | 2164904497 ps |
| CPU time | 174.98 seconds |
| Started | Aug 17 06:50:14 PM PDT 24 |
| Finished | Aug 17 06:53:09 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-458ed8b4-56a5-4621-873b-752aa871941d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090082007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all.1090082007 |
| Directory | /workspace/35.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_error.2810535400 |
| Short name | T2431 |
| Test name | |
| Test status | |
| Simulation time | 1538828024 ps |
| CPU time | 57.63 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:51:23 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-6862629d-5c51-4eb9-96dc-442d3eb259d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2810535400 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all_with_error.2810535400 |
| Directory | /workspace/35.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1791127321 |
| Short name | T2543 |
| Test name | |
| Test status | |
| Simulation time | 380362215 ps |
| CPU time | 134.45 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:52:41 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-0527b68c-321f-45c9-a999-0b5066a83d98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791127321 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_all _with_rand_reset.1791127321 |
| Directory | /workspace/35.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_stress_all_with_reset_error.1575486968 |
| Short name | T2378 |
| Test name | |
| Test status | |
| Simulation time | 6642304196 ps |
| CPU time | 389.72 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:56:56 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-b96bfdea-ef36-4184-a981-45ff851c448f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575486968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_stress_al l_with_reset_error.1575486968 |
| Directory | /workspace/35.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/35.xbar_unmapped_addr.1057038136 |
| Short name | T1795 |
| Test name | |
| Test status | |
| Simulation time | 249483330 ps |
| CPU time | 29.14 seconds |
| Started | Aug 17 06:50:14 PM PDT 24 |
| Finished | Aug 17 06:50:43 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-f2c8d596-a7e3-4b71-abf1-c8e9b893622c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057038136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.xbar_unmapped_addr.1057038136 |
| Directory | /workspace/35.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device.1863769631 |
| Short name | T1855 |
| Test name | |
| Test status | |
| Simulation time | 1322265145 ps |
| CPU time | 51.4 seconds |
| Started | Aug 17 06:50:27 PM PDT 24 |
| Finished | Aug 17 06:51:19 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-75647fc4-09b9-485c-9cff-f0f51d869387 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1863769631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_device .1863769631 |
| Directory | /workspace/36.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_access_same_device_slow_rsp.744351757 |
| Short name | T2779 |
| Test name | |
| Test status | |
| Simulation time | 13807511989 ps |
| CPU time | 218.92 seconds |
| Started | Aug 17 06:50:25 PM PDT 24 |
| Finished | Aug 17 06:54:04 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-6c99426d-0f07-49bd-bde9-fe78a7b3b610 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=744351757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_access_same_d evice_slow_rsp.744351757 |
| Directory | /workspace/36.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_and_unmapped_addr.61834209 |
| Short name | T2306 |
| Test name | |
| Test status | |
| Simulation time | 608141239 ps |
| CPU time | 26.3 seconds |
| Started | Aug 17 06:50:33 PM PDT 24 |
| Finished | Aug 17 06:50:59 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-26c4cb4d-600d-4a63-a214-89bbb09ddb14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61834209 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_and_unmapped_addr.61834209 |
| Directory | /workspace/36.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_error_random.4284876976 |
| Short name | T1386 |
| Test name | |
| Test status | |
| Simulation time | 446265538 ps |
| CPU time | 36.2 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:51:03 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-0af6070d-0b87-42b9-afac-791d1de64315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284876976 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_error_random.4284876976 |
| Directory | /workspace/36.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random.1638531681 |
| Short name | T2886 |
| Test name | |
| Test status | |
| Simulation time | 77831494 ps |
| CPU time | 9.2 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:50:36 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-6d76f9bb-7d86-4473-8fd9-8918638f4ad7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1638531681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random.1638531681 |
| Directory | /workspace/36.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_large_delays.2036767158 |
| Short name | T2660 |
| Test name | |
| Test status | |
| Simulation time | 29453908804 ps |
| CPU time | 328.55 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:55:55 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-86346632-ecfb-434d-bc14-2ec09f808d9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036767158 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_large_delays.2036767158 |
| Directory | /workspace/36.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_slow_rsp.453661413 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 55382541644 ps |
| CPU time | 974.65 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 07:06:41 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-0cb9da53-8af6-456b-b787-2051deb63449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453661413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_slow_rsp.453661413 |
| Directory | /workspace/36.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_random_zero_delays.3302206553 |
| Short name | T1515 |
| Test name | |
| Test status | |
| Simulation time | 615975256 ps |
| CPU time | 56.55 seconds |
| Started | Aug 17 06:50:28 PM PDT 24 |
| Finished | Aug 17 06:51:25 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-059d6603-bffb-49ae-8f70-25fb223bcfea |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3302206553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_random_zero_del ays.3302206553 |
| Directory | /workspace/36.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_same_source.283977823 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2427366144 ps |
| CPU time | 74.35 seconds |
| Started | Aug 17 06:50:27 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-f6d03f65-16dc-4f8c-8ae1-541b92f1a582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=283977823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_same_source.283977823 |
| Directory | /workspace/36.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke.605935532 |
| Short name | T2613 |
| Test name | |
| Test status | |
| Simulation time | 47725719 ps |
| CPU time | 6.38 seconds |
| Started | Aug 17 06:50:27 PM PDT 24 |
| Finished | Aug 17 06:50:34 PM PDT 24 |
| Peak memory | 573400 kb |
| Host | smart-802793aa-46a8-4162-9ec3-dc21a482a989 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605935532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke.605935532 |
| Directory | /workspace/36.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_large_delays.2248714041 |
| Short name | T1623 |
| Test name | |
| Test status | |
| Simulation time | 9493824970 ps |
| CPU time | 106.52 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:52:13 PM PDT 24 |
| Peak memory | 573572 kb |
| Host | smart-81d277c3-0177-404a-98c6-833063d5af2c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248714041 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_large_delays.2248714041 |
| Directory | /workspace/36.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_slow_rsp.3007544834 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 4257158646 ps |
| CPU time | 68.4 seconds |
| Started | Aug 17 06:50:27 PM PDT 24 |
| Finished | Aug 17 06:51:35 PM PDT 24 |
| Peak memory | 573672 kb |
| Host | smart-4a28a0bd-5130-40c7-a7ec-85827e3a2b32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007544834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_slow_rsp.3007544834 |
| Directory | /workspace/36.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_smoke_zero_delays.611280688 |
| Short name | T2073 |
| Test name | |
| Test status | |
| Simulation time | 51538799 ps |
| CPU time | 6.52 seconds |
| Started | Aug 17 06:50:25 PM PDT 24 |
| Finished | Aug 17 06:50:32 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-2207f54c-d2a6-46e1-ab87-2e1ccd27a7e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611280688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_smoke_zero_delays .611280688 |
| Directory | /workspace/36.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all.611475090 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2303740728 ps |
| CPU time | 171.94 seconds |
| Started | Aug 17 06:50:26 PM PDT 24 |
| Finished | Aug 17 06:53:18 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-99c24f38-06bf-4a46-b3f2-10742793b199 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611475090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all.611475090 |
| Directory | /workspace/36.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_error.1021735045 |
| Short name | T2184 |
| Test name | |
| Test status | |
| Simulation time | 510788154 ps |
| CPU time | 37.34 seconds |
| Started | Aug 17 06:50:30 PM PDT 24 |
| Finished | Aug 17 06:51:08 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-751f8468-da4e-4151-abec-20b170c61010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021735045 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all_with_error.1021735045 |
| Directory | /workspace/36.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_rand_reset.2377795307 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 14048839527 ps |
| CPU time | 677.16 seconds |
| Started | Aug 17 06:50:30 PM PDT 24 |
| Finished | Aug 17 07:01:47 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-9eb5c3ba-9e54-446c-bc8f-66f3a8fdbaf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2377795307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_rand_reset.2377795307 |
| Directory | /workspace/36.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.719548808 |
| Short name | T2565 |
| Test name | |
| Test status | |
| Simulation time | 643296034 ps |
| CPU time | 65.76 seconds |
| Started | Aug 17 06:50:33 PM PDT 24 |
| Finished | Aug 17 06:51:38 PM PDT 24 |
| Peak memory | 576224 kb |
| Host | smart-e1bfe98f-afcc-4dda-8764-38233e443b50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719548808 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_stress_all _with_reset_error.719548808 |
| Directory | /workspace/36.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/36.xbar_unmapped_addr.2224002242 |
| Short name | T1503 |
| Test name | |
| Test status | |
| Simulation time | 40952270 ps |
| CPU time | 7.55 seconds |
| Started | Aug 17 06:50:28 PM PDT 24 |
| Finished | Aug 17 06:50:35 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-12f3e90b-73e8-4f6f-a902-895633bda3bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2224002242 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.xbar_unmapped_addr.2224002242 |
| Directory | /workspace/36.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device.571857779 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 2591834070 ps |
| CPU time | 114.08 seconds |
| Started | Aug 17 06:50:27 PM PDT 24 |
| Finished | Aug 17 06:52:21 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-f6f820bc-cc8d-4b5d-a6cd-3223cfe10c26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571857779 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_device. 571857779 |
| Directory | /workspace/37.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_access_same_device_slow_rsp.1083079976 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 38508693846 ps |
| CPU time | 657.45 seconds |
| Started | Aug 17 06:50:32 PM PDT 24 |
| Finished | Aug 17 07:01:29 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-7d7615db-2813-40d5-aeeb-77623fb4d09a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083079976 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_access_same_ device_slow_rsp.1083079976 |
| Directory | /workspace/37.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_and_unmapped_addr.1111582909 |
| Short name | T1872 |
| Test name | |
| Test status | |
| Simulation time | 60797893 ps |
| CPU time | 8.86 seconds |
| Started | Aug 17 06:50:32 PM PDT 24 |
| Finished | Aug 17 06:50:41 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-f48a9aed-be9f-44b8-a7bd-aab501130369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111582909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_and_unmapped_add r.1111582909 |
| Directory | /workspace/37.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_error_random.2440726081 |
| Short name | T2621 |
| Test name | |
| Test status | |
| Simulation time | 458104125 ps |
| CPU time | 37.85 seconds |
| Started | Aug 17 06:50:27 PM PDT 24 |
| Finished | Aug 17 06:51:05 PM PDT 24 |
| Peak memory | 575308 kb |
| Host | smart-d85408d1-ad96-45e3-b623-8046f1c92e96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440726081 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_error_random.2440726081 |
| Directory | /workspace/37.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random.1053812110 |
| Short name | T2086 |
| Test name | |
| Test status | |
| Simulation time | 306354483 ps |
| CPU time | 27.43 seconds |
| Started | Aug 17 06:50:31 PM PDT 24 |
| Finished | Aug 17 06:50:59 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-ca6ac25b-5b14-46fb-8dd6-02d94baa452a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053812110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random.1053812110 |
| Directory | /workspace/37.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_large_delays.3771428221 |
| Short name | T2205 |
| Test name | |
| Test status | |
| Simulation time | 50868176864 ps |
| CPU time | 586.69 seconds |
| Started | Aug 17 06:50:28 PM PDT 24 |
| Finished | Aug 17 07:00:15 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-4b1051f1-4c05-4d82-bd39-eb40739ed509 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771428221 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_large_delays.3771428221 |
| Directory | /workspace/37.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2365422454 |
| Short name | T2898 |
| Test name | |
| Test status | |
| Simulation time | 48659398707 ps |
| CPU time | 783.62 seconds |
| Started | Aug 17 06:50:32 PM PDT 24 |
| Finished | Aug 17 07:03:36 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-cfc4ca20-ab45-40b8-b1fb-df3b4d96e1da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365422454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_slow_rsp.2365422454 |
| Directory | /workspace/37.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.3674150453 |
| Short name | T2429 |
| Test name | |
| Test status | |
| Simulation time | 250081636 ps |
| CPU time | 22.73 seconds |
| Started | Aug 17 06:50:29 PM PDT 24 |
| Finished | Aug 17 06:50:52 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-682d78a8-327d-4c32-9ce8-37d8bb69c7ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674150453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_random_zero_del ays.3674150453 |
| Directory | /workspace/37.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_same_source.3223343624 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 509596015 ps |
| CPU time | 35.12 seconds |
| Started | Aug 17 06:50:27 PM PDT 24 |
| Finished | Aug 17 06:51:02 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-2c431426-eb91-44a4-8591-9d4401814aba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223343624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_same_source.3223343624 |
| Directory | /workspace/37.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke.2176649746 |
| Short name | T1991 |
| Test name | |
| Test status | |
| Simulation time | 219327825 ps |
| CPU time | 9.55 seconds |
| Started | Aug 17 06:50:30 PM PDT 24 |
| Finished | Aug 17 06:50:39 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-84e2704f-e24d-4905-8850-3aa59b1340f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2176649746 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke.2176649746 |
| Directory | /workspace/37.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_large_delays.133370074 |
| Short name | T1426 |
| Test name | |
| Test status | |
| Simulation time | 9684287674 ps |
| CPU time | 98.66 seconds |
| Started | Aug 17 06:50:30 PM PDT 24 |
| Finished | Aug 17 06:52:09 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-b1a740d1-cb3d-446c-b8bb-a0547d6a7f68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133370074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_large_delays.133370074 |
| Directory | /workspace/37.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_slow_rsp.1372188610 |
| Short name | T1849 |
| Test name | |
| Test status | |
| Simulation time | 6166165555 ps |
| CPU time | 98.83 seconds |
| Started | Aug 17 06:50:28 PM PDT 24 |
| Finished | Aug 17 06:52:07 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-551da495-5cfc-4499-9be0-d1a6b7ebfcde |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372188610 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_slow_rsp.1372188610 |
| Directory | /workspace/37.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_smoke_zero_delays.2733943441 |
| Short name | T1490 |
| Test name | |
| Test status | |
| Simulation time | 44061993 ps |
| CPU time | 6.14 seconds |
| Started | Aug 17 06:50:29 PM PDT 24 |
| Finished | Aug 17 06:50:36 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-fa4bdc86-24f3-4a46-8ae1-fbe8667f0a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733943441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_smoke_zero_delay s.2733943441 |
| Directory | /workspace/37.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all.4047400823 |
| Short name | T2204 |
| Test name | |
| Test status | |
| Simulation time | 8396712166 ps |
| CPU time | 323.61 seconds |
| Started | Aug 17 06:50:33 PM PDT 24 |
| Finished | Aug 17 06:55:56 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-6bff450a-4975-4664-a341-0c059b122a65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047400823 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all.4047400823 |
| Directory | /workspace/37.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_error.2774369801 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 3746206803 ps |
| CPU time | 303.43 seconds |
| Started | Aug 17 06:50:34 PM PDT 24 |
| Finished | Aug 17 06:55:37 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-8a66aec8-f788-4202-bf26-c5663299cb26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774369801 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all_with_error.2774369801 |
| Directory | /workspace/37.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_rand_reset.3227389866 |
| Short name | T2155 |
| Test name | |
| Test status | |
| Simulation time | 307201669 ps |
| CPU time | 131.64 seconds |
| Started | Aug 17 06:50:28 PM PDT 24 |
| Finished | Aug 17 06:52:39 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-29182d8a-bc58-41af-a058-5a247d257d84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227389866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_all _with_rand_reset.3227389866 |
| Directory | /workspace/37.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_stress_all_with_reset_error.3620043391 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 297445236 ps |
| CPU time | 63.54 seconds |
| Started | Aug 17 06:50:37 PM PDT 24 |
| Finished | Aug 17 06:51:41 PM PDT 24 |
| Peak memory | 576244 kb |
| Host | smart-2c69673c-7014-40cf-b666-906438b48d46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620043391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_stress_al l_with_reset_error.3620043391 |
| Directory | /workspace/37.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/37.xbar_unmapped_addr.1576820456 |
| Short name | T2314 |
| Test name | |
| Test status | |
| Simulation time | 1054380958 ps |
| CPU time | 43.52 seconds |
| Started | Aug 17 06:50:33 PM PDT 24 |
| Finished | Aug 17 06:51:17 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-52f74f39-11bc-45ef-98b0-eab9cfe5a0b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576820456 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.xbar_unmapped_addr.1576820456 |
| Directory | /workspace/37.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device.1233702043 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 3214749317 ps |
| CPU time | 120.17 seconds |
| Started | Aug 17 06:50:34 PM PDT 24 |
| Finished | Aug 17 06:52:34 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-392ea249-f806-4a6f-86a9-70ac744f6657 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233702043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_device .1233702043 |
| Directory | /workspace/38.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_access_same_device_slow_rsp.1061700268 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 130068496994 ps |
| CPU time | 2521.9 seconds |
| Started | Aug 17 06:50:36 PM PDT 24 |
| Finished | Aug 17 07:32:38 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-81e21c45-19a7-43ef-be26-32f3bbdf0fdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061700268 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_access_same_ device_slow_rsp.1061700268 |
| Directory | /workspace/38.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_and_unmapped_addr.2483657794 |
| Short name | T2550 |
| Test name | |
| Test status | |
| Simulation time | 280567510 ps |
| CPU time | 12.15 seconds |
| Started | Aug 17 06:50:40 PM PDT 24 |
| Finished | Aug 17 06:50:53 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-d3173be4-fb7d-4589-8763-4d3fa181f268 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483657794 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_and_unmapped_add r.2483657794 |
| Directory | /workspace/38.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_error_random.2649680790 |
| Short name | T1395 |
| Test name | |
| Test status | |
| Simulation time | 361583050 ps |
| CPU time | 31.43 seconds |
| Started | Aug 17 06:50:37 PM PDT 24 |
| Finished | Aug 17 06:51:08 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-f08adbcc-7eae-4746-8dbf-a38a4e2dae29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649680790 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_error_random.2649680790 |
| Directory | /workspace/38.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random.2953725209 |
| Short name | T2342 |
| Test name | |
| Test status | |
| Simulation time | 1510691408 ps |
| CPU time | 56.36 seconds |
| Started | Aug 17 06:50:34 PM PDT 24 |
| Finished | Aug 17 06:51:30 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-b8680f15-3a3f-4830-b8ee-1119864a691d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953725209 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random.2953725209 |
| Directory | /workspace/38.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_large_delays.4003320447 |
| Short name | T2577 |
| Test name | |
| Test status | |
| Simulation time | 60029189717 ps |
| CPU time | 629.76 seconds |
| Started | Aug 17 06:50:37 PM PDT 24 |
| Finished | Aug 17 07:01:07 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-a29bd418-8d35-40d0-93f9-cd039aa9b4e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003320447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_large_delays.4003320447 |
| Directory | /workspace/38.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_slow_rsp.3166211397 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 18849372699 ps |
| CPU time | 303.54 seconds |
| Started | Aug 17 06:50:37 PM PDT 24 |
| Finished | Aug 17 06:55:41 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-10e79bbf-e8de-4595-aa86-21e0e12e7e6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166211397 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_slow_rsp.3166211397 |
| Directory | /workspace/38.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_random_zero_delays.1687616384 |
| Short name | T2071 |
| Test name | |
| Test status | |
| Simulation time | 32818515 ps |
| CPU time | 5.83 seconds |
| Started | Aug 17 06:50:36 PM PDT 24 |
| Finished | Aug 17 06:50:41 PM PDT 24 |
| Peak memory | 573424 kb |
| Host | smart-2f204773-b8c6-4cf7-9a6d-c2a9e2681f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687616384 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_random_zero_del ays.1687616384 |
| Directory | /workspace/38.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_same_source.786612017 |
| Short name | T2390 |
| Test name | |
| Test status | |
| Simulation time | 507482097 ps |
| CPU time | 36.65 seconds |
| Started | Aug 17 06:50:38 PM PDT 24 |
| Finished | Aug 17 06:51:14 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-647132d1-5cb0-41d7-9f1b-50102da940c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786612017 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_same_source.786612017 |
| Directory | /workspace/38.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke.415371346 |
| Short name | T2689 |
| Test name | |
| Test status | |
| Simulation time | 47288798 ps |
| CPU time | 5.8 seconds |
| Started | Aug 17 06:50:41 PM PDT 24 |
| Finished | Aug 17 06:50:47 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-f1685607-b316-490d-a940-9fae887ae056 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415371346 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke.415371346 |
| Directory | /workspace/38.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_large_delays.1190098196 |
| Short name | T2256 |
| Test name | |
| Test status | |
| Simulation time | 9387612136 ps |
| CPU time | 96.26 seconds |
| Started | Aug 17 06:50:39 PM PDT 24 |
| Finished | Aug 17 06:52:16 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-23bc10f3-1ac8-4eef-b83d-d56f5f696952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190098196 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_large_delays.1190098196 |
| Directory | /workspace/38.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_slow_rsp.2434581192 |
| Short name | T2508 |
| Test name | |
| Test status | |
| Simulation time | 4748747925 ps |
| CPU time | 67 seconds |
| Started | Aug 17 06:50:35 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-0cfc71c5-dec5-4aac-bf60-250a3972f0ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434581192 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_slow_rsp.2434581192 |
| Directory | /workspace/38.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_smoke_zero_delays.2122034280 |
| Short name | T1649 |
| Test name | |
| Test status | |
| Simulation time | 56351952 ps |
| CPU time | 7.47 seconds |
| Started | Aug 17 06:50:34 PM PDT 24 |
| Finished | Aug 17 06:50:42 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-cbd95523-89eb-4c2d-9239-8fb2163cd125 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122034280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_smoke_zero_delay s.2122034280 |
| Directory | /workspace/38.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all.2162402649 |
| Short name | T2337 |
| Test name | |
| Test status | |
| Simulation time | 12791906515 ps |
| CPU time | 505.18 seconds |
| Started | Aug 17 06:50:38 PM PDT 24 |
| Finished | Aug 17 06:59:04 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-7c74edb1-82cc-4d55-bea6-dbaf33f53d41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162402649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all.2162402649 |
| Directory | /workspace/38.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_error.2898296494 |
| Short name | T2393 |
| Test name | |
| Test status | |
| Simulation time | 2033651116 ps |
| CPU time | 144.87 seconds |
| Started | Aug 17 06:50:41 PM PDT 24 |
| Finished | Aug 17 06:53:06 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-258f4629-cb0e-4790-a81f-4f062f9db3ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898296494 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all_with_error.2898296494 |
| Directory | /workspace/38.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_rand_reset.2746655248 |
| Short name | T2445 |
| Test name | |
| Test status | |
| Simulation time | 240164233 ps |
| CPU time | 118.19 seconds |
| Started | Aug 17 06:50:36 PM PDT 24 |
| Finished | Aug 17 06:52:34 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-86cd7723-c953-4360-b2da-407fa1966aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746655248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_all _with_rand_reset.2746655248 |
| Directory | /workspace/38.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_stress_all_with_reset_error.2322121025 |
| Short name | T2802 |
| Test name | |
| Test status | |
| Simulation time | 336672669 ps |
| CPU time | 101.89 seconds |
| Started | Aug 17 06:50:35 PM PDT 24 |
| Finished | Aug 17 06:52:17 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-ea65b6dd-33d1-481d-b4ed-55d2c4aacc51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322121025 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_stress_al l_with_reset_error.2322121025 |
| Directory | /workspace/38.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/38.xbar_unmapped_addr.1317037165 |
| Short name | T1824 |
| Test name | |
| Test status | |
| Simulation time | 1302837913 ps |
| CPU time | 49.73 seconds |
| Started | Aug 17 06:50:38 PM PDT 24 |
| Finished | Aug 17 06:51:28 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-7d12fac3-4533-45b0-86df-c8a148db31f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317037165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.xbar_unmapped_addr.1317037165 |
| Directory | /workspace/38.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device.3136241179 |
| Short name | T2514 |
| Test name | |
| Test status | |
| Simulation time | 3790382969 ps |
| CPU time | 136.24 seconds |
| Started | Aug 17 06:50:43 PM PDT 24 |
| Finished | Aug 17 06:52:59 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-8c632f0f-c99f-4e03-ba9e-e183ca194802 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136241179 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_device .3136241179 |
| Directory | /workspace/39.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_access_same_device_slow_rsp.1427551761 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 13323994758 ps |
| CPU time | 233.55 seconds |
| Started | Aug 17 06:50:47 PM PDT 24 |
| Finished | Aug 17 06:54:41 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-a58acd7b-b372-4d82-a791-0ec169175cd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427551761 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_access_same_ device_slow_rsp.1427551761 |
| Directory | /workspace/39.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_and_unmapped_addr.2062925638 |
| Short name | T2104 |
| Test name | |
| Test status | |
| Simulation time | 1193986072 ps |
| CPU time | 49.35 seconds |
| Started | Aug 17 06:50:45 PM PDT 24 |
| Finished | Aug 17 06:51:34 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-302b613f-059a-4593-ba1f-46b258f308ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062925638 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_and_unmapped_add r.2062925638 |
| Directory | /workspace/39.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_error_random.293623552 |
| Short name | T2230 |
| Test name | |
| Test status | |
| Simulation time | 327973432 ps |
| CPU time | 30.37 seconds |
| Started | Aug 17 06:50:43 PM PDT 24 |
| Finished | Aug 17 06:51:14 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-76156b9d-ec2c-41e6-aa7b-ec21793f55cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=293623552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_error_random.293623552 |
| Directory | /workspace/39.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random.2274271466 |
| Short name | T2053 |
| Test name | |
| Test status | |
| Simulation time | 1467063050 ps |
| CPU time | 55.09 seconds |
| Started | Aug 17 06:50:34 PM PDT 24 |
| Finished | Aug 17 06:51:29 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-c0d6617a-6904-47c4-ad9e-417b7a13f621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274271466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random.2274271466 |
| Directory | /workspace/39.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_large_delays.2131083376 |
| Short name | T2538 |
| Test name | |
| Test status | |
| Simulation time | 38347848893 ps |
| CPU time | 404.46 seconds |
| Started | Aug 17 06:50:37 PM PDT 24 |
| Finished | Aug 17 06:57:21 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-7a69c3db-5ab6-4664-9b46-dd8168ed21b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131083376 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_large_delays.2131083376 |
| Directory | /workspace/39.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_slow_rsp.3421751189 |
| Short name | T2642 |
| Test name | |
| Test status | |
| Simulation time | 2024309805 ps |
| CPU time | 31.78 seconds |
| Started | Aug 17 06:50:39 PM PDT 24 |
| Finished | Aug 17 06:51:11 PM PDT 24 |
| Peak memory | 573404 kb |
| Host | smart-60887618-d394-4e41-8f16-db4b64de1e6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3421751189 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_slow_rsp.3421751189 |
| Directory | /workspace/39.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_random_zero_delays.4098028786 |
| Short name | T2618 |
| Test name | |
| Test status | |
| Simulation time | 547726187 ps |
| CPU time | 41.08 seconds |
| Started | Aug 17 06:50:41 PM PDT 24 |
| Finished | Aug 17 06:51:22 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-34375604-8359-46b0-9b69-8a0665a76fef |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098028786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_random_zero_del ays.4098028786 |
| Directory | /workspace/39.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_same_source.636736243 |
| Short name | T1968 |
| Test name | |
| Test status | |
| Simulation time | 1254032162 ps |
| CPU time | 37.94 seconds |
| Started | Aug 17 06:50:42 PM PDT 24 |
| Finished | Aug 17 06:51:20 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-e44a129b-a90e-488d-b0a9-45180df10ea4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636736243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_same_source.636736243 |
| Directory | /workspace/39.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke.565807183 |
| Short name | T2767 |
| Test name | |
| Test status | |
| Simulation time | 241336735 ps |
| CPU time | 10.79 seconds |
| Started | Aug 17 06:50:38 PM PDT 24 |
| Finished | Aug 17 06:50:49 PM PDT 24 |
| Peak memory | 574084 kb |
| Host | smart-ae22dfba-069a-4376-bdaf-4b5c311705ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565807183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke.565807183 |
| Directory | /workspace/39.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_large_delays.2263327951 |
| Short name | T2742 |
| Test name | |
| Test status | |
| Simulation time | 8111516658 ps |
| CPU time | 80.07 seconds |
| Started | Aug 17 06:50:41 PM PDT 24 |
| Finished | Aug 17 06:52:01 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-30d7a46a-117e-42e0-889f-623194b7ccea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263327951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_large_delays.2263327951 |
| Directory | /workspace/39.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_slow_rsp.3090779425 |
| Short name | T2265 |
| Test name | |
| Test status | |
| Simulation time | 6536127509 ps |
| CPU time | 115.94 seconds |
| Started | Aug 17 06:50:38 PM PDT 24 |
| Finished | Aug 17 06:52:34 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-2f43c578-6eea-4331-ad8d-a8db5f4f92be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090779425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_slow_rsp.3090779425 |
| Directory | /workspace/39.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_smoke_zero_delays.887752871 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 47569208 ps |
| CPU time | 6.36 seconds |
| Started | Aug 17 06:50:37 PM PDT 24 |
| Finished | Aug 17 06:50:43 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-7ea5750d-5583-4d21-99cc-aed37c98fb4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=887752871 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_smoke_zero_delays .887752871 |
| Directory | /workspace/39.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all.3962700683 |
| Short name | T2854 |
| Test name | |
| Test status | |
| Simulation time | 2549956548 ps |
| CPU time | 90.56 seconds |
| Started | Aug 17 06:50:44 PM PDT 24 |
| Finished | Aug 17 06:52:15 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-79bf1f38-66dc-4df5-bca3-8433c87fd8d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962700683 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all.3962700683 |
| Directory | /workspace/39.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_error.1303737690 |
| Short name | T2351 |
| Test name | |
| Test status | |
| Simulation time | 5846379209 ps |
| CPU time | 175.3 seconds |
| Started | Aug 17 06:50:44 PM PDT 24 |
| Finished | Aug 17 06:53:39 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-7e345443-fb0d-4d28-925a-3de77a016897 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303737690 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all_with_error.1303737690 |
| Directory | /workspace/39.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_rand_reset.1012358252 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 5746221615 ps |
| CPU time | 691.34 seconds |
| Started | Aug 17 06:50:44 PM PDT 24 |
| Finished | Aug 17 07:02:15 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-39b5997b-60ba-4d94-b4ab-0ee7ac586cb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012358252 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_all _with_rand_reset.1012358252 |
| Directory | /workspace/39.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_stress_all_with_reset_error.1916927330 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 296643436 ps |
| CPU time | 59.54 seconds |
| Started | Aug 17 06:50:43 PM PDT 24 |
| Finished | Aug 17 06:51:43 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-1a7d9213-837e-4ef6-ab20-12461435d9e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916927330 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_stress_al l_with_reset_error.1916927330 |
| Directory | /workspace/39.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/39.xbar_unmapped_addr.3808967448 |
| Short name | T1638 |
| Test name | |
| Test status | |
| Simulation time | 858682126 ps |
| CPU time | 37.2 seconds |
| Started | Aug 17 06:50:46 PM PDT 24 |
| Finished | Aug 17 06:51:23 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-18b492fe-6474-49fe-bcde-b703db72e6e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808967448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.xbar_unmapped_addr.3808967448 |
| Directory | /workspace/39.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_aliasing.1942961784 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 75040705336 ps |
| CPU time | 10371.9 seconds |
| Started | Aug 17 06:47:37 PM PDT 24 |
| Finished | Aug 17 09:40:30 PM PDT 24 |
| Peak memory | 641628 kb |
| Host | smart-e8f47daf-cf46-4bb9-a58e-33c9f1a455cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +csr_aliasing +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942961784 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/ null -cm_name 4.chip_csr_aliasing.1942961784 |
| Directory | /workspace/4.chip_csr_aliasing/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_bit_bash.3075695202 |
| Short name | T1739 |
| Test name | |
| Test status | |
| Simulation time | 43371931836 ps |
| CPU time | 5170.45 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 08:13:46 PM PDT 24 |
| Peak memory | 597696 kb |
| Host | smart-457a6384-9fc0-4f16-9c7b-669d732ba524 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +num_test_csrs=200 +csr_bit_bash +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_ NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3075695202 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_to p.vdb -cm_log /dev/null -cm_name 4.chip_csr_bit_bash.3075695202 |
| Directory | /workspace/4.chip_csr_bit_bash/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_hw_reset.305691452 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 6476785845 ps |
| CPU time | 316.38 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:52:50 PM PDT 24 |
| Peak memory | 661928 kb |
| Host | smart-1df3fc47-25bc-4666-9971-f0abeaa1b395 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305691452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_c ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_hw_re set.305691452 |
| Directory | /workspace/4.chip_csr_hw_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_mem_rw_with_rand_reset.2931523029 |
| Short name | T2494 |
| Test name | |
| Test status | |
| Simulation time | 7507812716 ps |
| CPU time | 472.65 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 06:55:26 PM PDT 24 |
| Peak memory | 638444 kb |
| Host | smart-26436a72-b9f8-48f3-a9ad-f5d37f4a77f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931523029 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 4.chip_csr_mem_rw_with_rand_reset.2931523029 |
| Directory | /workspace/4.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_csr_rw.280384659 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 4494030828 ps |
| CPU time | 409.37 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:54:45 PM PDT 24 |
| Peak memory | 597372 kb |
| Host | smart-04a97aa1-e996-4f63-b566-16ce9de52ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280384659 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_csr_rw.280384659 |
| Directory | /workspace/4.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_same_csr_outstanding.3770439474 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 29527618328 ps |
| CPU time | 3390.01 seconds |
| Started | Aug 17 06:47:35 PM PDT 24 |
| Finished | Aug 17 07:44:05 PM PDT 24 |
| Peak memory | 593696 kb |
| Host | smart-98fdbc94-c9a5-475f-a5da-76af75199b90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770439474 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 4.chip_same_csr_outstanding.3770439474 |
| Directory | /workspace/4.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/4.chip_tl_errors.1581886046 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 3168187332 ps |
| CPU time | 149.14 seconds |
| Started | Aug 17 06:47:46 PM PDT 24 |
| Finished | Aug 17 06:50:15 PM PDT 24 |
| Peak memory | 599116 kb |
| Host | smart-60ee66d1-d1e1-45a6-ba0c-1d9bb1f6dc17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581886046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.chip_tl_errors.1581886046 |
| Directory | /workspace/4.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device.1814854075 |
| Short name | T1478 |
| Test name | |
| Test status | |
| Simulation time | 129944311 ps |
| CPU time | 11.26 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:47:54 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-8f1debb0-23e5-4b6f-bcdd-8883690640a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814854075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_device. 1814854075 |
| Directory | /workspace/4.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_access_same_device_slow_rsp.3467822295 |
| Short name | T2116 |
| Test name | |
| Test status | |
| Simulation time | 39544649873 ps |
| CPU time | 642.43 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:58:16 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-9d9d7908-629f-4f4a-a632-d3acf0458fa7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3467822295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_access_same_d evice_slow_rsp.3467822295 |
| Directory | /workspace/4.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_and_unmapped_addr.3481227857 |
| Short name | T2296 |
| Test name | |
| Test status | |
| Simulation time | 622910066 ps |
| CPU time | 24.57 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:48:07 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-936965bc-4291-4390-81d5-480eaa73f38e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481227857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_and_unmapped_addr .3481227857 |
| Directory | /workspace/4.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_error_random.1392095032 |
| Short name | T2490 |
| Test name | |
| Test status | |
| Simulation time | 503664629 ps |
| CPU time | 36.12 seconds |
| Started | Aug 17 06:47:36 PM PDT 24 |
| Finished | Aug 17 06:48:12 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-236e7ec6-d25f-41a8-aeec-a9ef6b270192 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392095032 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_error_random.1392095032 |
| Directory | /workspace/4.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random.717898472 |
| Short name | T2178 |
| Test name | |
| Test status | |
| Simulation time | 558309916 ps |
| CPU time | 46.48 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:35 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-76d12e23-cb3a-4793-b3d8-3b9cd66936d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717898472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random.717898472 |
| Directory | /workspace/4.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_large_delays.1974962165 |
| Short name | T2491 |
| Test name | |
| Test status | |
| Simulation time | 15133148894 ps |
| CPU time | 148.76 seconds |
| Started | Aug 17 06:47:40 PM PDT 24 |
| Finished | Aug 17 06:50:09 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-8a45c84d-9151-423c-b6d5-a13cab27b278 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1974962165 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_large_delays.1974962165 |
| Directory | /workspace/4.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_slow_rsp.456779190 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 33713768622 ps |
| CPU time | 559.15 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:56:51 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-2fe979e9-8bf2-4f4f-bede-90b1f45768e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456779190 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_slow_rsp.456779190 |
| Directory | /workspace/4.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.391568475 |
| Short name | T1639 |
| Test name | |
| Test status | |
| Simulation time | 193452183 ps |
| CPU time | 17.69 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:48:00 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-ff979070-b443-42f5-ac07-0f3f62d60911 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391568475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_random_zero_delay s.391568475 |
| Directory | /workspace/4.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_same_source.3615607407 |
| Short name | T2041 |
| Test name | |
| Test status | |
| Simulation time | 1928678103 ps |
| CPU time | 52.14 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:48:23 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-e9e25deb-b19a-435c-8983-ab4012dc4b85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615607407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_same_source.3615607407 |
| Directory | /workspace/4.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke.2709002180 |
| Short name | T1965 |
| Test name | |
| Test status | |
| Simulation time | 180513287 ps |
| CPU time | 7.94 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:47:52 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-b72f08e4-c90a-47a3-8d73-7f721fb21b94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709002180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke.2709002180 |
| Directory | /workspace/4.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_large_delays.2154623927 |
| Short name | T2830 |
| Test name | |
| Test status | |
| Simulation time | 9476050736 ps |
| CPU time | 93.01 seconds |
| Started | Aug 17 06:47:38 PM PDT 24 |
| Finished | Aug 17 06:49:11 PM PDT 24 |
| Peak memory | 573296 kb |
| Host | smart-bccda82b-88e8-456a-a80a-5f5925e3cf0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154623927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_large_delays.2154623927 |
| Directory | /workspace/4.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_slow_rsp.2231749624 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 5770180098 ps |
| CPU time | 101.31 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:49:13 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-e15c97e2-d253-4e42-9b2d-d0ce9240abdd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231749624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_slow_rsp.2231749624 |
| Directory | /workspace/4.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_smoke_zero_delays.4240818805 |
| Short name | T2062 |
| Test name | |
| Test status | |
| Simulation time | 42405749 ps |
| CPU time | 5.87 seconds |
| Started | Aug 17 06:47:35 PM PDT 24 |
| Finished | Aug 17 06:47:41 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-0a7bd182-de0e-4f08-a5cc-235496be387c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240818805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_smoke_zero_delays .4240818805 |
| Directory | /workspace/4.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all.2447076291 |
| Short name | T2598 |
| Test name | |
| Test status | |
| Simulation time | 3507013688 ps |
| CPU time | 130.4 seconds |
| Started | Aug 17 06:47:38 PM PDT 24 |
| Finished | Aug 17 06:49:48 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-0c694cdb-286b-4fe5-b876-a01a637cc0fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447076291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all.2447076291 |
| Directory | /workspace/4.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.2182078886 |
| Short name | T2311 |
| Test name | |
| Test status | |
| Simulation time | 1297625801 ps |
| CPU time | 108.53 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:49:36 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-9abd5b5b-a302-46ac-95e0-6c3bf313a3c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182078886 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_with_error.2182078886 |
| Directory | /workspace/4.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_rand_reset.2638374506 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2475561071 ps |
| CPU time | 387.66 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:54:15 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-d485bcb0-53dc-4f2c-af2e-6ac7c50b24c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638374506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_rand_reset.2638374506 |
| Directory | /workspace/4.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_stress_all_with_reset_error.991501146 |
| Short name | T1459 |
| Test name | |
| Test status | |
| Simulation time | 25175349 ps |
| CPU time | 13.42 seconds |
| Started | Aug 17 06:47:37 PM PDT 24 |
| Finished | Aug 17 06:47:50 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-510d60df-0438-4aa9-a40a-c7f496db03ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991501146 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_stress_all_ with_reset_error.991501146 |
| Directory | /workspace/4.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/4.xbar_unmapped_addr.2917644820 |
| Short name | T2509 |
| Test name | |
| Test status | |
| Simulation time | 172168788 ps |
| CPU time | 20.38 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:48:07 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-b0060f4e-5ebe-4826-8c5a-1e6f89f355a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917644820 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.xbar_unmapped_addr.2917644820 |
| Directory | /workspace/4.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_access_same_device.3236724031 |
| Short name | T2620 |
| Test name | |
| Test status | |
| Simulation time | 785431897 ps |
| CPU time | 30.7 seconds |
| Started | Aug 17 06:50:52 PM PDT 24 |
| Finished | Aug 17 06:51:23 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-1cffb7e0-6b6b-47c3-96a7-bf5ccaa04687 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3236724031 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_access_same_device .3236724031 |
| Directory | /workspace/40.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_and_unmapped_addr.2237793792 |
| Short name | T1516 |
| Test name | |
| Test status | |
| Simulation time | 219654470 ps |
| CPU time | 10.96 seconds |
| Started | Aug 17 06:50:54 PM PDT 24 |
| Finished | Aug 17 06:51:05 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-11119868-4691-4988-9c63-03593ab9e0e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237793792 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_and_unmapped_add r.2237793792 |
| Directory | /workspace/40.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_error_random.451620927 |
| Short name | T1780 |
| Test name | |
| Test status | |
| Simulation time | 2255119879 ps |
| CPU time | 83.97 seconds |
| Started | Aug 17 06:50:50 PM PDT 24 |
| Finished | Aug 17 06:52:14 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-46c0a7ce-b719-4627-a222-31bc98632b0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451620927 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_error_random.451620927 |
| Directory | /workspace/40.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random.4267127147 |
| Short name | T1911 |
| Test name | |
| Test status | |
| Simulation time | 328649243 ps |
| CPU time | 30.27 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 06:51:23 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-45ce3924-acaf-4632-bae4-d65f408633dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267127147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random.4267127147 |
| Directory | /workspace/40.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_large_delays.213514901 |
| Short name | T1688 |
| Test name | |
| Test status | |
| Simulation time | 63463630268 ps |
| CPU time | 620.03 seconds |
| Started | Aug 17 06:50:52 PM PDT 24 |
| Finished | Aug 17 07:01:12 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-ad65ec93-471a-44e8-b79b-a7047cd120f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213514901 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_large_delays.213514901 |
| Directory | /workspace/40.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_slow_rsp.644327422 |
| Short name | T1735 |
| Test name | |
| Test status | |
| Simulation time | 12295215906 ps |
| CPU time | 207.09 seconds |
| Started | Aug 17 06:50:54 PM PDT 24 |
| Finished | Aug 17 06:54:21 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-45e45d30-e58b-4ce4-bd30-c8c13a439913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644327422 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_slow_rsp.644327422 |
| Directory | /workspace/40.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.3099335257 |
| Short name | T2663 |
| Test name | |
| Test status | |
| Simulation time | 70875913 ps |
| CPU time | 9.57 seconds |
| Started | Aug 17 06:50:57 PM PDT 24 |
| Finished | Aug 17 06:51:07 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-a076e281-a46c-4023-852c-4de2873dcaba |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099335257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_random_zero_del ays.3099335257 |
| Directory | /workspace/40.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_same_source.2970681870 |
| Short name | T1654 |
| Test name | |
| Test status | |
| Simulation time | 961035403 ps |
| CPU time | 28.96 seconds |
| Started | Aug 17 06:50:54 PM PDT 24 |
| Finished | Aug 17 06:51:23 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-f15bf4c8-7172-4e1d-9768-00053172ab69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970681870 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_same_source.2970681870 |
| Directory | /workspace/40.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke.239336549 |
| Short name | T1858 |
| Test name | |
| Test status | |
| Simulation time | 41256630 ps |
| CPU time | 5.72 seconds |
| Started | Aug 17 06:50:45 PM PDT 24 |
| Finished | Aug 17 06:50:51 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-f8042a10-10d2-4f20-b1cd-f1fb625837b6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239336549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke.239336549 |
| Directory | /workspace/40.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_large_delays.1610124317 |
| Short name | T1980 |
| Test name | |
| Test status | |
| Simulation time | 10403596934 ps |
| CPU time | 104.61 seconds |
| Started | Aug 17 06:50:45 PM PDT 24 |
| Finished | Aug 17 06:52:30 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-0371082b-e706-4a5d-8788-022a632b5963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610124317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_large_delays.1610124317 |
| Directory | /workspace/40.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_slow_rsp.821002006 |
| Short name | T2670 |
| Test name | |
| Test status | |
| Simulation time | 6014447697 ps |
| CPU time | 103.87 seconds |
| Started | Aug 17 06:50:57 PM PDT 24 |
| Finished | Aug 17 06:52:41 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-4b7b6373-861c-4c8f-8260-71fcf68b5e56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821002006 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_slow_rsp.821002006 |
| Directory | /workspace/40.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_smoke_zero_delays.3017872564 |
| Short name | T2263 |
| Test name | |
| Test status | |
| Simulation time | 43214819 ps |
| CPU time | 6.41 seconds |
| Started | Aug 17 06:50:45 PM PDT 24 |
| Finished | Aug 17 06:50:51 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-27c1360a-129d-47c9-8ffb-c89a0fa5fb18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017872564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_smoke_zero_delay s.3017872564 |
| Directory | /workspace/40.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all.2408154066 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 14132331562 ps |
| CPU time | 514.14 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 06:59:28 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-da2b34a1-5035-4867-8328-1f6e352466d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2408154066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all.2408154066 |
| Directory | /workspace/40.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_error.1924647698 |
| Short name | T1583 |
| Test name | |
| Test status | |
| Simulation time | 8264927842 ps |
| CPU time | 307.58 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 06:56:00 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-a3c3cd51-df17-4139-8285-a69be8352425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924647698 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_with_error.1924647698 |
| Directory | /workspace/40.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_rand_reset.862288324 |
| Short name | T2085 |
| Test name | |
| Test status | |
| Simulation time | 792230889 ps |
| CPU time | 290.47 seconds |
| Started | Aug 17 06:50:52 PM PDT 24 |
| Finished | Aug 17 06:55:42 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-71c015f4-4c01-4554-8521-11ccb78117ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862288324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_all_ with_rand_reset.862288324 |
| Directory | /workspace/40.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_stress_all_with_reset_error.3617166552 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 855105351 ps |
| CPU time | 288.9 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 06:55:42 PM PDT 24 |
| Peak memory | 576232 kb |
| Host | smart-58d40517-3f09-44b6-aa2b-42c9468cffae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3617166552 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_stress_al l_with_reset_error.3617166552 |
| Directory | /workspace/40.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/40.xbar_unmapped_addr.3449799766 |
| Short name | T2645 |
| Test name | |
| Test status | |
| Simulation time | 285875769 ps |
| CPU time | 13.26 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 06:51:07 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-451649e1-4a5f-4ac8-935a-584b04eb5b64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449799766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.xbar_unmapped_addr.3449799766 |
| Directory | /workspace/40.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device.1414688290 |
| Short name | T1930 |
| Test name | |
| Test status | |
| Simulation time | 2655720661 ps |
| CPU time | 115.46 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:52:56 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-04fe93b7-3a7e-480b-bca8-f6c58b591493 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1414688290 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_device .1414688290 |
| Directory | /workspace/41.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_access_same_device_slow_rsp.2013492805 |
| Short name | T2667 |
| Test name | |
| Test status | |
| Simulation time | 127508270758 ps |
| CPU time | 2463.16 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 07:31:56 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-2a74bf0b-e1de-4f5e-869d-132343c13ac2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2013492805 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_access_same_ device_slow_rsp.2013492805 |
| Directory | /workspace/41.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_and_unmapped_addr.2940602880 |
| Short name | T2243 |
| Test name | |
| Test status | |
| Simulation time | 301944077 ps |
| CPU time | 31.63 seconds |
| Started | Aug 17 06:50:56 PM PDT 24 |
| Finished | Aug 17 06:51:27 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-2607d351-06b6-46c0-b1cf-450cfa724ffb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940602880 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_and_unmapped_add r.2940602880 |
| Directory | /workspace/41.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_error_random.673443498 |
| Short name | T1603 |
| Test name | |
| Test status | |
| Simulation time | 1122240403 ps |
| CPU time | 38.01 seconds |
| Started | Aug 17 06:50:54 PM PDT 24 |
| Finished | Aug 17 06:51:32 PM PDT 24 |
| Peak memory | 575276 kb |
| Host | smart-361f937d-e519-4f19-8f6c-3d9010c3eaca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673443498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_error_random.673443498 |
| Directory | /workspace/41.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random.942275139 |
| Short name | T1677 |
| Test name | |
| Test status | |
| Simulation time | 586707667 ps |
| CPU time | 21.61 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 06:51:15 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-43cf4134-3d34-441d-9f86-0485e6031a5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942275139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random.942275139 |
| Directory | /workspace/41.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_large_delays.1178006007 |
| Short name | T1390 |
| Test name | |
| Test status | |
| Simulation time | 5366857591 ps |
| CPU time | 58.08 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:51:58 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-17776159-849c-44e2-b3e2-5c48d7427c73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178006007 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_large_delays.1178006007 |
| Directory | /workspace/41.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_slow_rsp.980691409 |
| Short name | T2794 |
| Test name | |
| Test status | |
| Simulation time | 35148945537 ps |
| CPU time | 601.62 seconds |
| Started | Aug 17 06:51:01 PM PDT 24 |
| Finished | Aug 17 07:01:03 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-53706214-0065-4ab8-b92d-d66473d0e42d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980691409 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_slow_rsp.980691409 |
| Directory | /workspace/41.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_random_zero_delays.1061201523 |
| Short name | T2448 |
| Test name | |
| Test status | |
| Simulation time | 70844419 ps |
| CPU time | 8.72 seconds |
| Started | Aug 17 06:50:56 PM PDT 24 |
| Finished | Aug 17 06:51:04 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-70232fc1-3b9e-4082-be1c-e4af8e861d9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061201523 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_random_zero_del ays.1061201523 |
| Directory | /workspace/41.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_same_source.1231630225 |
| Short name | T2894 |
| Test name | |
| Test status | |
| Simulation time | 135026642 ps |
| CPU time | 12.68 seconds |
| Started | Aug 17 06:51:02 PM PDT 24 |
| Finished | Aug 17 06:51:15 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-8c1432cc-ca5f-422e-9a33-0550cdd1fc2b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231630225 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_same_source.1231630225 |
| Directory | /workspace/41.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke.603518655 |
| Short name | T2031 |
| Test name | |
| Test status | |
| Simulation time | 224901396 ps |
| CPU time | 9.63 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:51:10 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-1e22998c-f7e2-43ec-bcf2-73ee55bd8465 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603518655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke.603518655 |
| Directory | /workspace/41.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_large_delays.1336859710 |
| Short name | T1953 |
| Test name | |
| Test status | |
| Simulation time | 8180383782 ps |
| CPU time | 85.12 seconds |
| Started | Aug 17 06:50:54 PM PDT 24 |
| Finished | Aug 17 06:52:20 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-ac882c22-c3ce-40bf-80a5-29e14ff98a46 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1336859710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_large_delays.1336859710 |
| Directory | /workspace/41.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_slow_rsp.1086256531 |
| Short name | T2524 |
| Test name | |
| Test status | |
| Simulation time | 6111937391 ps |
| CPU time | 104.41 seconds |
| Started | Aug 17 06:50:52 PM PDT 24 |
| Finished | Aug 17 06:52:37 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-d4b17f5c-1b07-45bf-b944-08578b2e9c32 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086256531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_slow_rsp.1086256531 |
| Directory | /workspace/41.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_smoke_zero_delays.2316546131 |
| Short name | T2910 |
| Test name | |
| Test status | |
| Simulation time | 44687653 ps |
| CPU time | 6.59 seconds |
| Started | Aug 17 06:50:53 PM PDT 24 |
| Finished | Aug 17 06:50:59 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-bde05cbe-80bf-46d8-a46d-6cb3a578fa73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316546131 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_smoke_zero_delay s.2316546131 |
| Directory | /workspace/41.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all.2340910307 |
| Short name | T1866 |
| Test name | |
| Test status | |
| Simulation time | 7148561339 ps |
| CPU time | 265.73 seconds |
| Started | Aug 17 06:50:58 PM PDT 24 |
| Finished | Aug 17 06:55:24 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-99642538-1fc9-4f80-b403-dc20acf36709 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340910307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all.2340910307 |
| Directory | /workspace/41.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_error.4082942782 |
| Short name | T2625 |
| Test name | |
| Test status | |
| Simulation time | 5258754106 ps |
| CPU time | 356.7 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:57:15 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-c49efdc6-e875-465d-a822-e9adb4faf273 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082942782 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all_with_error.4082942782 |
| Directory | /workspace/41.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_rand_reset.3118618912 |
| Short name | T2800 |
| Test name | |
| Test status | |
| Simulation time | 5339323992 ps |
| CPU time | 420.66 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:58:00 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-89136374-8dd9-4e5b-889e-c89e9128aa6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3118618912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_all _with_rand_reset.3118618912 |
| Directory | /workspace/41.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_stress_all_with_reset_error.2509593101 |
| Short name | T1604 |
| Test name | |
| Test status | |
| Simulation time | 28029754 ps |
| CPU time | 15.34 seconds |
| Started | Aug 17 06:51:01 PM PDT 24 |
| Finished | Aug 17 06:51:17 PM PDT 24 |
| Peak memory | 573636 kb |
| Host | smart-7798a803-a6e7-44ce-bce0-564840d54483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509593101 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_stress_al l_with_reset_error.2509593101 |
| Directory | /workspace/41.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/41.xbar_unmapped_addr.2449610572 |
| Short name | T1845 |
| Test name | |
| Test status | |
| Simulation time | 1321810323 ps |
| CPU time | 49.45 seconds |
| Started | Aug 17 06:51:02 PM PDT 24 |
| Finished | Aug 17 06:51:52 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-6084144c-6507-4026-861f-429a0250fa93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449610572 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.xbar_unmapped_addr.2449610572 |
| Directory | /workspace/41.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device.1512827667 |
| Short name | T1537 |
| Test name | |
| Test status | |
| Simulation time | 488492216 ps |
| CPU time | 35.77 seconds |
| Started | Aug 17 06:51:01 PM PDT 24 |
| Finished | Aug 17 06:51:36 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-6105ee8a-f400-48c1-ab7d-960ed8f9d3aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512827667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_device .1512827667 |
| Directory | /workspace/42.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.287768253 |
| Short name | T2513 |
| Test name | |
| Test status | |
| Simulation time | 48805726865 ps |
| CPU time | 843.86 seconds |
| Started | Aug 17 06:50:59 PM PDT 24 |
| Finished | Aug 17 07:05:03 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-d1ffbfd7-d4f3-4bd5-9fe8-231bc8bc4c65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=287768253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_access_same_d evice_slow_rsp.287768253 |
| Directory | /workspace/42.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_and_unmapped_addr.8925461 |
| Short name | T2113 |
| Test name | |
| Test status | |
| Simulation time | 888148097 ps |
| CPU time | 33.8 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:51:34 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-5a4aa5c3-7686-4fca-95b7-7b5a1d6f1a0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8925461 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_and_unmapped_addr.8925461 |
| Directory | /workspace/42.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_error_random.2165974963 |
| Short name | T2103 |
| Test name | |
| Test status | |
| Simulation time | 162752546 ps |
| CPU time | 15.5 seconds |
| Started | Aug 17 06:51:03 PM PDT 24 |
| Finished | Aug 17 06:51:18 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-7c249de6-a784-41c2-be64-68478b7f5acd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165974963 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_error_random.2165974963 |
| Directory | /workspace/42.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random.3966999313 |
| Short name | T2200 |
| Test name | |
| Test status | |
| Simulation time | 1884665057 ps |
| CPU time | 75.83 seconds |
| Started | Aug 17 06:51:01 PM PDT 24 |
| Finished | Aug 17 06:52:16 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-cec40cff-4ada-47d9-a184-9f4897316c34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966999313 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random.3966999313 |
| Directory | /workspace/42.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_large_delays.1433211714 |
| Short name | T2439 |
| Test name | |
| Test status | |
| Simulation time | 17221406739 ps |
| CPU time | 172.74 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:54:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-216dab19-5d4e-484e-9144-21fb48c82369 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433211714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_large_delays.1433211714 |
| Directory | /workspace/42.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_slow_rsp.2691336088 |
| Short name | T1719 |
| Test name | |
| Test status | |
| Simulation time | 76821708208 ps |
| CPU time | 1411.52 seconds |
| Started | Aug 17 06:51:03 PM PDT 24 |
| Finished | Aug 17 07:14:35 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-8c449c8a-c04d-479c-90d9-f554fc7eb368 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691336088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_slow_rsp.2691336088 |
| Directory | /workspace/42.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_random_zero_delays.1639299950 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 582034630 ps |
| CPU time | 48.25 seconds |
| Started | Aug 17 06:51:08 PM PDT 24 |
| Finished | Aug 17 06:51:56 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-273f7f2f-a42e-4661-ae5d-bf5fb9a376a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639299950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_random_zero_del ays.1639299950 |
| Directory | /workspace/42.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_same_source.2532943581 |
| Short name | T1465 |
| Test name | |
| Test status | |
| Simulation time | 447817131 ps |
| CPU time | 31.4 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:51:49 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-9de7ee6f-f96d-454a-a746-5f97c33d8362 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532943581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_same_source.2532943581 |
| Directory | /workspace/42.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke.3391210909 |
| Short name | T2918 |
| Test name | |
| Test status | |
| Simulation time | 135419645 ps |
| CPU time | 7.52 seconds |
| Started | Aug 17 06:51:17 PM PDT 24 |
| Finished | Aug 17 06:51:25 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-18812fa9-d47c-4732-8561-bd22b5ee7c96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391210909 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke.3391210909 |
| Directory | /workspace/42.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_large_delays.1344035083 |
| Short name | T2834 |
| Test name | |
| Test status | |
| Simulation time | 7143750659 ps |
| CPU time | 72.25 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:52:30 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-79aa0e7a-bdd8-45bb-af76-139d2045cce7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344035083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_large_delays.1344035083 |
| Directory | /workspace/42.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_slow_rsp.2068086848 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 5244353231 ps |
| CPU time | 92.23 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:52:32 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-28c991d3-65c7-41a7-a2e4-d1eccb626fc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068086848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_slow_rsp.2068086848 |
| Directory | /workspace/42.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_smoke_zero_delays.1348269026 |
| Short name | T1414 |
| Test name | |
| Test status | |
| Simulation time | 43055880 ps |
| CPU time | 6.42 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:51:06 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-c56efefe-2f8f-4d7e-a97e-72fe811bf2fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348269026 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_smoke_zero_delay s.1348269026 |
| Directory | /workspace/42.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all.4021687230 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 745724491 ps |
| CPU time | 32.61 seconds |
| Started | Aug 17 06:50:59 PM PDT 24 |
| Finished | Aug 17 06:51:32 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-b485ec35-3a65-4d63-84ef-dea476439b07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4021687230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all.4021687230 |
| Directory | /workspace/42.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_error.198842876 |
| Short name | T1573 |
| Test name | |
| Test status | |
| Simulation time | 12768572930 ps |
| CPU time | 419.79 seconds |
| Started | Aug 17 06:51:05 PM PDT 24 |
| Finished | Aug 17 06:58:05 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-55bae3fa-b461-4137-a617-ac0f69b62c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198842876 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_all_with_error.198842876 |
| Directory | /workspace/42.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_stress_all_with_reset_error.2205911780 |
| Short name | T2624 |
| Test name | |
| Test status | |
| Simulation time | 138727577 ps |
| CPU time | 76.45 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:52:16 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-45a01893-5128-43f5-95f0-7b43a82a37d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205911780 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_stress_al l_with_reset_error.2205911780 |
| Directory | /workspace/42.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/42.xbar_unmapped_addr.374609383 |
| Short name | T2808 |
| Test name | |
| Test status | |
| Simulation time | 521010981 ps |
| CPU time | 20.97 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:51:21 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-4b79f1b6-5e5e-4d9b-99f9-77a7144e9a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374609383 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.xbar_unmapped_addr.374609383 |
| Directory | /workspace/42.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device.3411011576 |
| Short name | T1966 |
| Test name | |
| Test status | |
| Simulation time | 1690945431 ps |
| CPU time | 71.03 seconds |
| Started | Aug 17 06:51:07 PM PDT 24 |
| Finished | Aug 17 06:52:18 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-a4e0c622-8330-43b3-9358-98002d441831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411011576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_device .3411011576 |
| Directory | /workspace/43.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_access_same_device_slow_rsp.790026708 |
| Short name | T1990 |
| Test name | |
| Test status | |
| Simulation time | 107764563284 ps |
| CPU time | 1972.23 seconds |
| Started | Aug 17 06:51:12 PM PDT 24 |
| Finished | Aug 17 07:24:04 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-5b41b844-dc4d-4e2c-9115-fb0007f46b9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790026708 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_access_same_d evice_slow_rsp.790026708 |
| Directory | /workspace/43.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_error_and_unmapped_addr.3326235894 |
| Short name | T1586 |
| Test name | |
| Test status | |
| Simulation time | 100035181 ps |
| CPU time | 12.75 seconds |
| Started | Aug 17 06:51:07 PM PDT 24 |
| Finished | Aug 17 06:51:20 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-85550a72-be21-464b-9a02-eec6cc9e9d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326235894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_error_and_unmapped_add r.3326235894 |
| Directory | /workspace/43.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random.4113647831 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 1209287100 ps |
| CPU time | 45.8 seconds |
| Started | Aug 17 06:51:00 PM PDT 24 |
| Finished | Aug 17 06:51:46 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-99338d35-d3e6-4a59-adbe-21a19aca1bb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113647831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random.4113647831 |
| Directory | /workspace/43.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_large_delays.2491239494 |
| Short name | T2833 |
| Test name | |
| Test status | |
| Simulation time | 3865200362 ps |
| CPU time | 40.46 seconds |
| Started | Aug 17 06:51:07 PM PDT 24 |
| Finished | Aug 17 06:51:48 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-e45633be-504c-46c9-b5c7-50da76e898e0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491239494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_large_delays.2491239494 |
| Directory | /workspace/43.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_slow_rsp.536333899 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 54481786607 ps |
| CPU time | 1022.23 seconds |
| Started | Aug 17 06:51:09 PM PDT 24 |
| Finished | Aug 17 07:08:12 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-376e4e36-e7ad-4deb-94e1-7af09331efd5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=536333899 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_slow_rsp.536333899 |
| Directory | /workspace/43.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_random_zero_delays.199955512 |
| Short name | T1500 |
| Test name | |
| Test status | |
| Simulation time | 118511132 ps |
| CPU time | 13.11 seconds |
| Started | Aug 17 06:51:02 PM PDT 24 |
| Finished | Aug 17 06:51:15 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-07ce5c7f-f8c3-41f8-a6ba-2751e1a0ab5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199955512 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_random_zero_dela ys.199955512 |
| Directory | /workspace/43.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_same_source.601233562 |
| Short name | T2743 |
| Test name | |
| Test status | |
| Simulation time | 569655740 ps |
| CPU time | 33.63 seconds |
| Started | Aug 17 06:51:20 PM PDT 24 |
| Finished | Aug 17 06:51:53 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-642b08df-9a72-4738-b4cf-9650a2423204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601233562 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_same_source.601233562 |
| Directory | /workspace/43.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke.2561919084 |
| Short name | T1625 |
| Test name | |
| Test status | |
| Simulation time | 255196070 ps |
| CPU time | 10.13 seconds |
| Started | Aug 17 06:51:01 PM PDT 24 |
| Finished | Aug 17 06:51:11 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-b4a0c990-fe1e-4102-8ef4-1be700125872 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2561919084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke.2561919084 |
| Directory | /workspace/43.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_large_delays.2210401542 |
| Short name | T1663 |
| Test name | |
| Test status | |
| Simulation time | 7822528305 ps |
| CPU time | 78.13 seconds |
| Started | Aug 17 06:51:01 PM PDT 24 |
| Finished | Aug 17 06:52:20 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-433d65a1-26ec-4b38-aae3-6cd2e1eefe03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210401542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_large_delays.2210401542 |
| Directory | /workspace/43.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3690688835 |
| Short name | T1958 |
| Test name | |
| Test status | |
| Simulation time | 5204069140 ps |
| CPU time | 88.94 seconds |
| Started | Aug 17 06:51:01 PM PDT 24 |
| Finished | Aug 17 06:52:30 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-1a4b6824-7443-49e6-9fd5-86c97ef3dfed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690688835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_slow_rsp.3690688835 |
| Directory | /workspace/43.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_smoke_zero_delays.3626282417 |
| Short name | T2142 |
| Test name | |
| Test status | |
| Simulation time | 46222287 ps |
| CPU time | 6.73 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:51:25 PM PDT 24 |
| Peak memory | 573408 kb |
| Host | smart-7d53ff59-1d71-4ac4-bcbb-7a7f8cc7a304 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626282417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_smoke_zero_delay s.3626282417 |
| Directory | /workspace/43.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all.3348506826 |
| Short name | T1657 |
| Test name | |
| Test status | |
| Simulation time | 7079226164 ps |
| CPU time | 266.34 seconds |
| Started | Aug 17 06:51:07 PM PDT 24 |
| Finished | Aug 17 06:55:33 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-41754eba-eb42-4d74-b1fd-9937c4182eb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348506826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all.3348506826 |
| Directory | /workspace/43.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_rand_reset.1227155801 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 3867429269 ps |
| CPU time | 495.45 seconds |
| Started | Aug 17 06:51:07 PM PDT 24 |
| Finished | Aug 17 06:59:23 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-5ea000c0-f98e-4ff7-839e-b6bda81e76c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227155801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_all _with_rand_reset.1227155801 |
| Directory | /workspace/43.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_stress_all_with_reset_error.3088350849 |
| Short name | T2119 |
| Test name | |
| Test status | |
| Simulation time | 10441972042 ps |
| CPU time | 536.8 seconds |
| Started | Aug 17 06:51:07 PM PDT 24 |
| Finished | Aug 17 07:00:04 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-2b382fae-4f2a-4f25-bcc2-f7838ffba058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3088350849 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_stress_al l_with_reset_error.3088350849 |
| Directory | /workspace/43.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/43.xbar_unmapped_addr.2702232057 |
| Short name | T2893 |
| Test name | |
| Test status | |
| Simulation time | 334885216 ps |
| CPU time | 37.39 seconds |
| Started | Aug 17 06:51:09 PM PDT 24 |
| Finished | Aug 17 06:51:46 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-6a63a52c-1259-4b26-92e5-7f7ba16cb952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702232057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.xbar_unmapped_addr.2702232057 |
| Directory | /workspace/43.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device.1508586111 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 522852077 ps |
| CPU time | 38.5 seconds |
| Started | Aug 17 06:51:17 PM PDT 24 |
| Finished | Aug 17 06:51:56 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-9f01b551-6161-48d8-b4da-4ee22093e79f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508586111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_device .1508586111 |
| Directory | /workspace/44.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2893835684 |
| Short name | T2160 |
| Test name | |
| Test status | |
| Simulation time | 129283682454 ps |
| CPU time | 2567.54 seconds |
| Started | Aug 17 06:51:16 PM PDT 24 |
| Finished | Aug 17 07:34:04 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-fcb0285d-352b-4ac0-8f99-0a7c6fbd9274 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893835684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_access_same_ device_slow_rsp.2893835684 |
| Directory | /workspace/44.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_and_unmapped_addr.2485766736 |
| Short name | T2219 |
| Test name | |
| Test status | |
| Simulation time | 327589911 ps |
| CPU time | 31.99 seconds |
| Started | Aug 17 06:51:13 PM PDT 24 |
| Finished | Aug 17 06:51:45 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-8c7da924-6f55-4838-ae59-8e099c5b639d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2485766736 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_and_unmapped_add r.2485766736 |
| Directory | /workspace/44.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_error_random.1333409977 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 294498409 ps |
| CPU time | 24.24 seconds |
| Started | Aug 17 06:51:27 PM PDT 24 |
| Finished | Aug 17 06:51:51 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-25ceedcf-8641-47e5-89c8-b376439b57ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333409977 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_error_random.1333409977 |
| Directory | /workspace/44.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random.2355470568 |
| Short name | T2860 |
| Test name | |
| Test status | |
| Simulation time | 631076427 ps |
| CPU time | 25.51 seconds |
| Started | Aug 17 06:51:17 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-3e6875ce-97dd-41f0-8228-504a6b5fb02e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355470568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random.2355470568 |
| Directory | /workspace/44.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_large_delays.559975931 |
| Short name | T2023 |
| Test name | |
| Test status | |
| Simulation time | 28417312037 ps |
| CPU time | 308.45 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:56:26 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-5c75d4a9-c4d3-4395-a2d1-2068eacd5ef0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559975931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_large_delays.559975931 |
| Directory | /workspace/44.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_slow_rsp.1620652903 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 60294372832 ps |
| CPU time | 1065.34 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 07:09:04 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-ddbb3744-36c2-4b01-9613-9fba0a04262c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620652903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_slow_rsp.1620652903 |
| Directory | /workspace/44.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_random_zero_delays.1555510733 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 227326474 ps |
| CPU time | 23.9 seconds |
| Started | Aug 17 06:51:16 PM PDT 24 |
| Finished | Aug 17 06:51:40 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-00a1eb5b-cfa4-4b3a-ace5-1264585aaf7b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1555510733 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_random_zero_del ays.1555510733 |
| Directory | /workspace/44.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_same_source.1837516102 |
| Short name | T2241 |
| Test name | |
| Test status | |
| Simulation time | 1665477359 ps |
| CPU time | 49.4 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:52:07 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-920ba9fb-c3b3-407f-ba6c-d0922cc22808 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837516102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_same_source.1837516102 |
| Directory | /workspace/44.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke.2892861317 |
| Short name | T2600 |
| Test name | |
| Test status | |
| Simulation time | 47191611 ps |
| CPU time | 6.62 seconds |
| Started | Aug 17 06:51:12 PM PDT 24 |
| Finished | Aug 17 06:51:18 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-d1c71932-0b5a-4edb-b9b2-5f225c688ae3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892861317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke.2892861317 |
| Directory | /workspace/44.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_large_delays.708837334 |
| Short name | T1767 |
| Test name | |
| Test status | |
| Simulation time | 8270523152 ps |
| CPU time | 82.96 seconds |
| Started | Aug 17 06:51:05 PM PDT 24 |
| Finished | Aug 17 06:52:29 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-6c2a3d06-d27a-4604-8ab6-751bb9368f18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708837334 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_large_delays.708837334 |
| Directory | /workspace/44.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.2843347706 |
| Short name | T1362 |
| Test name | |
| Test status | |
| Simulation time | 6065840348 ps |
| CPU time | 106.5 seconds |
| Started | Aug 17 06:51:08 PM PDT 24 |
| Finished | Aug 17 06:52:54 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-3fb1bd7d-fe07-447f-b522-50e279f9dcdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843347706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_slow_rsp.2843347706 |
| Directory | /workspace/44.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3255854748 |
| Short name | T2425 |
| Test name | |
| Test status | |
| Simulation time | 47114390 ps |
| CPU time | 5.91 seconds |
| Started | Aug 17 06:51:07 PM PDT 24 |
| Finished | Aug 17 06:51:13 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-e67b780f-a00d-480f-8d5c-1ae0b4250788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255854748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_smoke_zero_delay s.3255854748 |
| Directory | /workspace/44.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all.4115461653 |
| Short name | T2018 |
| Test name | |
| Test status | |
| Simulation time | 5346611704 ps |
| CPU time | 160.27 seconds |
| Started | Aug 17 06:51:15 PM PDT 24 |
| Finished | Aug 17 06:53:55 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-f1a2058b-44f9-4339-a7cc-93083f114eb0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4115461653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all.4115461653 |
| Directory | /workspace/44.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_error.3353666152 |
| Short name | T1986 |
| Test name | |
| Test status | |
| Simulation time | 1842606726 ps |
| CPU time | 143.8 seconds |
| Started | Aug 17 06:51:15 PM PDT 24 |
| Finished | Aug 17 06:53:39 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-543f6677-68f5-430c-a339-4a39d1525a97 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3353666152 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all_with_error.3353666152 |
| Directory | /workspace/44.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_rand_reset.3714421073 |
| Short name | T2541 |
| Test name | |
| Test status | |
| Simulation time | 566570937 ps |
| CPU time | 59.82 seconds |
| Started | Aug 17 06:51:28 PM PDT 24 |
| Finished | Aug 17 06:52:28 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-774bd4db-53f2-4df4-80df-eae4d7cb069f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3714421073 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_all _with_rand_reset.3714421073 |
| Directory | /workspace/44.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_stress_all_with_reset_error.3967948340 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 206194266 ps |
| CPU time | 35.12 seconds |
| Started | Aug 17 06:51:14 PM PDT 24 |
| Finished | Aug 17 06:51:49 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-073a9c57-db62-43a2-8f7f-c5917c0c0a4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967948340 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_stress_al l_with_reset_error.3967948340 |
| Directory | /workspace/44.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.2467815087 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 654201689 ps |
| CPU time | 31.33 seconds |
| Started | Aug 17 06:51:16 PM PDT 24 |
| Finished | Aug 17 06:51:47 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-342260a0-1f03-4352-8754-00759af07512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467815087 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.xbar_unmapped_addr.2467815087 |
| Directory | /workspace/44.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_access_same_device.3227884721 |
| Short name | T2935 |
| Test name | |
| Test status | |
| Simulation time | 406916166 ps |
| CPU time | 19.49 seconds |
| Started | Aug 17 06:51:37 PM PDT 24 |
| Finished | Aug 17 06:51:57 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-acdd97eb-ff30-4202-80fd-bd8f082501c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227884721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_access_same_device .3227884721 |
| Directory | /workspace/45.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_and_unmapped_addr.850780887 |
| Short name | T1398 |
| Test name | |
| Test status | |
| Simulation time | 1079648856 ps |
| CPU time | 45.61 seconds |
| Started | Aug 17 06:51:23 PM PDT 24 |
| Finished | Aug 17 06:52:09 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-010fbdd4-d07e-4be7-a3cc-59889814cc8b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850780887 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_and_unmapped_addr .850780887 |
| Directory | /workspace/45.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_error_random.3931208579 |
| Short name | T1954 |
| Test name | |
| Test status | |
| Simulation time | 426136556 ps |
| CPU time | 17.25 seconds |
| Started | Aug 17 06:51:38 PM PDT 24 |
| Finished | Aug 17 06:51:55 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-89b1bd91-87b6-4265-92d5-26f4666ab291 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931208579 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_error_random.3931208579 |
| Directory | /workspace/45.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random.499480574 |
| Short name | T2584 |
| Test name | |
| Test status | |
| Simulation time | 2471465503 ps |
| CPU time | 92.28 seconds |
| Started | Aug 17 06:51:20 PM PDT 24 |
| Finished | Aug 17 06:52:52 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-fc35d217-a5c1-41da-9e0e-3de9c5606d0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499480574 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random.499480574 |
| Directory | /workspace/45.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_large_delays.466945697 |
| Short name | T2303 |
| Test name | |
| Test status | |
| Simulation time | 99160563579 ps |
| CPU time | 1053.94 seconds |
| Started | Aug 17 06:51:22 PM PDT 24 |
| Finished | Aug 17 07:08:56 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-67fa88e0-43dc-44b8-a06d-f1da0b69453d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=466945697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_large_delays.466945697 |
| Directory | /workspace/45.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_slow_rsp.721390003 |
| Short name | T1942 |
| Test name | |
| Test status | |
| Simulation time | 15823602624 ps |
| CPU time | 259.49 seconds |
| Started | Aug 17 06:51:37 PM PDT 24 |
| Finished | Aug 17 06:55:57 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-93d365d4-f9c9-456d-ad71-0537fa91e719 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721390003 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_slow_rsp.721390003 |
| Directory | /workspace/45.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_random_zero_delays.2558753848 |
| Short name | T2274 |
| Test name | |
| Test status | |
| Simulation time | 411145491 ps |
| CPU time | 33.96 seconds |
| Started | Aug 17 06:51:21 PM PDT 24 |
| Finished | Aug 17 06:51:55 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-f43a9121-488c-472b-92fe-22a1107cf267 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558753848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_random_zero_del ays.2558753848 |
| Directory | /workspace/45.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_same_source.547876011 |
| Short name | T2843 |
| Test name | |
| Test status | |
| Simulation time | 371188771 ps |
| CPU time | 28.66 seconds |
| Started | Aug 17 06:51:21 PM PDT 24 |
| Finished | Aug 17 06:51:50 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-1beb4188-5a10-4691-bc44-7c65e0461820 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547876011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_same_source.547876011 |
| Directory | /workspace/45.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke.60965611 |
| Short name | T1950 |
| Test name | |
| Test status | |
| Simulation time | 208375545 ps |
| CPU time | 8.8 seconds |
| Started | Aug 17 06:51:18 PM PDT 24 |
| Finished | Aug 17 06:51:27 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-6b486cd1-1278-408c-9689-74c26d7eea02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60965611 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke.60965611 |
| Directory | /workspace/45.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_large_delays.757717887 |
| Short name | T2558 |
| Test name | |
| Test status | |
| Simulation time | 8920908830 ps |
| CPU time | 94.89 seconds |
| Started | Aug 17 06:51:23 PM PDT 24 |
| Finished | Aug 17 06:52:57 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-7672669b-19d5-433d-9f8b-c1a7cf449035 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=757717887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_large_delays.757717887 |
| Directory | /workspace/45.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_slow_rsp.818405036 |
| Short name | T2247 |
| Test name | |
| Test status | |
| Simulation time | 5566237623 ps |
| CPU time | 92 seconds |
| Started | Aug 17 06:51:22 PM PDT 24 |
| Finished | Aug 17 06:52:54 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-cfe33288-73cc-4045-9020-096eea624535 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818405036 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_slow_rsp.818405036 |
| Directory | /workspace/45.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_smoke_zero_delays.470072895 |
| Short name | T2756 |
| Test name | |
| Test status | |
| Simulation time | 34356654 ps |
| CPU time | 5.83 seconds |
| Started | Aug 17 06:51:15 PM PDT 24 |
| Finished | Aug 17 06:51:21 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-dbbabf23-65cf-47ac-904b-9b16fca5ab54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470072895 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_smoke_zero_delays .470072895 |
| Directory | /workspace/45.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all.1491169869 |
| Short name | T2786 |
| Test name | |
| Test status | |
| Simulation time | 10553092300 ps |
| CPU time | 397.4 seconds |
| Started | Aug 17 06:51:23 PM PDT 24 |
| Finished | Aug 17 06:58:01 PM PDT 24 |
| Peak memory | 575868 kb |
| Host | smart-0d9f4920-6757-4e59-9a22-8ebc06d57912 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491169869 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all.1491169869 |
| Directory | /workspace/45.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_error.1686211504 |
| Short name | T2196 |
| Test name | |
| Test status | |
| Simulation time | 3373135605 ps |
| CPU time | 204.55 seconds |
| Started | Aug 17 06:51:25 PM PDT 24 |
| Finished | Aug 17 06:54:50 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-7a56e885-002c-45f9-a637-67204347cfe8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686211504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all_with_error.1686211504 |
| Directory | /workspace/45.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_rand_reset.2243608230 |
| Short name | T2055 |
| Test name | |
| Test status | |
| Simulation time | 7917427829 ps |
| CPU time | 485.13 seconds |
| Started | Aug 17 06:51:22 PM PDT 24 |
| Finished | Aug 17 06:59:27 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-a0dde062-06a6-4b41-b946-be0e418dcea2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243608230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_rand_reset.2243608230 |
| Directory | /workspace/45.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_stress_all_with_reset_error.406462446 |
| Short name | T2033 |
| Test name | |
| Test status | |
| Simulation time | 7123398217 ps |
| CPU time | 420.2 seconds |
| Started | Aug 17 06:51:38 PM PDT 24 |
| Finished | Aug 17 06:58:38 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-bd82aa18-3705-4cac-a314-3ee307321851 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=406462446 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_stress_all _with_reset_error.406462446 |
| Directory | /workspace/45.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/45.xbar_unmapped_addr.2806512548 |
| Short name | T2691 |
| Test name | |
| Test status | |
| Simulation time | 183363508 ps |
| CPU time | 23.92 seconds |
| Started | Aug 17 06:51:23 PM PDT 24 |
| Finished | Aug 17 06:51:47 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-7fdb61a6-df11-4ecd-b4fb-6c6a9f728f63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806512548 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.xbar_unmapped_addr.2806512548 |
| Directory | /workspace/45.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device.1184933392 |
| Short name | T1970 |
| Test name | |
| Test status | |
| Simulation time | 2006426832 ps |
| CPU time | 87.27 seconds |
| Started | Aug 17 06:51:26 PM PDT 24 |
| Finished | Aug 17 06:52:53 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-1c9286b3-b224-452e-b9a4-09ba224ed827 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184933392 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_device .1184933392 |
| Directory | /workspace/46.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_access_same_device_slow_rsp.2265366274 |
| Short name | T1548 |
| Test name | |
| Test status | |
| Simulation time | 113549745082 ps |
| CPU time | 1974.03 seconds |
| Started | Aug 17 06:51:26 PM PDT 24 |
| Finished | Aug 17 07:24:20 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-553e7d7e-ed97-4a5d-a017-9d9a20ea7f7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265366274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_access_same_ device_slow_rsp.2265366274 |
| Directory | /workspace/46.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_and_unmapped_addr.4216578590 |
| Short name | T2412 |
| Test name | |
| Test status | |
| Simulation time | 191197061 ps |
| CPU time | 21.49 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 06:51:58 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-5c9d3bbd-599a-4e0f-b0da-3066c6e97385 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216578590 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_and_unmapped_add r.4216578590 |
| Directory | /workspace/46.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_error_random.4157193711 |
| Short name | T2680 |
| Test name | |
| Test status | |
| Simulation time | 1466772445 ps |
| CPU time | 51.09 seconds |
| Started | Aug 17 06:51:39 PM PDT 24 |
| Finished | Aug 17 06:52:30 PM PDT 24 |
| Peak memory | 575292 kb |
| Host | smart-e12487ba-9ec5-4c7b-83bd-fb2e5b999961 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157193711 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_error_random.4157193711 |
| Directory | /workspace/46.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random.4287931413 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2166531603 ps |
| CPU time | 81.51 seconds |
| Started | Aug 17 06:51:27 PM PDT 24 |
| Finished | Aug 17 06:52:49 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-1ac1fd81-7832-4269-a70b-a8b9c5e78318 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4287931413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random.4287931413 |
| Directory | /workspace/46.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_large_delays.2272219674 |
| Short name | T2559 |
| Test name | |
| Test status | |
| Simulation time | 26229426307 ps |
| CPU time | 292.67 seconds |
| Started | Aug 17 06:51:26 PM PDT 24 |
| Finished | Aug 17 06:56:19 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-c2659b4b-1bec-4fc8-a9d5-97e46c29d715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272219674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_large_delays.2272219674 |
| Directory | /workspace/46.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_slow_rsp.472830953 |
| Short name | T1363 |
| Test name | |
| Test status | |
| Simulation time | 3479316612 ps |
| CPU time | 57.85 seconds |
| Started | Aug 17 06:51:26 PM PDT 24 |
| Finished | Aug 17 06:52:23 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-18c39187-718f-4f27-827d-b91c0525a57c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472830953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_slow_rsp.472830953 |
| Directory | /workspace/46.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_random_zero_delays.855796630 |
| Short name | T2359 |
| Test name | |
| Test status | |
| Simulation time | 476749700 ps |
| CPU time | 42.06 seconds |
| Started | Aug 17 06:51:37 PM PDT 24 |
| Finished | Aug 17 06:52:19 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-dc5dc5d1-e62a-440e-b5b4-7936ea7bc56b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855796630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_random_zero_dela ys.855796630 |
| Directory | /workspace/46.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_same_source.635443097 |
| Short name | T2375 |
| Test name | |
| Test status | |
| Simulation time | 297487740 ps |
| CPU time | 10.28 seconds |
| Started | Aug 17 06:51:34 PM PDT 24 |
| Finished | Aug 17 06:51:44 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-3aaaf4e6-e99d-459b-b764-b7d40f3a6eb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635443097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_same_source.635443097 |
| Directory | /workspace/46.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke.4182570339 |
| Short name | T1680 |
| Test name | |
| Test status | |
| Simulation time | 211815671 ps |
| CPU time | 8.3 seconds |
| Started | Aug 17 06:51:20 PM PDT 24 |
| Finished | Aug 17 06:51:28 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-6ae9fab2-6541-453e-bc61-b40e4440a1e3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4182570339 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke.4182570339 |
| Directory | /workspace/46.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_large_delays.3259782804 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 10610621094 ps |
| CPU time | 110.13 seconds |
| Started | Aug 17 06:51:38 PM PDT 24 |
| Finished | Aug 17 06:53:28 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-fad15dcb-dcba-47e3-81e9-d3f868741985 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3259782804 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_large_delays.3259782804 |
| Directory | /workspace/46.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_slow_rsp.490612096 |
| Short name | T2130 |
| Test name | |
| Test status | |
| Simulation time | 5667789246 ps |
| CPU time | 97.72 seconds |
| Started | Aug 17 06:51:26 PM PDT 24 |
| Finished | Aug 17 06:53:04 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-66db11af-1bfc-49a6-bb60-ab18ede4f347 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=490612096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_slow_rsp.490612096 |
| Directory | /workspace/46.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_smoke_zero_delays.797372127 |
| Short name | T1488 |
| Test name | |
| Test status | |
| Simulation time | 44320528 ps |
| CPU time | 6.16 seconds |
| Started | Aug 17 06:51:20 PM PDT 24 |
| Finished | Aug 17 06:51:26 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-2baf24c4-80d7-4237-a69f-a44bd5d86295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797372127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_smoke_zero_delays .797372127 |
| Directory | /workspace/46.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all.3237074184 |
| Short name | T1353 |
| Test name | |
| Test status | |
| Simulation time | 206676799 ps |
| CPU time | 8.43 seconds |
| Started | Aug 17 06:51:37 PM PDT 24 |
| Finished | Aug 17 06:51:45 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-3ff0b310-5719-4c05-aab2-42d18dfa842f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237074184 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all.3237074184 |
| Directory | /workspace/46.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_error.1468164312 |
| Short name | T1538 |
| Test name | |
| Test status | |
| Simulation time | 6927609479 ps |
| CPU time | 243.16 seconds |
| Started | Aug 17 06:51:37 PM PDT 24 |
| Finished | Aug 17 06:55:40 PM PDT 24 |
| Peak memory | 575940 kb |
| Host | smart-aa33979b-b308-4188-bc76-d17f928e08c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468164312 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all_with_error.1468164312 |
| Directory | /workspace/46.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_rand_reset.3832285921 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 927166785 ps |
| CPU time | 266.67 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 06:56:03 PM PDT 24 |
| Peak memory | 576308 kb |
| Host | smart-fa85810c-21ff-4e3d-bf49-fd5c2e5709ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832285921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_all _with_rand_reset.3832285921 |
| Directory | /workspace/46.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_stress_all_with_reset_error.1350263604 |
| Short name | T1392 |
| Test name | |
| Test status | |
| Simulation time | 82334643 ps |
| CPU time | 14.39 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 06:51:51 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-30a6b902-9177-4721-8c00-c874fe075e9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1350263604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_stress_al l_with_reset_error.1350263604 |
| Directory | /workspace/46.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/46.xbar_unmapped_addr.1557859443 |
| Short name | T2735 |
| Test name | |
| Test status | |
| Simulation time | 962771036 ps |
| CPU time | 44 seconds |
| Started | Aug 17 06:51:35 PM PDT 24 |
| Finished | Aug 17 06:52:19 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-3df634ea-df87-44cf-87d7-8a76cf8818d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557859443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.xbar_unmapped_addr.1557859443 |
| Directory | /workspace/46.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device.1224694363 |
| Short name | T1473 |
| Test name | |
| Test status | |
| Simulation time | 15624291 ps |
| CPU time | 6.29 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-692076d0-2b86-41ea-adaf-9afd2c7d49c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1224694363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_device .1224694363 |
| Directory | /workspace/47.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_access_same_device_slow_rsp.2677371810 |
| Short name | T2075 |
| Test name | |
| Test status | |
| Simulation time | 51426915232 ps |
| CPU time | 927.97 seconds |
| Started | Aug 17 06:51:35 PM PDT 24 |
| Finished | Aug 17 07:07:04 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-cfe9199e-1364-4cef-a4fd-4e754863a487 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677371810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_access_same_ device_slow_rsp.2677371810 |
| Directory | /workspace/47.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_and_unmapped_addr.1136428926 |
| Short name | T2899 |
| Test name | |
| Test status | |
| Simulation time | 983529038 ps |
| CPU time | 40.39 seconds |
| Started | Aug 17 06:51:43 PM PDT 24 |
| Finished | Aug 17 06:52:23 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-1ed9a5c4-d0e0-4a44-9ebd-1781a7178cb9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136428926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_and_unmapped_add r.1136428926 |
| Directory | /workspace/47.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_error_random.2669937206 |
| Short name | T1443 |
| Test name | |
| Test status | |
| Simulation time | 53234453 ps |
| CPU time | 7.65 seconds |
| Started | Aug 17 06:51:45 PM PDT 24 |
| Finished | Aug 17 06:51:53 PM PDT 24 |
| Peak memory | 573352 kb |
| Host | smart-af6fad18-9766-4582-a4c8-c85fde82086e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669937206 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_error_random.2669937206 |
| Directory | /workspace/47.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random.2566386233 |
| Short name | T1368 |
| Test name | |
| Test status | |
| Simulation time | 1149747120 ps |
| CPU time | 43.65 seconds |
| Started | Aug 17 06:51:35 PM PDT 24 |
| Finished | Aug 17 06:52:19 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-fe9acad8-a4a3-441a-b1dd-d1785bd81950 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2566386233 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random.2566386233 |
| Directory | /workspace/47.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_large_delays.3784163499 |
| Short name | T1619 |
| Test name | |
| Test status | |
| Simulation time | 75280136978 ps |
| CPU time | 766.01 seconds |
| Started | Aug 17 06:51:38 PM PDT 24 |
| Finished | Aug 17 07:04:24 PM PDT 24 |
| Peak memory | 574264 kb |
| Host | smart-22cfd28b-288c-465e-af43-ff012ac389e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784163499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_large_delays.3784163499 |
| Directory | /workspace/47.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_slow_rsp.1094369473 |
| Short name | T1732 |
| Test name | |
| Test status | |
| Simulation time | 34227027296 ps |
| CPU time | 609.53 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 07:01:46 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-6f7b3c30-0d78-4f9d-b450-d4451eb561d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094369473 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_slow_rsp.1094369473 |
| Directory | /workspace/47.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_random_zero_delays.3203031293 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 372881561 ps |
| CPU time | 37.97 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 06:52:14 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-8d1ce0e2-6921-40ce-ab07-0134d1e04914 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203031293 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_random_zero_del ays.3203031293 |
| Directory | /workspace/47.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_same_source.3994161338 |
| Short name | T2446 |
| Test name | |
| Test status | |
| Simulation time | 1230602612 ps |
| CPU time | 38.3 seconds |
| Started | Aug 17 06:51:45 PM PDT 24 |
| Finished | Aug 17 06:52:23 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-affcde8c-f094-43d1-8d2d-cedb576f05bd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994161338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_same_source.3994161338 |
| Directory | /workspace/47.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke.686129606 |
| Short name | T2280 |
| Test name | |
| Test status | |
| Simulation time | 38482321 ps |
| CPU time | 5.8 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-7bc9718c-8a19-4acd-ae9d-f66190c5f74b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686129606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke.686129606 |
| Directory | /workspace/47.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_large_delays.1109462664 |
| Short name | T1653 |
| Test name | |
| Test status | |
| Simulation time | 6629705875 ps |
| CPU time | 68.31 seconds |
| Started | Aug 17 06:51:39 PM PDT 24 |
| Finished | Aug 17 06:52:47 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-fca0e793-5654-4399-bba8-39544b6e3284 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109462664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_large_delays.1109462664 |
| Directory | /workspace/47.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_slow_rsp.637231477 |
| Short name | T1707 |
| Test name | |
| Test status | |
| Simulation time | 5725953393 ps |
| CPU time | 101.53 seconds |
| Started | Aug 17 06:51:39 PM PDT 24 |
| Finished | Aug 17 06:53:20 PM PDT 24 |
| Peak memory | 572936 kb |
| Host | smart-d811984a-2a6d-462e-9190-01366bd19bab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637231477 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_slow_rsp.637231477 |
| Directory | /workspace/47.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_smoke_zero_delays.577168580 |
| Short name | T2581 |
| Test name | |
| Test status | |
| Simulation time | 44451662 ps |
| CPU time | 6.14 seconds |
| Started | Aug 17 06:51:36 PM PDT 24 |
| Finished | Aug 17 06:51:42 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-d5c8eceb-ba87-4533-a4e2-efbbd05527cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577168580 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_smoke_zero_delays .577168580 |
| Directory | /workspace/47.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all.3632480090 |
| Short name | T2556 |
| Test name | |
| Test status | |
| Simulation time | 2676012671 ps |
| CPU time | 218.34 seconds |
| Started | Aug 17 06:51:42 PM PDT 24 |
| Finished | Aug 17 06:55:20 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-0a5806d2-dd7d-4e25-93aa-584d7191ed70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632480090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all.3632480090 |
| Directory | /workspace/47.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_error.3505339170 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 8935578850 ps |
| CPU time | 326.42 seconds |
| Started | Aug 17 06:51:42 PM PDT 24 |
| Finished | Aug 17 06:57:09 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-423bc0e0-5a87-4ae4-b55a-39eec19a03b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505339170 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all_with_error.3505339170 |
| Directory | /workspace/47.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_rand_reset.3801186703 |
| Short name | T1789 |
| Test name | |
| Test status | |
| Simulation time | 1817260220 ps |
| CPU time | 155.85 seconds |
| Started | Aug 17 06:51:42 PM PDT 24 |
| Finished | Aug 17 06:54:18 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-44f0852f-d56c-47a5-a0ca-24deac66ced4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801186703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_all _with_rand_reset.3801186703 |
| Directory | /workspace/47.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_stress_all_with_reset_error.3618849965 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 9543209831 ps |
| CPU time | 378.31 seconds |
| Started | Aug 17 06:51:41 PM PDT 24 |
| Finished | Aug 17 06:58:00 PM PDT 24 |
| Peak memory | 576356 kb |
| Host | smart-9d4f37e0-b4ef-4dae-86db-56a7550e582e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618849965 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_stress_al l_with_reset_error.3618849965 |
| Directory | /workspace/47.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/47.xbar_unmapped_addr.747854886 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 175014618 ps |
| CPU time | 20.77 seconds |
| Started | Aug 17 06:51:42 PM PDT 24 |
| Finished | Aug 17 06:52:03 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-1c1b08a3-282b-48e3-b417-33e3d204b681 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747854886 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.xbar_unmapped_addr.747854886 |
| Directory | /workspace/47.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device.2404707022 |
| Short name | T2094 |
| Test name | |
| Test status | |
| Simulation time | 2258370464 ps |
| CPU time | 93.59 seconds |
| Started | Aug 17 06:51:41 PM PDT 24 |
| Finished | Aug 17 06:53:15 PM PDT 24 |
| Peak memory | 574444 kb |
| Host | smart-b6e9e240-7068-4eda-9089-f4bb6a54bfe4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404707022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_device .2404707022 |
| Directory | /workspace/48.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_access_same_device_slow_rsp.3726505240 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 110866217955 ps |
| CPU time | 2142.28 seconds |
| Started | Aug 17 06:51:55 PM PDT 24 |
| Finished | Aug 17 07:27:38 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d11def26-6501-424b-8e0a-269c3e21d1ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726505240 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_access_same_ device_slow_rsp.3726505240 |
| Directory | /workspace/48.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_and_unmapped_addr.1326268441 |
| Short name | T2136 |
| Test name | |
| Test status | |
| Simulation time | 185328806 ps |
| CPU time | 19.58 seconds |
| Started | Aug 17 06:51:48 PM PDT 24 |
| Finished | Aug 17 06:52:08 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-48c62334-6be3-47ef-bfb9-6b0065768380 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326268441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_and_unmapped_add r.1326268441 |
| Directory | /workspace/48.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_error_random.2170542396 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 1958570878 ps |
| CPU time | 77.41 seconds |
| Started | Aug 17 06:51:55 PM PDT 24 |
| Finished | Aug 17 06:53:13 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-72e5e6da-76a4-4fde-be40-f796f11fe5a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170542396 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_error_random.2170542396 |
| Directory | /workspace/48.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random.4129277464 |
| Short name | T1592 |
| Test name | |
| Test status | |
| Simulation time | 1411959055 ps |
| CPU time | 48.16 seconds |
| Started | Aug 17 06:51:45 PM PDT 24 |
| Finished | Aug 17 06:52:34 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-266b8dc5-9416-4792-abb0-3aa5bc8577b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129277464 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random.4129277464 |
| Directory | /workspace/48.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_large_delays.3093866912 |
| Short name | T1631 |
| Test name | |
| Test status | |
| Simulation time | 13583287176 ps |
| CPU time | 144.09 seconds |
| Started | Aug 17 06:51:43 PM PDT 24 |
| Finished | Aug 17 06:54:07 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-e06933ee-4ceb-4928-be73-5376b79f1fe5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093866912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_large_delays.3093866912 |
| Directory | /workspace/48.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_slow_rsp.504038253 |
| Short name | T1430 |
| Test name | |
| Test status | |
| Simulation time | 53466174106 ps |
| CPU time | 878.54 seconds |
| Started | Aug 17 06:51:40 PM PDT 24 |
| Finished | Aug 17 07:06:18 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-5fe69609-e2e0-42bd-9752-9701c29b39b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504038253 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_slow_rsp.504038253 |
| Directory | /workspace/48.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_random_zero_delays.3642715328 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 590230232 ps |
| CPU time | 43.8 seconds |
| Started | Aug 17 06:51:41 PM PDT 24 |
| Finished | Aug 17 06:52:25 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-c9a79350-0fde-4fe0-bcf5-f8454fea8d3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642715328 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_random_zero_del ays.3642715328 |
| Directory | /workspace/48.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_same_source.2303107602 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2590453720 ps |
| CPU time | 81.52 seconds |
| Started | Aug 17 06:51:50 PM PDT 24 |
| Finished | Aug 17 06:53:11 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-b020bccd-b8d2-4efe-bbde-ee79d2912f42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2303107602 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_same_source.2303107602 |
| Directory | /workspace/48.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke.3701514502 |
| Short name | T2360 |
| Test name | |
| Test status | |
| Simulation time | 239537817 ps |
| CPU time | 10.28 seconds |
| Started | Aug 17 06:51:45 PM PDT 24 |
| Finished | Aug 17 06:51:56 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-4d013103-3cb6-46cf-8e4d-c12968c2dd41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701514502 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke.3701514502 |
| Directory | /workspace/48.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_large_delays.3310988999 |
| Short name | T2095 |
| Test name | |
| Test status | |
| Simulation time | 8270992943 ps |
| CPU time | 87.35 seconds |
| Started | Aug 17 06:51:45 PM PDT 24 |
| Finished | Aug 17 06:53:13 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-b9be6d78-4214-43b3-b17d-583692e1969b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310988999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_large_delays.3310988999 |
| Directory | /workspace/48.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_slow_rsp.2971404594 |
| Short name | T1765 |
| Test name | |
| Test status | |
| Simulation time | 5817568721 ps |
| CPU time | 92.56 seconds |
| Started | Aug 17 06:51:42 PM PDT 24 |
| Finished | Aug 17 06:53:14 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-03efbdc6-5436-40b5-b866-909a4536b5b7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971404594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_slow_rsp.2971404594 |
| Directory | /workspace/48.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_smoke_zero_delays.1485052920 |
| Short name | T2736 |
| Test name | |
| Test status | |
| Simulation time | 45416534 ps |
| CPU time | 6.11 seconds |
| Started | Aug 17 06:51:44 PM PDT 24 |
| Finished | Aug 17 06:51:51 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-e11dfeea-336f-4674-a998-fb757485132e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485052920 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_smoke_zero_delay s.1485052920 |
| Directory | /workspace/48.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all.4058507648 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 79588132 ps |
| CPU time | 10.48 seconds |
| Started | Aug 17 06:51:51 PM PDT 24 |
| Finished | Aug 17 06:52:01 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-ff5a3b4a-c052-430e-a8b1-a8f22f1440be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058507648 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all.4058507648 |
| Directory | /workspace/48.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_error.932028325 |
| Short name | T1838 |
| Test name | |
| Test status | |
| Simulation time | 2984950384 ps |
| CPU time | 219.83 seconds |
| Started | Aug 17 06:51:56 PM PDT 24 |
| Finished | Aug 17 06:55:35 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-f160ab2c-f334-4fa3-ad1c-38547c64947f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=932028325 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all_with_error.932028325 |
| Directory | /workspace/48.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_rand_reset.3186924538 |
| Short name | T2502 |
| Test name | |
| Test status | |
| Simulation time | 486717652 ps |
| CPU time | 185.32 seconds |
| Started | Aug 17 06:51:52 PM PDT 24 |
| Finished | Aug 17 06:54:58 PM PDT 24 |
| Peak memory | 576292 kb |
| Host | smart-86c5982c-c374-401b-b0cd-cfe6c2c7f9be |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186924538 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_all _with_rand_reset.3186924538 |
| Directory | /workspace/48.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_stress_all_with_reset_error.1434377624 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 5360156372 ps |
| CPU time | 375.89 seconds |
| Started | Aug 17 06:51:52 PM PDT 24 |
| Finished | Aug 17 06:58:08 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-402cafd2-f2fc-4066-b5b0-4ddae9e96d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434377624 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_stress_al l_with_reset_error.1434377624 |
| Directory | /workspace/48.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/48.xbar_unmapped_addr.920534931 |
| Short name | T2877 |
| Test name | |
| Test status | |
| Simulation time | 273200038 ps |
| CPU time | 14.12 seconds |
| Started | Aug 17 06:51:52 PM PDT 24 |
| Finished | Aug 17 06:52:06 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-7f19f14c-61f1-4d17-b5d7-88e986beb536 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920534931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.xbar_unmapped_addr.920534931 |
| Directory | /workspace/48.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device.1892327567 |
| Short name | T2172 |
| Test name | |
| Test status | |
| Simulation time | 576962620 ps |
| CPU time | 47.71 seconds |
| Started | Aug 17 06:51:56 PM PDT 24 |
| Finished | Aug 17 06:52:44 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-2436ec9a-8ff1-4297-87c8-2527ac9d67dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892327567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_device .1892327567 |
| Directory | /workspace/49.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_access_same_device_slow_rsp.1421892636 |
| Short name | T2145 |
| Test name | |
| Test status | |
| Simulation time | 63350682960 ps |
| CPU time | 1130.19 seconds |
| Started | Aug 17 06:51:56 PM PDT 24 |
| Finished | Aug 17 07:10:46 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-15ca35ef-2980-4333-a187-1445c8537d62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421892636 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_access_same_ device_slow_rsp.1421892636 |
| Directory | /workspace/49.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_and_unmapped_addr.785973916 |
| Short name | T1749 |
| Test name | |
| Test status | |
| Simulation time | 381781692 ps |
| CPU time | 16.65 seconds |
| Started | Aug 17 06:51:57 PM PDT 24 |
| Finished | Aug 17 06:52:14 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-159e3bb6-3e9b-43ee-b146-477b113edfcf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785973916 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_and_unmapped_addr .785973916 |
| Directory | /workspace/49.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_error_random.3634083966 |
| Short name | T2426 |
| Test name | |
| Test status | |
| Simulation time | 562241022 ps |
| CPU time | 23.24 seconds |
| Started | Aug 17 06:51:57 PM PDT 24 |
| Finished | Aug 17 06:52:20 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-66855090-d908-4593-9592-6c8fbdd451c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634083966 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_error_random.3634083966 |
| Directory | /workspace/49.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random.2087260808 |
| Short name | T1839 |
| Test name | |
| Test status | |
| Simulation time | 556814545 ps |
| CPU time | 52.88 seconds |
| Started | Aug 17 06:51:50 PM PDT 24 |
| Finished | Aug 17 06:52:43 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-5f7fba36-27fc-42d7-87f5-229744259c9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2087260808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random.2087260808 |
| Directory | /workspace/49.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_large_delays.1074364972 |
| Short name | T2131 |
| Test name | |
| Test status | |
| Simulation time | 15554177696 ps |
| CPU time | 161.6 seconds |
| Started | Aug 17 06:51:52 PM PDT 24 |
| Finished | Aug 17 06:54:34 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-36cedcba-b388-4c5a-aeab-803399e8ee87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074364972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_large_delays.1074364972 |
| Directory | /workspace/49.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_slow_rsp.4054531803 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 46870215835 ps |
| CPU time | 790.9 seconds |
| Started | Aug 17 06:51:51 PM PDT 24 |
| Finished | Aug 17 07:05:03 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-858fe5ae-6d5f-40a9-a9dd-2a4a57c6e676 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054531803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_slow_rsp.4054531803 |
| Directory | /workspace/49.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_random_zero_delays.480718302 |
| Short name | T2092 |
| Test name | |
| Test status | |
| Simulation time | 526293663 ps |
| CPU time | 49.51 seconds |
| Started | Aug 17 06:51:49 PM PDT 24 |
| Finished | Aug 17 06:52:39 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-01b4707f-09e7-4307-9c2f-2e8a992ee90e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480718302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_random_zero_dela ys.480718302 |
| Directory | /workspace/49.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_same_source.2205154734 |
| Short name | T2125 |
| Test name | |
| Test status | |
| Simulation time | 327497760 ps |
| CPU time | 27.74 seconds |
| Started | Aug 17 06:51:55 PM PDT 24 |
| Finished | Aug 17 06:52:23 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-47ba48c8-62a0-4f04-9f32-c2e85b163f62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205154734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_same_source.2205154734 |
| Directory | /workspace/49.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke.249082951 |
| Short name | T2489 |
| Test name | |
| Test status | |
| Simulation time | 185901288 ps |
| CPU time | 8.62 seconds |
| Started | Aug 17 06:51:51 PM PDT 24 |
| Finished | Aug 17 06:52:00 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-076e2480-3d90-4b91-ab10-b30d4fd80294 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249082951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke.249082951 |
| Directory | /workspace/49.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_large_delays.4094797960 |
| Short name | T1525 |
| Test name | |
| Test status | |
| Simulation time | 9478287567 ps |
| CPU time | 99.03 seconds |
| Started | Aug 17 06:51:52 PM PDT 24 |
| Finished | Aug 17 06:53:31 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-f57cf900-a9bc-4fc6-b300-8237b0131e53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094797960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_large_delays.4094797960 |
| Directory | /workspace/49.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_slow_rsp.3782611563 |
| Short name | T1640 |
| Test name | |
| Test status | |
| Simulation time | 6608193627 ps |
| CPU time | 121.56 seconds |
| Started | Aug 17 06:51:48 PM PDT 24 |
| Finished | Aug 17 06:53:49 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-c82cb652-254a-42d5-9df3-09f6ebf84978 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782611563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_slow_rsp.3782611563 |
| Directory | /workspace/49.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_smoke_zero_delays.3560944888 |
| Short name | T2451 |
| Test name | |
| Test status | |
| Simulation time | 50192904 ps |
| CPU time | 6.55 seconds |
| Started | Aug 17 06:51:57 PM PDT 24 |
| Finished | Aug 17 06:52:03 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-f1dff0c2-18b4-4b1b-9fd0-60c21ba8dea7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560944888 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_smoke_zero_delay s.3560944888 |
| Directory | /workspace/49.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all.1599621489 |
| Short name | T2194 |
| Test name | |
| Test status | |
| Simulation time | 2547682278 ps |
| CPU time | 192.85 seconds |
| Started | Aug 17 06:51:58 PM PDT 24 |
| Finished | Aug 17 06:55:11 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-8ad77b25-9394-4d94-af35-f05e5efa542b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599621489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all.1599621489 |
| Directory | /workspace/49.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.947730994 |
| Short name | T1440 |
| Test name | |
| Test status | |
| Simulation time | 2612654714 ps |
| CPU time | 169.64 seconds |
| Started | Aug 17 06:51:56 PM PDT 24 |
| Finished | Aug 17 06:54:46 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-da7a4bff-b753-45c9-8e9f-599cae6214cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947730994 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_with_error.947730994 |
| Directory | /workspace/49.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_rand_reset.60128506 |
| Short name | T1830 |
| Test name | |
| Test status | |
| Simulation time | 166248570 ps |
| CPU time | 28.8 seconds |
| Started | Aug 17 06:51:56 PM PDT 24 |
| Finished | Aug 17 06:52:25 PM PDT 24 |
| Peak memory | 576000 kb |
| Host | smart-2c3e9134-2293-49a5-8acd-0e7b14fafb9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60128506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_rese t_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_all_w ith_rand_reset.60128506 |
| Directory | /workspace/49.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.2505801347 |
| Short name | T1687 |
| Test name | |
| Test status | |
| Simulation time | 182174632 ps |
| CPU time | 26.39 seconds |
| Started | Aug 17 06:52:00 PM PDT 24 |
| Finished | Aug 17 06:52:27 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-eef842f5-10d9-4f35-83e8-2112fd6cb5d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505801347 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_stress_al l_with_reset_error.2505801347 |
| Directory | /workspace/49.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/49.xbar_unmapped_addr.1101971889 |
| Short name | T1369 |
| Test name | |
| Test status | |
| Simulation time | 21898075 ps |
| CPU time | 5.54 seconds |
| Started | Aug 17 06:51:55 PM PDT 24 |
| Finished | Aug 17 06:52:00 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-7d5764ff-5e42-49ba-9b2c-9c11f8e10f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101971889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.xbar_unmapped_addr.1101971889 |
| Directory | /workspace/49.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_mem_rw_with_rand_reset.666951803 |
| Short name | T1895 |
| Test name | |
| Test status | |
| Simulation time | 7430420968 ps |
| CPU time | 435.82 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:55:05 PM PDT 24 |
| Peak memory | 644276 kb |
| Host | smart-ef54cb1f-d368-4ea2-94d5-1d81264d0ddb |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666951803 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top. vdb -cm_log /dev/null -cm_name 5.chip_csr_mem_rw_with_rand_reset.666951803 |
| Directory | /workspace/5.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_csr_rw.2752100911 |
| Short name | T2750 |
| Test name | |
| Test status | |
| Simulation time | 4396343214 ps |
| CPU time | 269.35 seconds |
| Started | Aug 17 06:47:40 PM PDT 24 |
| Finished | Aug 17 06:52:09 PM PDT 24 |
| Peak memory | 597848 kb |
| Host | smart-f96e7b85-75e4-4dff-828c-885958a87791 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752100911 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.chip_csr_rw.2752100911 |
| Directory | /workspace/5.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/5.chip_same_csr_outstanding.2082235699 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 26740339527 ps |
| CPU time | 3825.85 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 07:51:29 PM PDT 24 |
| Peak memory | 593388 kb |
| Host | smart-2d1bd193-ddf7-4709-beb9-272cc008263b |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2082235699 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 5.chip_same_csr_outstanding.2082235699 |
| Directory | /workspace/5.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device.3814520238 |
| Short name | T1463 |
| Test name | |
| Test status | |
| Simulation time | 117793722 ps |
| CPU time | 13.63 seconds |
| Started | Aug 17 06:47:30 PM PDT 24 |
| Finished | Aug 17 06:47:43 PM PDT 24 |
| Peak memory | 574236 kb |
| Host | smart-538d54a9-c121-46d6-978d-919097a25f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3814520238 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_device. 3814520238 |
| Directory | /workspace/5.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_access_same_device_slow_rsp.1470449748 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 30891536975 ps |
| CPU time | 518.88 seconds |
| Started | Aug 17 06:47:42 PM PDT 24 |
| Finished | Aug 17 06:56:21 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-09a01467-49a5-4cfb-9ba9-5a80a584e1a0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470449748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_access_same_d evice_slow_rsp.1470449748 |
| Directory | /workspace/5.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_and_unmapped_addr.1861908021 |
| Short name | T1370 |
| Test name | |
| Test status | |
| Simulation time | 72585309 ps |
| CPU time | 6.35 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:47:58 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-68ea8f9d-6608-4262-b467-cc60f632cbdf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861908021 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_and_unmapped_addr .1861908021 |
| Directory | /workspace/5.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_error_random.1443403784 |
| Short name | T2897 |
| Test name | |
| Test status | |
| Simulation time | 2030896878 ps |
| CPU time | 60.41 seconds |
| Started | Aug 17 06:47:34 PM PDT 24 |
| Finished | Aug 17 06:48:35 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-551a7bcf-f9ea-41b3-934c-c8483f5c80bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443403784 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_error_random.1443403784 |
| Directory | /workspace/5.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random.1852246585 |
| Short name | T1536 |
| Test name | |
| Test status | |
| Simulation time | 718208828 ps |
| CPU time | 24.32 seconds |
| Started | Aug 17 06:47:41 PM PDT 24 |
| Finished | Aug 17 06:48:05 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-5cf5a532-834e-4f29-8f83-6c2778c30900 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852246585 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random.1852246585 |
| Directory | /workspace/5.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_large_delays.2381723175 |
| Short name | T2764 |
| Test name | |
| Test status | |
| Simulation time | 41115703019 ps |
| CPU time | 405.1 seconds |
| Started | Aug 17 06:47:33 PM PDT 24 |
| Finished | Aug 17 06:54:18 PM PDT 24 |
| Peak memory | 574344 kb |
| Host | smart-9df6cd8c-a666-4b40-b30a-601ddadabe6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381723175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_large_delays.2381723175 |
| Directory | /workspace/5.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_slow_rsp.2135343274 |
| Short name | T1565 |
| Test name | |
| Test status | |
| Simulation time | 3852465131 ps |
| CPU time | 56.8 seconds |
| Started | Aug 17 06:47:42 PM PDT 24 |
| Finished | Aug 17 06:48:39 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-d2492e2f-df5c-4ed1-812b-cf76a9af9bc0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135343274 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_slow_rsp.2135343274 |
| Directory | /workspace/5.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_random_zero_delays.2952564903 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 513156602 ps |
| CPU time | 47.01 seconds |
| Started | Aug 17 06:47:31 PM PDT 24 |
| Finished | Aug 17 06:48:18 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-43c92aaa-62ea-458d-b296-4bc8209397a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952564903 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_random_zero_dela ys.2952564903 |
| Directory | /workspace/5.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_same_source.2812107183 |
| Short name | T2240 |
| Test name | |
| Test status | |
| Simulation time | 388440507 ps |
| CPU time | 29.77 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:18 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-7f24637a-77af-439d-ac48-27dc5ac907b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812107183 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_same_source.2812107183 |
| Directory | /workspace/5.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke.2992630086 |
| Short name | T1378 |
| Test name | |
| Test status | |
| Simulation time | 151546248 ps |
| CPU time | 7.4 seconds |
| Started | Aug 17 06:47:41 PM PDT 24 |
| Finished | Aug 17 06:47:48 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-25ea8233-f2b5-445b-a9f0-38080cd65672 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992630086 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke.2992630086 |
| Directory | /workspace/5.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_large_delays.2584253946 |
| Short name | T2523 |
| Test name | |
| Test status | |
| Simulation time | 8406178922 ps |
| CPU time | 85.37 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:49:13 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-b2b34f52-ce23-4f99-bab5-fb061077157b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584253946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_large_delays.2584253946 |
| Directory | /workspace/5.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_slow_rsp.3600143555 |
| Short name | T1878 |
| Test name | |
| Test status | |
| Simulation time | 5749474678 ps |
| CPU time | 93.94 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:49:24 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-19744fb3-2209-4bfa-88a8-03320cefdf8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600143555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_slow_rsp.3600143555 |
| Directory | /workspace/5.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_smoke_zero_delays.1717616366 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 49904366 ps |
| CPU time | 6.07 seconds |
| Started | Aug 17 06:47:59 PM PDT 24 |
| Finished | Aug 17 06:48:06 PM PDT 24 |
| Peak memory | 573332 kb |
| Host | smart-d703f176-15d3-45e3-95af-ba0d11ff4a83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717616366 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_smoke_zero_delays .1717616366 |
| Directory | /workspace/5.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all.3586374707 |
| Short name | T2157 |
| Test name | |
| Test status | |
| Simulation time | 2610226368 ps |
| CPU time | 202.6 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:51:07 PM PDT 24 |
| Peak memory | 575700 kb |
| Host | smart-2ab9858f-90dd-4ff4-81e5-afb500f41412 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586374707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all.3586374707 |
| Directory | /workspace/5.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_error.4202641712 |
| Short name | T1881 |
| Test name | |
| Test status | |
| Simulation time | 1702304069 ps |
| CPU time | 61.96 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:48:53 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-b3136ed2-67a4-45eb-962a-2212250d4aff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202641712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all_with_error.4202641712 |
| Directory | /workspace/5.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_stress_all_with_reset_error.2949940141 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2217707731 ps |
| CPU time | 305.11 seconds |
| Started | Aug 17 06:48:01 PM PDT 24 |
| Finished | Aug 17 06:53:06 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-be8eb0a5-4afe-427c-beb1-a43f01ba95fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949940141 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_stress_all _with_reset_error.2949940141 |
| Directory | /workspace/5.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/5.xbar_unmapped_addr.3175999756 |
| Short name | T1721 |
| Test name | |
| Test status | |
| Simulation time | 270009934 ps |
| CPU time | 12.43 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:47:56 PM PDT 24 |
| Peak memory | 575792 kb |
| Host | smart-33d99de6-a329-4428-ac23-a617720a3dc2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175999756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.xbar_unmapped_addr.3175999756 |
| Directory | /workspace/5.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device.330299367 |
| Short name | T2421 |
| Test name | |
| Test status | |
| Simulation time | 404458899 ps |
| CPU time | 35.31 seconds |
| Started | Aug 17 06:52:09 PM PDT 24 |
| Finished | Aug 17 06:52:45 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-39e996b6-13c4-4ad3-991c-b83f43f18f1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=330299367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_device. 330299367 |
| Directory | /workspace/50.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_access_same_device_slow_rsp.2951785833 |
| Short name | T2258 |
| Test name | |
| Test status | |
| Simulation time | 37795760410 ps |
| CPU time | 632.04 seconds |
| Started | Aug 17 06:52:01 PM PDT 24 |
| Finished | Aug 17 07:02:33 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-fcbf4bb2-8a01-46ab-8c17-ba4d572c591e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951785833 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_access_same_ device_slow_rsp.2951785833 |
| Directory | /workspace/50.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3267002099 |
| Short name | T2414 |
| Test name | |
| Test status | |
| Simulation time | 278525915 ps |
| CPU time | 33.11 seconds |
| Started | Aug 17 06:52:09 PM PDT 24 |
| Finished | Aug 17 06:52:42 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-5220ffd2-73a9-48e1-b664-1ea59754cfb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267002099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_and_unmapped_add r.3267002099 |
| Directory | /workspace/50.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_error_random.3910979174 |
| Short name | T1389 |
| Test name | |
| Test status | |
| Simulation time | 146483952 ps |
| CPU time | 14.06 seconds |
| Started | Aug 17 06:52:01 PM PDT 24 |
| Finished | Aug 17 06:52:15 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-50c1081f-149a-4783-b37d-01f8161ca9c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910979174 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_error_random.3910979174 |
| Directory | /workspace/50.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random.342825439 |
| Short name | T1906 |
| Test name | |
| Test status | |
| Simulation time | 190112286 ps |
| CPU time | 17.91 seconds |
| Started | Aug 17 06:52:04 PM PDT 24 |
| Finished | Aug 17 06:52:22 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-1904bb6b-26d5-46bc-b092-a5d597ee5eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342825439 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random.342825439 |
| Directory | /workspace/50.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_large_delays.1498146717 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 34182233811 ps |
| CPU time | 385.25 seconds |
| Started | Aug 17 06:52:03 PM PDT 24 |
| Finished | Aug 17 06:58:29 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-2baed752-91fe-4045-8f04-c39051bbf998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498146717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_large_delays.1498146717 |
| Directory | /workspace/50.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_slow_rsp.3331502229 |
| Short name | T2771 |
| Test name | |
| Test status | |
| Simulation time | 50561911173 ps |
| CPU time | 914.46 seconds |
| Started | Aug 17 06:52:02 PM PDT 24 |
| Finished | Aug 17 07:07:16 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-8730566f-1df8-4596-8bdb-26a2dcef990f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331502229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_slow_rsp.3331502229 |
| Directory | /workspace/50.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_random_zero_delays.1298875876 |
| Short name | T2391 |
| Test name | |
| Test status | |
| Simulation time | 618910527 ps |
| CPU time | 52.34 seconds |
| Started | Aug 17 06:52:02 PM PDT 24 |
| Finished | Aug 17 06:52:54 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-10db2cf9-bd60-45f5-8b5e-6aaea82e1d19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298875876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_random_zero_del ays.1298875876 |
| Directory | /workspace/50.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_same_source.591492071 |
| Short name | T1920 |
| Test name | |
| Test status | |
| Simulation time | 2536805931 ps |
| CPU time | 77.26 seconds |
| Started | Aug 17 06:52:05 PM PDT 24 |
| Finished | Aug 17 06:53:22 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-6a28f96f-dc37-409c-8fae-9c278df0c65d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591492071 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_same_source.591492071 |
| Directory | /workspace/50.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke.3089355701 |
| Short name | T2343 |
| Test name | |
| Test status | |
| Simulation time | 233578685 ps |
| CPU time | 9.64 seconds |
| Started | Aug 17 06:51:57 PM PDT 24 |
| Finished | Aug 17 06:52:06 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-c508c7ee-b8aa-4f3a-932a-9729ce79468d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089355701 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke.3089355701 |
| Directory | /workspace/50.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_large_delays.4048385921 |
| Short name | T2152 |
| Test name | |
| Test status | |
| Simulation time | 9214095950 ps |
| CPU time | 92.93 seconds |
| Started | Aug 17 06:51:59 PM PDT 24 |
| Finished | Aug 17 06:53:32 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-96ee3d99-c126-48e9-bbae-7a96f31dae44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4048385921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_large_delays.4048385921 |
| Directory | /workspace/50.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_slow_rsp.840979766 |
| Short name | T2216 |
| Test name | |
| Test status | |
| Simulation time | 4065667698 ps |
| CPU time | 72.69 seconds |
| Started | Aug 17 06:51:56 PM PDT 24 |
| Finished | Aug 17 06:53:09 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-12dddb1a-f7a4-4294-aab1-66f65a88fc69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840979766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_slow_rsp.840979766 |
| Directory | /workspace/50.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_smoke_zero_delays.1182676421 |
| Short name | T1805 |
| Test name | |
| Test status | |
| Simulation time | 41118712 ps |
| CPU time | 5.75 seconds |
| Started | Aug 17 06:51:57 PM PDT 24 |
| Finished | Aug 17 06:52:03 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-e11e4a46-4c00-4742-b038-001070a7e101 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1182676421 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_smoke_zero_delay s.1182676421 |
| Directory | /workspace/50.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all.2804626607 |
| Short name | T1661 |
| Test name | |
| Test status | |
| Simulation time | 10539008171 ps |
| CPU time | 348.32 seconds |
| Started | Aug 17 06:52:03 PM PDT 24 |
| Finished | Aug 17 06:57:51 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-97f21522-66e4-4992-a749-486d4cdb6fe9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804626607 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all.2804626607 |
| Directory | /workspace/50.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_error.485153017 |
| Short name | T2601 |
| Test name | |
| Test status | |
| Simulation time | 1138933708 ps |
| CPU time | 94.63 seconds |
| Started | Aug 17 06:52:03 PM PDT 24 |
| Finished | Aug 17 06:53:37 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-3d390a3a-a248-432d-9a4e-e83721afe8ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485153017 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all_with_error.485153017 |
| Directory | /workspace/50.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_stress_all_with_reset_error.505633969 |
| Short name | T1637 |
| Test name | |
| Test status | |
| Simulation time | 260988831 ps |
| CPU time | 54.58 seconds |
| Started | Aug 17 06:52:09 PM PDT 24 |
| Finished | Aug 17 06:53:04 PM PDT 24 |
| Peak memory | 576096 kb |
| Host | smart-e5546371-0985-45b8-bd20-d57e55912015 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505633969 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_stress_all _with_reset_error.505633969 |
| Directory | /workspace/50.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/50.xbar_unmapped_addr.1532057144 |
| Short name | T2356 |
| Test name | |
| Test status | |
| Simulation time | 1301483671 ps |
| CPU time | 57.53 seconds |
| Started | Aug 17 06:52:01 PM PDT 24 |
| Finished | Aug 17 06:52:59 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-517a745b-ee7a-48a5-854e-9dde00683529 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532057144 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 50.xbar_unmapped_addr.1532057144 |
| Directory | /workspace/50.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device.4022643453 |
| Short name | T2880 |
| Test name | |
| Test status | |
| Simulation time | 2982954544 ps |
| CPU time | 120.31 seconds |
| Started | Aug 17 06:52:08 PM PDT 24 |
| Finished | Aug 17 06:54:08 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-6eb6d4ed-09ef-478c-b36b-2f7bfe1d4688 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022643453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_device .4022643453 |
| Directory | /workspace/51.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.1245065567 |
| Short name | T1681 |
| Test name | |
| Test status | |
| Simulation time | 2409170177 ps |
| CPU time | 41.66 seconds |
| Started | Aug 17 06:52:09 PM PDT 24 |
| Finished | Aug 17 06:52:51 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-2c8b61a8-cff0-4776-83b3-4a9d61018a31 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245065567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_access_same_ device_slow_rsp.1245065567 |
| Directory | /workspace/51.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_and_unmapped_addr.2662929504 |
| Short name | T1931 |
| Test name | |
| Test status | |
| Simulation time | 192496489 ps |
| CPU time | 22.42 seconds |
| Started | Aug 17 06:52:13 PM PDT 24 |
| Finished | Aug 17 06:52:35 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-be91c672-74a9-4d7c-804b-8c07de3c4bef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662929504 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_and_unmapped_add r.2662929504 |
| Directory | /workspace/51.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_error_random.231912376 |
| Short name | T2450 |
| Test name | |
| Test status | |
| Simulation time | 399532233 ps |
| CPU time | 17.19 seconds |
| Started | Aug 17 06:52:12 PM PDT 24 |
| Finished | Aug 17 06:52:29 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-9a0e1465-5301-4c09-999d-68f6c13d40ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231912376 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_error_random.231912376 |
| Directory | /workspace/51.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random.612466971 |
| Short name | T2616 |
| Test name | |
| Test status | |
| Simulation time | 317535896 ps |
| CPU time | 27.32 seconds |
| Started | Aug 17 06:52:11 PM PDT 24 |
| Finished | Aug 17 06:52:38 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-cef25aeb-4f51-45e2-aa7c-1072bd3b3a26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612466971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random.612466971 |
| Directory | /workspace/51.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_large_delays.2731438320 |
| Short name | T2329 |
| Test name | |
| Test status | |
| Simulation time | 11725574904 ps |
| CPU time | 119.92 seconds |
| Started | Aug 17 06:52:10 PM PDT 24 |
| Finished | Aug 17 06:54:10 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-d63a404a-1cb8-4025-a73e-d914c210368d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731438320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_large_delays.2731438320 |
| Directory | /workspace/51.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.2603078808 |
| Short name | T2809 |
| Test name | |
| Test status | |
| Simulation time | 56988460510 ps |
| CPU time | 960.44 seconds |
| Started | Aug 17 06:52:11 PM PDT 24 |
| Finished | Aug 17 07:08:12 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-b1a46198-dcb7-4c0b-8527-c3de2179bb85 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2603078808 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_slow_rsp.2603078808 |
| Directory | /workspace/51.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_random_zero_delays.153137180 |
| Short name | T1491 |
| Test name | |
| Test status | |
| Simulation time | 415567020 ps |
| CPU time | 37.64 seconds |
| Started | Aug 17 06:52:10 PM PDT 24 |
| Finished | Aug 17 06:52:48 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c20da5a2-3017-4ba2-9d0e-ea529a92453c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153137180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_random_zero_dela ys.153137180 |
| Directory | /workspace/51.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_same_source.44652848 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 425095794 ps |
| CPU time | 27.85 seconds |
| Started | Aug 17 06:52:09 PM PDT 24 |
| Finished | Aug 17 06:52:37 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-a085e18d-6d4c-43ff-b400-e3eea3a3b1fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44652848 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_same_source.44652848 |
| Directory | /workspace/51.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke.1459454838 |
| Short name | T1723 |
| Test name | |
| Test status | |
| Simulation time | 267143978 ps |
| CPU time | 11.38 seconds |
| Started | Aug 17 06:52:11 PM PDT 24 |
| Finished | Aug 17 06:52:23 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-38e9a101-8558-4a62-88a3-fc759e542f06 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459454838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke.1459454838 |
| Directory | /workspace/51.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_large_delays.1483940076 |
| Short name | T1434 |
| Test name | |
| Test status | |
| Simulation time | 7766490491 ps |
| CPU time | 86.55 seconds |
| Started | Aug 17 06:52:13 PM PDT 24 |
| Finished | Aug 17 06:53:39 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-4d1f849b-a4dd-43a6-9948-5ad5dab23feb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1483940076 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_large_delays.1483940076 |
| Directory | /workspace/51.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_slow_rsp.1871078539 |
| Short name | T1890 |
| Test name | |
| Test status | |
| Simulation time | 5623943117 ps |
| CPU time | 97.87 seconds |
| Started | Aug 17 06:52:13 PM PDT 24 |
| Finished | Aug 17 06:53:51 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-10d64c08-414d-4daa-8660-f497fe8b5904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1871078539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_slow_rsp.1871078539 |
| Directory | /workspace/51.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_smoke_zero_delays.4253844923 |
| Short name | T2310 |
| Test name | |
| Test status | |
| Simulation time | 53309299 ps |
| CPU time | 6.02 seconds |
| Started | Aug 17 06:52:09 PM PDT 24 |
| Finished | Aug 17 06:52:15 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-46a6708f-f259-4329-a72d-b19ce48cdadb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253844923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_smoke_zero_delay s.4253844923 |
| Directory | /workspace/51.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all.1158339960 |
| Short name | T2656 |
| Test name | |
| Test status | |
| Simulation time | 5974932983 ps |
| CPU time | 223.63 seconds |
| Started | Aug 17 06:52:11 PM PDT 24 |
| Finished | Aug 17 06:55:55 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-82d4006b-4278-47be-a4eb-3572a870954f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158339960 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all.1158339960 |
| Directory | /workspace/51.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_error.2307627492 |
| Short name | T1424 |
| Test name | |
| Test status | |
| Simulation time | 3439141660 ps |
| CPU time | 120.19 seconds |
| Started | Aug 17 06:52:12 PM PDT 24 |
| Finished | Aug 17 06:54:12 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-f73bd57a-df61-4fdc-a4e8-64c0bfef0354 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307627492 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all_with_error.2307627492 |
| Directory | /workspace/51.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_rand_reset.3782015117 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 4781889735 ps |
| CPU time | 382.14 seconds |
| Started | Aug 17 06:52:10 PM PDT 24 |
| Finished | Aug 17 06:58:32 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-d8995228-11f8-45a7-91e4-a9b028fc496c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782015117 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_all _with_rand_reset.3782015117 |
| Directory | /workspace/51.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_stress_all_with_reset_error.1188880221 |
| Short name | T2641 |
| Test name | |
| Test status | |
| Simulation time | 1415490494 ps |
| CPU time | 273.38 seconds |
| Started | Aug 17 06:52:17 PM PDT 24 |
| Finished | Aug 17 06:56:51 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-ae19b59c-e07f-4f60-9cd5-24770e906abd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188880221 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_stress_al l_with_reset_error.1188880221 |
| Directory | /workspace/51.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/51.xbar_unmapped_addr.4026161063 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 717688968 ps |
| CPU time | 30.73 seconds |
| Started | Aug 17 06:52:10 PM PDT 24 |
| Finished | Aug 17 06:52:41 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-cf668eb8-058f-410b-9ca4-a99937d1aeb7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026161063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 51.xbar_unmapped_addr.4026161063 |
| Directory | /workspace/51.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device.2441222451 |
| Short name | T2785 |
| Test name | |
| Test status | |
| Simulation time | 1094558585 ps |
| CPU time | 71.89 seconds |
| Started | Aug 17 06:52:20 PM PDT 24 |
| Finished | Aug 17 06:53:31 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-b15f292d-9fc1-4f42-90dd-ae6900eadc18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441222451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_device .2441222451 |
| Directory | /workspace/52.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_access_same_device_slow_rsp.2926818134 |
| Short name | T2003 |
| Test name | |
| Test status | |
| Simulation time | 41403024303 ps |
| CPU time | 684.45 seconds |
| Started | Aug 17 06:52:17 PM PDT 24 |
| Finished | Aug 17 07:03:43 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-246ee10a-6264-411a-b8a1-8b2fa3b9d831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926818134 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_access_same_ device_slow_rsp.2926818134 |
| Directory | /workspace/52.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_and_unmapped_addr.3176401089 |
| Short name | T2313 |
| Test name | |
| Test status | |
| Simulation time | 592312679 ps |
| CPU time | 25.19 seconds |
| Started | Aug 17 06:52:19 PM PDT 24 |
| Finished | Aug 17 06:52:44 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-775c59ad-fc3b-44de-b76e-cad607e83d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176401089 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_and_unmapped_add r.3176401089 |
| Directory | /workspace/52.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_error_random.542783379 |
| Short name | T1438 |
| Test name | |
| Test status | |
| Simulation time | 1280246348 ps |
| CPU time | 41.52 seconds |
| Started | Aug 17 06:52:19 PM PDT 24 |
| Finished | Aug 17 06:53:01 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-210df727-bc44-480b-b1d8-dde3dd0b5bea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542783379 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_error_random.542783379 |
| Directory | /workspace/52.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random.2556439109 |
| Short name | T1599 |
| Test name | |
| Test status | |
| Simulation time | 519478284 ps |
| CPU time | 49.75 seconds |
| Started | Aug 17 06:52:19 PM PDT 24 |
| Finished | Aug 17 06:53:09 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-f59415c3-a083-46b0-b381-499c82f10acf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556439109 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random.2556439109 |
| Directory | /workspace/52.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_large_delays.3177336872 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 32739390030 ps |
| CPU time | 332.84 seconds |
| Started | Aug 17 06:52:16 PM PDT 24 |
| Finished | Aug 17 06:57:49 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-c97ce982-d704-4cb1-b071-a842c2341601 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177336872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_large_delays.3177336872 |
| Directory | /workspace/52.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_slow_rsp.260123305 |
| Short name | T1602 |
| Test name | |
| Test status | |
| Simulation time | 57370153835 ps |
| CPU time | 938.96 seconds |
| Started | Aug 17 06:52:19 PM PDT 24 |
| Finished | Aug 17 07:07:58 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-9e4b03eb-993f-4675-94aa-5178d7c1948d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260123305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_slow_rsp.260123305 |
| Directory | /workspace/52.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_random_zero_delays.20361143 |
| Short name | T2774 |
| Test name | |
| Test status | |
| Simulation time | 260648294 ps |
| CPU time | 21.66 seconds |
| Started | Aug 17 06:52:18 PM PDT 24 |
| Finished | Aug 17 06:52:40 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-fe6394b8-aec4-4d4e-be94-852be774474f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20361143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_random_zero_delay s.20361143 |
| Directory | /workspace/52.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_same_source.982757884 |
| Short name | T2057 |
| Test name | |
| Test status | |
| Simulation time | 1972522348 ps |
| CPU time | 60.5 seconds |
| Started | Aug 17 06:52:16 PM PDT 24 |
| Finished | Aug 17 06:53:17 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-8757a16b-e433-421c-8cf5-147c3391bdfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982757884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_same_source.982757884 |
| Directory | /workspace/52.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke.2260546466 |
| Short name | T2106 |
| Test name | |
| Test status | |
| Simulation time | 200250150 ps |
| CPU time | 9.02 seconds |
| Started | Aug 17 06:52:18 PM PDT 24 |
| Finished | Aug 17 06:52:27 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-9e8d0543-5481-42fc-992a-59631652b005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260546466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke.2260546466 |
| Directory | /workspace/52.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_large_delays.3119171839 |
| Short name | T2417 |
| Test name | |
| Test status | |
| Simulation time | 9875196481 ps |
| CPU time | 105.7 seconds |
| Started | Aug 17 06:52:19 PM PDT 24 |
| Finished | Aug 17 06:54:05 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-5ff06969-1890-4522-bc41-54a69f4cbd8d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119171839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_large_delays.3119171839 |
| Directory | /workspace/52.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_slow_rsp.1632753735 |
| Short name | T1957 |
| Test name | |
| Test status | |
| Simulation time | 5955125541 ps |
| CPU time | 97.91 seconds |
| Started | Aug 17 06:52:16 PM PDT 24 |
| Finished | Aug 17 06:53:54 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-c39b5b06-b4ae-4c4c-b3e2-aa64b7835f84 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1632753735 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_slow_rsp.1632753735 |
| Directory | /workspace/52.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_smoke_zero_delays.961735064 |
| Short name | T2795 |
| Test name | |
| Test status | |
| Simulation time | 39446263 ps |
| CPU time | 5.98 seconds |
| Started | Aug 17 06:52:17 PM PDT 24 |
| Finished | Aug 17 06:52:23 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-cc207201-a1fa-4f04-a704-40757362f90d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961735064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_smoke_zero_delays .961735064 |
| Directory | /workspace/52.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all.695366649 |
| Short name | T2441 |
| Test name | |
| Test status | |
| Simulation time | 2063476801 ps |
| CPU time | 190.16 seconds |
| Started | Aug 17 06:52:18 PM PDT 24 |
| Finished | Aug 17 06:55:28 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-b29aa3f3-e607-4aed-a843-5a9906dadf91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695366649 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all.695366649 |
| Directory | /workspace/52.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_error.4166080826 |
| Short name | T1996 |
| Test name | |
| Test status | |
| Simulation time | 1423827665 ps |
| CPU time | 115.91 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:54:22 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-fd5119bc-c1ef-4ea7-8dec-79363966f633 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166080826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all_with_error.4166080826 |
| Directory | /workspace/52.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_rand_reset.2852837096 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 175919438 ps |
| CPU time | 84.81 seconds |
| Started | Aug 17 06:52:30 PM PDT 24 |
| Finished | Aug 17 06:53:55 PM PDT 24 |
| Peak memory | 576312 kb |
| Host | smart-c64e1fed-177b-457d-8097-dd0b148d885a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852837096 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_all _with_rand_reset.2852837096 |
| Directory | /workspace/52.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.3770587218 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 68537656 ps |
| CPU time | 18.28 seconds |
| Started | Aug 17 06:52:23 PM PDT 24 |
| Finished | Aug 17 06:52:41 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-1862d7fd-f38a-491f-a2bd-ba78d4f190fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770587218 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_stress_al l_with_reset_error.3770587218 |
| Directory | /workspace/52.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/52.xbar_unmapped_addr.2978729311 |
| Short name | T2315 |
| Test name | |
| Test status | |
| Simulation time | 1376016937 ps |
| CPU time | 63.86 seconds |
| Started | Aug 17 06:52:17 PM PDT 24 |
| Finished | Aug 17 06:53:21 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-ef631512-acba-41e6-baa7-dc992f1ab4d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978729311 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 52.xbar_unmapped_addr.2978729311 |
| Directory | /workspace/52.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device.3508490798 |
| Short name | T2628 |
| Test name | |
| Test status | |
| Simulation time | 239596705 ps |
| CPU time | 26.43 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:52:53 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-48b841e5-2b72-4871-bb24-e57cb4ad2883 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508490798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_device .3508490798 |
| Directory | /workspace/53.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_access_same_device_slow_rsp.2807891305 |
| Short name | T2778 |
| Test name | |
| Test status | |
| Simulation time | 136330051536 ps |
| CPU time | 2462.2 seconds |
| Started | Aug 17 06:52:24 PM PDT 24 |
| Finished | Aug 17 07:33:26 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-fd696eef-fb8c-40eb-b348-3688725b8ae9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807891305 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_access_same_ device_slow_rsp.2807891305 |
| Directory | /workspace/53.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_and_unmapped_addr.442267997 |
| Short name | T2020 |
| Test name | |
| Test status | |
| Simulation time | 301570911 ps |
| CPU time | 25.59 seconds |
| Started | Aug 17 06:52:30 PM PDT 24 |
| Finished | Aug 17 06:52:56 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-5c4d2872-6222-44aa-9b76-8a4f1c850c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442267997 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_and_unmapped_addr .442267997 |
| Directory | /workspace/53.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_error_random.4037479498 |
| Short name | T1364 |
| Test name | |
| Test status | |
| Simulation time | 275021106 ps |
| CPU time | 22.15 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:52:48 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-751b0dec-f163-4d35-a7c6-5c1355af442e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037479498 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_error_random.4037479498 |
| Directory | /workspace/53.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random.1624053417 |
| Short name | T1605 |
| Test name | |
| Test status | |
| Simulation time | 469163586 ps |
| CPU time | 18.45 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:52:44 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-26ab69fb-fe1d-47da-b68d-0c93e9ab3c10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1624053417 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random.1624053417 |
| Directory | /workspace/53.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_large_delays.3461909796 |
| Short name | T2083 |
| Test name | |
| Test status | |
| Simulation time | 77211915823 ps |
| CPU time | 810.33 seconds |
| Started | Aug 17 06:52:24 PM PDT 24 |
| Finished | Aug 17 07:05:54 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-9f5a153a-e32c-498b-b090-c58da8d1b351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461909796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_large_delays.3461909796 |
| Directory | /workspace/53.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_slow_rsp.2646000250 |
| Short name | T2004 |
| Test name | |
| Test status | |
| Simulation time | 10660186791 ps |
| CPU time | 181.8 seconds |
| Started | Aug 17 06:52:23 PM PDT 24 |
| Finished | Aug 17 06:55:25 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-c880f2a7-ad0f-42f2-8f6e-9fe0eed18e41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2646000250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_slow_rsp.2646000250 |
| Directory | /workspace/53.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.3457975788 |
| Short name | T2606 |
| Test name | |
| Test status | |
| Simulation time | 159910124 ps |
| CPU time | 14.71 seconds |
| Started | Aug 17 06:52:28 PM PDT 24 |
| Finished | Aug 17 06:52:43 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-c29b9ac0-44b2-48f6-988a-45ba55c81371 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3457975788 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_random_zero_del ays.3457975788 |
| Directory | /workspace/53.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_same_source.4024761267 |
| Short name | T1402 |
| Test name | |
| Test status | |
| Simulation time | 105789915 ps |
| CPU time | 10.36 seconds |
| Started | Aug 17 06:52:24 PM PDT 24 |
| Finished | Aug 17 06:52:35 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-3b9e3a90-57ad-4070-8477-ce6d7618a0c8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024761267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_same_source.4024761267 |
| Directory | /workspace/53.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke.740964297 |
| Short name | T2603 |
| Test name | |
| Test status | |
| Simulation time | 211882014 ps |
| CPU time | 9.04 seconds |
| Started | Aug 17 06:52:25 PM PDT 24 |
| Finished | Aug 17 06:52:34 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-1e1bc902-e904-4b26-a7f9-7ca4e8b32009 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740964297 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke.740964297 |
| Directory | /workspace/53.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_large_delays.2440056972 |
| Short name | T2548 |
| Test name | |
| Test status | |
| Simulation time | 8277128849 ps |
| CPU time | 90.26 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:53:57 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-f2e412e2-22fc-48b6-b27a-4e0469bad580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2440056972 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_large_delays.2440056972 |
| Directory | /workspace/53.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_slow_rsp.1358355484 |
| Short name | T2836 |
| Test name | |
| Test status | |
| Simulation time | 5250857194 ps |
| CPU time | 90.72 seconds |
| Started | Aug 17 06:52:27 PM PDT 24 |
| Finished | Aug 17 06:53:58 PM PDT 24 |
| Peak memory | 574120 kb |
| Host | smart-87895c55-fb0d-4f87-803b-c62376afa8af |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358355484 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_slow_rsp.1358355484 |
| Directory | /workspace/53.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_smoke_zero_delays.2366376630 |
| Short name | T2141 |
| Test name | |
| Test status | |
| Simulation time | 50071834 ps |
| CPU time | 6.59 seconds |
| Started | Aug 17 06:52:23 PM PDT 24 |
| Finished | Aug 17 06:52:30 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-a9c03d2c-a210-4fec-a9f1-30196c139c26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366376630 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_smoke_zero_delay s.2366376630 |
| Directory | /workspace/53.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all.4191292264 |
| Short name | T1910 |
| Test name | |
| Test status | |
| Simulation time | 11778188914 ps |
| CPU time | 494.72 seconds |
| Started | Aug 17 06:52:30 PM PDT 24 |
| Finished | Aug 17 07:00:45 PM PDT 24 |
| Peak memory | 575808 kb |
| Host | smart-3c40e910-4972-4066-9580-b4a1655ff893 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191292264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all.4191292264 |
| Directory | /workspace/53.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_error.3061427075 |
| Short name | T2672 |
| Test name | |
| Test status | |
| Simulation time | 7628998818 ps |
| CPU time | 268.35 seconds |
| Started | Aug 17 06:52:25 PM PDT 24 |
| Finished | Aug 17 06:56:53 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-a8167325-7d71-456e-9099-e01e45a35e78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3061427075 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_all_with_error.3061427075 |
| Directory | /workspace/53.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_stress_all_with_reset_error.3158900508 |
| Short name | T2411 |
| Test name | |
| Test status | |
| Simulation time | 5650162399 ps |
| CPU time | 399.85 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:59:06 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-3e9d4e75-d05a-4761-9966-4c6e7d84ced5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158900508 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_stress_al l_with_reset_error.3158900508 |
| Directory | /workspace/53.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/53.xbar_unmapped_addr.4238292229 |
| Short name | T2701 |
| Test name | |
| Test status | |
| Simulation time | 461198517 ps |
| CPU time | 19.89 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:52:46 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-ec2af438-dbc1-4259-9ef9-ad7d0edf695a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238292229 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 53.xbar_unmapped_addr.4238292229 |
| Directory | /workspace/53.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device.2952918831 |
| Short name | T2825 |
| Test name | |
| Test status | |
| Simulation time | 3061587628 ps |
| CPU time | 115.44 seconds |
| Started | Aug 17 06:52:30 PM PDT 24 |
| Finished | Aug 17 06:54:25 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-91402816-9622-47f7-a060-75e50d0e302a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952918831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_device .2952918831 |
| Directory | /workspace/54.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_access_same_device_slow_rsp.2285054344 |
| Short name | T1701 |
| Test name | |
| Test status | |
| Simulation time | 126867661180 ps |
| CPU time | 2570.79 seconds |
| Started | Aug 17 06:52:31 PM PDT 24 |
| Finished | Aug 17 07:35:22 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-9340272c-4a96-4c66-bfaa-d1fb5efd2292 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285054344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_access_same_ device_slow_rsp.2285054344 |
| Directory | /workspace/54.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_and_unmapped_addr.61756838 |
| Short name | T2573 |
| Test name | |
| Test status | |
| Simulation time | 125373321 ps |
| CPU time | 13.81 seconds |
| Started | Aug 17 06:52:35 PM PDT 24 |
| Finished | Aug 17 06:52:49 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-ddf555a5-3ba2-4ba8-b425-a37a42634ade |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61756838 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_and_unmapped_addr.61756838 |
| Directory | /workspace/54.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_error_random.1696440926 |
| Short name | T1642 |
| Test name | |
| Test status | |
| Simulation time | 533088200 ps |
| CPU time | 21.8 seconds |
| Started | Aug 17 06:52:35 PM PDT 24 |
| Finished | Aug 17 06:52:57 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-354df282-f743-4b17-8284-a29a3890ad53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1696440926 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_error_random.1696440926 |
| Directory | /workspace/54.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random.180576621 |
| Short name | T1616 |
| Test name | |
| Test status | |
| Simulation time | 159501352 ps |
| CPU time | 16.14 seconds |
| Started | Aug 17 06:52:33 PM PDT 24 |
| Finished | Aug 17 06:52:49 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-7fab2dfd-d82f-4edf-a48f-01cc00c4698e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180576621 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random.180576621 |
| Directory | /workspace/54.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3998721835 |
| Short name | T1479 |
| Test name | |
| Test status | |
| Simulation time | 24797831999 ps |
| CPU time | 252.77 seconds |
| Started | Aug 17 06:52:32 PM PDT 24 |
| Finished | Aug 17 06:56:45 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-6d93d61f-0854-471f-8197-553a0673a725 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998721835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_large_delays.3998721835 |
| Directory | /workspace/54.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_slow_rsp.1545264832 |
| Short name | T1758 |
| Test name | |
| Test status | |
| Simulation time | 28974698199 ps |
| CPU time | 497.62 seconds |
| Started | Aug 17 06:52:31 PM PDT 24 |
| Finished | Aug 17 07:00:49 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-35deed40-1625-47b0-a064-5e93b61c7004 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545264832 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_slow_rsp.1545264832 |
| Directory | /workspace/54.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_random_zero_delays.189493337 |
| Short name | T2930 |
| Test name | |
| Test status | |
| Simulation time | 149486887 ps |
| CPU time | 18.35 seconds |
| Started | Aug 17 06:52:32 PM PDT 24 |
| Finished | Aug 17 06:52:50 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-a8a5b01c-3f48-4d59-95df-cf3cc9d79d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189493337 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_random_zero_dela ys.189493337 |
| Directory | /workspace/54.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_same_source.739482582 |
| Short name | T1628 |
| Test name | |
| Test status | |
| Simulation time | 222954040 ps |
| CPU time | 18.56 seconds |
| Started | Aug 17 06:52:33 PM PDT 24 |
| Finished | Aug 17 06:52:51 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-b594e326-6412-4e14-957a-a62c18ef2f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739482582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_same_source.739482582 |
| Directory | /workspace/54.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke.3454221517 |
| Short name | T2346 |
| Test name | |
| Test status | |
| Simulation time | 152411574 ps |
| CPU time | 6.97 seconds |
| Started | Aug 17 06:52:22 PM PDT 24 |
| Finished | Aug 17 06:52:29 PM PDT 24 |
| Peak memory | 573388 kb |
| Host | smart-93e49dcc-564b-424d-8699-1615f0b42034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454221517 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke.3454221517 |
| Directory | /workspace/54.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_large_delays.989244251 |
| Short name | T2639 |
| Test name | |
| Test status | |
| Simulation time | 9749182142 ps |
| CPU time | 96.6 seconds |
| Started | Aug 17 06:52:23 PM PDT 24 |
| Finished | Aug 17 06:54:00 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-9d3973f0-f6fd-42d8-b6aa-8dbe7743799b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989244251 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_large_delays.989244251 |
| Directory | /workspace/54.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_slow_rsp.3560931220 |
| Short name | T1826 |
| Test name | |
| Test status | |
| Simulation time | 4500913155 ps |
| CPU time | 72.75 seconds |
| Started | Aug 17 06:52:24 PM PDT 24 |
| Finished | Aug 17 06:53:37 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-55a5accd-0946-4a5f-9472-9fd10b7b76be |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560931220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_slow_rsp.3560931220 |
| Directory | /workspace/54.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_smoke_zero_delays.1708209178 |
| Short name | T1545 |
| Test name | |
| Test status | |
| Simulation time | 46344727 ps |
| CPU time | 6.25 seconds |
| Started | Aug 17 06:52:26 PM PDT 24 |
| Finished | Aug 17 06:52:32 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-4bb7b3b2-1d90-4660-85ab-f6afd6cc4a8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708209178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_smoke_zero_delay s.1708209178 |
| Directory | /workspace/54.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all.3961785 |
| Short name | T2374 |
| Test name | |
| Test status | |
| Simulation time | 943162665 ps |
| CPU time | 72.5 seconds |
| Started | Aug 17 06:52:32 PM PDT 24 |
| Finished | Aug 17 06:53:44 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-fdd6467c-e8d8-49ed-8a03-7d01bc9d09f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961785 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all.3961785 |
| Directory | /workspace/54.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_error.4242754309 |
| Short name | T1644 |
| Test name | |
| Test status | |
| Simulation time | 4722886006 ps |
| CPU time | 131.91 seconds |
| Started | Aug 17 06:52:31 PM PDT 24 |
| Finished | Aug 17 06:54:43 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-bf6175a7-9238-4cbe-ac0d-23dfe453f00a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242754309 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all_with_error.4242754309 |
| Directory | /workspace/54.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_rand_reset.3160251825 |
| Short name | T2153 |
| Test name | |
| Test status | |
| Simulation time | 766671677 ps |
| CPU time | 238.93 seconds |
| Started | Aug 17 06:52:31 PM PDT 24 |
| Finished | Aug 17 06:56:30 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-bee9aaf4-f845-49ba-b728-d85f2cdc5577 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3160251825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_all _with_rand_reset.3160251825 |
| Directory | /workspace/54.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_stress_all_with_reset_error.3710040041 |
| Short name | T2534 |
| Test name | |
| Test status | |
| Simulation time | 180892458 ps |
| CPU time | 101.17 seconds |
| Started | Aug 17 06:52:34 PM PDT 24 |
| Finished | Aug 17 06:54:15 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-41cad5d2-f470-49ad-9975-fea55d563071 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710040041 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_stress_al l_with_reset_error.3710040041 |
| Directory | /workspace/54.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1402612025 |
| Short name | T2403 |
| Test name | |
| Test status | |
| Simulation time | 226161617 ps |
| CPU time | 25.36 seconds |
| Started | Aug 17 06:52:33 PM PDT 24 |
| Finished | Aug 17 06:52:58 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-e43e34a9-248d-4644-ac1a-246228e85a12 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402612025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 54.xbar_unmapped_addr.1402612025 |
| Directory | /workspace/54.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device.2613406577 |
| Short name | T2714 |
| Test name | |
| Test status | |
| Simulation time | 1470135618 ps |
| CPU time | 87.39 seconds |
| Started | Aug 17 06:52:41 PM PDT 24 |
| Finished | Aug 17 06:54:09 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-07d96f6f-3840-4d5d-aba5-660355a504f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613406577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_device .2613406577 |
| Directory | /workspace/55.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_access_same_device_slow_rsp.410076435 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 125676941295 ps |
| CPU time | 2377.81 seconds |
| Started | Aug 17 06:52:39 PM PDT 24 |
| Finished | Aug 17 07:32:17 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-ebebdd2a-19b8-4f59-a1ac-a64069707420 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410076435 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_access_same_d evice_slow_rsp.410076435 |
| Directory | /workspace/55.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.1250959222 |
| Short name | T1783 |
| Test name | |
| Test status | |
| Simulation time | 1350829173 ps |
| CPU time | 54.08 seconds |
| Started | Aug 17 06:52:39 PM PDT 24 |
| Finished | Aug 17 06:53:33 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-9d0e8dc4-5bab-49b2-95c8-060b36c46c9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250959222 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_and_unmapped_add r.1250959222 |
| Directory | /workspace/55.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_error_random.1698322719 |
| Short name | T2516 |
| Test name | |
| Test status | |
| Simulation time | 1911486241 ps |
| CPU time | 61.69 seconds |
| Started | Aug 17 06:52:41 PM PDT 24 |
| Finished | Aug 17 06:53:43 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-abfd53c4-b101-43e2-8b50-63f204458b53 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698322719 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_error_random.1698322719 |
| Directory | /workspace/55.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random.81563064 |
| Short name | T2633 |
| Test name | |
| Test status | |
| Simulation time | 95089113 ps |
| CPU time | 11.67 seconds |
| Started | Aug 17 06:52:38 PM PDT 24 |
| Finished | Aug 17 06:52:50 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-5e481ecc-3aa8-442f-81c3-3308e571651b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81563064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random.81563064 |
| Directory | /workspace/55.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_large_delays.1068244063 |
| Short name | T1582 |
| Test name | |
| Test status | |
| Simulation time | 28749565772 ps |
| CPU time | 292.92 seconds |
| Started | Aug 17 06:52:42 PM PDT 24 |
| Finished | Aug 17 06:57:35 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-aece7d89-6a73-4d63-bea5-516a1e0ba034 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068244063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_large_delays.1068244063 |
| Directory | /workspace/55.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3382882582 |
| Short name | T1941 |
| Test name | |
| Test status | |
| Simulation time | 63205752277 ps |
| CPU time | 1052.02 seconds |
| Started | Aug 17 06:52:38 PM PDT 24 |
| Finished | Aug 17 07:10:11 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c8554268-f049-4055-b1d7-302b43884253 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382882582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_slow_rsp.3382882582 |
| Directory | /workspace/55.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.4238203707 |
| Short name | T2082 |
| Test name | |
| Test status | |
| Simulation time | 563778472 ps |
| CPU time | 51.73 seconds |
| Started | Aug 17 06:52:38 PM PDT 24 |
| Finished | Aug 17 06:53:30 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-7ae47435-a28f-4092-9df8-5aa3baa0f79a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238203707 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_random_zero_del ays.4238203707 |
| Directory | /workspace/55.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_same_source.1542494445 |
| Short name | T2749 |
| Test name | |
| Test status | |
| Simulation time | 947903203 ps |
| CPU time | 29.27 seconds |
| Started | Aug 17 06:52:37 PM PDT 24 |
| Finished | Aug 17 06:53:06 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-0727900d-69c8-4ebd-9792-945becafff6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542494445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_same_source.1542494445 |
| Directory | /workspace/55.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke.1451385303 |
| Short name | T2387 |
| Test name | |
| Test status | |
| Simulation time | 39201314 ps |
| CPU time | 6.08 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 06:52:52 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-e013c6e6-b496-41a5-86bf-1704ee9127f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451385303 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke.1451385303 |
| Directory | /workspace/55.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_large_delays.2175805558 |
| Short name | T1448 |
| Test name | |
| Test status | |
| Simulation time | 8736389972 ps |
| CPU time | 97.27 seconds |
| Started | Aug 17 06:52:39 PM PDT 24 |
| Finished | Aug 17 06:54:17 PM PDT 24 |
| Peak memory | 573576 kb |
| Host | smart-2443929c-905e-4615-b600-ff6a55d07580 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175805558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_large_delays.2175805558 |
| Directory | /workspace/55.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.2042524748 |
| Short name | T1636 |
| Test name | |
| Test status | |
| Simulation time | 7122190439 ps |
| CPU time | 118.31 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 06:54:44 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-6ec0a4b6-a62b-42b9-865d-7f0df2b57967 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042524748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_slow_rsp.2042524748 |
| Directory | /workspace/55.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_smoke_zero_delays.331219728 |
| Short name | T1646 |
| Test name | |
| Test status | |
| Simulation time | 47639019 ps |
| CPU time | 6.58 seconds |
| Started | Aug 17 06:52:38 PM PDT 24 |
| Finished | Aug 17 06:52:45 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-fcc06ba1-1390-4307-bd3a-2fb40244bf47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331219728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_smoke_zero_delays .331219728 |
| Directory | /workspace/55.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all.228412838 |
| Short name | T1932 |
| Test name | |
| Test status | |
| Simulation time | 14528934411 ps |
| CPU time | 548.46 seconds |
| Started | Aug 17 06:52:41 PM PDT 24 |
| Finished | Aug 17 07:01:50 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-511f9a0a-a855-4ef6-b871-dcc577a4cf92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228412838 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all.228412838 |
| Directory | /workspace/55.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_rand_reset.2934618670 |
| Short name | T2874 |
| Test name | |
| Test status | |
| Simulation time | 5747796702 ps |
| CPU time | 430.73 seconds |
| Started | Aug 17 06:52:40 PM PDT 24 |
| Finished | Aug 17 06:59:50 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-5b5f6365-6c2b-42d9-a5b2-91318011bcce |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934618670 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_rand_reset.2934618670 |
| Directory | /workspace/55.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_stress_all_with_reset_error.853010868 |
| Short name | T1987 |
| Test name | |
| Test status | |
| Simulation time | 545950409 ps |
| CPU time | 148.67 seconds |
| Started | Aug 17 06:52:42 PM PDT 24 |
| Finished | Aug 17 06:55:10 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-5ba1f017-2dc7-4592-9920-bb4d282c022d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853010868 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_stress_all _with_reset_error.853010868 |
| Directory | /workspace/55.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/55.xbar_unmapped_addr.831828996 |
| Short name | T2664 |
| Test name | |
| Test status | |
| Simulation time | 993074073 ps |
| CPU time | 40.88 seconds |
| Started | Aug 17 06:52:43 PM PDT 24 |
| Finished | Aug 17 06:53:24 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-82286a49-b21b-490c-bf28-757d93cb2bfa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831828996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 55.xbar_unmapped_addr.831828996 |
| Directory | /workspace/55.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device.3779546798 |
| Short name | T1518 |
| Test name | |
| Test status | |
| Simulation time | 2737982085 ps |
| CPU time | 125.29 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 06:54:51 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-9e4aa201-349e-4e16-ad8d-3c8f77c0c314 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3779546798 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_device .3779546798 |
| Directory | /workspace/56.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_access_same_device_slow_rsp.1981212018 |
| Short name | T2372 |
| Test name | |
| Test status | |
| Simulation time | 114482632877 ps |
| CPU time | 2025.05 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 07:26:32 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-0bc2f6a7-f716-435f-9789-b5809c3eed78 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981212018 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_access_same_ device_slow_rsp.1981212018 |
| Directory | /workspace/56.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_and_unmapped_addr.4009846822 |
| Short name | T2762 |
| Test name | |
| Test status | |
| Simulation time | 1083548822 ps |
| CPU time | 44.5 seconds |
| Started | Aug 17 06:52:47 PM PDT 24 |
| Finished | Aug 17 06:53:32 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-4c07757f-07df-486c-baf4-9f65065feca4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009846822 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_and_unmapped_add r.4009846822 |
| Directory | /workspace/56.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_error_random.3527321489 |
| Short name | T1365 |
| Test name | |
| Test status | |
| Simulation time | 139044581 ps |
| CPU time | 7.31 seconds |
| Started | Aug 17 06:52:49 PM PDT 24 |
| Finished | Aug 17 06:52:56 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-52c75e3c-9b31-47c8-bedb-3d7364326f71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527321489 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_error_random.3527321489 |
| Directory | /workspace/56.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random.1173193593 |
| Short name | T2634 |
| Test name | |
| Test status | |
| Simulation time | 701360721 ps |
| CPU time | 25.08 seconds |
| Started | Aug 17 06:52:43 PM PDT 24 |
| Finished | Aug 17 06:53:08 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-a0cf4495-82bb-4866-974c-372b942eab65 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173193593 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random.1173193593 |
| Directory | /workspace/56.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_large_delays.2486090442 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 12485164330 ps |
| CPU time | 133.89 seconds |
| Started | Aug 17 06:52:49 PM PDT 24 |
| Finished | Aug 17 06:55:03 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-f62a8a0b-9bd2-4401-9e11-e2193f27c224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486090442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_large_delays.2486090442 |
| Directory | /workspace/56.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_slow_rsp.4047391844 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 22834359195 ps |
| CPU time | 387.05 seconds |
| Started | Aug 17 06:52:49 PM PDT 24 |
| Finished | Aug 17 06:59:16 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-3535c680-3571-4049-b3ad-aeac09dd024c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4047391844 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_slow_rsp.4047391844 |
| Directory | /workspace/56.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_random_zero_delays.708164519 |
| Short name | T1862 |
| Test name | |
| Test status | |
| Simulation time | 161739641 ps |
| CPU time | 15.93 seconds |
| Started | Aug 17 06:52:53 PM PDT 24 |
| Finished | Aug 17 06:53:09 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-25a29646-af03-4ee7-b2e5-20b1d668649c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708164519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_random_zero_dela ys.708164519 |
| Directory | /workspace/56.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_same_source.3373223317 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 503782366 ps |
| CPU time | 38.57 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 06:53:24 PM PDT 24 |
| Peak memory | 575404 kb |
| Host | smart-36de3fa7-4bd7-4b42-a935-c44d34da7716 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373223317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_same_source.3373223317 |
| Directory | /workspace/56.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke.1218936120 |
| Short name | T2014 |
| Test name | |
| Test status | |
| Simulation time | 193954378 ps |
| CPU time | 8.24 seconds |
| Started | Aug 17 06:52:38 PM PDT 24 |
| Finished | Aug 17 06:52:47 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-b5e52c99-1ce3-44d0-b263-49692868b452 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1218936120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke.1218936120 |
| Directory | /workspace/56.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_large_delays.3840868953 |
| Short name | T1366 |
| Test name | |
| Test status | |
| Simulation time | 8800799972 ps |
| CPU time | 87.29 seconds |
| Started | Aug 17 06:52:38 PM PDT 24 |
| Finished | Aug 17 06:54:05 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-5c9f4b54-b4c4-47ee-a4dd-d68322ddb5a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840868953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_large_delays.3840868953 |
| Directory | /workspace/56.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.241995072 |
| Short name | T1458 |
| Test name | |
| Test status | |
| Simulation time | 4422269945 ps |
| CPU time | 71.35 seconds |
| Started | Aug 17 06:52:39 PM PDT 24 |
| Finished | Aug 17 06:53:50 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-46b45229-5646-4956-991f-974002a93b7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241995072 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_slow_rsp.241995072 |
| Directory | /workspace/56.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_smoke_zero_delays.2185557276 |
| Short name | T2863 |
| Test name | |
| Test status | |
| Simulation time | 52626627 ps |
| CPU time | 6.81 seconds |
| Started | Aug 17 06:52:37 PM PDT 24 |
| Finished | Aug 17 06:52:44 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-ff86c362-75fd-4d1c-9099-0acce992f2cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185557276 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_smoke_zero_delay s.2185557276 |
| Directory | /workspace/56.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all.3880588980 |
| Short name | T1689 |
| Test name | |
| Test status | |
| Simulation time | 2243981042 ps |
| CPU time | 67.32 seconds |
| Started | Aug 17 06:52:50 PM PDT 24 |
| Finished | Aug 17 06:53:58 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-9dcb7670-9b4b-4a4d-acd9-ede4f3ab3339 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880588980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all.3880588980 |
| Directory | /workspace/56.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_error.590454324 |
| Short name | T2154 |
| Test name | |
| Test status | |
| Simulation time | 764431304 ps |
| CPU time | 59.74 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 06:53:45 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-b93a51ec-fe55-49a6-9522-271549b04087 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590454324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all_with_error.590454324 |
| Directory | /workspace/56.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_stress_all_with_rand_reset.1321098414 |
| Short name | T2844 |
| Test name | |
| Test status | |
| Simulation time | 5984219040 ps |
| CPU time | 412.86 seconds |
| Started | Aug 17 06:52:50 PM PDT 24 |
| Finished | Aug 17 06:59:43 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-8637e4e1-d7ba-4a13-88b8-ee2232e46a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321098414 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_stress_all _with_rand_reset.1321098414 |
| Directory | /workspace/56.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.3822435615 |
| Short name | T2028 |
| Test name | |
| Test status | |
| Simulation time | 1310202543 ps |
| CPU time | 54.12 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 06:53:40 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-8d76faa3-9658-4e94-9491-7e6fd3c3d13d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822435615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 56.xbar_unmapped_addr.3822435615 |
| Directory | /workspace/56.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device.1194389234 |
| Short name | T1786 |
| Test name | |
| Test status | |
| Simulation time | 2307915477 ps |
| CPU time | 104.7 seconds |
| Started | Aug 17 06:52:56 PM PDT 24 |
| Finished | Aug 17 06:54:41 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-54f40e8f-e46d-4b5f-8287-4349f34652f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194389234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_device .1194389234 |
| Directory | /workspace/57.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.627945059 |
| Short name | T2424 |
| Test name | |
| Test status | |
| Simulation time | 159051869321 ps |
| CPU time | 2895.09 seconds |
| Started | Aug 17 06:52:59 PM PDT 24 |
| Finished | Aug 17 07:41:15 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ac5edb1e-2f93-4029-b8ad-d50c02c0fc0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627945059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_access_same_d evice_slow_rsp.627945059 |
| Directory | /workspace/57.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_and_unmapped_addr.1198441304 |
| Short name | T2496 |
| Test name | |
| Test status | |
| Simulation time | 165371233 ps |
| CPU time | 17.93 seconds |
| Started | Aug 17 06:53:00 PM PDT 24 |
| Finished | Aug 17 06:53:18 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-18693298-fd8a-4a73-8578-216d459e364d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1198441304 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_and_unmapped_add r.1198441304 |
| Directory | /workspace/57.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_error_random.424009454 |
| Short name | T2486 |
| Test name | |
| Test status | |
| Simulation time | 1544079988 ps |
| CPU time | 48.85 seconds |
| Started | Aug 17 06:52:56 PM PDT 24 |
| Finished | Aug 17 06:53:45 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-2d44220d-aa20-485a-bf88-d93d94ad2e26 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424009454 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_error_random.424009454 |
| Directory | /workspace/57.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random.3933805331 |
| Short name | T2901 |
| Test name | |
| Test status | |
| Simulation time | 81377561 ps |
| CPU time | 7.49 seconds |
| Started | Aug 17 06:52:54 PM PDT 24 |
| Finished | Aug 17 06:53:01 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-6dd3dd5f-9b52-418b-a286-7b5d2a548fd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933805331 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random.3933805331 |
| Directory | /workspace/57.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_large_delays.1433046731 |
| Short name | T2867 |
| Test name | |
| Test status | |
| Simulation time | 18391485738 ps |
| CPU time | 204.34 seconds |
| Started | Aug 17 06:52:55 PM PDT 24 |
| Finished | Aug 17 06:56:20 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-e63b828f-bc54-4d60-b1c6-ab0dcd0784cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433046731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_large_delays.1433046731 |
| Directory | /workspace/57.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_slow_rsp.651568667 |
| Short name | T2335 |
| Test name | |
| Test status | |
| Simulation time | 51015688739 ps |
| CPU time | 928.04 seconds |
| Started | Aug 17 06:52:55 PM PDT 24 |
| Finished | Aug 17 07:08:23 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-de75db01-9543-43b2-83ad-3b8492c8b1fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651568667 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_slow_rsp.651568667 |
| Directory | /workspace/57.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_random_zero_delays.521392178 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 577380852 ps |
| CPU time | 55.23 seconds |
| Started | Aug 17 06:52:56 PM PDT 24 |
| Finished | Aug 17 06:53:51 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-d3924371-1a89-4b68-9669-d16695b75378 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521392178 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_random_zero_dela ys.521392178 |
| Directory | /workspace/57.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_same_source.792267157 |
| Short name | T1374 |
| Test name | |
| Test status | |
| Simulation time | 320118630 ps |
| CPU time | 25.35 seconds |
| Started | Aug 17 06:52:55 PM PDT 24 |
| Finished | Aug 17 06:53:20 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-e88e956f-eef7-4776-b9c1-9a6dca415a40 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792267157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_same_source.792267157 |
| Directory | /workspace/57.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke.3503592438 |
| Short name | T2444 |
| Test name | |
| Test status | |
| Simulation time | 179845178 ps |
| CPU time | 8.32 seconds |
| Started | Aug 17 06:52:46 PM PDT 24 |
| Finished | Aug 17 06:52:54 PM PDT 24 |
| Peak memory | 574116 kb |
| Host | smart-d6e2eb02-01ce-4b5b-b4cb-532e76cea7cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503592438 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke.3503592438 |
| Directory | /workspace/57.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_large_delays.1949242539 |
| Short name | T2171 |
| Test name | |
| Test status | |
| Simulation time | 7004778193 ps |
| CPU time | 71.01 seconds |
| Started | Aug 17 06:52:47 PM PDT 24 |
| Finished | Aug 17 06:53:58 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-af03bcd6-5a64-41f5-9d06-430590307da8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949242539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_large_delays.1949242539 |
| Directory | /workspace/57.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.913150009 |
| Short name | T1698 |
| Test name | |
| Test status | |
| Simulation time | 7136460338 ps |
| CPU time | 116.97 seconds |
| Started | Aug 17 06:52:47 PM PDT 24 |
| Finished | Aug 17 06:54:44 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-c899757a-8859-44bb-850f-b862cffa2f33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913150009 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_slow_rsp.913150009 |
| Directory | /workspace/57.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_smoke_zero_delays.1630220025 |
| Short name | T1576 |
| Test name | |
| Test status | |
| Simulation time | 39811917 ps |
| CPU time | 6.29 seconds |
| Started | Aug 17 06:52:50 PM PDT 24 |
| Finished | Aug 17 06:52:56 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-4c53c471-52ee-4e46-92ce-d829d21b5c5f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630220025 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_smoke_zero_delay s.1630220025 |
| Directory | /workspace/57.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all.2813573065 |
| Short name | T2576 |
| Test name | |
| Test status | |
| Simulation time | 5285998794 ps |
| CPU time | 184.58 seconds |
| Started | Aug 17 06:52:54 PM PDT 24 |
| Finished | Aug 17 06:55:59 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-a3e8c413-9a97-4113-b65d-b343f61a6204 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813573065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all.2813573065 |
| Directory | /workspace/57.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_error.2662095637 |
| Short name | T2201 |
| Test name | |
| Test status | |
| Simulation time | 1297045498 ps |
| CPU time | 94.71 seconds |
| Started | Aug 17 06:52:57 PM PDT 24 |
| Finished | Aug 17 06:54:31 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-9a3c4a84-0e5d-4a95-b1f7-026f3f955eac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662095637 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all_with_error.2662095637 |
| Directory | /workspace/57.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_rand_reset.2487798884 |
| Short name | T1992 |
| Test name | |
| Test status | |
| Simulation time | 4694192027 ps |
| CPU time | 261.47 seconds |
| Started | Aug 17 06:53:00 PM PDT 24 |
| Finished | Aug 17 06:57:21 PM PDT 24 |
| Peak memory | 576384 kb |
| Host | smart-c3646603-79af-4f15-9aa0-b177520dd29b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487798884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_all _with_rand_reset.2487798884 |
| Directory | /workspace/57.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_stress_all_with_reset_error.3047097616 |
| Short name | T2134 |
| Test name | |
| Test status | |
| Simulation time | 9336750579 ps |
| CPU time | 550.89 seconds |
| Started | Aug 17 06:52:58 PM PDT 24 |
| Finished | Aug 17 07:02:09 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-512ba936-bb8e-47ad-967c-c69e4e74b8a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047097616 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_stress_al l_with_reset_error.3047097616 |
| Directory | /workspace/57.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/57.xbar_unmapped_addr.3157366728 |
| Short name | T2776 |
| Test name | |
| Test status | |
| Simulation time | 722114934 ps |
| CPU time | 30.08 seconds |
| Started | Aug 17 06:52:54 PM PDT 24 |
| Finished | Aug 17 06:53:24 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-cb7bd72b-9426-4b30-8779-e0bb9f6ba427 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157366728 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 57.xbar_unmapped_addr.3157366728 |
| Directory | /workspace/57.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device.2549406151 |
| Short name | T2339 |
| Test name | |
| Test status | |
| Simulation time | 368647620 ps |
| CPU time | 16.13 seconds |
| Started | Aug 17 06:52:59 PM PDT 24 |
| Finished | Aug 17 06:53:15 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-f3c28f33-1805-4e78-8009-90d3628a8379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549406151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_device .2549406151 |
| Directory | /workspace/58.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_access_same_device_slow_rsp.3659044256 |
| Short name | T2338 |
| Test name | |
| Test status | |
| Simulation time | 80065810400 ps |
| CPU time | 1507.45 seconds |
| Started | Aug 17 06:52:58 PM PDT 24 |
| Finished | Aug 17 07:18:06 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-40f83821-014d-4e29-ab7d-8beeeb256280 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659044256 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_access_same_ device_slow_rsp.3659044256 |
| Directory | /workspace/58.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_and_unmapped_addr.3186557289 |
| Short name | T2251 |
| Test name | |
| Test status | |
| Simulation time | 316660355 ps |
| CPU time | 13.25 seconds |
| Started | Aug 17 06:52:59 PM PDT 24 |
| Finished | Aug 17 06:53:13 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-5fb2f5d8-cd77-4248-80ef-adc41b4d5858 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186557289 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_and_unmapped_add r.3186557289 |
| Directory | /workspace/58.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_error_random.1680733603 |
| Short name | T1762 |
| Test name | |
| Test status | |
| Simulation time | 2455724720 ps |
| CPU time | 82.31 seconds |
| Started | Aug 17 06:52:57 PM PDT 24 |
| Finished | Aug 17 06:54:19 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-c9d869a7-ff46-4e40-8bd9-e60ea6f5a793 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680733603 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_error_random.1680733603 |
| Directory | /workspace/58.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random.2002836614 |
| Short name | T1597 |
| Test name | |
| Test status | |
| Simulation time | 1720846876 ps |
| CPU time | 52.18 seconds |
| Started | Aug 17 06:53:00 PM PDT 24 |
| Finished | Aug 17 06:53:52 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-535e70c5-6325-451f-aa5d-d300e91b238a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002836614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random.2002836614 |
| Directory | /workspace/58.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_large_delays.1984370220 |
| Short name | T1814 |
| Test name | |
| Test status | |
| Simulation time | 53347176440 ps |
| CPU time | 590.93 seconds |
| Started | Aug 17 06:52:54 PM PDT 24 |
| Finished | Aug 17 07:02:45 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-bcc827bd-8e2f-4757-b75c-23d59b6beadd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984370220 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_large_delays.1984370220 |
| Directory | /workspace/58.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_slow_rsp.259546880 |
| Short name | T2657 |
| Test name | |
| Test status | |
| Simulation time | 25636494922 ps |
| CPU time | 417.68 seconds |
| Started | Aug 17 06:52:58 PM PDT 24 |
| Finished | Aug 17 06:59:56 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-932c9811-8c2c-401e-92cd-19df5ad4952e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=259546880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_slow_rsp.259546880 |
| Directory | /workspace/58.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_random_zero_delays.2147160559 |
| Short name | T1703 |
| Test name | |
| Test status | |
| Simulation time | 254886779 ps |
| CPU time | 23.92 seconds |
| Started | Aug 17 06:52:56 PM PDT 24 |
| Finished | Aug 17 06:53:20 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-172f50bf-f52f-486e-8809-1a6d35cadbae |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147160559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_random_zero_del ays.2147160559 |
| Directory | /workspace/58.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_same_source.1850648760 |
| Short name | T1778 |
| Test name | |
| Test status | |
| Simulation time | 105558790 ps |
| CPU time | 10.63 seconds |
| Started | Aug 17 06:52:59 PM PDT 24 |
| Finished | Aug 17 06:53:09 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-b375c6a6-7af9-462c-b0e4-d66b10cbd6d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850648760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_same_source.1850648760 |
| Directory | /workspace/58.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke.4233116908 |
| Short name | T2198 |
| Test name | |
| Test status | |
| Simulation time | 147605598 ps |
| CPU time | 7.61 seconds |
| Started | Aug 17 06:52:56 PM PDT 24 |
| Finished | Aug 17 06:53:03 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-9956b12e-fd98-4663-8a73-4d4128d8131e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233116908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke.4233116908 |
| Directory | /workspace/58.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_large_delays.2048021893 |
| Short name | T2896 |
| Test name | |
| Test status | |
| Simulation time | 8714239410 ps |
| CPU time | 90.49 seconds |
| Started | Aug 17 06:52:56 PM PDT 24 |
| Finished | Aug 17 06:54:27 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-0b61f135-cbc2-43f9-9208-fc1f4404df6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048021893 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_large_delays.2048021893 |
| Directory | /workspace/58.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_slow_rsp.672872499 |
| Short name | T1985 |
| Test name | |
| Test status | |
| Simulation time | 7011731479 ps |
| CPU time | 115.31 seconds |
| Started | Aug 17 06:52:54 PM PDT 24 |
| Finished | Aug 17 06:54:49 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-a75cccc4-338f-45cf-ad2a-3897a40eefef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672872499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_slow_rsp.672872499 |
| Directory | /workspace/58.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.711713880 |
| Short name | T1387 |
| Test name | |
| Test status | |
| Simulation time | 42784286 ps |
| CPU time | 5.86 seconds |
| Started | Aug 17 06:52:59 PM PDT 24 |
| Finished | Aug 17 06:53:05 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-ab336c13-0dda-42d6-931e-4b879af50963 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711713880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_smoke_zero_delays .711713880 |
| Directory | /workspace/58.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all.889566923 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2453907604 ps |
| CPU time | 199.76 seconds |
| Started | Aug 17 06:53:02 PM PDT 24 |
| Finished | Aug 17 06:56:22 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-41c8e4d2-4836-4343-8c36-cd9338326b63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889566923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all.889566923 |
| Directory | /workspace/58.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3086423870 |
| Short name | T1546 |
| Test name | |
| Test status | |
| Simulation time | 8667304471 ps |
| CPU time | 307.26 seconds |
| Started | Aug 17 06:53:02 PM PDT 24 |
| Finished | Aug 17 06:58:09 PM PDT 24 |
| Peak memory | 575764 kb |
| Host | smart-f934dbe1-cc19-474c-a589-229752c60233 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086423870 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all_with_error.3086423870 |
| Directory | /workspace/58.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_rand_reset.2532029317 |
| Short name | T2712 |
| Test name | |
| Test status | |
| Simulation time | 2181168389 ps |
| CPU time | 384.73 seconds |
| Started | Aug 17 06:53:06 PM PDT 24 |
| Finished | Aug 17 06:59:31 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-ee25d258-c55a-4d44-a73d-16da700e85f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2532029317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_all _with_rand_reset.2532029317 |
| Directory | /workspace/58.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_stress_all_with_reset_error.1597841195 |
| Short name | T1567 |
| Test name | |
| Test status | |
| Simulation time | 4655951685 ps |
| CPU time | 242.98 seconds |
| Started | Aug 17 06:53:03 PM PDT 24 |
| Finished | Aug 17 06:57:06 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-ed5c6118-93d7-4d8a-9ed0-b784979dd11b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1597841195 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_stress_al l_with_reset_error.1597841195 |
| Directory | /workspace/58.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.1233941985 |
| Short name | T1547 |
| Test name | |
| Test status | |
| Simulation time | 243161473 ps |
| CPU time | 28.7 seconds |
| Started | Aug 17 06:53:06 PM PDT 24 |
| Finished | Aug 17 06:53:34 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-a9f32d1a-d763-4dfb-9889-946a5b4a38c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233941985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 58.xbar_unmapped_addr.1233941985 |
| Directory | /workspace/58.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device.364405258 |
| Short name | T2129 |
| Test name | |
| Test status | |
| Simulation time | 373111210 ps |
| CPU time | 16.24 seconds |
| Started | Aug 17 06:53:11 PM PDT 24 |
| Finished | Aug 17 06:53:27 PM PDT 24 |
| Peak memory | 575296 kb |
| Host | smart-11185921-a84a-49cc-985e-849039ac4484 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364405258 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_device. 364405258 |
| Directory | /workspace/59.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.3137947605 |
| Short name | T2554 |
| Test name | |
| Test status | |
| Simulation time | 124310883900 ps |
| CPU time | 2236.35 seconds |
| Started | Aug 17 06:53:06 PM PDT 24 |
| Finished | Aug 17 07:30:23 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-5c71201e-a770-4f95-b01c-423572e9da9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137947605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_access_same_ device_slow_rsp.3137947605 |
| Directory | /workspace/59.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_and_unmapped_addr.3718851002 |
| Short name | T2847 |
| Test name | |
| Test status | |
| Simulation time | 98289533 ps |
| CPU time | 12.56 seconds |
| Started | Aug 17 06:53:08 PM PDT 24 |
| Finished | Aug 17 06:53:20 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-2f871406-356f-49e0-b3a2-2cead447a464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718851002 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_and_unmapped_add r.3718851002 |
| Directory | /workspace/59.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_error_random.128947584 |
| Short name | T1381 |
| Test name | |
| Test status | |
| Simulation time | 293111252 ps |
| CPU time | 25.1 seconds |
| Started | Aug 17 06:53:10 PM PDT 24 |
| Finished | Aug 17 06:53:35 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-b52478e6-a824-47e4-bb26-9464b5854fbf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128947584 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_error_random.128947584 |
| Directory | /workspace/59.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random.2355839100 |
| Short name | T2006 |
| Test name | |
| Test status | |
| Simulation time | 1325212889 ps |
| CPU time | 46.6 seconds |
| Started | Aug 17 06:53:00 PM PDT 24 |
| Finished | Aug 17 06:53:46 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-f71b8619-3372-4141-bd01-67b45fbb03e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2355839100 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random.2355839100 |
| Directory | /workspace/59.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_large_delays.1327309470 |
| Short name | T1626 |
| Test name | |
| Test status | |
| Simulation time | 32221631607 ps |
| CPU time | 325.52 seconds |
| Started | Aug 17 06:53:07 PM PDT 24 |
| Finished | Aug 17 06:58:32 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-0902af2e-6efe-42e3-b3ad-ffab1baa0962 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327309470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_large_delays.1327309470 |
| Directory | /workspace/59.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_slow_rsp.3122676097 |
| Short name | T2137 |
| Test name | |
| Test status | |
| Simulation time | 44127726363 ps |
| CPU time | 774.15 seconds |
| Started | Aug 17 06:53:08 PM PDT 24 |
| Finished | Aug 17 07:06:03 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-ccf2f90e-c887-40e2-8a85-e17d98e209f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122676097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_slow_rsp.3122676097 |
| Directory | /workspace/59.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_random_zero_delays.4262323795 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 319843767 ps |
| CPU time | 28.87 seconds |
| Started | Aug 17 06:53:09 PM PDT 24 |
| Finished | Aug 17 06:53:38 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-3483630c-2b9d-4461-b07d-1426184e4a56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262323795 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_random_zero_del ays.4262323795 |
| Directory | /workspace/59.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_same_source.3414657710 |
| Short name | T2148 |
| Test name | |
| Test status | |
| Simulation time | 1524691727 ps |
| CPU time | 44.94 seconds |
| Started | Aug 17 06:53:11 PM PDT 24 |
| Finished | Aug 17 06:53:56 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-a3a8f4c0-9781-4b86-b0b8-7b432385ae0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414657710 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_same_source.3414657710 |
| Directory | /workspace/59.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke.3215496302 |
| Short name | T2791 |
| Test name | |
| Test status | |
| Simulation time | 252878220 ps |
| CPU time | 10.36 seconds |
| Started | Aug 17 06:53:02 PM PDT 24 |
| Finished | Aug 17 06:53:12 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-96fc0455-5ee0-403f-a378-83755876e910 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215496302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke.3215496302 |
| Directory | /workspace/59.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_large_delays.2238939729 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 9196951916 ps |
| CPU time | 99.54 seconds |
| Started | Aug 17 06:53:03 PM PDT 24 |
| Finished | Aug 17 06:54:43 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-4a351f6b-a812-4dca-bbe9-6a856b9e4c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238939729 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_large_delays.2238939729 |
| Directory | /workspace/59.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_slow_rsp.3128710064 |
| Short name | T1442 |
| Test name | |
| Test status | |
| Simulation time | 5076264918 ps |
| CPU time | 89.87 seconds |
| Started | Aug 17 06:53:02 PM PDT 24 |
| Finished | Aug 17 06:54:32 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-a685b726-133b-4ee4-a54c-52854ba537e9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128710064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_slow_rsp.3128710064 |
| Directory | /workspace/59.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_smoke_zero_delays.1875425982 |
| Short name | T1508 |
| Test name | |
| Test status | |
| Simulation time | 42364521 ps |
| CPU time | 6.03 seconds |
| Started | Aug 17 06:53:01 PM PDT 24 |
| Finished | Aug 17 06:53:07 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-bce822a4-6fc4-4676-a956-2b2235acbe5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875425982 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_smoke_zero_delay s.1875425982 |
| Directory | /workspace/59.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all.3867687926 |
| Short name | T1864 |
| Test name | |
| Test status | |
| Simulation time | 2250462935 ps |
| CPU time | 183.93 seconds |
| Started | Aug 17 06:53:08 PM PDT 24 |
| Finished | Aug 17 06:56:12 PM PDT 24 |
| Peak memory | 576444 kb |
| Host | smart-4de201cf-26af-4665-ba66-72b7d710bfea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867687926 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all.3867687926 |
| Directory | /workspace/59.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_error.767837023 |
| Short name | T2583 |
| Test name | |
| Test status | |
| Simulation time | 12366935238 ps |
| CPU time | 459.72 seconds |
| Started | Aug 17 06:53:16 PM PDT 24 |
| Finished | Aug 17 07:00:56 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-b82dbf3f-4619-47cb-95b2-ce7408cbd177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767837023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_with_error.767837023 |
| Directory | /workspace/59.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_rand_reset.521620783 |
| Short name | T2588 |
| Test name | |
| Test status | |
| Simulation time | 468821186 ps |
| CPU time | 269.27 seconds |
| Started | Aug 17 06:53:07 PM PDT 24 |
| Finished | Aug 17 06:57:37 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-ae8c3b59-56cb-428a-a4ce-eca40a6eb8c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=521620783 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_all_ with_rand_reset.521620783 |
| Directory | /workspace/59.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_stress_all_with_reset_error.3989976065 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 151551300 ps |
| CPU time | 44.27 seconds |
| Started | Aug 17 06:53:15 PM PDT 24 |
| Finished | Aug 17 06:54:00 PM PDT 24 |
| Peak memory | 575820 kb |
| Host | smart-adafa10a-4f41-456d-ba60-3f88cb76fea0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989976065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_stress_al l_with_reset_error.3989976065 |
| Directory | /workspace/59.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/59.xbar_unmapped_addr.176146066 |
| Short name | T2042 |
| Test name | |
| Test status | |
| Simulation time | 1259444510 ps |
| CPU time | 49.72 seconds |
| Started | Aug 17 06:53:07 PM PDT 24 |
| Finished | Aug 17 06:53:57 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-b606ede3-7016-4e3e-bc91-3e7a66e08da0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176146066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 59.xbar_unmapped_addr.176146066 |
| Directory | /workspace/59.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_mem_rw_with_rand_reset.1859858669 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 11189610585 ps |
| CPU time | 954.53 seconds |
| Started | Aug 17 06:47:46 PM PDT 24 |
| Finished | Aug 17 07:03:40 PM PDT 24 |
| Peak memory | 652984 kb |
| Host | smart-47043591-a621-414a-bb62-e9f1daee08fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859858669 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 6.chip_csr_mem_rw_with_rand_reset.1859858669 |
| Directory | /workspace/6.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_csr_rw.972634949 |
| Short name | T2495 |
| Test name | |
| Test status | |
| Simulation time | 6469882664 ps |
| CPU time | 586.54 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:57:35 PM PDT 24 |
| Peak memory | 599172 kb |
| Host | smart-d40416b7-d7e3-4002-a5c7-8e9a5db3300b |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=972634949 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_csr_rw.972634949 |
| Directory | /workspace/6.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_same_csr_outstanding.3602746817 |
| Short name | T2862 |
| Test name | |
| Test status | |
| Simulation time | 15280957107 ps |
| CPU time | 1652.52 seconds |
| Started | Aug 17 06:47:41 PM PDT 24 |
| Finished | Aug 17 07:15:14 PM PDT 24 |
| Peak memory | 592964 kb |
| Host | smart-b9c50163-78e9-442e-a4a4-c983b6f11c09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3602746817 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 6.chip_same_csr_outstanding.3602746817 |
| Directory | /workspace/6.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/6.chip_tl_errors.2180261750 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 3678657593 ps |
| CPU time | 172.63 seconds |
| Started | Aug 17 06:47:40 PM PDT 24 |
| Finished | Aug 17 06:50:33 PM PDT 24 |
| Peak memory | 603908 kb |
| Host | smart-7238b220-0b92-44a2-9efe-9bfe5345ec80 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180261750 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.chip_tl_errors.2180261750 |
| Directory | /workspace/6.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device.3323610626 |
| Short name | T2575 |
| Test name | |
| Test status | |
| Simulation time | 399677468 ps |
| CPU time | 16.39 seconds |
| Started | Aug 17 06:47:46 PM PDT 24 |
| Finished | Aug 17 06:48:02 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-aae076bb-8f48-4c1c-a258-19bd8734f89d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323610626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_device. 3323610626 |
| Directory | /workspace/6.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_access_same_device_slow_rsp.1921661059 |
| Short name | T2926 |
| Test name | |
| Test status | |
| Simulation time | 133056738556 ps |
| CPU time | 2564.23 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 07:30:29 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-53fa8f6d-0cd8-4f56-b897-123afc9788ca |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921661059 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_access_same_d evice_slow_rsp.1921661059 |
| Directory | /workspace/6.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_and_unmapped_addr.260373372 |
| Short name | T1673 |
| Test name | |
| Test status | |
| Simulation time | 166862266 ps |
| CPU time | 15.61 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 06:47:55 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-83a1e918-2cfe-48da-8c0c-9c4780aae397 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=260373372 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_and_unmapped_addr. 260373372 |
| Directory | /workspace/6.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_error_random.4060061433 |
| Short name | T1733 |
| Test name | |
| Test status | |
| Simulation time | 1261449929 ps |
| CPU time | 44.69 seconds |
| Started | Aug 17 06:47:42 PM PDT 24 |
| Finished | Aug 17 06:48:27 PM PDT 24 |
| Peak memory | 575264 kb |
| Host | smart-7ef7c43f-19cb-4ee1-9a9c-b1f71a8f0a01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4060061433 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_error_random.4060061433 |
| Directory | /workspace/6.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random.961743737 |
| Short name | T2527 |
| Test name | |
| Test status | |
| Simulation time | 1595673904 ps |
| CPU time | 52.67 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:48:37 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-935d9b7e-4dd1-4573-9e16-db2e9e316e9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961743737 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random.961743737 |
| Directory | /workspace/6.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_large_delays.206888341 |
| Short name | T1524 |
| Test name | |
| Test status | |
| Simulation time | 77173688430 ps |
| CPU time | 809.61 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 07:01:09 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-b9e123ca-ae68-45ee-9967-2f141f9da381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206888341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_large_delays.206888341 |
| Directory | /workspace/6.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_slow_rsp.3971987098 |
| Short name | T2290 |
| Test name | |
| Test status | |
| Simulation time | 8126020632 ps |
| CPU time | 145.37 seconds |
| Started | Aug 17 06:47:38 PM PDT 24 |
| Finished | Aug 17 06:50:03 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-ab5640c5-dd80-423d-b659-5252e68a5d7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971987098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_slow_rsp.3971987098 |
| Directory | /workspace/6.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_random_zero_delays.3458270049 |
| Short name | T2544 |
| Test name | |
| Test status | |
| Simulation time | 304481137 ps |
| CPU time | 28.75 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:19 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f1558794-e223-49a4-b34e-738330fdb995 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3458270049 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_random_zero_dela ys.3458270049 |
| Directory | /workspace/6.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_same_source.3759922606 |
| Short name | T2793 |
| Test name | |
| Test status | |
| Simulation time | 436334953 ps |
| CPU time | 14.44 seconds |
| Started | Aug 17 06:47:43 PM PDT 24 |
| Finished | Aug 17 06:47:58 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-f4ed09ce-e725-48f4-8f3e-b6aa61b1023d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759922606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_same_source.3759922606 |
| Directory | /workspace/6.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke.1098015101 |
| Short name | T2892 |
| Test name | |
| Test status | |
| Simulation time | 213892685 ps |
| CPU time | 9.15 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:00 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-c462d702-e609-4721-96bd-9c83f99c3fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098015101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke.1098015101 |
| Directory | /workspace/6.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_large_delays.3697767014 |
| Short name | T1869 |
| Test name | |
| Test status | |
| Simulation time | 9452569610 ps |
| CPU time | 98.01 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:49:27 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-4e01b46c-9179-4865-a80c-3de6d1ef07f1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697767014 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_large_delays.3697767014 |
| Directory | /workspace/6.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_slow_rsp.2269497697 |
| Short name | T2367 |
| Test name | |
| Test status | |
| Simulation time | 4427585757 ps |
| CPU time | 72.7 seconds |
| Started | Aug 17 06:47:42 PM PDT 24 |
| Finished | Aug 17 06:48:54 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-b98475c7-4dab-4340-bc62-880947723848 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269497697 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_slow_rsp.2269497697 |
| Directory | /workspace/6.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_smoke_zero_delays.1791465884 |
| Short name | T2328 |
| Test name | |
| Test status | |
| Simulation time | 54569778 ps |
| CPU time | 6.3 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:47:56 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-428f94cf-37a9-4412-b009-6883e1af6c4b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791465884 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_smoke_zero_delays .1791465884 |
| Directory | /workspace/6.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all.1857199994 |
| Short name | T1945 |
| Test name | |
| Test status | |
| Simulation time | 10848204354 ps |
| CPU time | 403.5 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:54:28 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-f5982c22-c2c9-42b0-82e5-9b959380f735 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1857199994 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all.1857199994 |
| Directory | /workspace/6.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_error.4112514415 |
| Short name | T1718 |
| Test name | |
| Test status | |
| Simulation time | 885423079 ps |
| CPU time | 55.15 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:48:40 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-6f999079-de62-4cbb-9a65-c908ecf658b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112514415 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_with_error.4112514415 |
| Directory | /workspace/6.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_rand_reset.956102559 |
| Short name | T2034 |
| Test name | |
| Test status | |
| Simulation time | 876884003 ps |
| CPU time | 129.92 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 06:49:49 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-6ce81b86-37ee-4a7a-be40-ebf202eb169e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956102559 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all_w ith_rand_reset.956102559 |
| Directory | /workspace/6.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2056729922 |
| Short name | T1738 |
| Test name | |
| Test status | |
| Simulation time | 87687482 ps |
| CPU time | 14.71 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:48:04 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-9be29d04-572c-4441-b5ad-4cc734221909 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056729922 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_stress_all _with_reset_error.2056729922 |
| Directory | /workspace/6.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/6.xbar_unmapped_addr.1879491745 |
| Short name | T2065 |
| Test name | |
| Test status | |
| Simulation time | 182238760 ps |
| CPU time | 22.37 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 06:48:01 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-cf46593c-04cb-4b20-bf03-4be8d1b06b41 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879491745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.xbar_unmapped_addr.1879491745 |
| Directory | /workspace/6.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device.188832992 |
| Short name | T2246 |
| Test name | |
| Test status | |
| Simulation time | 2500709807 ps |
| CPU time | 111.69 seconds |
| Started | Aug 17 06:53:17 PM PDT 24 |
| Finished | Aug 17 06:55:09 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-c076dda6-fc0d-4b02-a90a-06d5448e5569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188832992 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_device. 188832992 |
| Directory | /workspace/60.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_access_same_device_slow_rsp.17609249 |
| Short name | T1867 |
| Test name | |
| Test status | |
| Simulation time | 53019245982 ps |
| CPU time | 896.44 seconds |
| Started | Aug 17 06:53:26 PM PDT 24 |
| Finished | Aug 17 07:08:22 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-068a268e-58df-40ef-945d-0a9ffad6469a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17609249 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_access_same_de vice_slow_rsp.17609249 |
| Directory | /workspace/60.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_and_unmapped_addr.3502612391 |
| Short name | T1423 |
| Test name | |
| Test status | |
| Simulation time | 1206281312 ps |
| CPU time | 47.43 seconds |
| Started | Aug 17 06:53:17 PM PDT 24 |
| Finished | Aug 17 06:54:04 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-8a40282d-00e7-4f1c-9915-cf5e38c59ddd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3502612391 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_and_unmapped_add r.3502612391 |
| Directory | /workspace/60.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_error_random.66338827 |
| Short name | T2117 |
| Test name | |
| Test status | |
| Simulation time | 1545930796 ps |
| CPU time | 48.97 seconds |
| Started | Aug 17 06:53:17 PM PDT 24 |
| Finished | Aug 17 06:54:06 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-d6164dee-b759-4504-ad23-40940b24bc07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66338827 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_error_random.66338827 |
| Directory | /workspace/60.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random.1680056643 |
| Short name | T1460 |
| Test name | |
| Test status | |
| Simulation time | 339740580 ps |
| CPU time | 14.84 seconds |
| Started | Aug 17 06:53:19 PM PDT 24 |
| Finished | Aug 17 06:53:34 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-352e2a65-e38b-4d06-9828-512d660d1c5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680056643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random.1680056643 |
| Directory | /workspace/60.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_large_delays.4063984089 |
| Short name | T2206 |
| Test name | |
| Test status | |
| Simulation time | 83835205531 ps |
| CPU time | 929.68 seconds |
| Started | Aug 17 06:53:18 PM PDT 24 |
| Finished | Aug 17 07:08:48 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-1acd657c-00a6-414b-b70a-5487cef582b2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063984089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_large_delays.4063984089 |
| Directory | /workspace/60.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_slow_rsp.1704106858 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 49787972867 ps |
| CPU time | 944.44 seconds |
| Started | Aug 17 06:53:26 PM PDT 24 |
| Finished | Aug 17 07:09:11 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-c8ac8bc5-3672-4504-b3eb-1b23cb3a0299 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704106858 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_slow_rsp.1704106858 |
| Directory | /workspace/60.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_random_zero_delays.4170324589 |
| Short name | T2067 |
| Test name | |
| Test status | |
| Simulation time | 38816047 ps |
| CPU time | 6.78 seconds |
| Started | Aug 17 06:53:18 PM PDT 24 |
| Finished | Aug 17 06:53:25 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-e0b02cca-5128-4043-bceb-ce458b038090 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170324589 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_random_zero_del ays.4170324589 |
| Directory | /workspace/60.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_same_source.1747725353 |
| Short name | T2814 |
| Test name | |
| Test status | |
| Simulation time | 456974220 ps |
| CPU time | 35.43 seconds |
| Started | Aug 17 06:53:16 PM PDT 24 |
| Finished | Aug 17 06:53:52 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-e97543c0-0580-4a74-9575-641bc5cba58e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1747725353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_same_source.1747725353 |
| Directory | /workspace/60.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke.1010442605 |
| Short name | T2415 |
| Test name | |
| Test status | |
| Simulation time | 167009388 ps |
| CPU time | 8.04 seconds |
| Started | Aug 17 06:53:21 PM PDT 24 |
| Finished | Aug 17 06:53:29 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-3b9dd7e7-3021-43b5-9966-44b7f8cd8665 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010442605 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke.1010442605 |
| Directory | /workspace/60.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_large_delays.414362770 |
| Short name | T1909 |
| Test name | |
| Test status | |
| Simulation time | 7623014140 ps |
| CPU time | 83.72 seconds |
| Started | Aug 17 06:53:21 PM PDT 24 |
| Finished | Aug 17 06:54:45 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-24d27968-e0a7-4af0-b7bf-9fbaec355ffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414362770 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_large_delays.414362770 |
| Directory | /workspace/60.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.628729773 |
| Short name | T2027 |
| Test name | |
| Test status | |
| Simulation time | 5422467420 ps |
| CPU time | 87.28 seconds |
| Started | Aug 17 06:53:21 PM PDT 24 |
| Finished | Aug 17 06:54:49 PM PDT 24 |
| Peak memory | 574132 kb |
| Host | smart-80408de7-d151-4f03-a034-c76409c2d032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628729773 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_slow_rsp.628729773 |
| Directory | /workspace/60.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.43689234 |
| Short name | T2118 |
| Test name | |
| Test status | |
| Simulation time | 45390970 ps |
| CPU time | 6.74 seconds |
| Started | Aug 17 06:53:18 PM PDT 24 |
| Finished | Aug 17 06:53:25 PM PDT 24 |
| Peak memory | 574072 kb |
| Host | smart-1719a8bf-542e-42f2-b1e2-5a5e57fe35f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43689234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_smoke_zero_delays.43689234 |
| Directory | /workspace/60.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all.3903763402 |
| Short name | T2322 |
| Test name | |
| Test status | |
| Simulation time | 12247432075 ps |
| CPU time | 476.49 seconds |
| Started | Aug 17 06:53:17 PM PDT 24 |
| Finished | Aug 17 07:01:14 PM PDT 24 |
| Peak memory | 576460 kb |
| Host | smart-7fbdf182-6c2f-4db5-a059-3718013d6da0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3903763402 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all.3903763402 |
| Directory | /workspace/60.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_error.254226335 |
| Short name | T2775 |
| Test name | |
| Test status | |
| Simulation time | 3618467862 ps |
| CPU time | 273.69 seconds |
| Started | Aug 17 06:53:25 PM PDT 24 |
| Finished | Aug 17 06:57:59 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-aa180aa4-4b6b-4833-8114-cb2ee99d9170 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254226335 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_with_error.254226335 |
| Directory | /workspace/60.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_rand_reset.526591796 |
| Short name | T2270 |
| Test name | |
| Test status | |
| Simulation time | 6783759874 ps |
| CPU time | 391.98 seconds |
| Started | Aug 17 06:53:16 PM PDT 24 |
| Finished | Aug 17 06:59:48 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-b5cec96e-a0ca-4f29-8d7a-4bfbb7d35ff7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=526591796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_all_ with_rand_reset.526591796 |
| Directory | /workspace/60.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_stress_all_with_reset_error.1261145449 |
| Short name | T1692 |
| Test name | |
| Test status | |
| Simulation time | 365946553 ps |
| CPU time | 163.3 seconds |
| Started | Aug 17 06:53:17 PM PDT 24 |
| Finished | Aug 17 06:56:00 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-6e3c4b9a-c2e8-4fd2-87f9-c8c4e10a7411 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261145449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_stress_al l_with_reset_error.1261145449 |
| Directory | /workspace/60.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.91160389 |
| Short name | T1828 |
| Test name | |
| Test status | |
| Simulation time | 969120002 ps |
| CPU time | 39.88 seconds |
| Started | Aug 17 06:53:26 PM PDT 24 |
| Finished | Aug 17 06:54:06 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-aa89739d-154c-4fb7-82bf-74a8dce1e4de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91160389 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 60.xbar_unmapped_addr.91160389 |
| Directory | /workspace/60.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_access_same_device.1568687135 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 2304274804 ps |
| CPU time | 91.31 seconds |
| Started | Aug 17 06:53:23 PM PDT 24 |
| Finished | Aug 17 06:54:55 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-4b6e801f-8048-4b64-9195-1c97b4c140e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1568687135 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_access_same_device .1568687135 |
| Directory | /workspace/61.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_and_unmapped_addr.3287498057 |
| Short name | T1799 |
| Test name | |
| Test status | |
| Simulation time | 609512763 ps |
| CPU time | 23.3 seconds |
| Started | Aug 17 06:53:26 PM PDT 24 |
| Finished | Aug 17 06:53:49 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-4165ee39-0869-4fc7-a106-3405bda0a13e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287498057 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_and_unmapped_add r.3287498057 |
| Directory | /workspace/61.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_error_random.84407629 |
| Short name | T2839 |
| Test name | |
| Test status | |
| Simulation time | 2540825236 ps |
| CPU time | 90.49 seconds |
| Started | Aug 17 06:53:23 PM PDT 24 |
| Finished | Aug 17 06:54:54 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-14b9bdda-3cb3-4d7d-b2dc-2831fc189b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84407629 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_error_random.84407629 |
| Directory | /workspace/61.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random.2153366646 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 539009733 ps |
| CPU time | 46.72 seconds |
| Started | Aug 17 06:53:22 PM PDT 24 |
| Finished | Aug 17 06:54:08 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-284ffdf7-805d-44bf-9f17-0dfd5b9b2483 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153366646 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random.2153366646 |
| Directory | /workspace/61.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_large_delays.2442018689 |
| Short name | T2485 |
| Test name | |
| Test status | |
| Simulation time | 11201240791 ps |
| CPU time | 119.38 seconds |
| Started | Aug 17 06:53:22 PM PDT 24 |
| Finished | Aug 17 06:55:22 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-e95d505d-cac8-4cb3-948c-e93e504a426a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442018689 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_large_delays.2442018689 |
| Directory | /workspace/61.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_slow_rsp.174544814 |
| Short name | T1674 |
| Test name | |
| Test status | |
| Simulation time | 31998149966 ps |
| CPU time | 533.95 seconds |
| Started | Aug 17 06:53:22 PM PDT 24 |
| Finished | Aug 17 07:02:16 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-9a7227d2-8728-4073-b9db-c9cfaf04e081 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174544814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_slow_rsp.174544814 |
| Directory | /workspace/61.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_random_zero_delays.3303544731 |
| Short name | T1946 |
| Test name | |
| Test status | |
| Simulation time | 45591026 ps |
| CPU time | 6.58 seconds |
| Started | Aug 17 06:53:23 PM PDT 24 |
| Finished | Aug 17 06:53:29 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-eba76f77-51ab-40c0-94df-0b3f93207555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303544731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_random_zero_del ays.3303544731 |
| Directory | /workspace/61.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_same_source.1921524364 |
| Short name | T2064 |
| Test name | |
| Test status | |
| Simulation time | 1798760361 ps |
| CPU time | 59.32 seconds |
| Started | Aug 17 06:53:24 PM PDT 24 |
| Finished | Aug 17 06:54:23 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-ef317cfa-b3e1-4bf6-82e4-18472730634c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1921524364 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_same_source.1921524364 |
| Directory | /workspace/61.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke.1214055028 |
| Short name | T2009 |
| Test name | |
| Test status | |
| Simulation time | 196947940 ps |
| CPU time | 9.28 seconds |
| Started | Aug 17 06:53:17 PM PDT 24 |
| Finished | Aug 17 06:53:26 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-9886b0e7-b664-4da0-960c-38ad673c3b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214055028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke.1214055028 |
| Directory | /workspace/61.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_large_delays.902451295 |
| Short name | T1843 |
| Test name | |
| Test status | |
| Simulation time | 8305195515 ps |
| CPU time | 84.17 seconds |
| Started | Aug 17 06:53:16 PM PDT 24 |
| Finished | Aug 17 06:54:41 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-95c17762-18fb-4bf0-82ff-acca43d4205f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902451295 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_large_delays.902451295 |
| Directory | /workspace/61.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_slow_rsp.709928608 |
| Short name | T2870 |
| Test name | |
| Test status | |
| Simulation time | 5388841021 ps |
| CPU time | 88.9 seconds |
| Started | Aug 17 06:53:22 PM PDT 24 |
| Finished | Aug 17 06:54:51 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-f5c2abfb-c1f6-40bc-a920-e4dec7d94cdb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709928608 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_slow_rsp.709928608 |
| Directory | /workspace/61.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_smoke_zero_delays.3182787441 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 55833141 ps |
| CPU time | 6.73 seconds |
| Started | Aug 17 06:53:17 PM PDT 24 |
| Finished | Aug 17 06:53:24 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-90c73684-c5b0-452c-a25f-f7bd2865523d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182787441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_smoke_zero_delay s.3182787441 |
| Directory | /workspace/61.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all.3700310539 |
| Short name | T2079 |
| Test name | |
| Test status | |
| Simulation time | 2787409551 ps |
| CPU time | 246.3 seconds |
| Started | Aug 17 06:53:24 PM PDT 24 |
| Finished | Aug 17 06:57:31 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-38e9d285-7734-4377-81ff-e77da9e88d33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700310539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all.3700310539 |
| Directory | /workspace/61.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_error.1917281968 |
| Short name | T2730 |
| Test name | |
| Test status | |
| Simulation time | 3289229097 ps |
| CPU time | 108.07 seconds |
| Started | Aug 17 06:53:22 PM PDT 24 |
| Finished | Aug 17 06:55:10 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-b8469835-7dbc-4983-800f-9b1bc250cb62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1917281968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_all_with_error.1917281968 |
| Directory | /workspace/61.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_stress_all_with_reset_error.1915184060 |
| Short name | T2138 |
| Test name | |
| Test status | |
| Simulation time | 211213390 ps |
| CPU time | 57.45 seconds |
| Started | Aug 17 06:53:24 PM PDT 24 |
| Finished | Aug 17 06:54:22 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-14fc6965-cbe7-4fa4-b5b1-15c13ecceab2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915184060 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_stress_al l_with_reset_error.1915184060 |
| Directory | /workspace/61.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/61.xbar_unmapped_addr.2952060993 |
| Short name | T2882 |
| Test name | |
| Test status | |
| Simulation time | 324397670 ps |
| CPU time | 34.07 seconds |
| Started | Aug 17 06:53:25 PM PDT 24 |
| Finished | Aug 17 06:53:59 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-acd48113-af32-470f-9a2b-6dd4be34d10a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952060993 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 61.xbar_unmapped_addr.2952060993 |
| Directory | /workspace/61.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device.231426594 |
| Short name | T2765 |
| Test name | |
| Test status | |
| Simulation time | 488144400 ps |
| CPU time | 21.04 seconds |
| Started | Aug 17 06:53:29 PM PDT 24 |
| Finished | Aug 17 06:53:50 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-2c755b8f-9a8e-4ce7-9264-b2f34116b09d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231426594 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_device. 231426594 |
| Directory | /workspace/62.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_access_same_device_slow_rsp.33939180 |
| Short name | T1517 |
| Test name | |
| Test status | |
| Simulation time | 38217679656 ps |
| CPU time | 675.5 seconds |
| Started | Aug 17 06:53:31 PM PDT 24 |
| Finished | Aug 17 07:04:46 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-beb3894f-6fc0-45a2-b3ad-ad8b8cb77df1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33939180 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_access_same_de vice_slow_rsp.33939180 |
| Directory | /workspace/62.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_and_unmapped_addr.163380687 |
| Short name | T2889 |
| Test name | |
| Test status | |
| Simulation time | 393959914 ps |
| CPU time | 17.28 seconds |
| Started | Aug 17 06:53:31 PM PDT 24 |
| Finished | Aug 17 06:53:49 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-2081061a-47c9-4914-adbf-25d3655aef77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=163380687 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_and_unmapped_addr .163380687 |
| Directory | /workspace/62.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_error_random.704875482 |
| Short name | T2163 |
| Test name | |
| Test status | |
| Simulation time | 368761830 ps |
| CPU time | 27.14 seconds |
| Started | Aug 17 06:53:31 PM PDT 24 |
| Finished | Aug 17 06:53:58 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-9ee7e8b4-f0cf-4755-af39-561fce69bcbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704875482 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_error_random.704875482 |
| Directory | /workspace/62.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random.849178485 |
| Short name | T2688 |
| Test name | |
| Test status | |
| Simulation time | 554947915 ps |
| CPU time | 44.86 seconds |
| Started | Aug 17 06:53:30 PM PDT 24 |
| Finished | Aug 17 06:54:15 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-89727f91-07f2-4047-a8a1-fea2e73d3ac9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=849178485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random.849178485 |
| Directory | /workspace/62.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_large_delays.1310673132 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 18604893652 ps |
| CPU time | 184.44 seconds |
| Started | Aug 17 06:53:31 PM PDT 24 |
| Finished | Aug 17 06:56:36 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-5413411a-597b-46e7-b9b1-01b2b5615c22 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310673132 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_large_delays.1310673132 |
| Directory | /workspace/62.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_slow_rsp.3533038640 |
| Short name | T1526 |
| Test name | |
| Test status | |
| Simulation time | 12468957800 ps |
| CPU time | 201.71 seconds |
| Started | Aug 17 06:53:33 PM PDT 24 |
| Finished | Aug 17 06:56:55 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-0cc682ec-b755-4ba5-9a31-f5ade247af48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533038640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_slow_rsp.3533038640 |
| Directory | /workspace/62.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_random_zero_delays.3278176426 |
| Short name | T1521 |
| Test name | |
| Test status | |
| Simulation time | 160171992 ps |
| CPU time | 16.71 seconds |
| Started | Aug 17 06:53:31 PM PDT 24 |
| Finished | Aug 17 06:53:47 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-8d5fb755-e355-4921-a0d2-01c40e045c93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278176426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_random_zero_del ays.3278176426 |
| Directory | /workspace/62.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_same_source.2942201866 |
| Short name | T2769 |
| Test name | |
| Test status | |
| Simulation time | 461339462 ps |
| CPU time | 34.24 seconds |
| Started | Aug 17 06:53:32 PM PDT 24 |
| Finished | Aug 17 06:54:07 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-890fad22-cf1f-4279-8991-c75df1f285c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2942201866 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_same_source.2942201866 |
| Directory | /workspace/62.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke.468056693 |
| Short name | T2816 |
| Test name | |
| Test status | |
| Simulation time | 190193337 ps |
| CPU time | 8.22 seconds |
| Started | Aug 17 06:53:24 PM PDT 24 |
| Finished | Aug 17 06:53:33 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-f0c77f37-e314-4eaf-8cd4-47fba80b3393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468056693 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke.468056693 |
| Directory | /workspace/62.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_large_delays.1474606826 |
| Short name | T2127 |
| Test name | |
| Test status | |
| Simulation time | 7601746104 ps |
| CPU time | 82.67 seconds |
| Started | Aug 17 06:53:30 PM PDT 24 |
| Finished | Aug 17 06:54:53 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-bfe9f557-d604-4c6e-bac4-225120617c0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474606826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_large_delays.1474606826 |
| Directory | /workspace/62.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_slow_rsp.1147451150 |
| Short name | T1806 |
| Test name | |
| Test status | |
| Simulation time | 5106001105 ps |
| CPU time | 89.48 seconds |
| Started | Aug 17 06:53:29 PM PDT 24 |
| Finished | Aug 17 06:54:59 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-998fde4a-e1c8-4b66-adb7-a1ff2317266b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147451150 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_slow_rsp.1147451150 |
| Directory | /workspace/62.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_smoke_zero_delays.3383560067 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 46333965 ps |
| CPU time | 6.32 seconds |
| Started | Aug 17 06:53:24 PM PDT 24 |
| Finished | Aug 17 06:53:30 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-9f4d1c89-8752-49a7-a5a3-6e5851d16f83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383560067 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_smoke_zero_delay s.3383560067 |
| Directory | /workspace/62.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all.2332384361 |
| Short name | T2607 |
| Test name | |
| Test status | |
| Simulation time | 2824521492 ps |
| CPU time | 231.91 seconds |
| Started | Aug 17 06:53:33 PM PDT 24 |
| Finished | Aug 17 06:57:25 PM PDT 24 |
| Peak memory | 576436 kb |
| Host | smart-7de9686a-56f7-49a0-9438-7f80e1079873 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332384361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all.2332384361 |
| Directory | /workspace/62.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.791128953 |
| Short name | T2931 |
| Test name | |
| Test status | |
| Simulation time | 8055661926 ps |
| CPU time | 331.9 seconds |
| Started | Aug 17 06:53:31 PM PDT 24 |
| Finished | Aug 17 06:59:03 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-3aaa5731-11a9-435d-9f12-8dcc6f2dc232 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791128953 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all_with_error.791128953 |
| Directory | /workspace/62.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_rand_reset.4011989124 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 352726193 ps |
| CPU time | 58.93 seconds |
| Started | Aug 17 06:53:32 PM PDT 24 |
| Finished | Aug 17 06:54:31 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-d745bb43-eea9-4b8d-b2a7-20dc7a4c299b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011989124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_all _with_rand_reset.4011989124 |
| Directory | /workspace/62.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.1636965967 |
| Short name | T1856 |
| Test name | |
| Test status | |
| Simulation time | 3330776609 ps |
| CPU time | 168.29 seconds |
| Started | Aug 17 06:53:39 PM PDT 24 |
| Finished | Aug 17 06:56:27 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-2dffd5ff-0bf4-44a4-b63e-2d84615a34f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1636965967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_stress_al l_with_reset_error.1636965967 |
| Directory | /workspace/62.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/62.xbar_unmapped_addr.1944738335 |
| Short name | T2267 |
| Test name | |
| Test status | |
| Simulation time | 1343601056 ps |
| CPU time | 51.99 seconds |
| Started | Aug 17 06:53:30 PM PDT 24 |
| Finished | Aug 17 06:54:22 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-e125e274-90bb-40ae-9b89-54aac0d0525e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944738335 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 62.xbar_unmapped_addr.1944738335 |
| Directory | /workspace/62.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_access_same_device_slow_rsp.1488280716 |
| Short name | T1505 |
| Test name | |
| Test status | |
| Simulation time | 9840258370 ps |
| CPU time | 167.96 seconds |
| Started | Aug 17 06:53:39 PM PDT 24 |
| Finished | Aug 17 06:56:27 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-324c5e73-9ab6-43c8-91f2-fd9dcca45e62 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488280716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_access_same_ device_slow_rsp.1488280716 |
| Directory | /workspace/63.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_and_unmapped_addr.3007981149 |
| Short name | T2209 |
| Test name | |
| Test status | |
| Simulation time | 1392705650 ps |
| CPU time | 52.07 seconds |
| Started | Aug 17 06:53:36 PM PDT 24 |
| Finished | Aug 17 06:54:28 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-61b1a8c2-0921-4acd-b8a8-eaa188456784 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007981149 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_and_unmapped_add r.3007981149 |
| Directory | /workspace/63.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_error_random.2570405190 |
| Short name | T1412 |
| Test name | |
| Test status | |
| Simulation time | 321558900 ps |
| CPU time | 12.66 seconds |
| Started | Aug 17 06:53:36 PM PDT 24 |
| Finished | Aug 17 06:53:49 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-1ed0a712-729c-4a3b-8c7d-6c200fd31315 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570405190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_error_random.2570405190 |
| Directory | /workspace/63.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random.7640291 |
| Short name | T2891 |
| Test name | |
| Test status | |
| Simulation time | 2091629936 ps |
| CPU time | 67.47 seconds |
| Started | Aug 17 06:53:42 PM PDT 24 |
| Finished | Aug 17 06:54:49 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-684712d3-d3e7-4774-acc3-3ade7554e5d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7640291 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random.7640291 |
| Directory | /workspace/63.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_large_delays.606728027 |
| Short name | T2214 |
| Test name | |
| Test status | |
| Simulation time | 57277149270 ps |
| CPU time | 616.14 seconds |
| Started | Aug 17 06:53:35 PM PDT 24 |
| Finished | Aug 17 07:03:52 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-c0bd00dd-a7aa-4def-b9c8-67a5bfaac9b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606728027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_large_delays.606728027 |
| Directory | /workspace/63.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_slow_rsp.3175787080 |
| Short name | T2308 |
| Test name | |
| Test status | |
| Simulation time | 63999162335 ps |
| CPU time | 1152.49 seconds |
| Started | Aug 17 06:53:38 PM PDT 24 |
| Finished | Aug 17 07:12:50 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-4ccaecd0-8e07-480a-9d47-09f581d2d6dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175787080 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_slow_rsp.3175787080 |
| Directory | /workspace/63.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_random_zero_delays.978834074 |
| Short name | T1880 |
| Test name | |
| Test status | |
| Simulation time | 437001521 ps |
| CPU time | 34.88 seconds |
| Started | Aug 17 06:53:42 PM PDT 24 |
| Finished | Aug 17 06:54:17 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-62f0c4dc-9149-4677-93ca-0630dd8a463e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978834074 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_random_zero_dela ys.978834074 |
| Directory | /workspace/63.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_same_source.2745196302 |
| Short name | T2846 |
| Test name | |
| Test status | |
| Simulation time | 426128624 ps |
| CPU time | 28.46 seconds |
| Started | Aug 17 06:53:39 PM PDT 24 |
| Finished | Aug 17 06:54:07 PM PDT 24 |
| Peak memory | 575372 kb |
| Host | smart-d5ea85be-7d4c-47ae-8a7c-ed65abd567d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745196302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_same_source.2745196302 |
| Directory | /workspace/63.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke.3984473762 |
| Short name | T2380 |
| Test name | |
| Test status | |
| Simulation time | 114582732 ps |
| CPU time | 6.7 seconds |
| Started | Aug 17 06:53:39 PM PDT 24 |
| Finished | Aug 17 06:53:46 PM PDT 24 |
| Peak memory | 574276 kb |
| Host | smart-9c66f567-0098-4237-a1ce-b4c6dc307d39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984473762 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke.3984473762 |
| Directory | /workspace/63.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_large_delays.3724699124 |
| Short name | T1720 |
| Test name | |
| Test status | |
| Simulation time | 9839477742 ps |
| CPU time | 99.52 seconds |
| Started | Aug 17 06:53:38 PM PDT 24 |
| Finished | Aug 17 06:55:18 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-05613504-f202-4091-b392-f111eb4ca1a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724699124 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_large_delays.3724699124 |
| Directory | /workspace/63.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_slow_rsp.2040219506 |
| Short name | T2139 |
| Test name | |
| Test status | |
| Simulation time | 4541228542 ps |
| CPU time | 77.28 seconds |
| Started | Aug 17 06:53:38 PM PDT 24 |
| Finished | Aug 17 06:54:55 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-39c9a05a-7822-456e-bb1c-011a7d7b47c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040219506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_slow_rsp.2040219506 |
| Directory | /workspace/63.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_smoke_zero_delays.615168786 |
| Short name | T1715 |
| Test name | |
| Test status | |
| Simulation time | 50042012 ps |
| CPU time | 6.09 seconds |
| Started | Aug 17 06:53:36 PM PDT 24 |
| Finished | Aug 17 06:53:42 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-63b5134c-77b1-48e7-a431-bd732ec650d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=615168786 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_smoke_zero_delays .615168786 |
| Directory | /workspace/63.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all.1676045107 |
| Short name | T2478 |
| Test name | |
| Test status | |
| Simulation time | 9946314416 ps |
| CPU time | 392.05 seconds |
| Started | Aug 17 06:53:36 PM PDT 24 |
| Finished | Aug 17 07:00:08 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-8e0c443e-10ad-4e3f-8623-6e10ceaace3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676045107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all.1676045107 |
| Directory | /workspace/63.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_error.2666030478 |
| Short name | T2234 |
| Test name | |
| Test status | |
| Simulation time | 3891362314 ps |
| CPU time | 132.96 seconds |
| Started | Aug 17 06:53:41 PM PDT 24 |
| Finished | Aug 17 06:55:54 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-ee0dfc5c-aa4a-41c4-96b6-176edfdbcdf4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666030478 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all_with_error.2666030478 |
| Directory | /workspace/63.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4091864880 |
| Short name | T2671 |
| Test name | |
| Test status | |
| Simulation time | 4094301748 ps |
| CPU time | 434.14 seconds |
| Started | Aug 17 06:53:36 PM PDT 24 |
| Finished | Aug 17 07:00:50 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-65913cd7-d7bf-4a5c-8e73-3037e700e980 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4091864880 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_rand_reset.4091864880 |
| Directory | /workspace/63.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_stress_all_with_reset_error.641344955 |
| Short name | T2563 |
| Test name | |
| Test status | |
| Simulation time | 20287735072 ps |
| CPU time | 1016.51 seconds |
| Started | Aug 17 06:53:38 PM PDT 24 |
| Finished | Aug 17 07:10:34 PM PDT 24 |
| Peak memory | 577540 kb |
| Host | smart-eedeedca-eecd-4812-8f7a-1a0a5a974286 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641344955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_stress_all _with_reset_error.641344955 |
| Directory | /workspace/63.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/63.xbar_unmapped_addr.3441856070 |
| Short name | T1425 |
| Test name | |
| Test status | |
| Simulation time | 113860489 ps |
| CPU time | 7.56 seconds |
| Started | Aug 17 06:53:36 PM PDT 24 |
| Finished | Aug 17 06:53:44 PM PDT 24 |
| Peak memory | 573620 kb |
| Host | smart-87f258fa-e63f-4022-a14b-9fa2e32dc307 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441856070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 63.xbar_unmapped_addr.3441856070 |
| Directory | /workspace/63.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device.2672908248 |
| Short name | T2796 |
| Test name | |
| Test status | |
| Simulation time | 722703711 ps |
| CPU time | 33.12 seconds |
| Started | Aug 17 06:53:50 PM PDT 24 |
| Finished | Aug 17 06:54:23 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-3506cf08-f424-4d27-8478-773be7894340 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672908248 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_device .2672908248 |
| Directory | /workspace/64.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_access_same_device_slow_rsp.464806842 |
| Short name | T1691 |
| Test name | |
| Test status | |
| Simulation time | 49426085969 ps |
| CPU time | 795.85 seconds |
| Started | Aug 17 06:53:44 PM PDT 24 |
| Finished | Aug 17 07:07:00 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-8a41dcb3-7bdb-402c-9f79-0ca95b0b50cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464806842 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_access_same_d evice_slow_rsp.464806842 |
| Directory | /workspace/64.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_and_unmapped_addr.693773444 |
| Short name | T1955 |
| Test name | |
| Test status | |
| Simulation time | 361525300 ps |
| CPU time | 13.99 seconds |
| Started | Aug 17 06:53:44 PM PDT 24 |
| Finished | Aug 17 06:53:58 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-e2b8f503-05c2-42b7-a045-dc64aee36293 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693773444 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_and_unmapped_addr .693773444 |
| Directory | /workspace/64.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_error_random.862719201 |
| Short name | T2858 |
| Test name | |
| Test status | |
| Simulation time | 731804898 ps |
| CPU time | 25.31 seconds |
| Started | Aug 17 06:53:44 PM PDT 24 |
| Finished | Aug 17 06:54:10 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-ec3b0051-3283-4390-8881-9cbd16904e9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862719201 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_error_random.862719201 |
| Directory | /workspace/64.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random.2647120483 |
| Short name | T2165 |
| Test name | |
| Test status | |
| Simulation time | 247467768 ps |
| CPU time | 19.97 seconds |
| Started | Aug 17 06:53:49 PM PDT 24 |
| Finished | Aug 17 06:54:09 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-1295d0b4-2f78-4e29-b800-2b5d0fd13df7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647120483 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random.2647120483 |
| Directory | /workspace/64.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_large_delays.39099396 |
| Short name | T1563 |
| Test name | |
| Test status | |
| Simulation time | 93496885715 ps |
| CPU time | 946.22 seconds |
| Started | Aug 17 06:53:54 PM PDT 24 |
| Finished | Aug 17 07:09:41 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c6c4b623-fc68-4e2a-abd0-4d9dd9fc1132 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39099396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_large_delays.39099396 |
| Directory | /workspace/64.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_slow_rsp.1165851782 |
| Short name | T1804 |
| Test name | |
| Test status | |
| Simulation time | 4827912145 ps |
| CPU time | 81.48 seconds |
| Started | Aug 17 06:53:45 PM PDT 24 |
| Finished | Aug 17 06:55:06 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-dbcdf366-a8ee-41e7-92bb-d15d610698ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165851782 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_slow_rsp.1165851782 |
| Directory | /workspace/64.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.2382944740 |
| Short name | T1959 |
| Test name | |
| Test status | |
| Simulation time | 230437863 ps |
| CPU time | 22.2 seconds |
| Started | Aug 17 06:53:45 PM PDT 24 |
| Finished | Aug 17 06:54:07 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-c2ee3206-241d-45d5-b47d-d3da93f0ebec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382944740 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_random_zero_del ays.2382944740 |
| Directory | /workspace/64.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_same_source.3212742011 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 542412425 ps |
| CPU time | 33.59 seconds |
| Started | Aug 17 06:53:49 PM PDT 24 |
| Finished | Aug 17 06:54:22 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-f9684990-85aa-4c6b-97e4-0ffed6105283 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212742011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_same_source.3212742011 |
| Directory | /workspace/64.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke.1454007984 |
| Short name | T1769 |
| Test name | |
| Test status | |
| Simulation time | 44541089 ps |
| CPU time | 6.12 seconds |
| Started | Aug 17 06:53:40 PM PDT 24 |
| Finished | Aug 17 06:53:46 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-c6f6084b-9109-4cdd-9d9c-c41e77042cea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454007984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke.1454007984 |
| Directory | /workspace/64.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_large_delays.113140986 |
| Short name | T2151 |
| Test name | |
| Test status | |
| Simulation time | 8848333440 ps |
| CPU time | 88.24 seconds |
| Started | Aug 17 06:53:45 PM PDT 24 |
| Finished | Aug 17 06:55:13 PM PDT 24 |
| Peak memory | 574164 kb |
| Host | smart-1489cad8-d597-4402-8693-62b45bab98a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=113140986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_large_delays.113140986 |
| Directory | /workspace/64.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_slow_rsp.2292645194 |
| Short name | T2596 |
| Test name | |
| Test status | |
| Simulation time | 4185103362 ps |
| CPU time | 64.87 seconds |
| Started | Aug 17 06:53:44 PM PDT 24 |
| Finished | Aug 17 06:54:49 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-17e719e9-95ae-4b44-9e02-6fdbacbd2949 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292645194 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_slow_rsp.2292645194 |
| Directory | /workspace/64.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_smoke_zero_delays.450180083 |
| Short name | T2038 |
| Test name | |
| Test status | |
| Simulation time | 39650112 ps |
| CPU time | 6.23 seconds |
| Started | Aug 17 06:53:39 PM PDT 24 |
| Finished | Aug 17 06:53:45 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-4b654303-838a-4198-a105-da3608938ac6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450180083 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_smoke_zero_delays .450180083 |
| Directory | /workspace/64.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all.982939569 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 1845006787 ps |
| CPU time | 161.72 seconds |
| Started | Aug 17 06:53:48 PM PDT 24 |
| Finished | Aug 17 06:56:29 PM PDT 24 |
| Peak memory | 576080 kb |
| Host | smart-ff038622-761e-4cbb-819a-64304f17b998 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982939569 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all.982939569 |
| Directory | /workspace/64.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_error.2476461370 |
| Short name | T2902 |
| Test name | |
| Test status | |
| Simulation time | 11264649520 ps |
| CPU time | 432.57 seconds |
| Started | Aug 17 06:53:44 PM PDT 24 |
| Finished | Aug 17 07:00:56 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-9a4f945d-395f-4609-b3b7-7c0d6e19366a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476461370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_with_error.2476461370 |
| Directory | /workspace/64.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_rand_reset.958281099 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 2707209427 ps |
| CPU time | 364.71 seconds |
| Started | Aug 17 06:53:46 PM PDT 24 |
| Finished | Aug 17 06:59:51 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-33bab13d-f538-4677-ac38-6bf2073473d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958281099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all_ with_rand_reset.958281099 |
| Directory | /workspace/64.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.278589909 |
| Short name | T2213 |
| Test name | |
| Test status | |
| Simulation time | 489386142 ps |
| CPU time | 63.68 seconds |
| Started | Aug 17 06:53:46 PM PDT 24 |
| Finished | Aug 17 06:54:49 PM PDT 24 |
| Peak memory | 576300 kb |
| Host | smart-d6bb885e-905d-41e2-86a9-f185d08ad28f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278589909 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_stress_all _with_reset_error.278589909 |
| Directory | /workspace/64.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/64.xbar_unmapped_addr.2251179923 |
| Short name | T2821 |
| Test name | |
| Test status | |
| Simulation time | 409663090 ps |
| CPU time | 19.94 seconds |
| Started | Aug 17 06:53:49 PM PDT 24 |
| Finished | Aug 17 06:54:09 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-a926cada-552c-4f0d-ab4f-00e2710331bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251179923 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 64.xbar_unmapped_addr.2251179923 |
| Directory | /workspace/64.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device.2820113160 |
| Short name | T1655 |
| Test name | |
| Test status | |
| Simulation time | 3347818154 ps |
| CPU time | 150.68 seconds |
| Started | Aug 17 06:53:51 PM PDT 24 |
| Finished | Aug 17 06:56:22 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-0a13bd7e-d568-4583-8f36-27a7c7f37b36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820113160 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_device .2820113160 |
| Directory | /workspace/65.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1956239415 |
| Short name | T1591 |
| Test name | |
| Test status | |
| Simulation time | 24698316973 ps |
| CPU time | 452.44 seconds |
| Started | Aug 17 06:53:50 PM PDT 24 |
| Finished | Aug 17 07:01:23 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-743a1413-7aa0-4bc1-af5c-003369cf2287 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956239415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_access_same_ device_slow_rsp.1956239415 |
| Directory | /workspace/65.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_and_unmapped_addr.829187300 |
| Short name | T1593 |
| Test name | |
| Test status | |
| Simulation time | 154537409 ps |
| CPU time | 16.96 seconds |
| Started | Aug 17 06:53:59 PM PDT 24 |
| Finished | Aug 17 06:54:16 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-49490c80-c3ed-48b3-9a2e-63d3046e1426 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829187300 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_and_unmapped_addr .829187300 |
| Directory | /workspace/65.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_error_random.3778328933 |
| Short name | T2754 |
| Test name | |
| Test status | |
| Simulation time | 1676144870 ps |
| CPU time | 53.09 seconds |
| Started | Aug 17 06:53:51 PM PDT 24 |
| Finished | Aug 17 06:54:45 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-5b36c178-8d8d-4609-a6e2-7ced6be24e76 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778328933 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_error_random.3778328933 |
| Directory | /workspace/65.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random.4158127442 |
| Short name | T1564 |
| Test name | |
| Test status | |
| Simulation time | 240162296 ps |
| CPU time | 20.57 seconds |
| Started | Aug 17 06:53:52 PM PDT 24 |
| Finished | Aug 17 06:54:13 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-80f9f220-e472-49e5-aed4-3d020c886416 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158127442 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random.4158127442 |
| Directory | /workspace/65.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_large_delays.2779505816 |
| Short name | T1598 |
| Test name | |
| Test status | |
| Simulation time | 42004108709 ps |
| CPU time | 426.64 seconds |
| Started | Aug 17 06:53:58 PM PDT 24 |
| Finished | Aug 17 07:01:05 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-1fa15820-b6c8-456f-9445-b0f283140a37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779505816 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_large_delays.2779505816 |
| Directory | /workspace/65.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_slow_rsp.3701555320 |
| Short name | T2464 |
| Test name | |
| Test status | |
| Simulation time | 37959753954 ps |
| CPU time | 650.36 seconds |
| Started | Aug 17 06:53:51 PM PDT 24 |
| Finished | Aug 17 07:04:42 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-e32f9fac-ed54-43ff-9c2c-8a78feb02393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3701555320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_slow_rsp.3701555320 |
| Directory | /workspace/65.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_random_zero_delays.3809073105 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 122613036 ps |
| CPU time | 14.42 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:54:11 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-128839a6-a6c4-4bf0-8df1-846a4ddf1e33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809073105 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_random_zero_del ays.3809073105 |
| Directory | /workspace/65.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_same_source.2138225948 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 300349540 ps |
| CPU time | 22.06 seconds |
| Started | Aug 17 06:53:59 PM PDT 24 |
| Finished | Aug 17 06:54:21 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-9a2d74d2-1a90-4dad-9e9f-6da9c39206de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138225948 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_same_source.2138225948 |
| Directory | /workspace/65.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke.817668344 |
| Short name | T1754 |
| Test name | |
| Test status | |
| Simulation time | 214159459 ps |
| CPU time | 9.12 seconds |
| Started | Aug 17 06:53:45 PM PDT 24 |
| Finished | Aug 17 06:53:55 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-b5df0770-a107-402d-9d31-642573b7ba03 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=817668344 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke.817668344 |
| Directory | /workspace/65.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_large_delays.1804410065 |
| Short name | T1533 |
| Test name | |
| Test status | |
| Simulation time | 6567340347 ps |
| CPU time | 66.47 seconds |
| Started | Aug 17 06:53:56 PM PDT 24 |
| Finished | Aug 17 06:55:03 PM PDT 24 |
| Peak memory | 574144 kb |
| Host | smart-8732a9f8-575e-46ff-8512-624b471c9c8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1804410065 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_large_delays.1804410065 |
| Directory | /workspace/65.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.3157543864 |
| Short name | T1883 |
| Test name | |
| Test status | |
| Simulation time | 4694184105 ps |
| CPU time | 76.28 seconds |
| Started | Aug 17 06:53:46 PM PDT 24 |
| Finished | Aug 17 06:55:03 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-f1b5bab2-aef0-41c0-bfc1-09a68761b019 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157543864 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_slow_rsp.3157543864 |
| Directory | /workspace/65.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.1691856619 |
| Short name | T2723 |
| Test name | |
| Test status | |
| Simulation time | 49692070 ps |
| CPU time | 6.41 seconds |
| Started | Aug 17 06:53:49 PM PDT 24 |
| Finished | Aug 17 06:53:55 PM PDT 24 |
| Peak memory | 573328 kb |
| Host | smart-8b6f4cf9-93e6-41f0-bede-1e6794fdaa09 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691856619 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_smoke_zero_delay s.1691856619 |
| Directory | /workspace/65.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all.2324712068 |
| Short name | T2287 |
| Test name | |
| Test status | |
| Simulation time | 556961277 ps |
| CPU time | 41.08 seconds |
| Started | Aug 17 06:53:52 PM PDT 24 |
| Finished | Aug 17 06:54:33 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-d8aa782a-dd56-41e9-86d2-156581618b77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324712068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all.2324712068 |
| Directory | /workspace/65.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1438297873 |
| Short name | T1539 |
| Test name | |
| Test status | |
| Simulation time | 5475302639 ps |
| CPU time | 176.2 seconds |
| Started | Aug 17 06:53:54 PM PDT 24 |
| Finished | Aug 17 06:56:50 PM PDT 24 |
| Peak memory | 575768 kb |
| Host | smart-e35ead3b-6112-4aaf-adde-82c73a5d2c7f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438297873 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all_with_error.1438297873 |
| Directory | /workspace/65.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_rand_reset.4093426801 |
| Short name | T1748 |
| Test name | |
| Test status | |
| Simulation time | 289982317 ps |
| CPU time | 133.87 seconds |
| Started | Aug 17 06:53:51 PM PDT 24 |
| Finished | Aug 17 06:56:05 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-e112186c-bfca-444b-8a20-0d363d54c559 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093426801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_all _with_rand_reset.4093426801 |
| Directory | /workspace/65.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_stress_all_with_reset_error.3907347200 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 208816500 ps |
| CPU time | 118.11 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:55:55 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-4c843488-7579-44ab-85d1-7306e928fe50 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907347200 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_stress_al l_with_reset_error.3907347200 |
| Directory | /workspace/65.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/65.xbar_unmapped_addr.1470150463 |
| Short name | T1933 |
| Test name | |
| Test status | |
| Simulation time | 93144452 ps |
| CPU time | 13.47 seconds |
| Started | Aug 17 06:53:53 PM PDT 24 |
| Finished | Aug 17 06:54:06 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-ac17a537-7d62-449d-8ad8-88387f2b7c1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470150463 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 65.xbar_unmapped_addr.1470150463 |
| Directory | /workspace/65.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device.2018198153 |
| Short name | T2609 |
| Test name | |
| Test status | |
| Simulation time | 3017806187 ps |
| CPU time | 132.87 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:56:10 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-88f77f41-22e8-442b-b608-8cb30f4c4282 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018198153 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_device .2018198153 |
| Directory | /workspace/66.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_access_same_device_slow_rsp.1126304260 |
| Short name | T1585 |
| Test name | |
| Test status | |
| Simulation time | 110111245574 ps |
| CPU time | 2112.68 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 07:29:10 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-7d6e04ed-3dfc-4cd7-a317-1626b446983d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126304260 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_access_same_ device_slow_rsp.1126304260 |
| Directory | /workspace/66.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_and_unmapped_addr.788840276 |
| Short name | T2849 |
| Test name | |
| Test status | |
| Simulation time | 177113443 ps |
| CPU time | 19.12 seconds |
| Started | Aug 17 06:53:58 PM PDT 24 |
| Finished | Aug 17 06:54:17 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-b7fb27c4-3261-4572-ac22-8cd5b94f566c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788840276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_and_unmapped_addr .788840276 |
| Directory | /workspace/66.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_error_random.492782013 |
| Short name | T2909 |
| Test name | |
| Test status | |
| Simulation time | 609495667 ps |
| CPU time | 20.67 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:54:18 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-5071bf28-1a9c-42fa-98fb-2734aab9e9c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492782013 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_error_random.492782013 |
| Directory | /workspace/66.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random.295368234 |
| Short name | T2281 |
| Test name | |
| Test status | |
| Simulation time | 1777671777 ps |
| CPU time | 66.21 seconds |
| Started | Aug 17 06:53:55 PM PDT 24 |
| Finished | Aug 17 06:55:01 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-0fc006e8-aafa-462a-858f-daaba45b9060 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295368234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random.295368234 |
| Directory | /workspace/66.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_large_delays.3805527674 |
| Short name | T2531 |
| Test name | |
| Test status | |
| Simulation time | 45630539539 ps |
| CPU time | 489.83 seconds |
| Started | Aug 17 06:53:53 PM PDT 24 |
| Finished | Aug 17 07:02:03 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-937b2868-b2d3-4405-b736-879f49ec31c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805527674 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_large_delays.3805527674 |
| Directory | /workspace/66.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_slow_rsp.26087084 |
| Short name | T2542 |
| Test name | |
| Test status | |
| Simulation time | 47893141900 ps |
| CPU time | 873.23 seconds |
| Started | Aug 17 06:53:58 PM PDT 24 |
| Finished | Aug 17 07:08:31 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-628d561c-da88-4baf-ba8e-5bfa6197d419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26087084 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_slow_rsp.26087084 |
| Directory | /workspace/66.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_random_zero_delays.3911469354 |
| Short name | T2597 |
| Test name | |
| Test status | |
| Simulation time | 298393933 ps |
| CPU time | 27.43 seconds |
| Started | Aug 17 06:53:52 PM PDT 24 |
| Finished | Aug 17 06:54:19 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-ddb2b634-d698-494f-858b-0c8e10d71d77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911469354 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_random_zero_del ays.3911469354 |
| Directory | /workspace/66.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_same_source.2924944088 |
| Short name | T2709 |
| Test name | |
| Test status | |
| Simulation time | 1571734316 ps |
| CPU time | 44.97 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:54:42 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-7461fdb4-3ff9-4bc1-8893-275f5b550da9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924944088 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_same_source.2924944088 |
| Directory | /workspace/66.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke.1992277035 |
| Short name | T2804 |
| Test name | |
| Test status | |
| Simulation time | 42298505 ps |
| CPU time | 5.88 seconds |
| Started | Aug 17 06:53:53 PM PDT 24 |
| Finished | Aug 17 06:53:59 PM PDT 24 |
| Peak memory | 573600 kb |
| Host | smart-fd5a7fc8-3a04-4488-942a-95bd91dbd5b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992277035 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke.1992277035 |
| Directory | /workspace/66.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_large_delays.1174776734 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 8342966902 ps |
| CPU time | 92.17 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:55:29 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-0dc64c69-78a7-4b41-9bd0-b4bbef8e9249 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174776734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_large_delays.1174776734 |
| Directory | /workspace/66.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_slow_rsp.1837985363 |
| Short name | T1766 |
| Test name | |
| Test status | |
| Simulation time | 4676951635 ps |
| CPU time | 78.06 seconds |
| Started | Aug 17 06:53:55 PM PDT 24 |
| Finished | Aug 17 06:55:13 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-b51214bc-7b82-49ac-a708-a7a4c9bf5542 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837985363 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_slow_rsp.1837985363 |
| Directory | /workspace/66.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_smoke_zero_delays.989098191 |
| Short name | T2370 |
| Test name | |
| Test status | |
| Simulation time | 54097636 ps |
| CPU time | 6.76 seconds |
| Started | Aug 17 06:53:50 PM PDT 24 |
| Finished | Aug 17 06:53:57 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-a3f3add2-5665-4691-82f9-16641d0be09f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989098191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_smoke_zero_delays .989098191 |
| Directory | /workspace/66.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all.2978935472 |
| Short name | T1904 |
| Test name | |
| Test status | |
| Simulation time | 360772151 ps |
| CPU time | 29.64 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:54:27 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-aa0a5a7f-a787-4b21-ab97-7484481ee5a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978935472 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all.2978935472 |
| Directory | /workspace/66.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_error.4285710894 |
| Short name | T2578 |
| Test name | |
| Test status | |
| Simulation time | 2703724803 ps |
| CPU time | 188.05 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:57:05 PM PDT 24 |
| Peak memory | 576020 kb |
| Host | smart-c08a6a2a-55a0-46d3-b86e-dbd90bef7915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285710894 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all_with_error.4285710894 |
| Directory | /workspace/66.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_rand_reset.2462925910 |
| Short name | T2515 |
| Test name | |
| Test status | |
| Simulation time | 94827708 ps |
| CPU time | 40.85 seconds |
| Started | Aug 17 06:53:55 PM PDT 24 |
| Finished | Aug 17 06:54:36 PM PDT 24 |
| Peak memory | 575740 kb |
| Host | smart-79182aed-48f6-4184-a45b-3d25f1b4bdad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462925910 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_all _with_rand_reset.2462925910 |
| Directory | /workspace/66.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_stress_all_with_reset_error.1243235447 |
| Short name | T2536 |
| Test name | |
| Test status | |
| Simulation time | 5955518638 ps |
| CPU time | 279.66 seconds |
| Started | Aug 17 06:53:58 PM PDT 24 |
| Finished | Aug 17 06:58:37 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-2c7de29d-c80d-42e7-b575-9c404925cb18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243235447 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_stress_al l_with_reset_error.1243235447 |
| Directory | /workspace/66.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.456311485 |
| Short name | T1907 |
| Test name | |
| Test status | |
| Simulation time | 318199153 ps |
| CPU time | 30.6 seconds |
| Started | Aug 17 06:53:56 PM PDT 24 |
| Finished | Aug 17 06:54:27 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-299aa397-bc8c-4879-b492-68f0beade025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456311485 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 66.xbar_unmapped_addr.456311485 |
| Directory | /workspace/66.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device.3622755760 |
| Short name | T1590 |
| Test name | |
| Test status | |
| Simulation time | 2375530296 ps |
| CPU time | 82.68 seconds |
| Started | Aug 17 06:54:06 PM PDT 24 |
| Finished | Aug 17 06:55:28 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-354e7e66-ce0e-4b3c-ad00-824f3c991f34 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622755760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_device .3622755760 |
| Directory | /workspace/67.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_access_same_device_slow_rsp.3795019576 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 75056880388 ps |
| CPU time | 1449.35 seconds |
| Started | Aug 17 06:54:06 PM PDT 24 |
| Finished | Aug 17 07:18:15 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-79353d69-35aa-451a-833a-4f518971f0d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795019576 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_access_same_ device_slow_rsp.3795019576 |
| Directory | /workspace/67.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_and_unmapped_addr.3828546190 |
| Short name | T1842 |
| Test name | |
| Test status | |
| Simulation time | 176748179 ps |
| CPU time | 18.66 seconds |
| Started | Aug 17 06:54:06 PM PDT 24 |
| Finished | Aug 17 06:54:25 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-e57fcc29-d780-491f-be43-3b30ec1db3a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828546190 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_and_unmapped_add r.3828546190 |
| Directory | /workspace/67.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_error_random.2701202086 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 2673302865 ps |
| CPU time | 96.1 seconds |
| Started | Aug 17 06:54:05 PM PDT 24 |
| Finished | Aug 17 06:55:41 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-6a1be36f-4fad-462a-8753-cdae4eab0393 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701202086 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_error_random.2701202086 |
| Directory | /workspace/67.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random.1021390934 |
| Short name | T1699 |
| Test name | |
| Test status | |
| Simulation time | 556555305 ps |
| CPU time | 23.4 seconds |
| Started | Aug 17 06:54:07 PM PDT 24 |
| Finished | Aug 17 06:54:30 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-7c7bf7e9-c19a-451b-bc73-50906fb3525c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021390934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random.1021390934 |
| Directory | /workspace/67.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_large_delays.869460338 |
| Short name | T2036 |
| Test name | |
| Test status | |
| Simulation time | 100253347259 ps |
| CPU time | 1134.13 seconds |
| Started | Aug 17 06:54:03 PM PDT 24 |
| Finished | Aug 17 07:12:58 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-41917067-8a26-43a1-9621-5bf7d15cacd2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869460338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_large_delays.869460338 |
| Directory | /workspace/67.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_slow_rsp.3943963614 |
| Short name | T1396 |
| Test name | |
| Test status | |
| Simulation time | 4645846262 ps |
| CPU time | 76.83 seconds |
| Started | Aug 17 06:54:10 PM PDT 24 |
| Finished | Aug 17 06:55:27 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-52755807-ef3e-4c74-8be3-5937dde4ef61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943963614 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_slow_rsp.3943963614 |
| Directory | /workspace/67.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_random_zero_delays.59968796 |
| Short name | T1461 |
| Test name | |
| Test status | |
| Simulation time | 338589639 ps |
| CPU time | 29.21 seconds |
| Started | Aug 17 06:54:05 PM PDT 24 |
| Finished | Aug 17 06:54:34 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-bd99242c-f138-416e-a860-d83f3f006495 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59968796 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_random_zero_delay s.59968796 |
| Directory | /workspace/67.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_same_source.1887978488 |
| Short name | T2212 |
| Test name | |
| Test status | |
| Simulation time | 2594668667 ps |
| CPU time | 71.28 seconds |
| Started | Aug 17 06:54:06 PM PDT 24 |
| Finished | Aug 17 06:55:17 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-15a6f4c7-837c-4160-9376-fca40d8337e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887978488 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_same_source.1887978488 |
| Directory | /workspace/67.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke.2742556341 |
| Short name | T2030 |
| Test name | |
| Test status | |
| Simulation time | 48945820 ps |
| CPU time | 6.47 seconds |
| Started | Aug 17 06:53:57 PM PDT 24 |
| Finished | Aug 17 06:54:03 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-1d56534a-1f5c-45fe-94d9-b87c5e4e5e23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2742556341 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke.2742556341 |
| Directory | /workspace/67.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_large_delays.2803161317 |
| Short name | T1377 |
| Test name | |
| Test status | |
| Simulation time | 7009201817 ps |
| CPU time | 73.51 seconds |
| Started | Aug 17 06:54:04 PM PDT 24 |
| Finished | Aug 17 06:55:17 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-36cb91fd-65da-4082-9ecc-2017b35c47d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803161317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_large_delays.2803161317 |
| Directory | /workspace/67.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_slow_rsp.1578579550 |
| Short name | T2135 |
| Test name | |
| Test status | |
| Simulation time | 4549924303 ps |
| CPU time | 77.52 seconds |
| Started | Aug 17 06:54:04 PM PDT 24 |
| Finished | Aug 17 06:55:22 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-711ed06b-acab-4825-9179-625e416d0729 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578579550 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_slow_rsp.1578579550 |
| Directory | /workspace/67.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_smoke_zero_delays.3723892243 |
| Short name | T2407 |
| Test name | |
| Test status | |
| Simulation time | 53924706 ps |
| CPU time | 6.74 seconds |
| Started | Aug 17 06:54:06 PM PDT 24 |
| Finished | Aug 17 06:54:12 PM PDT 24 |
| Peak memory | 574036 kb |
| Host | smart-81442b9e-98c6-4072-988b-61473195410c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723892243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_smoke_zero_delay s.3723892243 |
| Directory | /workspace/67.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all.1227067554 |
| Short name | T2646 |
| Test name | |
| Test status | |
| Simulation time | 2139926416 ps |
| CPU time | 172.05 seconds |
| Started | Aug 17 06:54:10 PM PDT 24 |
| Finished | Aug 17 06:57:02 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-cde2e5dd-1427-458d-891e-4eb221c2c8d7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1227067554 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all.1227067554 |
| Directory | /workspace/67.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_error.2277109818 |
| Short name | T1550 |
| Test name | |
| Test status | |
| Simulation time | 10253538489 ps |
| CPU time | 327.69 seconds |
| Started | Aug 17 06:54:13 PM PDT 24 |
| Finished | Aug 17 06:59:41 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-aa962a4b-db35-40f1-be32-32efb85cca44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277109818 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all_with_error.2277109818 |
| Directory | /workspace/67.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_rand_reset.1444168110 |
| Short name | T1543 |
| Test name | |
| Test status | |
| Simulation time | 113689691 ps |
| CPU time | 45.47 seconds |
| Started | Aug 17 06:54:11 PM PDT 24 |
| Finished | Aug 17 06:54:57 PM PDT 24 |
| Peak memory | 576200 kb |
| Host | smart-76e2ba54-4ceb-45e5-acc2-e70dc0004d4c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444168110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_all _with_rand_reset.1444168110 |
| Directory | /workspace/67.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_stress_all_with_reset_error.2142550450 |
| Short name | T1923 |
| Test name | |
| Test status | |
| Simulation time | 18829953885 ps |
| CPU time | 944.74 seconds |
| Started | Aug 17 06:54:12 PM PDT 24 |
| Finished | Aug 17 07:09:57 PM PDT 24 |
| Peak memory | 577432 kb |
| Host | smart-19e497f9-de71-4444-9afb-4c13c3501913 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142550450 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_stress_al l_with_reset_error.2142550450 |
| Directory | /workspace/67.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.3278097986 |
| Short name | T1650 |
| Test name | |
| Test status | |
| Simulation time | 216092773 ps |
| CPU time | 27.31 seconds |
| Started | Aug 17 06:54:04 PM PDT 24 |
| Finished | Aug 17 06:54:31 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-821a57ac-911b-4ea7-9f49-ac64ab1034fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278097986 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 67.xbar_unmapped_addr.3278097986 |
| Directory | /workspace/67.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device.1052407053 |
| Short name | T2288 |
| Test name | |
| Test status | |
| Simulation time | 1198203984 ps |
| CPU time | 52.55 seconds |
| Started | Aug 17 06:54:15 PM PDT 24 |
| Finished | Aug 17 06:55:07 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-a6b4144a-6f33-4b84-99a4-a94d1709d629 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052407053 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_device .1052407053 |
| Directory | /workspace/68.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_access_same_device_slow_rsp.1064095752 |
| Short name | T2503 |
| Test name | |
| Test status | |
| Simulation time | 63254402513 ps |
| CPU time | 1123.99 seconds |
| Started | Aug 17 06:54:14 PM PDT 24 |
| Finished | Aug 17 07:12:58 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-a56dfac7-bba3-42c5-80da-7eaa3f85fc6f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064095752 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_access_same_ device_slow_rsp.1064095752 |
| Directory | /workspace/68.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_and_unmapped_addr.1241839828 |
| Short name | T1571 |
| Test name | |
| Test status | |
| Simulation time | 639150249 ps |
| CPU time | 27.13 seconds |
| Started | Aug 17 06:54:25 PM PDT 24 |
| Finished | Aug 17 06:54:52 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-c23fd8bb-6319-4f58-bac2-67eaf2f7fd0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1241839828 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_and_unmapped_add r.1241839828 |
| Directory | /workspace/68.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_error_random.2516285276 |
| Short name | T1566 |
| Test name | |
| Test status | |
| Simulation time | 412272078 ps |
| CPU time | 15.29 seconds |
| Started | Aug 17 06:54:14 PM PDT 24 |
| Finished | Aug 17 06:54:30 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-d2fcaa54-b099-4ccb-a3f3-c539c4bcba2a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516285276 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_error_random.2516285276 |
| Directory | /workspace/68.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random.1617292535 |
| Short name | T2530 |
| Test name | |
| Test status | |
| Simulation time | 224265096 ps |
| CPU time | 20.53 seconds |
| Started | Aug 17 06:54:13 PM PDT 24 |
| Finished | Aug 17 06:54:34 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-c0537931-e90d-4624-a840-e77aae86d279 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1617292535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random.1617292535 |
| Directory | /workspace/68.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1273551110 |
| Short name | T2555 |
| Test name | |
| Test status | |
| Simulation time | 64979197266 ps |
| CPU time | 707.22 seconds |
| Started | Aug 17 06:54:11 PM PDT 24 |
| Finished | Aug 17 07:05:58 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-9b1e74ac-85e4-4871-8da3-1c2e96eb1eef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1273551110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_large_delays.1273551110 |
| Directory | /workspace/68.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_slow_rsp.877961969 |
| Short name | T2389 |
| Test name | |
| Test status | |
| Simulation time | 58229869966 ps |
| CPU time | 1068.96 seconds |
| Started | Aug 17 06:54:10 PM PDT 24 |
| Finished | Aug 17 07:12:00 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-586136bc-f8b4-49ea-be05-336c0f9b7755 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877961969 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_slow_rsp.877961969 |
| Directory | /workspace/68.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_random_zero_delays.915185092 |
| Short name | T2629 |
| Test name | |
| Test status | |
| Simulation time | 506939108 ps |
| CPU time | 42.04 seconds |
| Started | Aug 17 06:54:12 PM PDT 24 |
| Finished | Aug 17 06:54:54 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-646aea23-1cca-4266-9d59-4ec2c2d91be9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=915185092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_random_zero_dela ys.915185092 |
| Directory | /workspace/68.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_same_source.1788022294 |
| Short name | T1709 |
| Test name | |
| Test status | |
| Simulation time | 72525041 ps |
| CPU time | 7.77 seconds |
| Started | Aug 17 06:54:13 PM PDT 24 |
| Finished | Aug 17 06:54:21 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-2e1f31b6-0fee-4131-83a1-d080dd61f748 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788022294 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_same_source.1788022294 |
| Directory | /workspace/68.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke.2117211265 |
| Short name | T1763 |
| Test name | |
| Test status | |
| Simulation time | 209689718 ps |
| CPU time | 9.17 seconds |
| Started | Aug 17 06:54:10 PM PDT 24 |
| Finished | Aug 17 06:54:20 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-edff1c53-af86-44dc-a28b-f610daef5e92 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117211265 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke.2117211265 |
| Directory | /workspace/68.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_large_delays.2159167445 |
| Short name | T2259 |
| Test name | |
| Test status | |
| Simulation time | 5774894817 ps |
| CPU time | 61.61 seconds |
| Started | Aug 17 06:54:11 PM PDT 24 |
| Finished | Aug 17 06:55:13 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-01d9b7d4-3aaf-4a61-9fb0-be72512196bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2159167445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_large_delays.2159167445 |
| Directory | /workspace/68.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_slow_rsp.2113462868 |
| Short name | T1356 |
| Test name | |
| Test status | |
| Simulation time | 5154263682 ps |
| CPU time | 88.09 seconds |
| Started | Aug 17 06:54:12 PM PDT 24 |
| Finished | Aug 17 06:55:40 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-9e84e11b-ba06-4482-9cf1-4642bd43a9f6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2113462868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_slow_rsp.2113462868 |
| Directory | /workspace/68.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.2690692315 |
| Short name | T1837 |
| Test name | |
| Test status | |
| Simulation time | 49782775 ps |
| CPU time | 6.51 seconds |
| Started | Aug 17 06:54:09 PM PDT 24 |
| Finished | Aug 17 06:54:16 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-e5671780-4cf2-4b30-b272-5fade02221ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690692315 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_smoke_zero_delay s.2690692315 |
| Directory | /workspace/68.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all.1971919658 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 4618979432 ps |
| CPU time | 158.44 seconds |
| Started | Aug 17 06:54:26 PM PDT 24 |
| Finished | Aug 17 06:57:04 PM PDT 24 |
| Peak memory | 575988 kb |
| Host | smart-f1a71fa5-b743-45b5-9256-6299491396ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971919658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all.1971919658 |
| Directory | /workspace/68.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_error.1861839968 |
| Short name | T2469 |
| Test name | |
| Test status | |
| Simulation time | 4761847665 ps |
| CPU time | 399.38 seconds |
| Started | Aug 17 06:54:16 PM PDT 24 |
| Finished | Aug 17 07:00:56 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-8575ff16-d8b7-4765-a0ae-f13a8330e4c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861839968 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all_with_error.1861839968 |
| Directory | /workspace/68.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_rand_reset.2813759092 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 7734267297 ps |
| CPU time | 415.75 seconds |
| Started | Aug 17 06:54:20 PM PDT 24 |
| Finished | Aug 17 07:01:16 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-56c0918d-022c-4bb5-a65d-31c6aaa6841a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813759092 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_all _with_rand_reset.2813759092 |
| Directory | /workspace/68.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_stress_all_with_reset_error.2521992787 |
| Short name | T1967 |
| Test name | |
| Test status | |
| Simulation time | 959027155 ps |
| CPU time | 235.18 seconds |
| Started | Aug 17 06:54:17 PM PDT 24 |
| Finished | Aug 17 06:58:12 PM PDT 24 |
| Peak memory | 576336 kb |
| Host | smart-5749eb24-d051-4b0d-a552-64cb5475fdf5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521992787 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_stress_al l_with_reset_error.2521992787 |
| Directory | /workspace/68.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/68.xbar_unmapped_addr.3420270640 |
| Short name | T1579 |
| Test name | |
| Test status | |
| Simulation time | 218904189 ps |
| CPU time | 11.92 seconds |
| Started | Aug 17 06:54:17 PM PDT 24 |
| Finished | Aug 17 06:54:29 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-7107f649-cd66-4ec4-b075-282efaa80391 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420270640 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 68.xbar_unmapped_addr.3420270640 |
| Directory | /workspace/68.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device.1811069934 |
| Short name | T2252 |
| Test name | |
| Test status | |
| Simulation time | 77790988 ps |
| CPU time | 7.43 seconds |
| Started | Aug 17 06:54:30 PM PDT 24 |
| Finished | Aug 17 06:54:38 PM PDT 24 |
| Peak memory | 573396 kb |
| Host | smart-f2d5219f-a9cd-4bc2-8122-925c28382952 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811069934 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_device .1811069934 |
| Directory | /workspace/69.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_access_same_device_slow_rsp.746068912 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 114880826568 ps |
| CPU time | 2297.01 seconds |
| Started | Aug 17 06:54:26 PM PDT 24 |
| Finished | Aug 17 07:32:43 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-5fb3a6bd-56b8-44b6-9e8d-4360a409c4ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746068912 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_access_same_d evice_slow_rsp.746068912 |
| Directory | /workspace/69.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_and_unmapped_addr.3185742762 |
| Short name | T2242 |
| Test name | |
| Test status | |
| Simulation time | 351328620 ps |
| CPU time | 15.89 seconds |
| Started | Aug 17 06:54:30 PM PDT 24 |
| Finished | Aug 17 06:54:46 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-86b62782-63c1-4649-981f-79d60f559946 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3185742762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_and_unmapped_add r.3185742762 |
| Directory | /workspace/69.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_error_random.1684886985 |
| Short name | T1471 |
| Test name | |
| Test status | |
| Simulation time | 1379311263 ps |
| CPU time | 48.98 seconds |
| Started | Aug 17 06:54:24 PM PDT 24 |
| Finished | Aug 17 06:55:13 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-f3df8cbb-8533-4449-a0d0-27bba9c977ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684886985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_error_random.1684886985 |
| Directory | /workspace/69.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random.2202343449 |
| Short name | T1764 |
| Test name | |
| Test status | |
| Simulation time | 568268849 ps |
| CPU time | 20.05 seconds |
| Started | Aug 17 06:54:21 PM PDT 24 |
| Finished | Aug 17 06:54:41 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-57e3e56c-c620-40e1-8acd-8d4ce0b748e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202343449 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random.2202343449 |
| Directory | /workspace/69.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_large_delays.3875677944 |
| Short name | T1693 |
| Test name | |
| Test status | |
| Simulation time | 107793765687 ps |
| CPU time | 1100.89 seconds |
| Started | Aug 17 06:54:31 PM PDT 24 |
| Finished | Aug 17 07:12:52 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-2d64a5fc-ae4c-4653-b0eb-9aecee1ea6e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3875677944 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_large_delays.3875677944 |
| Directory | /workspace/69.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_slow_rsp.2332484494 |
| Short name | T2354 |
| Test name | |
| Test status | |
| Simulation time | 64119059855 ps |
| CPU time | 1079.57 seconds |
| Started | Aug 17 06:54:26 PM PDT 24 |
| Finished | Aug 17 07:12:26 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-becea7c5-3ed7-4572-849d-241244138191 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332484494 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_slow_rsp.2332484494 |
| Directory | /workspace/69.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_random_zero_delays.1509194486 |
| Short name | T2857 |
| Test name | |
| Test status | |
| Simulation time | 113075052 ps |
| CPU time | 12.69 seconds |
| Started | Aug 17 06:54:18 PM PDT 24 |
| Finished | Aug 17 06:54:31 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-c0c59850-939a-4032-a5b6-65f0af5a0aec |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509194486 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_random_zero_del ays.1509194486 |
| Directory | /workspace/69.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_same_source.3939704011 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 1454026209 ps |
| CPU time | 42.4 seconds |
| Started | Aug 17 06:54:27 PM PDT 24 |
| Finished | Aug 17 06:55:09 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c4738830-7287-4d5e-a3b9-e4334fb9e78f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939704011 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_same_source.3939704011 |
| Directory | /workspace/69.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke.3278235905 |
| Short name | T2733 |
| Test name | |
| Test status | |
| Simulation time | 258519793 ps |
| CPU time | 10.2 seconds |
| Started | Aug 17 06:54:18 PM PDT 24 |
| Finished | Aug 17 06:54:29 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-32b7781c-2412-40e9-8185-ff6655b334f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278235905 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke.3278235905 |
| Directory | /workspace/69.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_large_delays.432433973 |
| Short name | T2146 |
| Test name | |
| Test status | |
| Simulation time | 5708952818 ps |
| CPU time | 60.9 seconds |
| Started | Aug 17 06:54:26 PM PDT 24 |
| Finished | Aug 17 06:55:27 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-3d877086-528b-4d37-a17c-596a9c79df6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432433973 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_large_delays.432433973 |
| Directory | /workspace/69.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_slow_rsp.1686410672 |
| Short name | T2574 |
| Test name | |
| Test status | |
| Simulation time | 6534887543 ps |
| CPU time | 111.05 seconds |
| Started | Aug 17 06:54:26 PM PDT 24 |
| Finished | Aug 17 06:56:17 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-034a8de1-7975-45df-80d7-55b8e37a90f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686410672 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_slow_rsp.1686410672 |
| Directory | /workspace/69.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_smoke_zero_delays.1824747227 |
| Short name | T1875 |
| Test name | |
| Test status | |
| Simulation time | 36369921 ps |
| CPU time | 5.95 seconds |
| Started | Aug 17 06:54:17 PM PDT 24 |
| Finished | Aug 17 06:54:23 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-cc00906b-0a7e-43ce-82ed-c1dc1435396d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824747227 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_smoke_zero_delay s.1824747227 |
| Directory | /workspace/69.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all.3872186089 |
| Short name | T2521 |
| Test name | |
| Test status | |
| Simulation time | 2858340303 ps |
| CPU time | 119.72 seconds |
| Started | Aug 17 06:54:29 PM PDT 24 |
| Finished | Aug 17 06:56:29 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-1035f64a-0770-467d-9c3a-bc205834ba14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872186089 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all.3872186089 |
| Directory | /workspace/69.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_error.1801869857 |
| Short name | T2851 |
| Test name | |
| Test status | |
| Simulation time | 960042550 ps |
| CPU time | 77.91 seconds |
| Started | Aug 17 06:54:26 PM PDT 24 |
| Finished | Aug 17 06:55:44 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-14d83953-65ae-40e3-a0de-fe3926b39425 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801869857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all_with_error.1801869857 |
| Directory | /workspace/69.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.2627944453 |
| Short name | T1551 |
| Test name | |
| Test status | |
| Simulation time | 197055595 ps |
| CPU time | 60.23 seconds |
| Started | Aug 17 06:54:27 PM PDT 24 |
| Finished | Aug 17 06:55:28 PM PDT 24 |
| Peak memory | 576280 kb |
| Host | smart-9a220566-0178-4dc7-aab4-47bdaa0f342a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627944453 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_all _with_rand_reset.2627944453 |
| Directory | /workspace/69.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_stress_all_with_reset_error.2759596033 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 4120163983 ps |
| CPU time | 307.19 seconds |
| Started | Aug 17 06:54:25 PM PDT 24 |
| Finished | Aug 17 06:59:32 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-d2a7595b-b288-4058-9372-ea3f97de4a44 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759596033 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_stress_al l_with_reset_error.2759596033 |
| Directory | /workspace/69.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/69.xbar_unmapped_addr.2662223984 |
| Short name | T2920 |
| Test name | |
| Test status | |
| Simulation time | 898501777 ps |
| CPU time | 40.48 seconds |
| Started | Aug 17 06:54:25 PM PDT 24 |
| Finished | Aug 17 06:55:05 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-5fcb33f0-fccc-4243-9236-41ed00095dae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2662223984 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 69.xbar_unmapped_addr.2662223984 |
| Directory | /workspace/69.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_mem_rw_with_rand_reset.3466036642 |
| Short name | T1846 |
| Test name | |
| Test status | |
| Simulation time | 5535987456 ps |
| CPU time | 428.43 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:54:53 PM PDT 24 |
| Peak memory | 645344 kb |
| Host | smart-6e444c71-f6a8-4f3b-9d88-65e5172a40e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466036642 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 7.chip_csr_mem_rw_with_rand_reset.3466036642 |
| Directory | /workspace/7.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_csr_rw.791757905 |
| Short name | T2435 |
| Test name | |
| Test status | |
| Simulation time | 3570099280 ps |
| CPU time | 234.91 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:51:43 PM PDT 24 |
| Peak memory | 597348 kb |
| Host | smart-5bd6496d-2af6-4968-8be2-7a251e54eb96 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=791757905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_csr_rw.791757905 |
| Directory | /workspace/7.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_same_csr_outstanding.3571225168 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 30710931111 ps |
| CPU time | 3094.59 seconds |
| Started | Aug 17 06:47:37 PM PDT 24 |
| Finished | Aug 17 07:39:12 PM PDT 24 |
| Peak memory | 593844 kb |
| Host | smart-061f2cba-3b60-4fde-a398-c25d3cf81f13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571225168 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 7.chip_same_csr_outstanding.3571225168 |
| Directory | /workspace/7.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/7.chip_tl_errors.3854481498 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 3928749104 ps |
| CPU time | 233.84 seconds |
| Started | Aug 17 06:47:37 PM PDT 24 |
| Finished | Aug 17 06:51:31 PM PDT 24 |
| Peak memory | 603812 kb |
| Host | smart-87dc8a7d-7245-420a-ac86-e1f4735a4402 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854481498 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.chip_tl_errors.3854481498 |
| Directory | /workspace/7.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device.778203413 |
| Short name | T1775 |
| Test name | |
| Test status | |
| Simulation time | 326079724 ps |
| CPU time | 14.46 seconds |
| Started | Aug 17 06:47:41 PM PDT 24 |
| Finished | Aug 17 06:47:56 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-742d1305-5c72-470e-99c3-3bda614fda18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778203413 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_device.778203413 |
| Directory | /workspace/7.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_access_same_device_slow_rsp.2976481777 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 125106177434 ps |
| CPU time | 2264.45 seconds |
| Started | Aug 17 06:47:42 PM PDT 24 |
| Finished | Aug 17 07:25:27 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-0a470aa0-1f51-44be-a1f5-010cbc44d60e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976481777 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_access_same_d evice_slow_rsp.2976481777 |
| Directory | /workspace/7.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_and_unmapped_addr.4190247529 |
| Short name | T1407 |
| Test name | |
| Test status | |
| Simulation time | 326771717 ps |
| CPU time | 15.84 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:48:05 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-b7013345-0ec5-4bf5-90c2-6d95ce4494a8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4190247529 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_and_unmapped_addr .4190247529 |
| Directory | /workspace/7.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_error_random.1491763065 |
| Short name | T2532 |
| Test name | |
| Test status | |
| Simulation time | 564066782 ps |
| CPU time | 19.52 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:07 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-2162c903-40f6-4bc4-830c-1273d98938ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491763065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_error_random.1491763065 |
| Directory | /workspace/7.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random.155498123 |
| Short name | T1922 |
| Test name | |
| Test status | |
| Simulation time | 1546158247 ps |
| CPU time | 52.55 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:48:38 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-c4199f28-dc40-47a7-907b-ac0d6fac771c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155498123 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random.155498123 |
| Directory | /workspace/7.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_large_delays.4070609441 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 67546203743 ps |
| CPU time | 733.75 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 06:59:53 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-02ca6841-f7d4-49f8-8a1a-e73d44ddcc00 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070609441 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_large_delays.4070609441 |
| Directory | /workspace/7.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_slow_rsp.2820867176 |
| Short name | T1454 |
| Test name | |
| Test status | |
| Simulation time | 28456404975 ps |
| CPU time | 455.22 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:55:20 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-e9f8af93-f5f4-49cc-abc4-f7f1d11ef1a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820867176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_slow_rsp.2820867176 |
| Directory | /workspace/7.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.2538335638 |
| Short name | T2921 |
| Test name | |
| Test status | |
| Simulation time | 331086453 ps |
| CPU time | 29.67 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:48:17 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-eb954a2a-b246-4800-8629-3a91e186e819 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538335638 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_random_zero_dela ys.2538335638 |
| Directory | /workspace/7.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_same_source.2389532664 |
| Short name | T2815 |
| Test name | |
| Test status | |
| Simulation time | 371076653 ps |
| CPU time | 26.79 seconds |
| Started | Aug 17 06:48:09 PM PDT 24 |
| Finished | Aug 17 06:48:36 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-b58ff2bb-b69a-4925-9d6b-44df378657c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389532664 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_same_source.2389532664 |
| Directory | /workspace/7.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke.3076821971 |
| Short name | T2837 |
| Test name | |
| Test status | |
| Simulation time | 47348117 ps |
| CPU time | 5.62 seconds |
| Started | Aug 17 06:47:41 PM PDT 24 |
| Finished | Aug 17 06:47:47 PM PDT 24 |
| Peak memory | 574108 kb |
| Host | smart-d9a4f00b-7763-4121-bb6f-48f249cc317b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076821971 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke.3076821971 |
| Directory | /workspace/7.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_large_delays.2640413854 |
| Short name | T2321 |
| Test name | |
| Test status | |
| Simulation time | 9961507631 ps |
| CPU time | 108.81 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:49:45 PM PDT 24 |
| Peak memory | 574176 kb |
| Host | smart-e6a27b89-24e7-47d4-aebb-3b11e8281464 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640413854 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_large_delays.2640413854 |
| Directory | /workspace/7.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_slow_rsp.2178301768 |
| Short name | T2507 |
| Test name | |
| Test status | |
| Simulation time | 3831666317 ps |
| CPU time | 65.65 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:48:50 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-b7563272-d18c-46f1-a6c3-119d75ea6053 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178301768 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_slow_rsp.2178301768 |
| Directory | /workspace/7.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_smoke_zero_delays.3460363415 |
| Short name | T2797 |
| Test name | |
| Test status | |
| Simulation time | 60369660 ps |
| CPU time | 7.05 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 06:47:46 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-c8a7eece-45b3-4526-8f09-a10159065177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3460363415 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_smoke_zero_delays .3460363415 |
| Directory | /workspace/7.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all.3352532557 |
| Short name | T2693 |
| Test name | |
| Test status | |
| Simulation time | 654512378 ps |
| CPU time | 24.76 seconds |
| Started | Aug 17 06:47:39 PM PDT 24 |
| Finished | Aug 17 06:48:04 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-83aa532f-cf87-490e-8d25-f96491257c07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352532557 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all.3352532557 |
| Directory | /workspace/7.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_error.2907624257 |
| Short name | T2183 |
| Test name | |
| Test status | |
| Simulation time | 3847088434 ps |
| CPU time | 291.25 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:52:40 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-8d8af448-b5c7-4a06-bc2b-7a3ab17479ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907624257 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_with_error.2907624257 |
| Directory | /workspace/7.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_rand_reset.146252508 |
| Short name | T2623 |
| Test name | |
| Test status | |
| Simulation time | 503363049 ps |
| CPU time | 233 seconds |
| Started | Aug 17 06:48:00 PM PDT 24 |
| Finished | Aug 17 06:51:54 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-c9eeeeb0-679c-4f1d-971e-f1d01f53c63c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=146252508 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_w ith_rand_reset.146252508 |
| Directory | /workspace/7.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_stress_all_with_reset_error.902512798 |
| Short name | T1462 |
| Test name | |
| Test status | |
| Simulation time | 305223686 ps |
| CPU time | 112.41 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:49:40 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-12a6deae-d222-4c4c-9dbc-032433e9add0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902512798 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_stress_all_ with_reset_error.902512798 |
| Directory | /workspace/7.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/7.xbar_unmapped_addr.3360238692 |
| Short name | T1514 |
| Test name | |
| Test status | |
| Simulation time | 349702356 ps |
| CPU time | 41.34 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:31 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-6745d67e-cd1f-4778-a0ae-230357e2ce33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360238692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.xbar_unmapped_addr.3360238692 |
| Directory | /workspace/7.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device.1935254375 |
| Short name | T1467 |
| Test name | |
| Test status | |
| Simulation time | 535241313 ps |
| CPU time | 27.27 seconds |
| Started | Aug 17 06:54:33 PM PDT 24 |
| Finished | Aug 17 06:55:01 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-894fb624-e309-4887-a29c-2e9a4876a1b9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935254375 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_device .1935254375 |
| Directory | /workspace/70.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_access_same_device_slow_rsp.554194669 |
| Short name | T2914 |
| Test name | |
| Test status | |
| Simulation time | 118035911556 ps |
| CPU time | 2176.02 seconds |
| Started | Aug 17 06:54:33 PM PDT 24 |
| Finished | Aug 17 07:30:49 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-f59d7d36-0916-4aa2-9475-9650254c62ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=554194669 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_access_same_d evice_slow_rsp.554194669 |
| Directory | /workspace/70.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.3874990649 |
| Short name | T2888 |
| Test name | |
| Test status | |
| Simulation time | 585800330 ps |
| CPU time | 27.57 seconds |
| Started | Aug 17 06:54:31 PM PDT 24 |
| Finished | Aug 17 06:54:59 PM PDT 24 |
| Peak memory | 575352 kb |
| Host | smart-5a807539-49a3-4404-92ed-945211334a68 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874990649 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_and_unmapped_add r.3874990649 |
| Directory | /workspace/70.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_error_random.4093990125 |
| Short name | T1418 |
| Test name | |
| Test status | |
| Simulation time | 67446165 ps |
| CPU time | 7.73 seconds |
| Started | Aug 17 06:54:34 PM PDT 24 |
| Finished | Aug 17 06:54:42 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a43a1c45-357a-4f80-94f1-d93555f0aff3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4093990125 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_error_random.4093990125 |
| Directory | /workspace/70.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random.1450818102 |
| Short name | T2054 |
| Test name | |
| Test status | |
| Simulation time | 773225756 ps |
| CPU time | 26.98 seconds |
| Started | Aug 17 06:54:30 PM PDT 24 |
| Finished | Aug 17 06:54:57 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-5462f7b7-433c-468f-88fc-3efb0b111fa2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450818102 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random.1450818102 |
| Directory | /workspace/70.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_large_delays.1417385108 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 84152116151 ps |
| CPU time | 919.29 seconds |
| Started | Aug 17 06:54:35 PM PDT 24 |
| Finished | Aug 17 07:09:54 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-a1023874-f1d2-4549-9192-95470bd1a351 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1417385108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_large_delays.1417385108 |
| Directory | /workspace/70.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_slow_rsp.10321057 |
| Short name | T1587 |
| Test name | |
| Test status | |
| Simulation time | 16484253172 ps |
| CPU time | 278.75 seconds |
| Started | Aug 17 06:54:32 PM PDT 24 |
| Finished | Aug 17 06:59:11 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-678debf8-799b-46a0-bfde-222fa606795c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10321057 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_slow_rsp.10321057 |
| Directory | /workspace/70.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_random_zero_delays.2139720204 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 112181606 ps |
| CPU time | 11.31 seconds |
| Started | Aug 17 06:54:44 PM PDT 24 |
| Finished | Aug 17 06:54:55 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-3d665f38-fc09-4b53-9ce6-90c751a6ae94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139720204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_random_zero_del ays.2139720204 |
| Directory | /workspace/70.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_same_source.363267115 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 346468204 ps |
| CPU time | 25.05 seconds |
| Started | Aug 17 06:54:35 PM PDT 24 |
| Finished | Aug 17 06:55:00 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-2d91eddb-161a-44dd-9634-a971aec7ca74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363267115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_same_source.363267115 |
| Directory | /workspace/70.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke.3300676136 |
| Short name | T2879 |
| Test name | |
| Test status | |
| Simulation time | 211684714 ps |
| CPU time | 8.92 seconds |
| Started | Aug 17 06:54:30 PM PDT 24 |
| Finished | Aug 17 06:54:40 PM PDT 24 |
| Peak memory | 574060 kb |
| Host | smart-f302f01a-1fbe-4117-9acd-d04bb789912b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300676136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke.3300676136 |
| Directory | /workspace/70.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_large_delays.1150371817 |
| Short name | T1976 |
| Test name | |
| Test status | |
| Simulation time | 6419154024 ps |
| CPU time | 67.25 seconds |
| Started | Aug 17 06:54:25 PM PDT 24 |
| Finished | Aug 17 06:55:32 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-653465c6-ae2e-46fa-88af-9d77f8c58326 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150371817 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_large_delays.1150371817 |
| Directory | /workspace/70.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_slow_rsp.3141504802 |
| Short name | T1492 |
| Test name | |
| Test status | |
| Simulation time | 4455425436 ps |
| CPU time | 76.79 seconds |
| Started | Aug 17 06:54:25 PM PDT 24 |
| Finished | Aug 17 06:55:42 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-76afda06-a76b-4326-b3f0-1e2392472671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141504802 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_slow_rsp.3141504802 |
| Directory | /workspace/70.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_smoke_zero_delays.53891692 |
| Short name | T1400 |
| Test name | |
| Test status | |
| Simulation time | 43556135 ps |
| CPU time | 6.65 seconds |
| Started | Aug 17 06:54:24 PM PDT 24 |
| Finished | Aug 17 06:54:31 PM PDT 24 |
| Peak memory | 573344 kb |
| Host | smart-d4510984-7d16-4f02-9205-729fdfcae135 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53891692 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_smoke_zero_delays.53891692 |
| Directory | /workspace/70.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all.1744423169 |
| Short name | T2463 |
| Test name | |
| Test status | |
| Simulation time | 10651502089 ps |
| CPU time | 365.15 seconds |
| Started | Aug 17 06:54:33 PM PDT 24 |
| Finished | Aug 17 07:00:38 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-5a084b96-e8b9-4e27-a757-b3744b881439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744423169 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all.1744423169 |
| Directory | /workspace/70.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_error.3348667065 |
| Short name | T2021 |
| Test name | |
| Test status | |
| Simulation time | 10162623077 ps |
| CPU time | 356.07 seconds |
| Started | Aug 17 06:54:33 PM PDT 24 |
| Finished | Aug 17 07:00:29 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-ba561ace-9bde-4791-9c19-a26fca98cb79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348667065 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_with_error.3348667065 |
| Directory | /workspace/70.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_rand_reset.480432814 |
| Short name | T2925 |
| Test name | |
| Test status | |
| Simulation time | 783056971 ps |
| CPU time | 55.21 seconds |
| Started | Aug 17 06:54:33 PM PDT 24 |
| Finished | Aug 17 06:55:29 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-63fda8ef-d3ea-463c-8e59-336c98387919 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480432814 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_all_ with_rand_reset.480432814 |
| Directory | /workspace/70.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_stress_all_with_reset_error.2374462124 |
| Short name | T2072 |
| Test name | |
| Test status | |
| Simulation time | 108662512 ps |
| CPU time | 25.21 seconds |
| Started | Aug 17 06:54:43 PM PDT 24 |
| Finished | Aug 17 06:55:08 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-ca687b44-459c-4afb-8c6e-670a8a50b621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374462124 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_stress_al l_with_reset_error.2374462124 |
| Directory | /workspace/70.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/70.xbar_unmapped_addr.3264349567 |
| Short name | T1974 |
| Test name | |
| Test status | |
| Simulation time | 711514898 ps |
| CPU time | 26.62 seconds |
| Started | Aug 17 06:54:31 PM PDT 24 |
| Finished | Aug 17 06:54:57 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-36c337d0-8007-49b5-aa16-78f2c57f3e49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3264349567 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 70.xbar_unmapped_addr.3264349567 |
| Directory | /workspace/70.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_access_same_device.2189718631 |
| Short name | T2366 |
| Test name | |
| Test status | |
| Simulation time | 125243128 ps |
| CPU time | 11.89 seconds |
| Started | Aug 17 06:54:40 PM PDT 24 |
| Finished | Aug 17 06:54:52 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-6d9ae901-7514-419c-a8f3-7c7ceeeaee77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189718631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_access_same_device .2189718631 |
| Directory | /workspace/71.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_and_unmapped_addr.2428272505 |
| Short name | T2823 |
| Test name | |
| Test status | |
| Simulation time | 66774664 ps |
| CPU time | 9.45 seconds |
| Started | Aug 17 06:54:40 PM PDT 24 |
| Finished | Aug 17 06:54:49 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-d293df6a-027d-4c3c-80c4-7d340fa70a42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428272505 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_and_unmapped_add r.2428272505 |
| Directory | /workspace/71.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_error_random.961972099 |
| Short name | T1827 |
| Test name | |
| Test status | |
| Simulation time | 231031267 ps |
| CPU time | 21.78 seconds |
| Started | Aug 17 06:54:38 PM PDT 24 |
| Finished | Aug 17 06:54:59 PM PDT 24 |
| Peak memory | 575396 kb |
| Host | smart-b22669bf-b838-4d64-bdc9-0297aa17386e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961972099 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_error_random.961972099 |
| Directory | /workspace/71.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random.3183841451 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 238101346 ps |
| CPU time | 21.57 seconds |
| Started | Aug 17 06:54:30 PM PDT 24 |
| Finished | Aug 17 06:54:52 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-842bdbd7-266e-4413-a1e8-8f21ce584ee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183841451 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random.3183841451 |
| Directory | /workspace/71.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2865810981 |
| Short name | T2479 |
| Test name | |
| Test status | |
| Simulation time | 38976001731 ps |
| CPU time | 446.27 seconds |
| Started | Aug 17 06:54:43 PM PDT 24 |
| Finished | Aug 17 07:02:10 PM PDT 24 |
| Peak memory | 575640 kb |
| Host | smart-759b250a-a475-4bf9-af7f-380710c3e321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865810981 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_large_delays.2865810981 |
| Directory | /workspace/71.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_slow_rsp.3968078615 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 8000334196 ps |
| CPU time | 132.21 seconds |
| Started | Aug 17 06:54:39 PM PDT 24 |
| Finished | Aug 17 06:56:51 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-6b43cd56-d518-4cf6-bc3e-ddb15bd59f19 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968078615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_slow_rsp.3968078615 |
| Directory | /workspace/71.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.3133856681 |
| Short name | T2333 |
| Test name | |
| Test status | |
| Simulation time | 480839489 ps |
| CPU time | 45.51 seconds |
| Started | Aug 17 06:54:33 PM PDT 24 |
| Finished | Aug 17 06:55:18 PM PDT 24 |
| Peak memory | 575324 kb |
| Host | smart-8d4e3f6c-1dcb-41c1-8d95-6f8842bd84aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3133856681 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_random_zero_del ays.3133856681 |
| Directory | /workspace/71.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_same_source.588552917 |
| Short name | T1413 |
| Test name | |
| Test status | |
| Simulation time | 239415866 ps |
| CPU time | 18.2 seconds |
| Started | Aug 17 06:54:40 PM PDT 24 |
| Finished | Aug 17 06:54:58 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-96c94f59-bb97-47ce-a103-5a1fa6de6e1f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588552917 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_same_source.588552917 |
| Directory | /workspace/71.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke.2559322282 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 53410970 ps |
| CPU time | 6.47 seconds |
| Started | Aug 17 06:54:35 PM PDT 24 |
| Finished | Aug 17 06:54:42 PM PDT 24 |
| Peak memory | 573412 kb |
| Host | smart-7e165c2b-9be3-4837-b8e2-fe8f7f57316f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2559322282 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke.2559322282 |
| Directory | /workspace/71.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_large_delays.1176626173 |
| Short name | T1391 |
| Test name | |
| Test status | |
| Simulation time | 5015081391 ps |
| CPU time | 53.28 seconds |
| Started | Aug 17 06:54:34 PM PDT 24 |
| Finished | Aug 17 06:55:27 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-cd11d5c9-1f48-48b1-9508-46b9df449e83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176626173 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_large_delays.1176626173 |
| Directory | /workspace/71.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_slow_rsp.1424493234 |
| Short name | T1713 |
| Test name | |
| Test status | |
| Simulation time | 5745729344 ps |
| CPU time | 93.82 seconds |
| Started | Aug 17 06:54:43 PM PDT 24 |
| Finished | Aug 17 06:56:17 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-c833d7ac-d015-40d0-931f-98dd8b0d3d38 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1424493234 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_slow_rsp.1424493234 |
| Directory | /workspace/71.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_smoke_zero_delays.1501234837 |
| Short name | T2272 |
| Test name | |
| Test status | |
| Simulation time | 52663497 ps |
| CPU time | 6.99 seconds |
| Started | Aug 17 06:54:31 PM PDT 24 |
| Finished | Aug 17 06:54:38 PM PDT 24 |
| Peak memory | 574032 kb |
| Host | smart-48b1bf15-1717-42c4-9d88-7243a52298cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501234837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_smoke_zero_delay s.1501234837 |
| Directory | /workspace/71.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all.3630694181 |
| Short name | T2420 |
| Test name | |
| Test status | |
| Simulation time | 2794485774 ps |
| CPU time | 235.25 seconds |
| Started | Aug 17 06:54:45 PM PDT 24 |
| Finished | Aug 17 06:58:40 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-bdbe1fac-a7c3-422e-bd80-a16827dc794a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630694181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all.3630694181 |
| Directory | /workspace/71.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_error.2187519051 |
| Short name | T2474 |
| Test name | |
| Test status | |
| Simulation time | 10996039885 ps |
| CPU time | 390.09 seconds |
| Started | Aug 17 06:54:37 PM PDT 24 |
| Finished | Aug 17 07:01:08 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-306dd5e7-3cbb-48d3-b558-4c6109faf621 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2187519051 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all_with_error.2187519051 |
| Directory | /workspace/71.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_stress_all_with_rand_reset.3805934957 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 1866607835 ps |
| CPU time | 374.81 seconds |
| Started | Aug 17 06:54:38 PM PDT 24 |
| Finished | Aug 17 07:00:53 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-2856d9f4-270c-46d3-b917-ab469081caff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805934957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_stress_all _with_rand_reset.3805934957 |
| Directory | /workspace/71.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/71.xbar_unmapped_addr.3622668892 |
| Short name | T2332 |
| Test name | |
| Test status | |
| Simulation time | 713806909 ps |
| CPU time | 28.11 seconds |
| Started | Aug 17 06:54:36 PM PDT 24 |
| Finished | Aug 17 06:55:04 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-8aae841e-d438-4d44-95fa-3dc773612528 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3622668892 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 71.xbar_unmapped_addr.3622668892 |
| Directory | /workspace/71.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device.3981638351 |
| Short name | T2780 |
| Test name | |
| Test status | |
| Simulation time | 898211923 ps |
| CPU time | 65.3 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:55:51 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-3a8fc33f-156e-4d48-bdce-68b7a65ca4a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981638351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_device .3981638351 |
| Directory | /workspace/72.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_access_same_device_slow_rsp.3370898721 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 15031344384 ps |
| CPU time | 246.09 seconds |
| Started | Aug 17 06:54:47 PM PDT 24 |
| Finished | Aug 17 06:58:53 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-020e61b9-bb52-41e6-9fb3-dbc40078d878 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370898721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_access_same_ device_slow_rsp.3370898721 |
| Directory | /workspace/72.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_and_unmapped_addr.2037027298 |
| Short name | T1797 |
| Test name | |
| Test status | |
| Simulation time | 479085195 ps |
| CPU time | 21.24 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:55:08 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-6b31a255-04b8-4882-918f-ee76a580e2f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037027298 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_and_unmapped_add r.2037027298 |
| Directory | /workspace/72.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_error_random.2381376900 |
| Short name | T2676 |
| Test name | |
| Test status | |
| Simulation time | 228374006 ps |
| CPU time | 21.93 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:55:08 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-a7847fe6-c214-4b1e-a143-4637e3c55010 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381376900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_error_random.2381376900 |
| Directory | /workspace/72.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random.4082024598 |
| Short name | T2912 |
| Test name | |
| Test status | |
| Simulation time | 372265126 ps |
| CPU time | 33.3 seconds |
| Started | Aug 17 06:54:50 PM PDT 24 |
| Finished | Aug 17 06:55:23 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-85bfe0ca-30dd-4081-ae87-3a40a157728c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082024598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random.4082024598 |
| Directory | /workspace/72.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_large_delays.4148885847 |
| Short name | T2269 |
| Test name | |
| Test status | |
| Simulation time | 62129631816 ps |
| CPU time | 741.76 seconds |
| Started | Aug 17 06:54:45 PM PDT 24 |
| Finished | Aug 17 07:07:07 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-6c1ac15a-3c5c-44f3-a259-8cc51ae6731e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148885847 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_large_delays.4148885847 |
| Directory | /workspace/72.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_slow_rsp.2405473528 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 54090304778 ps |
| CPU time | 1078.67 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 07:12:45 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-8ad57d64-6cb1-43b8-99a6-b70aa89438c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405473528 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_slow_rsp.2405473528 |
| Directory | /workspace/72.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_random_zero_delays.1719805853 |
| Short name | T2047 |
| Test name | |
| Test status | |
| Simulation time | 143203511 ps |
| CPU time | 14.76 seconds |
| Started | Aug 17 06:54:50 PM PDT 24 |
| Finished | Aug 17 06:55:05 PM PDT 24 |
| Peak memory | 575612 kb |
| Host | smart-17f9c833-5a61-42b7-9a4a-96ff76764c33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719805853 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_random_zero_del ays.1719805853 |
| Directory | /workspace/72.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_same_source.2902964032 |
| Short name | T1746 |
| Test name | |
| Test status | |
| Simulation time | 1434303954 ps |
| CPU time | 46.15 seconds |
| Started | Aug 17 06:54:50 PM PDT 24 |
| Finished | Aug 17 06:55:36 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-73a396c4-1b9e-4595-b2e1-9bc409c23741 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902964032 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_same_source.2902964032 |
| Directory | /workspace/72.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke.512468224 |
| Short name | T1394 |
| Test name | |
| Test status | |
| Simulation time | 52472223 ps |
| CPU time | 6.55 seconds |
| Started | Aug 17 06:54:50 PM PDT 24 |
| Finished | Aug 17 06:54:57 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-41115613-1d26-4161-a780-e72fdbf4df7d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512468224 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke.512468224 |
| Directory | /workspace/72.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_large_delays.1055025941 |
| Short name | T2526 |
| Test name | |
| Test status | |
| Simulation time | 8377932476 ps |
| CPU time | 82.32 seconds |
| Started | Aug 17 06:54:50 PM PDT 24 |
| Finished | Aug 17 06:56:13 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-94fc2554-8ca3-4501-aae9-4da8a20bfa64 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055025941 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_large_delays.1055025941 |
| Directory | /workspace/72.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_slow_rsp.3499172136 |
| Short name | T1435 |
| Test name | |
| Test status | |
| Simulation time | 4797546496 ps |
| CPU time | 81.74 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:56:08 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-ddf725cc-ccba-4aa4-9a12-34e75f726428 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499172136 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_slow_rsp.3499172136 |
| Directory | /workspace/72.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_smoke_zero_delays.2273677149 |
| Short name | T2652 |
| Test name | |
| Test status | |
| Simulation time | 44297741 ps |
| CPU time | 6.42 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:54:52 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-4c21f6fe-f453-4acf-bf60-b6e1679d581b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273677149 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_smoke_zero_delay s.2273677149 |
| Directory | /workspace/72.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all.3152296386 |
| Short name | T2789 |
| Test name | |
| Test status | |
| Simulation time | 767712603 ps |
| CPU time | 67.62 seconds |
| Started | Aug 17 06:54:50 PM PDT 24 |
| Finished | Aug 17 06:55:58 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-ab24f507-3826-46ae-a1fc-412578313324 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152296386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all.3152296386 |
| Directory | /workspace/72.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_error.3577324066 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 2938113337 ps |
| CPU time | 230.56 seconds |
| Started | Aug 17 06:54:48 PM PDT 24 |
| Finished | Aug 17 06:58:39 PM PDT 24 |
| Peak memory | 576304 kb |
| Host | smart-d4938143-919e-4a93-b270-441e077e7a17 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577324066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all_with_error.3577324066 |
| Directory | /workspace/72.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_rand_reset.3879919308 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 96841265 ps |
| CPU time | 44.39 seconds |
| Started | Aug 17 06:54:47 PM PDT 24 |
| Finished | Aug 17 06:55:32 PM PDT 24 |
| Peak memory | 576284 kb |
| Host | smart-e04cfc15-61c2-4e7a-91d6-d4c25f946207 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879919308 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_rand_reset.3879919308 |
| Directory | /workspace/72.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_stress_all_with_reset_error.700430742 |
| Short name | T1989 |
| Test name | |
| Test status | |
| Simulation time | 3130728822 ps |
| CPU time | 474.18 seconds |
| Started | Aug 17 06:54:50 PM PDT 24 |
| Finished | Aug 17 07:02:44 PM PDT 24 |
| Peak memory | 576404 kb |
| Host | smart-165a0f5a-ca1f-4e82-9722-0ee31c13dfd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700430742 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_stress_all _with_reset_error.700430742 |
| Directory | /workspace/72.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/72.xbar_unmapped_addr.1348449876 |
| Short name | T1833 |
| Test name | |
| Test status | |
| Simulation time | 603030151 ps |
| CPU time | 26.07 seconds |
| Started | Aug 17 06:54:47 PM PDT 24 |
| Finished | Aug 17 06:55:14 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-5b471ac3-6a9a-4b5a-9830-ce15302fb24b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348449876 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 72.xbar_unmapped_addr.1348449876 |
| Directory | /workspace/72.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device.175952961 |
| Short name | T2766 |
| Test name | |
| Test status | |
| Simulation time | 287072557 ps |
| CPU time | 27.23 seconds |
| Started | Aug 17 06:54:56 PM PDT 24 |
| Finished | Aug 17 06:55:23 PM PDT 24 |
| Peak memory | 575368 kb |
| Host | smart-47f11e41-fdbb-4fee-ab0f-7620035082c0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=175952961 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_device. 175952961 |
| Directory | /workspace/73.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_access_same_device_slow_rsp.4272751906 |
| Short name | T2647 |
| Test name | |
| Test status | |
| Simulation time | 140398099256 ps |
| CPU time | 2665.39 seconds |
| Started | Aug 17 06:54:52 PM PDT 24 |
| Finished | Aug 17 07:39:18 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-fe454358-07f9-4a33-ab6a-fdec3aee3f7c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272751906 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_access_same_ device_slow_rsp.4272751906 |
| Directory | /workspace/73.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_and_unmapped_addr.3956359907 |
| Short name | T1581 |
| Test name | |
| Test status | |
| Simulation time | 166426341 ps |
| CPU time | 9.35 seconds |
| Started | Aug 17 06:54:59 PM PDT 24 |
| Finished | Aug 17 06:55:08 PM PDT 24 |
| Peak memory | 573464 kb |
| Host | smart-1831149c-54d5-476e-857a-3daaf99b4f9e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956359907 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_and_unmapped_add r.3956359907 |
| Directory | /workspace/73.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_error_random.1586813659 |
| Short name | T2187 |
| Test name | |
| Test status | |
| Simulation time | 2306753933 ps |
| CPU time | 71.94 seconds |
| Started | Aug 17 06:54:59 PM PDT 24 |
| Finished | Aug 17 06:56:11 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-c328000b-82d1-4d26-8d95-735246d1535c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586813659 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_error_random.1586813659 |
| Directory | /workspace/73.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random.3866196881 |
| Short name | T1948 |
| Test name | |
| Test status | |
| Simulation time | 2381272136 ps |
| CPU time | 91.46 seconds |
| Started | Aug 17 06:54:47 PM PDT 24 |
| Finished | Aug 17 06:56:18 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-ef44da2e-4306-42ed-8bb6-2c9881e8bf9d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866196881 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random.3866196881 |
| Directory | /workspace/73.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_large_delays.2271910146 |
| Short name | T1777 |
| Test name | |
| Test status | |
| Simulation time | 18033254685 ps |
| CPU time | 186.88 seconds |
| Started | Aug 17 06:54:53 PM PDT 24 |
| Finished | Aug 17 06:58:00 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-69afd0fa-d6a7-479b-bbb0-1ab20bc90000 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271910146 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_large_delays.2271910146 |
| Directory | /workspace/73.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_slow_rsp.762732286 |
| Short name | T2377 |
| Test name | |
| Test status | |
| Simulation time | 35599539226 ps |
| CPU time | 654.53 seconds |
| Started | Aug 17 06:54:54 PM PDT 24 |
| Finished | Aug 17 07:05:49 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-b7eaff4f-79b7-4470-84fd-81ce0cd71860 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762732286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_slow_rsp.762732286 |
| Directory | /workspace/73.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_random_zero_delays.1100407166 |
| Short name | T2907 |
| Test name | |
| Test status | |
| Simulation time | 527271849 ps |
| CPU time | 43.32 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:55:29 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-c7589058-bb82-4bf3-88cf-8a6cbafbdddf |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100407166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_random_zero_del ays.1100407166 |
| Directory | /workspace/73.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_same_source.3599976217 |
| Short name | T2933 |
| Test name | |
| Test status | |
| Simulation time | 476648487 ps |
| CPU time | 33.48 seconds |
| Started | Aug 17 06:54:57 PM PDT 24 |
| Finished | Aug 17 06:55:31 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-b02cac9b-7745-4f3f-9230-f6cfae3936a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599976217 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_same_source.3599976217 |
| Directory | /workspace/73.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke.3066574958 |
| Short name | T2099 |
| Test name | |
| Test status | |
| Simulation time | 182214563 ps |
| CPU time | 8.88 seconds |
| Started | Aug 17 06:54:51 PM PDT 24 |
| Finished | Aug 17 06:55:00 PM PDT 24 |
| Peak memory | 573472 kb |
| Host | smart-65726eaf-1b53-49f5-aef6-bea3d5032a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066574958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke.3066574958 |
| Directory | /workspace/73.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_large_delays.189580340 |
| Short name | T1615 |
| Test name | |
| Test status | |
| Simulation time | 9384286352 ps |
| CPU time | 99.3 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:56:26 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-559a5481-4c18-47be-b7a2-9f568058cd30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189580340 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_large_delays.189580340 |
| Directory | /workspace/73.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_slow_rsp.1174748542 |
| Short name | T1406 |
| Test name | |
| Test status | |
| Simulation time | 5308882177 ps |
| CPU time | 90.98 seconds |
| Started | Aug 17 06:54:46 PM PDT 24 |
| Finished | Aug 17 06:56:17 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-d1f4fcca-bf9d-429b-80e9-c92c1729e15a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174748542 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_slow_rsp.1174748542 |
| Directory | /workspace/73.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_smoke_zero_delays.2814438699 |
| Short name | T2249 |
| Test name | |
| Test status | |
| Simulation time | 53506540 ps |
| CPU time | 6.52 seconds |
| Started | Aug 17 06:54:48 PM PDT 24 |
| Finished | Aug 17 06:54:54 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-88322375-3d8f-4d28-ac2a-0f70cbf889f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814438699 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_smoke_zero_delay s.2814438699 |
| Directory | /workspace/73.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all.3381074139 |
| Short name | T2697 |
| Test name | |
| Test status | |
| Simulation time | 3802995070 ps |
| CPU time | 278.76 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 06:59:39 PM PDT 24 |
| Peak memory | 576464 kb |
| Host | smart-d91b589d-d1fd-4c74-b2dc-9119f8cf1920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381074139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all.3381074139 |
| Directory | /workspace/73.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_error.1100454516 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 2671337518 ps |
| CPU time | 171.56 seconds |
| Started | Aug 17 06:54:51 PM PDT 24 |
| Finished | Aug 17 06:57:43 PM PDT 24 |
| Peak memory | 575760 kb |
| Host | smart-adefac98-877a-4149-8e24-b4f3460b7c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100454516 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_with_error.1100454516 |
| Directory | /workspace/73.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_rand_reset.257739419 |
| Short name | T1794 |
| Test name | |
| Test status | |
| Simulation time | 592677916 ps |
| CPU time | 239.64 seconds |
| Started | Aug 17 06:54:53 PM PDT 24 |
| Finished | Aug 17 06:58:53 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-1e2cfa95-0f99-4175-90a4-b35031cd8032 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257739419 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_all_ with_rand_reset.257739419 |
| Directory | /workspace/73.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_stress_all_with_reset_error.3471472321 |
| Short name | T1791 |
| Test name | |
| Test status | |
| Simulation time | 6574685440 ps |
| CPU time | 628.52 seconds |
| Started | Aug 17 06:54:55 PM PDT 24 |
| Finished | Aug 17 07:05:24 PM PDT 24 |
| Peak memory | 581212 kb |
| Host | smart-51fc9f83-7737-4914-bf75-c13093735cef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471472321 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_stress_al l_with_reset_error.3471472321 |
| Directory | /workspace/73.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/73.xbar_unmapped_addr.338511999 |
| Short name | T2528 |
| Test name | |
| Test status | |
| Simulation time | 1153944125 ps |
| CPU time | 46.55 seconds |
| Started | Aug 17 06:54:55 PM PDT 24 |
| Finished | Aug 17 06:55:42 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-bc629d7d-97a1-46f0-92a8-40652062ea2e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338511999 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 73.xbar_unmapped_addr.338511999 |
| Directory | /workspace/73.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device.4119418855 |
| Short name | T2233 |
| Test name | |
| Test status | |
| Simulation time | 575285250 ps |
| CPU time | 37.39 seconds |
| Started | Aug 17 06:54:54 PM PDT 24 |
| Finished | Aug 17 06:55:31 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-fa80b184-3931-4f18-a756-f98a0d7b21c3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119418855 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_device .4119418855 |
| Directory | /workspace/74.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_access_same_device_slow_rsp.4117121487 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 33744339315 ps |
| CPU time | 593.1 seconds |
| Started | Aug 17 06:54:53 PM PDT 24 |
| Finished | Aug 17 07:04:46 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-b4c4c14e-a311-4bd6-9e97-5f680dabb4da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117121487 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_access_same_ device_slow_rsp.4117121487 |
| Directory | /workspace/74.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_and_unmapped_addr.2420202604 |
| Short name | T2695 |
| Test name | |
| Test status | |
| Simulation time | 367714517 ps |
| CPU time | 16.06 seconds |
| Started | Aug 17 06:55:01 PM PDT 24 |
| Finished | Aug 17 06:55:17 PM PDT 24 |
| Peak memory | 575728 kb |
| Host | smart-e3f59690-4ad5-4763-8ad9-ca3b79e18ede |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420202604 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_and_unmapped_add r.2420202604 |
| Directory | /workspace/74.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_error_random.1574519413 |
| Short name | T1455 |
| Test name | |
| Test status | |
| Simulation time | 651790625 ps |
| CPU time | 24.25 seconds |
| Started | Aug 17 06:54:56 PM PDT 24 |
| Finished | Aug 17 06:55:21 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-8c8367ac-c46e-4fc8-bb6b-e3368197d7d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574519413 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_error_random.1574519413 |
| Directory | /workspace/74.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random.4278128766 |
| Short name | T2781 |
| Test name | |
| Test status | |
| Simulation time | 1957214515 ps |
| CPU time | 68.28 seconds |
| Started | Aug 17 06:54:53 PM PDT 24 |
| Finished | Aug 17 06:56:01 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-4613402f-4193-4c98-9c82-6f8a8b2ef084 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278128766 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random.4278128766 |
| Directory | /workspace/74.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_large_delays.3524517278 |
| Short name | T1498 |
| Test name | |
| Test status | |
| Simulation time | 6803994230 ps |
| CPU time | 70.86 seconds |
| Started | Aug 17 06:54:53 PM PDT 24 |
| Finished | Aug 17 06:56:03 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-f86bf33b-4345-4075-97f7-0852ad9856e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3524517278 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_large_delays.3524517278 |
| Directory | /workspace/74.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_slow_rsp.1492698353 |
| Short name | T2222 |
| Test name | |
| Test status | |
| Simulation time | 31170645219 ps |
| CPU time | 552.45 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 07:04:13 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-3942a224-2e7b-4d54-bcc0-0b04102fccc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492698353 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_slow_rsp.1492698353 |
| Directory | /workspace/74.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_random_zero_delays.1667507243 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 136133975 ps |
| CPU time | 13.25 seconds |
| Started | Aug 17 06:54:56 PM PDT 24 |
| Finished | Aug 17 06:55:10 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-0627cbef-878d-4d66-afb2-0c78bd70cb10 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667507243 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_random_zero_del ays.1667507243 |
| Directory | /workspace/74.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_same_source.361315516 |
| Short name | T1887 |
| Test name | |
| Test status | |
| Simulation time | 2098040846 ps |
| CPU time | 60.71 seconds |
| Started | Aug 17 06:54:57 PM PDT 24 |
| Finished | Aug 17 06:55:58 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-7c3b50af-8073-4998-8162-b02afc14b7fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361315516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_same_source.361315516 |
| Directory | /workspace/74.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke.1058457506 |
| Short name | T2525 |
| Test name | |
| Test status | |
| Simulation time | 221448338 ps |
| CPU time | 9.66 seconds |
| Started | Aug 17 06:54:54 PM PDT 24 |
| Finished | Aug 17 06:55:04 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-93647d3d-2c0a-4722-a157-74ef38aafebc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058457506 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke.1058457506 |
| Directory | /workspace/74.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_large_delays.1154154181 |
| Short name | T2093 |
| Test name | |
| Test status | |
| Simulation time | 6009929741 ps |
| CPU time | 62.2 seconds |
| Started | Aug 17 06:55:01 PM PDT 24 |
| Finished | Aug 17 06:56:03 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-8e4cc081-821e-448a-9008-152fc1da89ba |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154154181 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_large_delays.1154154181 |
| Directory | /workspace/74.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_slow_rsp.1402540475 |
| Short name | T2110 |
| Test name | |
| Test status | |
| Simulation time | 5440683225 ps |
| CPU time | 92.69 seconds |
| Started | Aug 17 06:54:56 PM PDT 24 |
| Finished | Aug 17 06:56:29 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-5fdc668f-908c-4014-b8a1-cd5d73543e71 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402540475 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_slow_rsp.1402540475 |
| Directory | /workspace/74.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_smoke_zero_delays.2125102857 |
| Short name | T1411 |
| Test name | |
| Test status | |
| Simulation time | 48641519 ps |
| CPU time | 6.49 seconds |
| Started | Aug 17 06:54:52 PM PDT 24 |
| Finished | Aug 17 06:54:58 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-3a29fb12-c0f3-4850-ada2-8c5998d56e42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2125102857 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_smoke_zero_delay s.2125102857 |
| Directory | /workspace/74.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all.181383835 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 9338010173 ps |
| CPU time | 357.67 seconds |
| Started | Aug 17 06:55:02 PM PDT 24 |
| Finished | Aug 17 07:01:00 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-3268e903-3252-4644-b943-1a5e346c576b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181383835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all.181383835 |
| Directory | /workspace/74.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_error.614475874 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 12374251221 ps |
| CPU time | 407.51 seconds |
| Started | Aug 17 06:55:01 PM PDT 24 |
| Finished | Aug 17 07:01:48 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-25bac4db-fb78-46f1-84ac-e9b8113f0a4e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=614475874 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all_with_error.614475874 |
| Directory | /workspace/74.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_rand_reset.2165422063 |
| Short name | T2174 |
| Test name | |
| Test status | |
| Simulation time | 555104547 ps |
| CPU time | 203.35 seconds |
| Started | Aug 17 06:55:01 PM PDT 24 |
| Finished | Aug 17 06:58:24 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-87e0e795-7ec7-48f2-825d-a814fbba7d5d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165422063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_all _with_rand_reset.2165422063 |
| Directory | /workspace/74.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_stress_all_with_reset_error.3273531093 |
| Short name | T1668 |
| Test name | |
| Test status | |
| Simulation time | 343394931 ps |
| CPU time | 136.43 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 06:57:16 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-d673f639-48e1-45eb-8986-bd2660f9e418 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3273531093 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_stress_al l_with_reset_error.3273531093 |
| Directory | /workspace/74.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/74.xbar_unmapped_addr.2850554111 |
| Short name | T2186 |
| Test name | |
| Test status | |
| Simulation time | 591022798 ps |
| CPU time | 24.67 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 06:55:25 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-1cda6db2-6a7a-44ca-9397-24ce0a70e567 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850554111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 74.xbar_unmapped_addr.2850554111 |
| Directory | /workspace/74.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device.866783759 |
| Short name | T2324 |
| Test name | |
| Test status | |
| Simulation time | 927820382 ps |
| CPU time | 64.57 seconds |
| Started | Aug 17 06:55:01 PM PDT 24 |
| Finished | Aug 17 06:56:06 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-16d71d3a-28a2-40aa-b69b-7feb88f236b3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866783759 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_device. 866783759 |
| Directory | /workspace/75.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_access_same_device_slow_rsp.3908304008 |
| Short name | T2572 |
| Test name | |
| Test status | |
| Simulation time | 94341838070 ps |
| CPU time | 1771.55 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 07:24:32 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-7552fcb0-8c4c-44fa-a18b-ba11e1d2b15c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908304008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_access_same_ device_slow_rsp.3908304008 |
| Directory | /workspace/75.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_and_unmapped_addr.2269373370 |
| Short name | T2436 |
| Test name | |
| Test status | |
| Simulation time | 258603484 ps |
| CPU time | 31.11 seconds |
| Started | Aug 17 06:55:07 PM PDT 24 |
| Finished | Aug 17 06:55:38 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-2b717546-2c72-4e5a-9953-e45a5e300c95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269373370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_and_unmapped_add r.2269373370 |
| Directory | /workspace/75.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_error_random.1949859663 |
| Short name | T1404 |
| Test name | |
| Test status | |
| Simulation time | 1344461607 ps |
| CPU time | 39.74 seconds |
| Started | Aug 17 06:55:09 PM PDT 24 |
| Finished | Aug 17 06:55:49 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-67c9b6a5-13af-48de-9b8f-ab0ffd3595da |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949859663 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_error_random.1949859663 |
| Directory | /workspace/75.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random.543825650 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2512903660 ps |
| CPU time | 83.54 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 06:56:24 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-6db76031-9162-4221-a15f-48e742349b5b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=543825650 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random.543825650 |
| Directory | /workspace/75.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_large_delays.2391667302 |
| Short name | T2244 |
| Test name | |
| Test status | |
| Simulation time | 45594926813 ps |
| CPU time | 517.12 seconds |
| Started | Aug 17 06:55:01 PM PDT 24 |
| Finished | Aug 17 07:03:39 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-f15617b0-10c0-48cc-8a44-76832d2ae523 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391667302 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_large_delays.2391667302 |
| Directory | /workspace/75.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_slow_rsp.3220361361 |
| Short name | T2283 |
| Test name | |
| Test status | |
| Simulation time | 49471446814 ps |
| CPU time | 907.91 seconds |
| Started | Aug 17 06:54:58 PM PDT 24 |
| Finished | Aug 17 07:10:07 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-6b650a84-e524-4714-957c-c6bbb94e9077 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220361361 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_slow_rsp.3220361361 |
| Directory | /workspace/75.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_random_zero_delays.3432788715 |
| Short name | T2506 |
| Test name | |
| Test status | |
| Simulation time | 66944057 ps |
| CPU time | 8.22 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 06:55:09 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-c7bdda72-297f-48b8-b870-daef9e08834a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432788715 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_random_zero_del ays.3432788715 |
| Directory | /workspace/75.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_same_source.1458321085 |
| Short name | T2029 |
| Test name | |
| Test status | |
| Simulation time | 1955190853 ps |
| CPU time | 54.84 seconds |
| Started | Aug 17 06:55:06 PM PDT 24 |
| Finished | Aug 17 06:56:01 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-361c4011-5793-4b7e-8347-676ef9e35103 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458321085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_same_source.1458321085 |
| Directory | /workspace/75.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke.3035368307 |
| Short name | T2699 |
| Test name | |
| Test status | |
| Simulation time | 45783965 ps |
| CPU time | 6.23 seconds |
| Started | Aug 17 06:54:59 PM PDT 24 |
| Finished | Aug 17 06:55:06 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-3141bdbf-47b3-421d-9e15-7a37858c0ba3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035368307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke.3035368307 |
| Directory | /workspace/75.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_large_delays.1849679395 |
| Short name | T2553 |
| Test name | |
| Test status | |
| Simulation time | 8693642430 ps |
| CPU time | 84.75 seconds |
| Started | Aug 17 06:55:01 PM PDT 24 |
| Finished | Aug 17 06:56:26 PM PDT 24 |
| Peak memory | 573480 kb |
| Host | smart-3437b5ca-84af-4bb8-98f7-915c2517f0e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849679395 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_large_delays.1849679395 |
| Directory | /workspace/75.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_slow_rsp.3914242771 |
| Short name | T2069 |
| Test name | |
| Test status | |
| Simulation time | 5021487892 ps |
| CPU time | 85.54 seconds |
| Started | Aug 17 06:55:00 PM PDT 24 |
| Finished | Aug 17 06:56:26 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-897b5b65-32ba-4c53-bbd3-63184fd18ab3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3914242771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_slow_rsp.3914242771 |
| Directory | /workspace/75.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_smoke_zero_delays.3005293810 |
| Short name | T2546 |
| Test name | |
| Test status | |
| Simulation time | 44684273 ps |
| CPU time | 5.92 seconds |
| Started | Aug 17 06:55:03 PM PDT 24 |
| Finished | Aug 17 06:55:09 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-2b58645d-b9c3-417b-8caa-fcd7dc604179 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005293810 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_smoke_zero_delay s.3005293810 |
| Directory | /workspace/75.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all.553933655 |
| Short name | T2853 |
| Test name | |
| Test status | |
| Simulation time | 7654817268 ps |
| CPU time | 262.76 seconds |
| Started | Aug 17 06:55:16 PM PDT 24 |
| Finished | Aug 17 06:59:39 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-87d86916-36cf-4816-8764-3842eab1ae8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=553933655 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all.553933655 |
| Directory | /workspace/75.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_error.3759498900 |
| Short name | T1520 |
| Test name | |
| Test status | |
| Simulation time | 6100139390 ps |
| CPU time | 465.91 seconds |
| Started | Aug 17 06:55:16 PM PDT 24 |
| Finished | Aug 17 07:03:02 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-828083c9-5544-415a-b414-4aa26d7fb180 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759498900 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all_with_error.3759498900 |
| Directory | /workspace/75.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_rand_reset.3864341028 |
| Short name | T2504 |
| Test name | |
| Test status | |
| Simulation time | 6820832546 ps |
| CPU time | 393.43 seconds |
| Started | Aug 17 06:55:12 PM PDT 24 |
| Finished | Aug 17 07:01:46 PM PDT 24 |
| Peak memory | 576388 kb |
| Host | smart-575443cc-d053-4d36-9816-c9819fce0092 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864341028 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_all _with_rand_reset.3864341028 |
| Directory | /workspace/75.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_stress_all_with_reset_error.2581028531 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 444785066 ps |
| CPU time | 123.67 seconds |
| Started | Aug 17 06:55:08 PM PDT 24 |
| Finished | Aug 17 06:57:11 PM PDT 24 |
| Peak memory | 576320 kb |
| Host | smart-352d6317-6df4-420b-b465-a62253419392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581028531 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_stress_al l_with_reset_error.2581028531 |
| Directory | /workspace/75.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/75.xbar_unmapped_addr.1859034790 |
| Short name | T2472 |
| Test name | |
| Test status | |
| Simulation time | 1344270798 ps |
| CPU time | 53.85 seconds |
| Started | Aug 17 06:55:07 PM PDT 24 |
| Finished | Aug 17 06:56:01 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-7c18a1fc-7751-49b8-b5b0-1e1f46fb49df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859034790 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 75.xbar_unmapped_addr.1859034790 |
| Directory | /workspace/75.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_access_same_device.3575208020 |
| Short name | T2859 |
| Test name | |
| Test status | |
| Simulation time | 192711868 ps |
| CPU time | 16.03 seconds |
| Started | Aug 17 06:55:13 PM PDT 24 |
| Finished | Aug 17 06:55:29 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-6e662428-b874-4ce3-ba50-79792bf48423 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575208020 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_access_same_device .3575208020 |
| Directory | /workspace/76.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_and_unmapped_addr.2879908771 |
| Short name | T2635 |
| Test name | |
| Test status | |
| Simulation time | 367169775 ps |
| CPU time | 15.73 seconds |
| Started | Aug 17 06:55:14 PM PDT 24 |
| Finished | Aug 17 06:55:30 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-d4b7ec0f-6810-4b5a-a145-5030b9be40e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2879908771 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_and_unmapped_add r.2879908771 |
| Directory | /workspace/76.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_error_random.1535980079 |
| Short name | T1453 |
| Test name | |
| Test status | |
| Simulation time | 42549568 ps |
| CPU time | 6.21 seconds |
| Started | Aug 17 06:55:14 PM PDT 24 |
| Finished | Aug 17 06:55:20 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-ea027fb5-3fcd-4763-8ecc-ab625a032507 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535980079 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_error_random.1535980079 |
| Directory | /workspace/76.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random.737093556 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 539172334 ps |
| CPU time | 51.78 seconds |
| Started | Aug 17 06:55:08 PM PDT 24 |
| Finished | Aug 17 06:56:00 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-5f31ad14-d375-4b19-96b4-b3385cb11a36 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737093556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random.737093556 |
| Directory | /workspace/76.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_large_delays.2019808318 |
| Short name | T2024 |
| Test name | |
| Test status | |
| Simulation time | 51838599135 ps |
| CPU time | 613 seconds |
| Started | Aug 17 06:55:07 PM PDT 24 |
| Finished | Aug 17 07:05:20 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-4c6307fc-45b2-434d-b932-fa67f5c23fd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019808318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_large_delays.2019808318 |
| Directory | /workspace/76.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_slow_rsp.1255407027 |
| Short name | T1900 |
| Test name | |
| Test status | |
| Simulation time | 70305653385 ps |
| CPU time | 1300.36 seconds |
| Started | Aug 17 06:55:16 PM PDT 24 |
| Finished | Aug 17 07:16:57 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-cc7c992a-750e-47ed-a375-7a1e6444d038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255407027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_slow_rsp.1255407027 |
| Directory | /workspace/76.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_random_zero_delays.3322241016 |
| Short name | T2357 |
| Test name | |
| Test status | |
| Simulation time | 520288952 ps |
| CPU time | 41.66 seconds |
| Started | Aug 17 06:55:08 PM PDT 24 |
| Finished | Aug 17 06:55:50 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-b3a40e31-ddd5-4f7a-9486-942e3c7276f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322241016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_random_zero_del ays.3322241016 |
| Directory | /workspace/76.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_same_source.1495734448 |
| Short name | T2078 |
| Test name | |
| Test status | |
| Simulation time | 426124802 ps |
| CPU time | 28.07 seconds |
| Started | Aug 17 06:55:14 PM PDT 24 |
| Finished | Aug 17 06:55:42 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-03cfe782-c880-4a75-8269-0aeb01403788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495734448 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_same_source.1495734448 |
| Directory | /workspace/76.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke.3007946712 |
| Short name | T2732 |
| Test name | |
| Test status | |
| Simulation time | 42771679 ps |
| CPU time | 6.06 seconds |
| Started | Aug 17 06:55:13 PM PDT 24 |
| Finished | Aug 17 06:55:19 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-d58e5ece-d32e-4922-b8ef-c56eaec7dcc1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007946712 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke.3007946712 |
| Directory | /workspace/76.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_large_delays.1918826418 |
| Short name | T1431 |
| Test name | |
| Test status | |
| Simulation time | 7936400215 ps |
| CPU time | 91.84 seconds |
| Started | Aug 17 06:55:08 PM PDT 24 |
| Finished | Aug 17 06:56:40 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-e659f796-ede5-44f1-8feb-05b4cc8ac8bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918826418 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_large_delays.1918826418 |
| Directory | /workspace/76.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_slow_rsp.438488615 |
| Short name | T2788 |
| Test name | |
| Test status | |
| Simulation time | 5842021051 ps |
| CPU time | 94.3 seconds |
| Started | Aug 17 06:55:09 PM PDT 24 |
| Finished | Aug 17 06:56:43 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-9b6b7735-b96a-4f89-8c76-191f20c51b60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=438488615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_slow_rsp.438488615 |
| Directory | /workspace/76.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_smoke_zero_delays.1203965535 |
| Short name | T2000 |
| Test name | |
| Test status | |
| Simulation time | 35054716 ps |
| CPU time | 6.06 seconds |
| Started | Aug 17 06:55:08 PM PDT 24 |
| Finished | Aug 17 06:55:14 PM PDT 24 |
| Peak memory | 573344 kb |
| Host | smart-e455c0c3-30b4-467f-a002-9664c722ec9c |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203965535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_smoke_zero_delay s.1203965535 |
| Directory | /workspace/76.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all.2265489553 |
| Short name | T1852 |
| Test name | |
| Test status | |
| Simulation time | 6334543206 ps |
| CPU time | 221.79 seconds |
| Started | Aug 17 06:55:09 PM PDT 24 |
| Finished | Aug 17 06:58:51 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-8ffde4fb-9512-4e20-964a-440c87832547 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265489553 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all.2265489553 |
| Directory | /workspace/76.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_error.1722997059 |
| Short name | T1666 |
| Test name | |
| Test status | |
| Simulation time | 1413387080 ps |
| CPU time | 99.49 seconds |
| Started | Aug 17 06:55:19 PM PDT 24 |
| Finished | Aug 17 06:56:59 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-8482b28a-5672-47cb-b7cc-b625b8a5a41a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722997059 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all_with_error.1722997059 |
| Directory | /workspace/76.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_rand_reset.1380959831 |
| Short name | T2124 |
| Test name | |
| Test status | |
| Simulation time | 4070449183 ps |
| CPU time | 212.09 seconds |
| Started | Aug 17 06:55:14 PM PDT 24 |
| Finished | Aug 17 06:58:46 PM PDT 24 |
| Peak memory | 576364 kb |
| Host | smart-25c6c085-887a-4507-b529-877b02f5e4ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380959831 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_all _with_rand_reset.1380959831 |
| Directory | /workspace/76.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_stress_all_with_reset_error.2110335066 |
| Short name | T2228 |
| Test name | |
| Test status | |
| Simulation time | 2807338918 ps |
| CPU time | 235.16 seconds |
| Started | Aug 17 06:55:29 PM PDT 24 |
| Finished | Aug 17 06:59:24 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-e6e8b5a1-a07a-4d2b-be7e-a1596344910d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110335066 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_stress_al l_with_reset_error.2110335066 |
| Directory | /workspace/76.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/76.xbar_unmapped_addr.4153764925 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 228378575 ps |
| CPU time | 26.58 seconds |
| Started | Aug 17 06:55:08 PM PDT 24 |
| Finished | Aug 17 06:55:35 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-63c92c60-8b9f-4287-b5f1-3e3234f29259 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153764925 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 76.xbar_unmapped_addr.4153764925 |
| Directory | /workspace/76.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device.2027598836 |
| Short name | T2567 |
| Test name | |
| Test status | |
| Simulation time | 679075563 ps |
| CPU time | 44.24 seconds |
| Started | Aug 17 06:55:18 PM PDT 24 |
| Finished | Aug 17 06:56:02 PM PDT 24 |
| Peak memory | 575316 kb |
| Host | smart-08882d5f-355a-4d27-87c9-aafd1b8c23c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027598836 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_device .2027598836 |
| Directory | /workspace/77.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_access_same_device_slow_rsp.1055200582 |
| Short name | T1683 |
| Test name | |
| Test status | |
| Simulation time | 53563646248 ps |
| CPU time | 1002.45 seconds |
| Started | Aug 17 06:55:14 PM PDT 24 |
| Finished | Aug 17 07:11:57 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-e257bd74-d5c4-40d6-9056-16811e782038 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055200582 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_access_same_ device_slow_rsp.1055200582 |
| Directory | /workspace/77.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.1612842233 |
| Short name | T2653 |
| Test name | |
| Test status | |
| Simulation time | 1328930625 ps |
| CPU time | 46.76 seconds |
| Started | Aug 17 06:55:22 PM PDT 24 |
| Finished | Aug 17 06:56:08 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-ff13c3a9-a62a-4787-9e7b-c3a59fd7b400 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612842233 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_and_unmapped_add r.1612842233 |
| Directory | /workspace/77.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_error_random.36177370 |
| Short name | T1785 |
| Test name | |
| Test status | |
| Simulation time | 537404347 ps |
| CPU time | 44.38 seconds |
| Started | Aug 17 06:55:18 PM PDT 24 |
| Finished | Aug 17 06:56:03 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-9ccf0ac2-365f-4e10-946d-de68a5f52d02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36177370 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_error_random.36177370 |
| Directory | /workspace/77.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random.1899654734 |
| Short name | T2818 |
| Test name | |
| Test status | |
| Simulation time | 147089595 ps |
| CPU time | 14.18 seconds |
| Started | Aug 17 06:55:16 PM PDT 24 |
| Finished | Aug 17 06:55:30 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-f9cbc634-a2a9-4537-b6f1-92b8514d475c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899654734 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random.1899654734 |
| Directory | /workspace/77.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_large_delays.1875646447 |
| Short name | T2260 |
| Test name | |
| Test status | |
| Simulation time | 65359582511 ps |
| CPU time | 738.79 seconds |
| Started | Aug 17 06:55:16 PM PDT 24 |
| Finished | Aug 17 07:07:35 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-2982b31b-fdb3-448c-ae9c-a9a82c8ea054 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875646447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_large_delays.1875646447 |
| Directory | /workspace/77.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_slow_rsp.2497283367 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 54924482594 ps |
| CPU time | 1036.87 seconds |
| Started | Aug 17 06:55:28 PM PDT 24 |
| Finished | Aug 17 07:12:45 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-56ecc4fb-95a6-41b7-aa32-c1e9484d4ba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497283367 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_slow_rsp.2497283367 |
| Directory | /workspace/77.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_random_zero_delays.1800334470 |
| Short name | T2748 |
| Test name | |
| Test status | |
| Simulation time | 282728907 ps |
| CPU time | 25.31 seconds |
| Started | Aug 17 06:55:15 PM PDT 24 |
| Finished | Aug 17 06:55:41 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-87480d29-f3b0-4af2-b77e-fa35c1e98b30 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1800334470 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_random_zero_del ays.1800334470 |
| Directory | /workspace/77.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_same_source.3809071959 |
| Short name | T2936 |
| Test name | |
| Test status | |
| Simulation time | 675630349 ps |
| CPU time | 19.74 seconds |
| Started | Aug 17 06:55:14 PM PDT 24 |
| Finished | Aug 17 06:55:34 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-aad19805-6b2a-4e0e-b8a5-c42efc8af1f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809071959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_same_source.3809071959 |
| Directory | /workspace/77.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke.1793182825 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 176547074 ps |
| CPU time | 8.32 seconds |
| Started | Aug 17 06:55:16 PM PDT 24 |
| Finished | Aug 17 06:55:25 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-b94a8621-9865-46db-b0d8-af96a6c8fb79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793182825 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke.1793182825 |
| Directory | /workspace/77.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_large_delays.1478932682 |
| Short name | T1409 |
| Test name | |
| Test status | |
| Simulation time | 8475180153 ps |
| CPU time | 84.02 seconds |
| Started | Aug 17 06:55:16 PM PDT 24 |
| Finished | Aug 17 06:56:40 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-da358eb6-1e84-47ad-9d1e-223c2451f2f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1478932682 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_large_delays.1478932682 |
| Directory | /workspace/77.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_slow_rsp.1164157703 |
| Short name | T1633 |
| Test name | |
| Test status | |
| Simulation time | 3535684551 ps |
| CPU time | 61.2 seconds |
| Started | Aug 17 06:55:19 PM PDT 24 |
| Finished | Aug 17 06:56:20 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-0e69897b-0cd8-49b1-9b3a-4bd812433c70 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164157703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_slow_rsp.1164157703 |
| Directory | /workspace/77.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2497271237 |
| Short name | T1800 |
| Test name | |
| Test status | |
| Simulation time | 46331133 ps |
| CPU time | 5.65 seconds |
| Started | Aug 17 06:55:26 PM PDT 24 |
| Finished | Aug 17 06:55:32 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-bd8f0583-deb0-41b9-a95f-66f82b4ddf1e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497271237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_smoke_zero_delay s.2497271237 |
| Directory | /workspace/77.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all.3563042590 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2121915267 ps |
| CPU time | 75.74 seconds |
| Started | Aug 17 06:55:21 PM PDT 24 |
| Finished | Aug 17 06:56:37 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-1592de70-e236-48d9-9bd7-1ec8e8837a98 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563042590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all.3563042590 |
| Directory | /workspace/77.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_error.2156926091 |
| Short name | T2820 |
| Test name | |
| Test status | |
| Simulation time | 1260097265 ps |
| CPU time | 96.3 seconds |
| Started | Aug 17 06:55:21 PM PDT 24 |
| Finished | Aug 17 06:56:58 PM PDT 24 |
| Peak memory | 575624 kb |
| Host | smart-350bc83b-aace-426f-96a6-b17be1d47943 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156926091 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_with_error.2156926091 |
| Directory | /workspace/77.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.431902467 |
| Short name | T2140 |
| Test name | |
| Test status | |
| Simulation time | 127708330 ps |
| CPU time | 93.17 seconds |
| Started | Aug 17 06:55:22 PM PDT 24 |
| Finished | Aug 17 06:56:55 PM PDT 24 |
| Peak memory | 576184 kb |
| Host | smart-00b7b3e1-58d9-4c4e-80f8-9244d869f2b8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431902467 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_all_ with_rand_reset.431902467 |
| Directory | /workspace/77.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.3747286030 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 3583070413 ps |
| CPU time | 385.58 seconds |
| Started | Aug 17 06:55:22 PM PDT 24 |
| Finished | Aug 17 07:01:48 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-60266dbb-3d0b-499a-8c35-8e51b5595b61 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747286030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_stress_al l_with_reset_error.3747286030 |
| Directory | /workspace/77.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/77.xbar_unmapped_addr.3144410951 |
| Short name | T2922 |
| Test name | |
| Test status | |
| Simulation time | 36944874 ps |
| CPU time | 6.87 seconds |
| Started | Aug 17 06:55:14 PM PDT 24 |
| Finished | Aug 17 06:55:21 PM PDT 24 |
| Peak memory | 573580 kb |
| Host | smart-8374dd3f-2698-4c0c-9cdc-0f473ba0d5e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144410951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 77.xbar_unmapped_addr.3144410951 |
| Directory | /workspace/77.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device.2876250143 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 2980944024 ps |
| CPU time | 126.88 seconds |
| Started | Aug 17 06:55:23 PM PDT 24 |
| Finished | Aug 17 06:57:30 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-5825077d-3209-4f74-bf17-75385dadda49 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876250143 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_device .2876250143 |
| Directory | /workspace/78.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.2419484127 |
| Short name | T2746 |
| Test name | |
| Test status | |
| Simulation time | 89036138273 ps |
| CPU time | 1735.88 seconds |
| Started | Aug 17 06:55:23 PM PDT 24 |
| Finished | Aug 17 07:24:19 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-948365b1-5015-4eff-99dc-3dc5be12f8d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419484127 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_access_same_ device_slow_rsp.2419484127 |
| Directory | /workspace/78.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_and_unmapped_addr.1270654851 |
| Short name | T1792 |
| Test name | |
| Test status | |
| Simulation time | 206362290 ps |
| CPU time | 22.9 seconds |
| Started | Aug 17 06:55:22 PM PDT 24 |
| Finished | Aug 17 06:55:45 PM PDT 24 |
| Peak memory | 575564 kb |
| Host | smart-1826f28e-d5f0-43d1-b58e-8f66cf29a379 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270654851 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_and_unmapped_add r.1270654851 |
| Directory | /workspace/78.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_error_random.3461686697 |
| Short name | T2076 |
| Test name | |
| Test status | |
| Simulation time | 301025522 ps |
| CPU time | 12.78 seconds |
| Started | Aug 17 06:55:37 PM PDT 24 |
| Finished | Aug 17 06:55:50 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-46ba2b60-ea75-4944-9192-5e8bb0867e5c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461686697 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_error_random.3461686697 |
| Directory | /workspace/78.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random.2520945954 |
| Short name | T1886 |
| Test name | |
| Test status | |
| Simulation time | 640563029 ps |
| CPU time | 25.21 seconds |
| Started | Aug 17 06:55:24 PM PDT 24 |
| Finished | Aug 17 06:55:49 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-f730ade4-1cac-4384-9871-3fe4d8f16578 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520945954 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random.2520945954 |
| Directory | /workspace/78.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_large_delays.3645451727 |
| Short name | T1908 |
| Test name | |
| Test status | |
| Simulation time | 64567956381 ps |
| CPU time | 708.06 seconds |
| Started | Aug 17 06:55:22 PM PDT 24 |
| Finished | Aug 17 07:07:10 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-a60405c5-ec84-4fd4-9e09-8abbd1496aa9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645451727 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_large_delays.3645451727 |
| Directory | /workspace/78.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_slow_rsp.200466792 |
| Short name | T2580 |
| Test name | |
| Test status | |
| Simulation time | 18729394054 ps |
| CPU time | 344.49 seconds |
| Started | Aug 17 06:55:21 PM PDT 24 |
| Finished | Aug 17 07:01:05 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-e7157c8f-3423-4279-b97f-d061c3cfd89f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200466792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_slow_rsp.200466792 |
| Directory | /workspace/78.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_random_zero_delays.2636697115 |
| Short name | T2895 |
| Test name | |
| Test status | |
| Simulation time | 337431442 ps |
| CPU time | 32.34 seconds |
| Started | Aug 17 06:55:35 PM PDT 24 |
| Finished | Aug 17 06:56:08 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-1808608e-34f0-4054-83ec-062af23186de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2636697115 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_random_zero_del ays.2636697115 |
| Directory | /workspace/78.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_same_source.1024454839 |
| Short name | T2659 |
| Test name | |
| Test status | |
| Simulation time | 1331715930 ps |
| CPU time | 41.29 seconds |
| Started | Aug 17 06:55:21 PM PDT 24 |
| Finished | Aug 17 06:56:03 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-1fbfe620-2992-4c1a-9a94-53a6a0b563e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024454839 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_same_source.1024454839 |
| Directory | /workspace/78.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke.4107764945 |
| Short name | T1483 |
| Test name | |
| Test status | |
| Simulation time | 43297803 ps |
| CPU time | 6.37 seconds |
| Started | Aug 17 06:55:24 PM PDT 24 |
| Finished | Aug 17 06:55:30 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-39d867ed-6333-4f25-8e7b-452c17b1633a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107764945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke.4107764945 |
| Directory | /workspace/78.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.3016155008 |
| Short name | T2687 |
| Test name | |
| Test status | |
| Simulation time | 6527080544 ps |
| CPU time | 65.88 seconds |
| Started | Aug 17 06:55:20 PM PDT 24 |
| Finished | Aug 17 06:56:26 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-ca5164d1-94e2-4e80-9136-d37e5f70646f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016155008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_large_delays.3016155008 |
| Directory | /workspace/78.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_slow_rsp.3222658819 |
| Short name | T2185 |
| Test name | |
| Test status | |
| Simulation time | 5412912068 ps |
| CPU time | 95.04 seconds |
| Started | Aug 17 06:55:37 PM PDT 24 |
| Finished | Aug 17 06:57:12 PM PDT 24 |
| Peak memory | 573548 kb |
| Host | smart-0b9cc486-7d69-4602-af89-4860445365e8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222658819 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_slow_rsp.3222658819 |
| Directory | /workspace/78.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_smoke_zero_delays.2702447015 |
| Short name | T2107 |
| Test name | |
| Test status | |
| Simulation time | 43830031 ps |
| CPU time | 6.55 seconds |
| Started | Aug 17 06:55:21 PM PDT 24 |
| Finished | Aug 17 06:55:27 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-79d7394e-f43d-467f-b943-1569e6e6c421 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702447015 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_smoke_zero_delay s.2702447015 |
| Directory | /workspace/78.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all.2832709781 |
| Short name | T1934 |
| Test name | |
| Test status | |
| Simulation time | 2939689737 ps |
| CPU time | 215.32 seconds |
| Started | Aug 17 06:55:31 PM PDT 24 |
| Finished | Aug 17 06:59:07 PM PDT 24 |
| Peak memory | 575840 kb |
| Host | smart-47aa9553-a8c0-4023-a34f-cc96c9dda1c4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832709781 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all.2832709781 |
| Directory | /workspace/78.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_rand_reset.696075345 |
| Short name | T2250 |
| Test name | |
| Test status | |
| Simulation time | 216430386 ps |
| CPU time | 114.95 seconds |
| Started | Aug 17 06:55:23 PM PDT 24 |
| Finished | Aug 17 06:57:18 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-150414ff-f203-421e-9e1a-906900d602d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696075345 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_all_ with_rand_reset.696075345 |
| Directory | /workspace/78.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_stress_all_with_reset_error.3689138967 |
| Short name | T2747 |
| Test name | |
| Test status | |
| Simulation time | 13793304828 ps |
| CPU time | 612.01 seconds |
| Started | Aug 17 06:55:31 PM PDT 24 |
| Finished | Aug 17 07:05:43 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-ce9129e3-5fcd-49d9-b08e-31049f0af915 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689138967 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_stress_al l_with_reset_error.3689138967 |
| Directory | /workspace/78.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/78.xbar_unmapped_addr.3019674416 |
| Short name | T1529 |
| Test name | |
| Test status | |
| Simulation time | 356698011 ps |
| CPU time | 16.74 seconds |
| Started | Aug 17 06:55:37 PM PDT 24 |
| Finished | Aug 17 06:55:54 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-116216a6-0e29-4a41-9fe5-cd7ceec4c9c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019674416 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 78.xbar_unmapped_addr.3019674416 |
| Directory | /workspace/78.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device.1679464950 |
| Short name | T2539 |
| Test name | |
| Test status | |
| Simulation time | 1059921112 ps |
| CPU time | 84.09 seconds |
| Started | Aug 17 06:55:29 PM PDT 24 |
| Finished | Aug 17 06:56:53 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-9a2ea73b-58aa-44b9-bc2a-9ea40d0162aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679464950 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_device .1679464950 |
| Directory | /workspace/79.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_access_same_device_slow_rsp.922303070 |
| Short name | T1574 |
| Test name | |
| Test status | |
| Simulation time | 84119032365 ps |
| CPU time | 1596.3 seconds |
| Started | Aug 17 06:55:33 PM PDT 24 |
| Finished | Aug 17 07:22:10 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-4ece2abf-0dbe-4ddb-8942-05ce91cad20f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922303070 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_access_same_d evice_slow_rsp.922303070 |
| Directory | /workspace/79.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_and_unmapped_addr.2711349193 |
| Short name | T1725 |
| Test name | |
| Test status | |
| Simulation time | 1129056311 ps |
| CPU time | 42.43 seconds |
| Started | Aug 17 06:55:28 PM PDT 24 |
| Finished | Aug 17 06:56:11 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-8ecee898-4da5-4b3b-b6fd-d8309572d039 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711349193 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_and_unmapped_add r.2711349193 |
| Directory | /workspace/79.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_error_random.3044844955 |
| Short name | T2254 |
| Test name | |
| Test status | |
| Simulation time | 1330918306 ps |
| CPU time | 41.05 seconds |
| Started | Aug 17 06:55:27 PM PDT 24 |
| Finished | Aug 17 06:56:08 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-61195e83-1b0e-409e-8237-d1c90aa56742 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044844955 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_error_random.3044844955 |
| Directory | /workspace/79.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random.1591692300 |
| Short name | T2385 |
| Test name | |
| Test status | |
| Simulation time | 1665681415 ps |
| CPU time | 59.9 seconds |
| Started | Aug 17 06:55:27 PM PDT 24 |
| Finished | Aug 17 06:56:27 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-ed02b641-c611-457d-850b-e29c190a132c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591692300 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random.1591692300 |
| Directory | /workspace/79.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_large_delays.3065473128 |
| Short name | T2406 |
| Test name | |
| Test status | |
| Simulation time | 47319222784 ps |
| CPU time | 482.9 seconds |
| Started | Aug 17 06:55:29 PM PDT 24 |
| Finished | Aug 17 07:03:32 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-0e19b320-9a7e-4675-ae2d-4a7548fdc7c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065473128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_large_delays.3065473128 |
| Directory | /workspace/79.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_slow_rsp.2554440166 |
| Short name | T2226 |
| Test name | |
| Test status | |
| Simulation time | 55461677619 ps |
| CPU time | 1008.67 seconds |
| Started | Aug 17 06:55:33 PM PDT 24 |
| Finished | Aug 17 07:12:22 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-a07f97cd-4a12-4b74-ba3c-6fc5983bbcfe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554440166 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_slow_rsp.2554440166 |
| Directory | /workspace/79.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_random_zero_delays.3637173447 |
| Short name | T1918 |
| Test name | |
| Test status | |
| Simulation time | 126819770 ps |
| CPU time | 14.69 seconds |
| Started | Aug 17 06:55:27 PM PDT 24 |
| Finished | Aug 17 06:55:42 PM PDT 24 |
| Peak memory | 575328 kb |
| Host | smart-8c1be446-16ff-49ff-a590-adf3271a5177 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637173447 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_random_zero_del ays.3637173447 |
| Directory | /workspace/79.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_same_source.2327790090 |
| Short name | T1620 |
| Test name | |
| Test status | |
| Simulation time | 1613819667 ps |
| CPU time | 46.55 seconds |
| Started | Aug 17 06:55:31 PM PDT 24 |
| Finished | Aug 17 06:56:17 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-bce7b911-8a0a-4261-8ff1-8d88cae78831 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327790090 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_same_source.2327790090 |
| Directory | /workspace/79.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke.2882194351 |
| Short name | T1540 |
| Test name | |
| Test status | |
| Simulation time | 39434738 ps |
| CPU time | 5.74 seconds |
| Started | Aug 17 06:55:28 PM PDT 24 |
| Finished | Aug 17 06:55:34 PM PDT 24 |
| Peak memory | 574104 kb |
| Host | smart-f4f0b5a7-e6de-41dc-8d36-71c2d72543ed |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882194351 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke.2882194351 |
| Directory | /workspace/79.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_large_delays.3669284082 |
| Short name | T2278 |
| Test name | |
| Test status | |
| Simulation time | 8901974336 ps |
| CPU time | 88.5 seconds |
| Started | Aug 17 06:55:28 PM PDT 24 |
| Finished | Aug 17 06:56:56 PM PDT 24 |
| Peak memory | 574180 kb |
| Host | smart-f1f8aa80-9d03-4667-8504-6defaae15e8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669284082 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_large_delays.3669284082 |
| Directory | /workspace/79.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_slow_rsp.2778719332 |
| Short name | T2722 |
| Test name | |
| Test status | |
| Simulation time | 5799475567 ps |
| CPU time | 97.93 seconds |
| Started | Aug 17 06:55:31 PM PDT 24 |
| Finished | Aug 17 06:57:09 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-d33d45e7-742c-49c8-afda-dc0bfda553e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778719332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_slow_rsp.2778719332 |
| Directory | /workspace/79.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.3697164108 |
| Short name | T2353 |
| Test name | |
| Test status | |
| Simulation time | 40506884 ps |
| CPU time | 6.04 seconds |
| Started | Aug 17 06:55:28 PM PDT 24 |
| Finished | Aug 17 06:55:34 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-57aea692-638f-47a8-b4dd-02b2ea2a05f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697164108 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_smoke_zero_delay s.3697164108 |
| Directory | /workspace/79.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all.3156572204 |
| Short name | T2476 |
| Test name | |
| Test status | |
| Simulation time | 6662348149 ps |
| CPU time | 225.28 seconds |
| Started | Aug 17 06:55:38 PM PDT 24 |
| Finished | Aug 17 06:59:23 PM PDT 24 |
| Peak memory | 576316 kb |
| Host | smart-c906ebb1-7a44-483f-8ec8-f60323a73bc8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156572204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all.3156572204 |
| Directory | /workspace/79.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_error.994196310 |
| Short name | T2855 |
| Test name | |
| Test status | |
| Simulation time | 3092753664 ps |
| CPU time | 217.89 seconds |
| Started | Aug 17 06:55:31 PM PDT 24 |
| Finished | Aug 17 06:59:09 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-29aef8d7-411c-43fa-a044-4b58b3002361 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994196310 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_with_error.994196310 |
| Directory | /workspace/79.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_rand_reset.4125486524 |
| Short name | T2087 |
| Test name | |
| Test status | |
| Simulation time | 255873821 ps |
| CPU time | 156.77 seconds |
| Started | Aug 17 06:55:32 PM PDT 24 |
| Finished | Aug 17 06:58:09 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-1d599f65-e0d4-4e5a-a452-50b53cfdd78a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125486524 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all _with_rand_reset.4125486524 |
| Directory | /workspace/79.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_stress_all_with_reset_error.34655739 |
| Short name | T1632 |
| Test name | |
| Test status | |
| Simulation time | 3995408717 ps |
| CPU time | 454.25 seconds |
| Started | Aug 17 06:55:33 PM PDT 24 |
| Finished | Aug 17 07:03:08 PM PDT 24 |
| Peak memory | 576416 kb |
| Host | smart-ba8fbe28-7869-4999-a729-8b17026c9c1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34655739 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_stress_all_ with_reset_error.34655739 |
| Directory | /workspace/79.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/79.xbar_unmapped_addr.3642059130 |
| Short name | T1584 |
| Test name | |
| Test status | |
| Simulation time | 24362676 ps |
| CPU time | 5.7 seconds |
| Started | Aug 17 06:55:29 PM PDT 24 |
| Finished | Aug 17 06:55:34 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-1f61dff3-29b4-4ea5-9a02-7a33a065eb91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642059130 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 79.xbar_unmapped_addr.3642059130 |
| Directory | /workspace/79.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_mem_rw_with_rand_reset.1991668709 |
| Short name | T2231 |
| Test name | |
| Test status | |
| Simulation time | 12139766896 ps |
| CPU time | 1029.22 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 07:05:06 PM PDT 24 |
| Peak memory | 652928 kb |
| Host | smart-07db6a35-483c-4e82-85f6-b8a8d0469fba |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991668709 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 8.chip_csr_mem_rw_with_rand_reset.1991668709 |
| Directory | /workspace/8.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_csr_rw.2156057287 |
| Short name | T2719 |
| Test name | |
| Test status | |
| Simulation time | 3739708072 ps |
| CPU time | 286.37 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:52:36 PM PDT 24 |
| Peak memory | 598620 kb |
| Host | smart-4470b53d-e045-4408-ae28-c3b1657f649f |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156057287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_csr_rw.2156057287 |
| Directory | /workspace/8.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_same_csr_outstanding.3318205222 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 33363009324 ps |
| CPU time | 3386.14 seconds |
| Started | Aug 17 06:47:41 PM PDT 24 |
| Finished | Aug 17 07:44:07 PM PDT 24 |
| Peak memory | 593728 kb |
| Host | smart-f4db98a2-d1c4-49ae-887e-3c62e413bb18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3318205222 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 8.chip_same_csr_outstanding.3318205222 |
| Directory | /workspace/8.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/8.chip_tl_errors.31887538 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 4319407800 ps |
| CPU time | 294.54 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:52:39 PM PDT 24 |
| Peak memory | 603908 kb |
| Host | smart-71764fc6-940d-4952-93c4-e5f25b625ee5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31887538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.chip_tl_errors.31887538 |
| Directory | /workspace/8.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device.415846653 |
| Short name | T1772 |
| Test name | |
| Test status | |
| Simulation time | 302541954 ps |
| CPU time | 20.22 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:48:10 PM PDT 24 |
| Peak memory | 575504 kb |
| Host | smart-c7c11dc3-c455-400e-a261-3df151acfa94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415846653 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_device.415846653 |
| Directory | /workspace/8.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.284457581 |
| Short name | T1927 |
| Test name | |
| Test status | |
| Simulation time | 47671025563 ps |
| CPU time | 799.21 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 07:01:11 PM PDT 24 |
| Peak memory | 575440 kb |
| Host | smart-ea36c61a-0713-4a08-ba2d-078e2e9b5d4f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284457581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_access_same_de vice_slow_rsp.284457581 |
| Directory | /workspace/8.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_and_unmapped_addr.33573204 |
| Short name | T1664 |
| Test name | |
| Test status | |
| Simulation time | 63782274 ps |
| CPU time | 5.58 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:47:54 PM PDT 24 |
| Peak memory | 573376 kb |
| Host | smart-b1e3aa23-7912-47e1-ac1a-b2932bd9e94d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33573204 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_and_unmapped_addr.33573204 |
| Directory | /workspace/8.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_error_random.3167946567 |
| Short name | T2828 |
| Test name | |
| Test status | |
| Simulation time | 570320695 ps |
| CPU time | 19.77 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:08 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-50b4a6ce-b73a-449c-a56d-5e9847c6bba2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167946567 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_error_random.3167946567 |
| Directory | /workspace/8.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random.1092809296 |
| Short name | T2298 |
| Test name | |
| Test status | |
| Simulation time | 2264771143 ps |
| CPU time | 71.04 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:49:02 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-a8a08848-295b-47ab-bdbd-b02b8cfca025 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092809296 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random.1092809296 |
| Directory | /workspace/8.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_large_delays.2040134896 |
| Short name | T1705 |
| Test name | |
| Test status | |
| Simulation time | 52916165965 ps |
| CPU time | 534.33 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:56:43 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-bbca9d6e-5034-4a8b-b8b0-02accea7b33f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040134896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_large_delays.2040134896 |
| Directory | /workspace/8.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.2667845541 |
| Short name | T1474 |
| Test name | |
| Test status | |
| Simulation time | 6059138718 ps |
| CPU time | 101.37 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:49:31 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-736b9934-a7ab-4ce5-9d72-af3149ddd0d1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667845541 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_slow_rsp.2667845541 |
| Directory | /workspace/8.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_random_zero_delays.3640000997 |
| Short name | T2772 |
| Test name | |
| Test status | |
| Simulation time | 482865034 ps |
| CPU time | 40.63 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:29 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-633f5359-d446-42cc-acf4-ed81f8d365c7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3640000997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_random_zero_dela ys.3640000997 |
| Directory | /workspace/8.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_same_source.3462394386 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2547034159 ps |
| CPU time | 74.62 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:49:01 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-a93511ce-7d5a-4aab-82fe-83c01397be29 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462394386 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_same_source.3462394386 |
| Directory | /workspace/8.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke.1593943317 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 233975422 ps |
| CPU time | 9.49 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:47:55 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-03210359-5e10-41db-b9be-3599c67a4dbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593943317 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke.1593943317 |
| Directory | /workspace/8.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_large_delays.3367979771 |
| Short name | T1817 |
| Test name | |
| Test status | |
| Simulation time | 7753454524 ps |
| CPU time | 79.82 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:49:07 PM PDT 24 |
| Peak memory | 574168 kb |
| Host | smart-d3c0a07f-2fc5-48dc-bd0b-6efd02e75dd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3367979771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_large_delays.3367979771 |
| Directory | /workspace/8.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_slow_rsp.3614911806 |
| Short name | T2908 |
| Test name | |
| Test status | |
| Simulation time | 6349987813 ps |
| CPU time | 97.32 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:49:29 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-a50a70af-7340-4ea3-934c-187e6aeeec1a |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614911806 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_slow_rsp.3614911806 |
| Directory | /workspace/8.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_smoke_zero_delays.2194967868 |
| Short name | T2012 |
| Test name | |
| Test status | |
| Simulation time | 37922813 ps |
| CPU time | 5.52 seconds |
| Started | Aug 17 06:47:47 PM PDT 24 |
| Finished | Aug 17 06:47:52 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-dbfe98a8-8b05-4901-8a56-98c9f00997d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194967868 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_smoke_zero_delays .2194967868 |
| Directory | /workspace/8.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all.1437903535 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 6674920042 ps |
| CPU time | 273.73 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:52:18 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-1da360f1-d115-4d8f-bfe2-92535a64a907 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437903535 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all.1437903535 |
| Directory | /workspace/8.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_error.841270441 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 10868168223 ps |
| CPU time | 398.45 seconds |
| Started | Aug 17 06:47:57 PM PDT 24 |
| Finished | Aug 17 06:54:35 PM PDT 24 |
| Peak memory | 576372 kb |
| Host | smart-f689eade-40b8-4d33-a5b2-f0a421be041f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841270441 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_with_error.841270441 |
| Directory | /workspace/8.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_rand_reset.1018044889 |
| Short name | T2011 |
| Test name | |
| Test status | |
| Simulation time | 4849930827 ps |
| CPU time | 277.97 seconds |
| Started | Aug 17 06:47:51 PM PDT 24 |
| Finished | Aug 17 06:52:29 PM PDT 24 |
| Peak memory | 575284 kb |
| Host | smart-21b2d768-0167-47f8-9fe1-73be3b800e77 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018044889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all_ with_rand_reset.1018044889 |
| Directory | /workspace/8.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_stress_all_with_reset_error.1577794805 |
| Short name | T2466 |
| Test name | |
| Test status | |
| Simulation time | 6883441270 ps |
| CPU time | 572.35 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:57:21 PM PDT 24 |
| Peak memory | 576380 kb |
| Host | smart-a3db0d14-bc32-4422-94f0-65405330d608 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577794805 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_stress_all _with_reset_error.1577794805 |
| Directory | /workspace/8.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/8.xbar_unmapped_addr.4032996719 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 331755162 ps |
| CPU time | 35.34 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:26 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-d038682b-c1fa-4ef3-bb71-d0eb63078dbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032996719 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.xbar_unmapped_addr.4032996719 |
| Directory | /workspace/8.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device.2785242332 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2399735126 ps |
| CPU time | 98.01 seconds |
| Started | Aug 17 06:55:33 PM PDT 24 |
| Finished | Aug 17 06:57:11 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-4ec77ac5-79ff-4222-a6c6-d79b3a361bbd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785242332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_device .2785242332 |
| Directory | /workspace/80.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_access_same_device_slow_rsp.4267703507 |
| Short name | T2827 |
| Test name | |
| Test status | |
| Simulation time | 118156549837 ps |
| CPU time | 1945.41 seconds |
| Started | Aug 17 06:55:40 PM PDT 24 |
| Finished | Aug 17 07:28:05 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-58d5fa1c-8366-4fbb-81a4-a2efee735c54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267703507 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_access_same_ device_slow_rsp.4267703507 |
| Directory | /workspace/80.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_and_unmapped_addr.319889507 |
| Short name | T1929 |
| Test name | |
| Test status | |
| Simulation time | 51269691 ps |
| CPU time | 7.98 seconds |
| Started | Aug 17 06:55:34 PM PDT 24 |
| Finished | Aug 17 06:55:42 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-8e730627-05f2-494f-bf6a-1621658b53e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319889507 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_and_unmapped_addr .319889507 |
| Directory | /workspace/80.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_error_random.1688993502 |
| Short name | T2449 |
| Test name | |
| Test status | |
| Simulation time | 315751477 ps |
| CPU time | 26.64 seconds |
| Started | Aug 17 06:55:33 PM PDT 24 |
| Finished | Aug 17 06:56:00 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-ebba6c01-fcdb-4d52-910e-66c54c813e9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688993502 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_error_random.1688993502 |
| Directory | /workspace/80.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random.1752217185 |
| Short name | T1926 |
| Test name | |
| Test status | |
| Simulation time | 66250827 ps |
| CPU time | 8.69 seconds |
| Started | Aug 17 06:55:34 PM PDT 24 |
| Finished | Aug 17 06:55:43 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-d4329c63-a9eb-41e5-bff0-4927f059d74d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752217185 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random.1752217185 |
| Directory | /workspace/80.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_large_delays.848512552 |
| Short name | T1622 |
| Test name | |
| Test status | |
| Simulation time | 69338862280 ps |
| CPU time | 781.33 seconds |
| Started | Aug 17 06:55:33 PM PDT 24 |
| Finished | Aug 17 07:08:35 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-3f0c0ced-4a35-415f-bdaa-22098f248b75 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848512552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_large_delays.848512552 |
| Directory | /workspace/80.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_slow_rsp.3474779632 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 41372411487 ps |
| CPU time | 825.99 seconds |
| Started | Aug 17 06:55:35 PM PDT 24 |
| Finished | Aug 17 07:09:21 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-ca7f8a27-05b2-4fe4-879f-a0f33eaf055f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474779632 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_slow_rsp.3474779632 |
| Directory | /workspace/80.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_random_zero_delays.2847309148 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 504130163 ps |
| CPU time | 42.98 seconds |
| Started | Aug 17 06:55:37 PM PDT 24 |
| Finished | Aug 17 06:56:20 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-2aff381f-38d7-4a74-a629-4fb1a63bea48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847309148 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_random_zero_del ays.2847309148 |
| Directory | /workspace/80.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_same_source.747895717 |
| Short name | T2091 |
| Test name | |
| Test status | |
| Simulation time | 572958802 ps |
| CPU time | 36.97 seconds |
| Started | Aug 17 06:55:39 PM PDT 24 |
| Finished | Aug 17 06:56:16 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-3ded0138-7c27-4f42-be95-9ce3c593c5a2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=747895717 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_same_source.747895717 |
| Directory | /workspace/80.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke.596648226 |
| Short name | T2462 |
| Test name | |
| Test status | |
| Simulation time | 179759346 ps |
| CPU time | 8.03 seconds |
| Started | Aug 17 06:55:37 PM PDT 24 |
| Finished | Aug 17 06:55:45 PM PDT 24 |
| Peak memory | 574128 kb |
| Host | smart-108adf47-2714-4e9f-aefe-fccef065f2d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596648226 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke.596648226 |
| Directory | /workspace/80.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_large_delays.1861313946 |
| Short name | T2763 |
| Test name | |
| Test status | |
| Simulation time | 6942286885 ps |
| CPU time | 77.08 seconds |
| Started | Aug 17 06:55:34 PM PDT 24 |
| Finished | Aug 17 06:56:51 PM PDT 24 |
| Peak memory | 573460 kb |
| Host | smart-566095c5-b102-4087-aa2e-29d4c240a3e5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861313946 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_large_delays.1861313946 |
| Directory | /workspace/80.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.2439769113 |
| Short name | T1388 |
| Test name | |
| Test status | |
| Simulation time | 6266884825 ps |
| CPU time | 106.27 seconds |
| Started | Aug 17 06:55:34 PM PDT 24 |
| Finished | Aug 17 06:57:20 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-52d629e8-3944-4418-a79c-e2939ffb5228 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439769113 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_slow_rsp.2439769113 |
| Directory | /workspace/80.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_smoke_zero_delays.4100358642 |
| Short name | T1495 |
| Test name | |
| Test status | |
| Simulation time | 50313739 ps |
| CPU time | 6.8 seconds |
| Started | Aug 17 06:55:37 PM PDT 24 |
| Finished | Aug 17 06:55:43 PM PDT 24 |
| Peak memory | 574100 kb |
| Host | smart-45586c19-313b-49ba-afa1-f7526462fc0a |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100358642 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_smoke_zero_delay s.4100358642 |
| Directory | /workspace/80.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all.2647952222 |
| Short name | T2150 |
| Test name | |
| Test status | |
| Simulation time | 7955142337 ps |
| CPU time | 253.35 seconds |
| Started | Aug 17 06:55:35 PM PDT 24 |
| Finished | Aug 17 06:59:48 PM PDT 24 |
| Peak memory | 576412 kb |
| Host | smart-c8077e30-3f4a-46d5-a5b4-72ac57b03899 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647952222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all.2647952222 |
| Directory | /workspace/80.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.2429306615 |
| Short name | T1982 |
| Test name | |
| Test status | |
| Simulation time | 7349071271 ps |
| CPU time | 338.29 seconds |
| Started | Aug 17 06:55:47 PM PDT 24 |
| Finished | Aug 17 07:01:26 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-d2505ff4-f3ce-4ed6-a106-a79b9a420459 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429306615 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_all _with_rand_reset.2429306615 |
| Directory | /workspace/80.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_stress_all_with_reset_error.4131256471 |
| Short name | T1947 |
| Test name | |
| Test status | |
| Simulation time | 489077351 ps |
| CPU time | 195.36 seconds |
| Started | Aug 17 06:55:42 PM PDT 24 |
| Finished | Aug 17 06:58:57 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-24f0fbd1-a215-4dc9-96ec-d5c28041cb69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131256471 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_stress_al l_with_reset_error.4131256471 |
| Directory | /workspace/80.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/80.xbar_unmapped_addr.4145913462 |
| Short name | T1729 |
| Test name | |
| Test status | |
| Simulation time | 41749887 ps |
| CPU time | 8.35 seconds |
| Started | Aug 17 06:55:36 PM PDT 24 |
| Finished | Aug 17 06:55:44 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-5fc74477-6c5e-4239-993a-113b13deed88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145913462 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 80.xbar_unmapped_addr.4145913462 |
| Directory | /workspace/80.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device.4136496120 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 2710250627 ps |
| CPU time | 100.21 seconds |
| Started | Aug 17 06:55:40 PM PDT 24 |
| Finished | Aug 17 06:57:21 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-d7df33ea-df4a-416c-93bf-1e69a9a06a8e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136496120 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_device .4136496120 |
| Directory | /workspace/81.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_access_same_device_slow_rsp.3089396259 |
| Short name | T2505 |
| Test name | |
| Test status | |
| Simulation time | 8907401127 ps |
| CPU time | 151.53 seconds |
| Started | Aug 17 06:55:42 PM PDT 24 |
| Finished | Aug 17 06:58:14 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-adf2a8bc-1bc2-4a44-90d0-0f48b7eaed51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089396259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_access_same_ device_slow_rsp.3089396259 |
| Directory | /workspace/81.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_and_unmapped_addr.2032758030 |
| Short name | T1607 |
| Test name | |
| Test status | |
| Simulation time | 172611208 ps |
| CPU time | 10.26 seconds |
| Started | Aug 17 06:55:51 PM PDT 24 |
| Finished | Aug 17 06:56:01 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-72a7e892-5d90-4746-a7b9-728d22a36239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032758030 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_and_unmapped_add r.2032758030 |
| Directory | /workspace/81.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_error_random.1849416748 |
| Short name | T2410 |
| Test name | |
| Test status | |
| Simulation time | 406196859 ps |
| CPU time | 30.44 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:56:20 PM PDT 24 |
| Peak memory | 575400 kb |
| Host | smart-616ccf39-0600-4d23-a323-4ae3fe18b565 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849416748 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_error_random.1849416748 |
| Directory | /workspace/81.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random.351520626 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 1991920864 ps |
| CPU time | 64.22 seconds |
| Started | Aug 17 06:55:44 PM PDT 24 |
| Finished | Aug 17 06:56:48 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-280b83ec-d67e-44ed-8101-9f28b45bccf8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351520626 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random.351520626 |
| Directory | /workspace/81.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_large_delays.4002952583 |
| Short name | T1452 |
| Test name | |
| Test status | |
| Simulation time | 74236802797 ps |
| CPU time | 858.97 seconds |
| Started | Aug 17 06:55:42 PM PDT 24 |
| Finished | Aug 17 07:10:01 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-72dd8bb8-8c63-4299-8b98-24df5ac51bfc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002952583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_large_delays.4002952583 |
| Directory | /workspace/81.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_slow_rsp.4105272445 |
| Short name | T1921 |
| Test name | |
| Test status | |
| Simulation time | 65890682114 ps |
| CPU time | 1233.65 seconds |
| Started | Aug 17 06:55:45 PM PDT 24 |
| Finished | Aug 17 07:16:19 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-fb57e067-7ba7-4a6c-9cb5-0c1f8887dc48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105272445 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_slow_rsp.4105272445 |
| Directory | /workspace/81.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_random_zero_delays.3338217197 |
| Short name | T2455 |
| Test name | |
| Test status | |
| Simulation time | 145124030 ps |
| CPU time | 16.3 seconds |
| Started | Aug 17 06:55:42 PM PDT 24 |
| Finished | Aug 17 06:55:58 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-06516755-b956-42ce-9c76-eaf0ed529603 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338217197 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_random_zero_del ays.3338217197 |
| Directory | /workspace/81.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_same_source.1596722491 |
| Short name | T2396 |
| Test name | |
| Test status | |
| Simulation time | 2260125101 ps |
| CPU time | 64.94 seconds |
| Started | Aug 17 06:55:48 PM PDT 24 |
| Finished | Aug 17 06:56:53 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-8dba4197-3679-4947-a841-24789cf8623e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596722491 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_same_source.1596722491 |
| Directory | /workspace/81.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke.2595260039 |
| Short name | T2398 |
| Test name | |
| Test status | |
| Simulation time | 235921755 ps |
| CPU time | 8.98 seconds |
| Started | Aug 17 06:55:42 PM PDT 24 |
| Finished | Aug 17 06:55:51 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-5463200e-71ca-4ac9-bba7-88f8f94431e7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595260039 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke.2595260039 |
| Directory | /workspace/81.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_large_delays.2983608830 |
| Short name | T2501 |
| Test name | |
| Test status | |
| Simulation time | 8550295671 ps |
| CPU time | 93.69 seconds |
| Started | Aug 17 06:55:40 PM PDT 24 |
| Finished | Aug 17 06:57:14 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-cbe5d3be-601c-43fb-9a8c-e92c019ffa28 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983608830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_large_delays.2983608830 |
| Directory | /workspace/81.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_slow_rsp.2748127327 |
| Short name | T1802 |
| Test name | |
| Test status | |
| Simulation time | 5486927598 ps |
| CPU time | 89.9 seconds |
| Started | Aug 17 06:55:43 PM PDT 24 |
| Finished | Aug 17 06:57:13 PM PDT 24 |
| Peak memory | 574188 kb |
| Host | smart-81457e3b-dbb6-418b-b95e-b18932407cb8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748127327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_slow_rsp.2748127327 |
| Directory | /workspace/81.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_smoke_zero_delays.1999555716 |
| Short name | T2903 |
| Test name | |
| Test status | |
| Simulation time | 52922488 ps |
| CPU time | 6.45 seconds |
| Started | Aug 17 06:55:42 PM PDT 24 |
| Finished | Aug 17 06:55:49 PM PDT 24 |
| Peak memory | 573392 kb |
| Host | smart-fc97232d-cc69-430f-9c44-e4b3983a4bb1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999555716 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_smoke_zero_delay s.1999555716 |
| Directory | /workspace/81.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all.64802043 |
| Short name | T1651 |
| Test name | |
| Test status | |
| Simulation time | 22238038910 ps |
| CPU time | 876.63 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 07:10:26 PM PDT 24 |
| Peak memory | 576480 kb |
| Host | smart-a21cf683-2c27-4851-b3bc-624d97826242 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64802043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all.64802043 |
| Directory | /workspace/81.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_rand_reset.1616312721 |
| Short name | T1971 |
| Test name | |
| Test status | |
| Simulation time | 77684133 ps |
| CPU time | 37.9 seconds |
| Started | Aug 17 06:55:53 PM PDT 24 |
| Finished | Aug 17 06:56:31 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-4c691100-3588-45ca-a804-8b1564d6aa3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616312721 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_all _with_rand_reset.1616312721 |
| Directory | /workspace/81.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_stress_all_with_reset_error.4175300317 |
| Short name | T1745 |
| Test name | |
| Test status | |
| Simulation time | 472420269 ps |
| CPU time | 127.96 seconds |
| Started | Aug 17 06:55:48 PM PDT 24 |
| Finished | Aug 17 06:57:56 PM PDT 24 |
| Peak memory | 576324 kb |
| Host | smart-c0b00a20-324d-4cca-9d4a-3116bf73c95c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175300317 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_stress_al l_with_reset_error.4175300317 |
| Directory | /workspace/81.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/81.xbar_unmapped_addr.544910588 |
| Short name | T2590 |
| Test name | |
| Test status | |
| Simulation time | 40194486 ps |
| CPU time | 6.93 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:55:57 PM PDT 24 |
| Peak memory | 573568 kb |
| Host | smart-df62cbff-7f91-42aa-8c95-02923b8cbf48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544910588 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 81.xbar_unmapped_addr.544910588 |
| Directory | /workspace/81.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device.1574236324 |
| Short name | T1750 |
| Test name | |
| Test status | |
| Simulation time | 2395221695 ps |
| CPU time | 95.29 seconds |
| Started | Aug 17 06:55:54 PM PDT 24 |
| Finished | Aug 17 06:57:29 PM PDT 24 |
| Peak memory | 575432 kb |
| Host | smart-e450cc64-10c3-479a-ad4d-fefde76578ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574236324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_device .1574236324 |
| Directory | /workspace/82.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_access_same_device_slow_rsp.2263284342 |
| Short name | T1553 |
| Test name | |
| Test status | |
| Simulation time | 41463078483 ps |
| CPU time | 709.33 seconds |
| Started | Aug 17 06:55:48 PM PDT 24 |
| Finished | Aug 17 07:07:38 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-b51bac20-bf86-458a-8d91-2dee45bf9bfb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263284342 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_access_same_ device_slow_rsp.2263284342 |
| Directory | /workspace/82.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_and_unmapped_addr.3121342921 |
| Short name | T2561 |
| Test name | |
| Test status | |
| Simulation time | 189332483 ps |
| CPU time | 10.42 seconds |
| Started | Aug 17 06:55:58 PM PDT 24 |
| Finished | Aug 17 06:56:09 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-7891e834-a171-45bc-bcbe-1ab033049352 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121342921 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_and_unmapped_add r.3121342921 |
| Directory | /workspace/82.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_error_random.2592285388 |
| Short name | T1355 |
| Test name | |
| Test status | |
| Simulation time | 2398753387 ps |
| CPU time | 93.08 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:57:23 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-a2d6f02f-ef7b-4904-a08f-e0baf166ccd8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2592285388 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_error_random.2592285388 |
| Directory | /workspace/82.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random.2428902625 |
| Short name | T1779 |
| Test name | |
| Test status | |
| Simulation time | 1097842968 ps |
| CPU time | 38.29 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:56:28 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-e5cdb9fd-3e08-4d54-bb86-916619333217 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428902625 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random.2428902625 |
| Directory | /workspace/82.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_large_delays.2166230945 |
| Short name | T2924 |
| Test name | |
| Test status | |
| Simulation time | 72197822746 ps |
| CPU time | 666.82 seconds |
| Started | Aug 17 06:55:50 PM PDT 24 |
| Finished | Aug 17 07:06:57 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-88135b42-f45e-4217-b7e6-a2f5b5a9b027 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166230945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_large_delays.2166230945 |
| Directory | /workspace/82.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_slow_rsp.2234250412 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 7147417214 ps |
| CPU time | 124.83 seconds |
| Started | Aug 17 06:55:55 PM PDT 24 |
| Finished | Aug 17 06:58:00 PM PDT 24 |
| Peak memory | 575444 kb |
| Host | smart-575fab19-3586-4326-a2b9-6e913bf092ee |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234250412 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_slow_rsp.2234250412 |
| Directory | /workspace/82.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_random_zero_delays.2054252379 |
| Short name | T1420 |
| Test name | |
| Test status | |
| Simulation time | 184448030 ps |
| CPU time | 18.62 seconds |
| Started | Aug 17 06:55:53 PM PDT 24 |
| Finished | Aug 17 06:56:12 PM PDT 24 |
| Peak memory | 575356 kb |
| Host | smart-d7e01b6f-d87d-42f2-96d2-d09b1489dee7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2054252379 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_random_zero_del ays.2054252379 |
| Directory | /workspace/82.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_same_source.1009630068 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 1258811639 ps |
| CPU time | 41.07 seconds |
| Started | Aug 17 06:55:48 PM PDT 24 |
| Finished | Aug 17 06:56:29 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-5bf91a2f-26cc-4552-8cc4-74fde790e024 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1009630068 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_same_source.1009630068 |
| Directory | /workspace/82.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke.278837099 |
| Short name | T2669 |
| Test name | |
| Test status | |
| Simulation time | 59124118 ps |
| CPU time | 7.08 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:55:57 PM PDT 24 |
| Peak memory | 573492 kb |
| Host | smart-31c6a2f5-44c2-44e0-9b5d-b3ddea2b285d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278837099 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke.278837099 |
| Directory | /workspace/82.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3333364552 |
| Short name | T1712 |
| Test name | |
| Test status | |
| Simulation time | 8116698569 ps |
| CPU time | 79.6 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:57:09 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-b457e17d-b25a-4d28-853e-698dda06b814 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333364552 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_large_delays.3333364552 |
| Directory | /workspace/82.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_slow_rsp.2825677658 |
| Short name | T1614 |
| Test name | |
| Test status | |
| Simulation time | 3231636932 ps |
| CPU time | 50.25 seconds |
| Started | Aug 17 06:55:51 PM PDT 24 |
| Finished | Aug 17 06:56:41 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-8cadf2f3-479d-4cb7-b775-256675f0cc02 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825677658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_slow_rsp.2825677658 |
| Directory | /workspace/82.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_smoke_zero_delays.3689920497 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 44592789 ps |
| CPU time | 6.5 seconds |
| Started | Aug 17 06:55:49 PM PDT 24 |
| Finished | Aug 17 06:55:56 PM PDT 24 |
| Peak memory | 573364 kb |
| Host | smart-4ab756fb-70eb-4894-bd9e-07084913881e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689920497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_smoke_zero_delay s.3689920497 |
| Directory | /workspace/82.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all.1258874091 |
| Short name | T2551 |
| Test name | |
| Test status | |
| Simulation time | 5960581563 ps |
| CPU time | 256.42 seconds |
| Started | Aug 17 06:55:57 PM PDT 24 |
| Finished | Aug 17 07:00:14 PM PDT 24 |
| Peak memory | 575736 kb |
| Host | smart-2733aab7-d5f3-4f82-bdae-034fe67444ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258874091 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all.1258874091 |
| Directory | /workspace/82.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_error.1360122385 |
| Short name | T1998 |
| Test name | |
| Test status | |
| Simulation time | 297957119 ps |
| CPU time | 28.82 seconds |
| Started | Aug 17 06:56:06 PM PDT 24 |
| Finished | Aug 17 06:56:35 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-e1e6561f-d7ac-4e7c-a9ba-569e8a8389a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360122385 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_with_error.1360122385 |
| Directory | /workspace/82.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_rand_reset.715040688 |
| Short name | T2173 |
| Test name | |
| Test status | |
| Simulation time | 4436557334 ps |
| CPU time | 388.49 seconds |
| Started | Aug 17 06:56:07 PM PDT 24 |
| Finished | Aug 17 07:02:35 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-8c8bf7c5-35f5-4f80-b275-326f4250ce6a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715040688 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_all_ with_rand_reset.715040688 |
| Directory | /workspace/82.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1348912857 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 7588077217 ps |
| CPU time | 393.96 seconds |
| Started | Aug 17 06:55:55 PM PDT 24 |
| Finished | Aug 17 07:02:29 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-c1c36319-4d95-472e-93ef-7027e543c68d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348912857 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_stress_al l_with_reset_error.1348912857 |
| Directory | /workspace/82.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/82.xbar_unmapped_addr.3416105583 |
| Short name | T2522 |
| Test name | |
| Test status | |
| Simulation time | 69471234 ps |
| CPU time | 10.62 seconds |
| Started | Aug 17 06:55:54 PM PDT 24 |
| Finished | Aug 17 06:56:05 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-64ba0a72-2521-42ef-af33-22676e1d4188 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416105583 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 82.xbar_unmapped_addr.3416105583 |
| Directory | /workspace/82.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device.433657259 |
| Short name | T1776 |
| Test name | |
| Test status | |
| Simulation time | 529172992 ps |
| CPU time | 38.1 seconds |
| Started | Aug 17 06:55:57 PM PDT 24 |
| Finished | Aug 17 06:56:35 PM PDT 24 |
| Peak memory | 575408 kb |
| Host | smart-4109169c-d06e-428d-bebb-d9140e70d902 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433657259 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_device. 433657259 |
| Directory | /workspace/83.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_access_same_device_slow_rsp.2798016645 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 22323472193 ps |
| CPU time | 419.01 seconds |
| Started | Aug 17 06:55:55 PM PDT 24 |
| Finished | Aug 17 07:02:54 PM PDT 24 |
| Peak memory | 575664 kb |
| Host | smart-693853a0-175f-4a48-86ca-7dae3ce8e7fe |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798016645 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_access_same_ device_slow_rsp.2798016645 |
| Directory | /workspace/83.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_and_unmapped_addr.2696695572 |
| Short name | T1877 |
| Test name | |
| Test status | |
| Simulation time | 139603857 ps |
| CPU time | 16.47 seconds |
| Started | Aug 17 06:56:00 PM PDT 24 |
| Finished | Aug 17 06:56:17 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-c76f1c9f-17ee-424b-8185-b69a0113e51f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696695572 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_and_unmapped_add r.2696695572 |
| Directory | /workspace/83.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_error_random.1581246324 |
| Short name | T1511 |
| Test name | |
| Test status | |
| Simulation time | 1946148100 ps |
| CPU time | 69.17 seconds |
| Started | Aug 17 06:56:00 PM PDT 24 |
| Finished | Aug 17 06:57:10 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-e45bc78b-7163-4578-bb5e-f202f18848d3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581246324 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_error_random.1581246324 |
| Directory | /workspace/83.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random.2595642641 |
| Short name | T2492 |
| Test name | |
| Test status | |
| Simulation time | 961407125 ps |
| CPU time | 33.77 seconds |
| Started | Aug 17 06:55:55 PM PDT 24 |
| Finished | Aug 17 06:56:28 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-5d1d0fa7-1ad7-4c99-90dd-77cc2244f439 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595642641 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random.2595642641 |
| Directory | /workspace/83.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_large_delays.2743729022 |
| Short name | T2619 |
| Test name | |
| Test status | |
| Simulation time | 69783572757 ps |
| CPU time | 836.88 seconds |
| Started | Aug 17 06:56:06 PM PDT 24 |
| Finished | Aug 17 07:10:04 PM PDT 24 |
| Peak memory | 575592 kb |
| Host | smart-6ffc3794-3c23-419f-8b05-cef93c12b56b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2743729022 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_large_delays.2743729022 |
| Directory | /workspace/83.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_slow_rsp.1274400865 |
| Short name | T2817 |
| Test name | |
| Test status | |
| Simulation time | 57089927291 ps |
| CPU time | 963.89 seconds |
| Started | Aug 17 06:55:58 PM PDT 24 |
| Finished | Aug 17 07:12:02 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-625b319c-ab94-4e35-bad4-1588fb674403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274400865 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_slow_rsp.1274400865 |
| Directory | /workspace/83.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_random_zero_delays.1226421706 |
| Short name | T1801 |
| Test name | |
| Test status | |
| Simulation time | 598677596 ps |
| CPU time | 52.97 seconds |
| Started | Aug 17 06:55:56 PM PDT 24 |
| Finished | Aug 17 06:56:50 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-9cf8d8b5-16a5-4a33-8c4c-64fff13f2a82 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226421706 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_random_zero_del ays.1226421706 |
| Directory | /workspace/83.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_same_source.2259389097 |
| Short name | T2181 |
| Test name | |
| Test status | |
| Simulation time | 540254897 ps |
| CPU time | 36.95 seconds |
| Started | Aug 17 06:55:57 PM PDT 24 |
| Finished | Aug 17 06:56:34 PM PDT 24 |
| Peak memory | 575344 kb |
| Host | smart-283f2175-30a7-4a23-a925-28757ef887a3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259389097 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_same_source.2259389097 |
| Directory | /workspace/83.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke.904775705 |
| Short name | T1480 |
| Test name | |
| Test status | |
| Simulation time | 44503303 ps |
| CPU time | 6.28 seconds |
| Started | Aug 17 06:55:55 PM PDT 24 |
| Finished | Aug 17 06:56:02 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-b69f1187-ad11-420f-9e8b-6e3960b1772a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904775705 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke.904775705 |
| Directory | /workspace/83.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_large_delays.1309732896 |
| Short name | T2890 |
| Test name | |
| Test status | |
| Simulation time | 9636050267 ps |
| CPU time | 96.45 seconds |
| Started | Aug 17 06:56:06 PM PDT 24 |
| Finished | Aug 17 06:57:43 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-1a156210-2894-4399-8345-6c6cdf6c1777 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309732896 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_large_delays.1309732896 |
| Directory | /workspace/83.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_slow_rsp.3723155476 |
| Short name | T2037 |
| Test name | |
| Test status | |
| Simulation time | 3630984643 ps |
| CPU time | 59.33 seconds |
| Started | Aug 17 06:55:59 PM PDT 24 |
| Finished | Aug 17 06:56:58 PM PDT 24 |
| Peak memory | 573468 kb |
| Host | smart-22c82c42-9251-4896-bb8b-88f66a66f7ce |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723155476 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_slow_rsp.3723155476 |
| Directory | /workspace/83.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_smoke_zero_delays.1660226324 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 45487401 ps |
| CPU time | 6.72 seconds |
| Started | Aug 17 06:55:59 PM PDT 24 |
| Finished | Aug 17 06:56:05 PM PDT 24 |
| Peak memory | 574076 kb |
| Host | smart-22750be4-4c6f-4529-aa75-da1cfe88b312 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660226324 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_smoke_zero_delay s.1660226324 |
| Directory | /workspace/83.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all.1189536021 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2845050349 ps |
| CPU time | 210.59 seconds |
| Started | Aug 17 06:56:09 PM PDT 24 |
| Finished | Aug 17 06:59:39 PM PDT 24 |
| Peak memory | 575732 kb |
| Host | smart-258f6bd8-a630-4add-a5b5-d906a0a6ba52 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1189536021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all.1189536021 |
| Directory | /workspace/83.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_error.4238710589 |
| Short name | T2651 |
| Test name | |
| Test status | |
| Simulation time | 471965595 ps |
| CPU time | 37.87 seconds |
| Started | Aug 17 06:56:04 PM PDT 24 |
| Finished | Aug 17 06:56:42 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-311c98a1-df67-4f6a-8232-ddf3c60b5cd1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238710589 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_all_with_error.4238710589 |
| Directory | /workspace/83.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_stress_all_with_reset_error.3208489743 |
| Short name | T2826 |
| Test name | |
| Test status | |
| Simulation time | 503500145 ps |
| CPU time | 197.85 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 06:59:18 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-d573e938-98eb-43f2-ac6d-5134e5f473c6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208489743 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_stress_al l_with_reset_error.3208489743 |
| Directory | /workspace/83.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/83.xbar_unmapped_addr.1229555957 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 129584195 ps |
| CPU time | 16.44 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 06:56:18 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-867a2dcc-af9b-45fc-b1b3-29928ea8e141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229555957 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 83.xbar_unmapped_addr.1229555957 |
| Directory | /workspace/83.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device.4039934598 |
| Short name | T2721 |
| Test name | |
| Test status | |
| Simulation time | 17074439 ps |
| CPU time | 6.97 seconds |
| Started | Aug 17 06:56:00 PM PDT 24 |
| Finished | Aug 17 06:56:07 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-ac0bb2de-cb5c-4b07-b588-572471f0e55f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4039934598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_device .4039934598 |
| Directory | /workspace/84.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_access_same_device_slow_rsp.346625427 |
| Short name | T2585 |
| Test name | |
| Test status | |
| Simulation time | 2532848526 ps |
| CPU time | 43.74 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 06:56:45 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-50831348-5cb4-48cc-813a-6f7a3109070b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346625427 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_access_same_d evice_slow_rsp.346625427 |
| Directory | /workspace/84.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_and_unmapped_addr.1148027806 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 268476148 ps |
| CPU time | 30.2 seconds |
| Started | Aug 17 06:56:10 PM PDT 24 |
| Finished | Aug 17 06:56:40 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-930c8d1d-9157-4b54-9557-85d5bd0079b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148027806 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_and_unmapped_add r.1148027806 |
| Directory | /workspace/84.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_error_random.2728658546 |
| Short name | T2655 |
| Test name | |
| Test status | |
| Simulation time | 603190983 ps |
| CPU time | 45.98 seconds |
| Started | Aug 17 06:56:09 PM PDT 24 |
| Finished | Aug 17 06:56:55 PM PDT 24 |
| Peak memory | 575272 kb |
| Host | smart-120132bf-318e-433c-991c-496cfdd2a87c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2728658546 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_error_random.2728658546 |
| Directory | /workspace/84.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random.3696680168 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 378145444 ps |
| CPU time | 32.51 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 06:56:34 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-51a64a46-8409-4d03-a81e-546d912ca9ab |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696680168 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random.3696680168 |
| Directory | /workspace/84.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_large_delays.3645668454 |
| Short name | T1969 |
| Test name | |
| Test status | |
| Simulation time | 2906132336 ps |
| CPU time | 29.71 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 06:56:31 PM PDT 24 |
| Peak memory | 573544 kb |
| Host | smart-30796334-bedd-4977-94dd-0502f23568f9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645668454 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_large_delays.3645668454 |
| Directory | /workspace/84.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_slow_rsp.3889114027 |
| Short name | T2605 |
| Test name | |
| Test status | |
| Simulation time | 49925129475 ps |
| CPU time | 935.87 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 07:11:37 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-bbffab43-b761-4d62-bd00-d3bd873cd082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889114027 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_slow_rsp.3889114027 |
| Directory | /workspace/84.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_random_zero_delays.3135521807 |
| Short name | T2713 |
| Test name | |
| Test status | |
| Simulation time | 423914735 ps |
| CPU time | 38.17 seconds |
| Started | Aug 17 06:56:00 PM PDT 24 |
| Finished | Aug 17 06:56:38 PM PDT 24 |
| Peak memory | 575348 kb |
| Host | smart-d2ecab42-8608-4cce-a9bd-3bc29fd44b5e |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135521807 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_random_zero_del ays.3135521807 |
| Directory | /workspace/84.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_same_source.1267408942 |
| Short name | T2331 |
| Test name | |
| Test status | |
| Simulation time | 2460362872 ps |
| CPU time | 71.34 seconds |
| Started | Aug 17 06:56:02 PM PDT 24 |
| Finished | Aug 17 06:57:13 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-86d1b7a7-245e-4a21-b354-50dc8d1069d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1267408942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_same_source.1267408942 |
| Directory | /workspace/84.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke.734768661 |
| Short name | T1375 |
| Test name | |
| Test status | |
| Simulation time | 141115142 ps |
| CPU time | 7.35 seconds |
| Started | Aug 17 06:56:01 PM PDT 24 |
| Finished | Aug 17 06:56:08 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-bea41adc-6997-4755-a696-fce28147c7aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734768661 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke.734768661 |
| Directory | /workspace/84.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_large_delays.2448747532 |
| Short name | T2876 |
| Test name | |
| Test status | |
| Simulation time | 8335454706 ps |
| CPU time | 83.19 seconds |
| Started | Aug 17 06:56:05 PM PDT 24 |
| Finished | Aug 17 06:57:28 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-8eced7d7-1aff-46d0-849c-3dbefa629b7e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448747532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_large_delays.2448747532 |
| Directory | /workspace/84.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_slow_rsp.842902644 |
| Short name | T1685 |
| Test name | |
| Test status | |
| Simulation time | 3485613696 ps |
| CPU time | 56.32 seconds |
| Started | Aug 17 06:56:03 PM PDT 24 |
| Finished | Aug 17 06:57:00 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-7c432911-a063-4bba-999a-8f52a16298a1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842902644 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_slow_rsp.842902644 |
| Directory | /workspace/84.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_smoke_zero_delays.3979205978 |
| Short name | T1357 |
| Test name | |
| Test status | |
| Simulation time | 52673734 ps |
| CPU time | 6.44 seconds |
| Started | Aug 17 06:56:00 PM PDT 24 |
| Finished | Aug 17 06:56:07 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-04d394a5-3553-40b4-849d-59085d294cce |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979205978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_smoke_zero_delay s.3979205978 |
| Directory | /workspace/84.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all.3558786577 |
| Short name | T1572 |
| Test name | |
| Test status | |
| Simulation time | 1557544949 ps |
| CPU time | 121.42 seconds |
| Started | Aug 17 06:56:11 PM PDT 24 |
| Finished | Aug 17 06:58:12 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-95942d99-a5f0-4c3d-8f7c-62c122b4ef93 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558786577 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all.3558786577 |
| Directory | /workspace/84.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_error.3962766957 |
| Short name | T2008 |
| Test name | |
| Test status | |
| Simulation time | 7179427661 ps |
| CPU time | 269.86 seconds |
| Started | Aug 17 06:56:10 PM PDT 24 |
| Finished | Aug 17 07:00:40 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-bb64f401-1ae3-4aa7-9ba1-b073994f3b55 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3962766957 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_with_error.3962766957 |
| Directory | /workspace/84.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_stress_all_with_rand_reset.394358677 |
| Short name | T2197 |
| Test name | |
| Test status | |
| Simulation time | 287492606 ps |
| CPU time | 155.17 seconds |
| Started | Aug 17 06:56:13 PM PDT 24 |
| Finished | Aug 17 06:58:48 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-340434ae-3005-4d9c-9fd7-e550b0bf54f7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394358677 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_stress_all_ with_rand_reset.394358677 |
| Directory | /workspace/84.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.4095278056 |
| Short name | T1444 |
| Test name | |
| Test status | |
| Simulation time | 1232075033 ps |
| CPU time | 55.11 seconds |
| Started | Aug 17 06:56:11 PM PDT 24 |
| Finished | Aug 17 06:57:06 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-7b060e4b-15fa-4a87-a1cc-e516cfaf2fae |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095278056 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 84.xbar_unmapped_addr.4095278056 |
| Directory | /workspace/84.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device.312795267 |
| Short name | T2759 |
| Test name | |
| Test status | |
| Simulation time | 144774140 ps |
| CPU time | 18.98 seconds |
| Started | Aug 17 06:56:14 PM PDT 24 |
| Finished | Aug 17 06:56:33 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-6fd6e997-0291-414f-9fd0-b89b377066de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312795267 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_device. 312795267 |
| Directory | /workspace/85.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_access_same_device_slow_rsp.3648987139 |
| Short name | T1859 |
| Test name | |
| Test status | |
| Simulation time | 127125101030 ps |
| CPU time | 2318.09 seconds |
| Started | Aug 17 06:56:09 PM PDT 24 |
| Finished | Aug 17 07:34:47 PM PDT 24 |
| Peak memory | 575644 kb |
| Host | smart-c9c694ea-eb64-4ac2-8b0e-4f7201996c27 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648987139 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_access_same_ device_slow_rsp.3648987139 |
| Directory | /workspace/85.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_and_unmapped_addr.2822142599 |
| Short name | T2046 |
| Test name | |
| Test status | |
| Simulation time | 238753536 ps |
| CPU time | 24.42 seconds |
| Started | Aug 17 06:56:31 PM PDT 24 |
| Finished | Aug 17 06:56:55 PM PDT 24 |
| Peak memory | 575532 kb |
| Host | smart-8e4a8973-4d03-4b68-929e-df95ae05fd54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822142599 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_and_unmapped_add r.2822142599 |
| Directory | /workspace/85.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_error_random.227599826 |
| Short name | T1696 |
| Test name | |
| Test status | |
| Simulation time | 520134769 ps |
| CPU time | 38.3 seconds |
| Started | Aug 17 06:56:09 PM PDT 24 |
| Finished | Aug 17 06:56:48 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-30142b49-938c-47e4-afb6-87a2c331d1a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227599826 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_error_random.227599826 |
| Directory | /workspace/85.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random.362786338 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 509049222 ps |
| CPU time | 47.16 seconds |
| Started | Aug 17 06:56:08 PM PDT 24 |
| Finished | Aug 17 06:56:56 PM PDT 24 |
| Peak memory | 575520 kb |
| Host | smart-083fdb0b-d5a3-46e4-b908-105486c073bb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=362786338 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random.362786338 |
| Directory | /workspace/85.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_large_delays.954706497 |
| Short name | T1669 |
| Test name | |
| Test status | |
| Simulation time | 9440030884 ps |
| CPU time | 101.69 seconds |
| Started | Aug 17 06:56:10 PM PDT 24 |
| Finished | Aug 17 06:57:52 PM PDT 24 |
| Peak memory | 574208 kb |
| Host | smart-cc201433-b8ca-40d6-854e-974478e55245 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954706497 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_large_delays.954706497 |
| Directory | /workspace/85.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_slow_rsp.947493348 |
| Short name | T2640 |
| Test name | |
| Test status | |
| Simulation time | 18960801649 ps |
| CPU time | 322.31 seconds |
| Started | Aug 17 06:56:11 PM PDT 24 |
| Finished | Aug 17 07:01:33 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-7ec659d6-8cb2-4a9c-bb90-3278cd73c058 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947493348 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_slow_rsp.947493348 |
| Directory | /workspace/85.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_random_zero_delays.2248724771 |
| Short name | T1358 |
| Test name | |
| Test status | |
| Simulation time | 47081315 ps |
| CPU time | 6.93 seconds |
| Started | Aug 17 06:56:09 PM PDT 24 |
| Finished | Aug 17 06:56:16 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-02f9369f-bcba-43bd-9253-97c049898cf0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248724771 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_random_zero_del ays.2248724771 |
| Directory | /workspace/85.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_same_source.1566535147 |
| Short name | T2705 |
| Test name | |
| Test status | |
| Simulation time | 412447406 ps |
| CPU time | 27.86 seconds |
| Started | Aug 17 06:56:12 PM PDT 24 |
| Finished | Aug 17 06:56:39 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-d4de7ff5-3ac3-486d-be85-32cbb00dbebb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566535147 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_same_source.1566535147 |
| Directory | /workspace/85.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke.1127614222 |
| Short name | T1612 |
| Test name | |
| Test status | |
| Simulation time | 182969721 ps |
| CPU time | 8.74 seconds |
| Started | Aug 17 06:56:09 PM PDT 24 |
| Finished | Aug 17 06:56:18 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-04c09fb9-a2b4-4f39-9537-b6ae66641ad3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127614222 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke.1127614222 |
| Directory | /workspace/85.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_large_delays.2760594665 |
| Short name | T2626 |
| Test name | |
| Test status | |
| Simulation time | 9092985387 ps |
| CPU time | 102.83 seconds |
| Started | Aug 17 06:56:14 PM PDT 24 |
| Finished | Aug 17 06:57:57 PM PDT 24 |
| Peak memory | 574328 kb |
| Host | smart-ced78286-47de-4b7d-93d3-15b27fc1ee88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760594665 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_large_delays.2760594665 |
| Directory | /workspace/85.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_slow_rsp.822844748 |
| Short name | T2363 |
| Test name | |
| Test status | |
| Simulation time | 3491093330 ps |
| CPU time | 62.46 seconds |
| Started | Aug 17 06:56:08 PM PDT 24 |
| Finished | Aug 17 06:57:11 PM PDT 24 |
| Peak memory | 574160 kb |
| Host | smart-23ff2693-a208-4543-888d-82e254c15f07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=822844748 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_slow_rsp.822844748 |
| Directory | /workspace/85.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_smoke_zero_delays.1574630204 |
| Short name | T1405 |
| Test name | |
| Test status | |
| Simulation time | 43544592 ps |
| CPU time | 5.95 seconds |
| Started | Aug 17 06:56:08 PM PDT 24 |
| Finished | Aug 17 06:56:14 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-e8555b1b-5954-477a-9600-64c6212e98e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574630204 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_smoke_zero_delay s.1574630204 |
| Directory | /workspace/85.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all.3321105214 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2314766674 ps |
| CPU time | 155.81 seconds |
| Started | Aug 17 06:56:31 PM PDT 24 |
| Finished | Aug 17 06:59:07 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-f9ef8108-cccb-4338-9a26-623be7659a6e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321105214 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all.3321105214 |
| Directory | /workspace/85.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_error.4230226813 |
| Short name | T2345 |
| Test name | |
| Test status | |
| Simulation time | 15083178658 ps |
| CPU time | 597.57 seconds |
| Started | Aug 17 06:56:17 PM PDT 24 |
| Finished | Aug 17 07:06:15 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-10589770-3bd2-4495-afcd-03a2e30269ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4230226813 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all_with_error.4230226813 |
| Directory | /workspace/85.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.1889101396 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 274553752 ps |
| CPU time | 108.01 seconds |
| Started | Aug 17 06:56:31 PM PDT 24 |
| Finished | Aug 17 06:58:19 PM PDT 24 |
| Peak memory | 576268 kb |
| Host | smart-5dfb5ea7-5d21-41f6-acb3-c73fbdcca66f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889101396 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_rand_reset.1889101396 |
| Directory | /workspace/85.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_stress_all_with_reset_error.873761709 |
| Short name | T2798 |
| Test name | |
| Test status | |
| Simulation time | 168643627 ps |
| CPU time | 62.76 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:57:33 PM PDT 24 |
| Peak memory | 576220 kb |
| Host | smart-e0d7f091-58a2-4c45-9022-01173f3edfc5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873761709 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_stress_all _with_reset_error.873761709 |
| Directory | /workspace/85.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/85.xbar_unmapped_addr.4241632388 |
| Short name | T1534 |
| Test name | |
| Test status | |
| Simulation time | 1389386193 ps |
| CPU time | 52.81 seconds |
| Started | Aug 17 06:56:08 PM PDT 24 |
| Finished | Aug 17 06:57:01 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-782292b6-a157-4ecd-a136-9e04dc2d6082 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241632388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 85.xbar_unmapped_addr.4241632388 |
| Directory | /workspace/85.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device.2965190980 |
| Short name | T2105 |
| Test name | |
| Test status | |
| Simulation time | 2345011501 ps |
| CPU time | 96.44 seconds |
| Started | Aug 17 06:56:23 PM PDT 24 |
| Finished | Aug 17 06:57:59 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-1c7e4757-0401-4b47-a901-16d3a5df1fe6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2965190980 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_device .2965190980 |
| Directory | /workspace/86.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_access_same_device_slow_rsp.417977988 |
| Short name | T1790 |
| Test name | |
| Test status | |
| Simulation time | 11483180131 ps |
| CPU time | 193.09 seconds |
| Started | Aug 17 06:56:24 PM PDT 24 |
| Finished | Aug 17 06:59:37 PM PDT 24 |
| Peak memory | 574124 kb |
| Host | smart-ae822f96-6d84-4992-8722-e6ef09a4fe33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417977988 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_access_same_d evice_slow_rsp.417977988 |
| Directory | /workspace/86.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3538072004 |
| Short name | T1436 |
| Test name | |
| Test status | |
| Simulation time | 636961106 ps |
| CPU time | 27.02 seconds |
| Started | Aug 17 06:56:23 PM PDT 24 |
| Finished | Aug 17 06:56:50 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-598fa5c3-545e-4667-bd68-aa956ded504a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538072004 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_and_unmapped_add r.3538072004 |
| Directory | /workspace/86.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_error_random.4078480538 |
| Short name | T1352 |
| Test name | |
| Test status | |
| Simulation time | 518392007 ps |
| CPU time | 19.84 seconds |
| Started | Aug 17 06:56:23 PM PDT 24 |
| Finished | Aug 17 06:56:43 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-0e9db933-06cf-4ea4-a39d-c26ee65fdb3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078480538 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_error_random.4078480538 |
| Directory | /workspace/86.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random.2903256744 |
| Short name | T1753 |
| Test name | |
| Test status | |
| Simulation time | 104673979 ps |
| CPU time | 11.04 seconds |
| Started | Aug 17 06:56:20 PM PDT 24 |
| Finished | Aug 17 06:56:31 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-bb3593c0-9840-4557-ad73-adfd6bdbfb07 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903256744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random.2903256744 |
| Directory | /workspace/86.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_large_delays.1239235549 |
| Short name | T2829 |
| Test name | |
| Test status | |
| Simulation time | 5739547249 ps |
| CPU time | 57.97 seconds |
| Started | Aug 17 06:56:20 PM PDT 24 |
| Finished | Aug 17 06:57:18 PM PDT 24 |
| Peak memory | 573560 kb |
| Host | smart-d5f46877-e751-4b36-9d7d-8d4f589e6af0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239235549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_large_delays.1239235549 |
| Directory | /workspace/86.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_slow_rsp.862078617 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3587928753 ps |
| CPU time | 59.77 seconds |
| Started | Aug 17 06:56:19 PM PDT 24 |
| Finished | Aug 17 06:57:18 PM PDT 24 |
| Peak memory | 573476 kb |
| Host | smart-f6f6775e-6bf0-4c77-af18-f7bb98be57ae |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=862078617 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_slow_rsp.862078617 |
| Directory | /workspace/86.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_random_zero_delays.3590920563 |
| Short name | T2674 |
| Test name | |
| Test status | |
| Simulation time | 195887354 ps |
| CPU time | 21.4 seconds |
| Started | Aug 17 06:56:18 PM PDT 24 |
| Finished | Aug 17 06:56:39 PM PDT 24 |
| Peak memory | 575340 kb |
| Host | smart-5eff4d45-0494-4558-a288-9b03c7ba652d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590920563 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_random_zero_del ays.3590920563 |
| Directory | /workspace/86.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_same_source.1625758949 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 567665612 ps |
| CPU time | 38.34 seconds |
| Started | Aug 17 06:56:23 PM PDT 24 |
| Finished | Aug 17 06:57:02 PM PDT 24 |
| Peak memory | 575500 kb |
| Host | smart-8cdd5b03-2fbb-458f-8ac1-8161557a2329 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625758949 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_same_source.1625758949 |
| Directory | /workspace/86.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke.2666234245 |
| Short name | T2058 |
| Test name | |
| Test status | |
| Simulation time | 56470951 ps |
| CPU time | 7.08 seconds |
| Started | Aug 17 06:56:16 PM PDT 24 |
| Finished | Aug 17 06:56:23 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-92c923e3-b68e-43d7-b0c0-d3819c063d66 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2666234245 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke.2666234245 |
| Directory | /workspace/86.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_large_delays.4072347800 |
| Short name | T1441 |
| Test name | |
| Test status | |
| Simulation time | 7420878292 ps |
| CPU time | 73.92 seconds |
| Started | Aug 17 06:56:17 PM PDT 24 |
| Finished | Aug 17 06:57:31 PM PDT 24 |
| Peak memory | 574152 kb |
| Host | smart-bcfe6962-f5c5-403d-a0ed-a9fe95fbc295 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072347800 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_large_delays.4072347800 |
| Directory | /workspace/86.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_slow_rsp.16984457 |
| Short name | T1464 |
| Test name | |
| Test status | |
| Simulation time | 6128713018 ps |
| CPU time | 96.14 seconds |
| Started | Aug 17 06:56:16 PM PDT 24 |
| Finished | Aug 17 06:57:52 PM PDT 24 |
| Peak memory | 573500 kb |
| Host | smart-d3fa1377-c188-442b-8535-b78ba39c7e56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16984457 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_slow_rsp.16984457 |
| Directory | /workspace/86.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_smoke_zero_delays.1703526834 |
| Short name | T2822 |
| Test name | |
| Test status | |
| Simulation time | 48205463 ps |
| CPU time | 6.14 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:56:36 PM PDT 24 |
| Peak memory | 573348 kb |
| Host | smart-40912894-6f4c-4cb5-81f9-bd1a16166512 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703526834 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_smoke_zero_delay s.1703526834 |
| Directory | /workspace/86.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all.2039494426 |
| Short name | T2654 |
| Test name | |
| Test status | |
| Simulation time | 11432258886 ps |
| CPU time | 441.34 seconds |
| Started | Aug 17 06:56:28 PM PDT 24 |
| Finished | Aug 17 07:03:50 PM PDT 24 |
| Peak memory | 576428 kb |
| Host | smart-6b7a69a4-63c7-4f68-85c4-b889d3cf8330 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039494426 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all.2039494426 |
| Directory | /workspace/86.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_error.3282882540 |
| Short name | T2126 |
| Test name | |
| Test status | |
| Simulation time | 3238776756 ps |
| CPU time | 123.66 seconds |
| Started | Aug 17 06:56:27 PM PDT 24 |
| Finished | Aug 17 06:58:31 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-6942e02f-eeb8-49df-b9d7-f04b227c1a47 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282882540 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all_with_error.3282882540 |
| Directory | /workspace/86.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.2380851107 |
| Short name | T2114 |
| Test name | |
| Test status | |
| Simulation time | 2435332701 ps |
| CPU time | 274.91 seconds |
| Started | Aug 17 06:56:24 PM PDT 24 |
| Finished | Aug 17 07:00:59 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-b3d9ff6b-dce7-4620-920f-e2cb68650a13 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380851107 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_rand_reset.2380851107 |
| Directory | /workspace/86.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_stress_all_with_reset_error.245623236 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 16207724225 ps |
| CPU time | 729.73 seconds |
| Started | Aug 17 06:56:25 PM PDT 24 |
| Finished | Aug 17 07:08:35 PM PDT 24 |
| Peak memory | 576376 kb |
| Host | smart-36417809-3cc0-474e-b253-3ba964d2c1f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245623236 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_stress_all _with_reset_error.245623236 |
| Directory | /workspace/86.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/86.xbar_unmapped_addr.795196362 |
| Short name | T1868 |
| Test name | |
| Test status | |
| Simulation time | 414744494 ps |
| CPU time | 17.52 seconds |
| Started | Aug 17 06:56:24 PM PDT 24 |
| Finished | Aug 17 06:56:41 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-45b700d0-c854-4f4e-9e07-5a5a815ec05a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795196362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 86.xbar_unmapped_addr.795196362 |
| Directory | /workspace/86.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device.1581376756 |
| Short name | T1449 |
| Test name | |
| Test status | |
| Simulation time | 403563679 ps |
| CPU time | 42.82 seconds |
| Started | Aug 17 06:56:31 PM PDT 24 |
| Finished | Aug 17 06:57:14 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-2f6d99fd-844b-4ce1-8454-d4c9ad616d51 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581376756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_device .1581376756 |
| Directory | /workspace/87.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_access_same_device_slow_rsp.3084578921 |
| Short name | T2643 |
| Test name | |
| Test status | |
| Simulation time | 9333537643 ps |
| CPU time | 163.09 seconds |
| Started | Aug 17 06:56:29 PM PDT 24 |
| Finished | Aug 17 06:59:12 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-b47b35f1-e042-4d47-9f2c-017fd56f16d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084578921 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_access_same_ device_slow_rsp.3084578921 |
| Directory | /workspace/87.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_and_unmapped_addr.2934220718 |
| Short name | T2084 |
| Test name | |
| Test status | |
| Simulation time | 167537870 ps |
| CPU time | 9.4 seconds |
| Started | Aug 17 06:56:32 PM PDT 24 |
| Finished | Aug 17 06:56:42 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-a67e0e3d-0cfb-4e8e-a515-14efffaff8cb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934220718 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_and_unmapped_add r.2934220718 |
| Directory | /workspace/87.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_error_random.1181395627 |
| Short name | T1513 |
| Test name | |
| Test status | |
| Simulation time | 594311164 ps |
| CPU time | 41.06 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:57:11 PM PDT 24 |
| Peak memory | 574324 kb |
| Host | smart-6f1c2cf9-4054-4351-bc81-e3419f33a2fb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181395627 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_error_random.1181395627 |
| Directory | /workspace/87.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random.1254571985 |
| Short name | T2519 |
| Test name | |
| Test status | |
| Simulation time | 355375117 ps |
| CPU time | 29.68 seconds |
| Started | Aug 17 06:56:24 PM PDT 24 |
| Finished | Aug 17 06:56:54 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-d7930ed0-0720-43d4-b4bb-fd15b2021efd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254571985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random.1254571985 |
| Directory | /workspace/87.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_large_delays.3866691459 |
| Short name | T2015 |
| Test name | |
| Test status | |
| Simulation time | 51868860258 ps |
| CPU time | 580.94 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 07:06:11 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-d7c0e5d1-74f8-4a33-8d80-63397d2b16ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866691459 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_large_delays.3866691459 |
| Directory | /workspace/87.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_slow_rsp.942201801 |
| Short name | T2615 |
| Test name | |
| Test status | |
| Simulation time | 27393937179 ps |
| CPU time | 492.54 seconds |
| Started | Aug 17 06:56:29 PM PDT 24 |
| Finished | Aug 17 07:04:42 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-3ef38b0b-41a6-42e1-a007-afba439b8ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942201801 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_slow_rsp.942201801 |
| Directory | /workspace/87.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_random_zero_delays.355732516 |
| Short name | T1469 |
| Test name | |
| Test status | |
| Simulation time | 213134387 ps |
| CPU time | 20.09 seconds |
| Started | Aug 17 06:56:37 PM PDT 24 |
| Finished | Aug 17 06:56:57 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-8060a550-42cb-49ba-945f-a876ccb50ec4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355732516 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_random_zero_dela ys.355732516 |
| Directory | /workspace/87.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_same_source.2907982643 |
| Short name | T1660 |
| Test name | |
| Test status | |
| Simulation time | 2573863398 ps |
| CPU time | 69.65 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:57:40 PM PDT 24 |
| Peak memory | 575636 kb |
| Host | smart-2495c0f7-7d4d-479e-847d-cce8697bd06a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907982643 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_same_source.2907982643 |
| Directory | /workspace/87.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke.2453504551 |
| Short name | T1506 |
| Test name | |
| Test status | |
| Simulation time | 50451726 ps |
| CPU time | 6.66 seconds |
| Started | Aug 17 06:56:27 PM PDT 24 |
| Finished | Aug 17 06:56:33 PM PDT 24 |
| Peak memory | 573456 kb |
| Host | smart-f0d1c10c-1a00-4770-8143-9cf73e7bdd4d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453504551 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke.2453504551 |
| Directory | /workspace/87.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1891849157 |
| Short name | T2706 |
| Test name | |
| Test status | |
| Simulation time | 8077752183 ps |
| CPU time | 80.75 seconds |
| Started | Aug 17 06:56:23 PM PDT 24 |
| Finished | Aug 17 06:57:44 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-8eb1ff65-5068-4242-88d3-bfbe4603f018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1891849157 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_large_delays.1891849157 |
| Directory | /workspace/87.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_slow_rsp.2642836835 |
| Short name | T2878 |
| Test name | |
| Test status | |
| Simulation time | 5709344052 ps |
| CPU time | 91.08 seconds |
| Started | Aug 17 06:56:27 PM PDT 24 |
| Finished | Aug 17 06:57:58 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-d6e4b8fa-922b-445b-8d4a-ef8f76e12360 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642836835 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_slow_rsp.2642836835 |
| Directory | /workspace/87.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_smoke_zero_delays.3265738069 |
| Short name | T2195 |
| Test name | |
| Test status | |
| Simulation time | 43987057 ps |
| CPU time | 5.98 seconds |
| Started | Aug 17 06:56:26 PM PDT 24 |
| Finished | Aug 17 06:56:32 PM PDT 24 |
| Peak memory | 573372 kb |
| Host | smart-c3047f8f-f484-4705-be39-d8fcb813b941 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265738069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_smoke_zero_delay s.3265738069 |
| Directory | /workspace/87.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all.1390764889 |
| Short name | T2301 |
| Test name | |
| Test status | |
| Simulation time | 1872950644 ps |
| CPU time | 136.98 seconds |
| Started | Aug 17 06:56:31 PM PDT 24 |
| Finished | Aug 17 06:58:48 PM PDT 24 |
| Peak memory | 574468 kb |
| Host | smart-b7026bb1-545d-4508-a58a-127ab7036569 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390764889 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all.1390764889 |
| Directory | /workspace/87.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_error.21674545 |
| Short name | T1902 |
| Test name | |
| Test status | |
| Simulation time | 12106463061 ps |
| CPU time | 434.44 seconds |
| Started | Aug 17 06:56:33 PM PDT 24 |
| Finished | Aug 17 07:03:47 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-22f311f7-0a56-4ba6-8816-cd79a330b923 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21674545 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all_with_error.21674545 |
| Directory | /workspace/87.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_rand_reset.3130025111 |
| Short name | T1734 |
| Test name | |
| Test status | |
| Simulation time | 206094990 ps |
| CPU time | 49.03 seconds |
| Started | Aug 17 06:56:29 PM PDT 24 |
| Finished | Aug 17 06:57:18 PM PDT 24 |
| Peak memory | 575900 kb |
| Host | smart-c3518488-dc91-4a5a-9315-2d8737a22da3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130025111 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_rand_reset.3130025111 |
| Directory | /workspace/87.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_stress_all_with_reset_error.955646403 |
| Short name | T1549 |
| Test name | |
| Test status | |
| Simulation time | 163374227 ps |
| CPU time | 46.55 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:57:17 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-1da65071-f198-4d9f-b3fd-0129af75c121 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955646403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_stress_all _with_reset_error.955646403 |
| Directory | /workspace/87.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/87.xbar_unmapped_addr.1209031098 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 1324021387 ps |
| CPU time | 49.95 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:57:20 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-97e5ada0-848e-4658-b992-d402c29af2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209031098 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 87.xbar_unmapped_addr.1209031098 |
| Directory | /workspace/87.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device.2346135900 |
| Short name | T1884 |
| Test name | |
| Test status | |
| Simulation time | 212442065 ps |
| CPU time | 14 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:56:44 PM PDT 24 |
| Peak memory | 575540 kb |
| Host | smart-22a46b96-7bdd-41ed-ab75-7bd22a5ed823 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346135900 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_device .2346135900 |
| Directory | /workspace/88.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.1256268927 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 54770155091 ps |
| CPU time | 1052.44 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 07:14:03 PM PDT 24 |
| Peak memory | 575660 kb |
| Host | smart-922ab5d9-ca2a-4cf5-8557-f63e6113f6a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1256268927 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_access_same_ device_slow_rsp.1256268927 |
| Directory | /workspace/88.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_and_unmapped_addr.194221835 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 258902282 ps |
| CPU time | 29.47 seconds |
| Started | Aug 17 06:56:39 PM PDT 24 |
| Finished | Aug 17 06:57:09 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-fd6b2d56-a268-4b1d-8791-6a73c0ea84f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=194221835 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_and_unmapped_addr .194221835 |
| Directory | /workspace/88.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_error_random.2868061182 |
| Short name | T2423 |
| Test name | |
| Test status | |
| Simulation time | 297368638 ps |
| CPU time | 22.28 seconds |
| Started | Aug 17 06:56:37 PM PDT 24 |
| Finished | Aug 17 06:56:59 PM PDT 24 |
| Peak memory | 575460 kb |
| Host | smart-a47d4889-87d8-45d6-bd2a-9a1f63b698b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868061182 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_error_random.2868061182 |
| Directory | /workspace/88.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random.3139048176 |
| Short name | T2564 |
| Test name | |
| Test status | |
| Simulation time | 379772636 ps |
| CPU time | 14.58 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:56:45 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-1d329d5c-45b4-4907-8c04-8599371d7255 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139048176 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random.3139048176 |
| Directory | /workspace/88.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_large_delays.958116064 |
| Short name | T2819 |
| Test name | |
| Test status | |
| Simulation time | 57980872369 ps |
| CPU time | 623.87 seconds |
| Started | Aug 17 06:56:28 PM PDT 24 |
| Finished | Aug 17 07:06:53 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-79d47306-4abc-47d0-ab1e-2f884da1b463 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958116064 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_large_delays.958116064 |
| Directory | /workspace/88.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.565798175 |
| Short name | T1951 |
| Test name | |
| Test status | |
| Simulation time | 66093185711 ps |
| CPU time | 1053.7 seconds |
| Started | Aug 17 06:56:39 PM PDT 24 |
| Finished | Aug 17 07:14:12 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-8451e47a-0519-41eb-a28c-2040a999236e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565798175 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_slow_rsp.565798175 |
| Directory | /workspace/88.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_random_zero_delays.257431212 |
| Short name | T2591 |
| Test name | |
| Test status | |
| Simulation time | 478714864 ps |
| CPU time | 41 seconds |
| Started | Aug 17 06:56:30 PM PDT 24 |
| Finished | Aug 17 06:57:11 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-342706f8-f21c-4f43-ab9c-3f90e0369d23 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257431212 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_random_zero_dela ys.257431212 |
| Directory | /workspace/88.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_same_source.4032780590 |
| Short name | T2841 |
| Test name | |
| Test status | |
| Simulation time | 342892590 ps |
| CPU time | 26.01 seconds |
| Started | Aug 17 06:56:32 PM PDT 24 |
| Finished | Aug 17 06:56:58 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-e7f029b2-7762-4e1f-ae04-0bef16ca136e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032780590 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_same_source.4032780590 |
| Directory | /workspace/88.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke.391173837 |
| Short name | T2261 |
| Test name | |
| Test status | |
| Simulation time | 53089226 ps |
| CPU time | 6.47 seconds |
| Started | Aug 17 06:56:34 PM PDT 24 |
| Finished | Aug 17 06:56:41 PM PDT 24 |
| Peak memory | 573512 kb |
| Host | smart-e6cdcde9-5495-483a-8567-848291d92a99 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391173837 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke.391173837 |
| Directory | /workspace/88.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_large_delays.2466782887 |
| Short name | T1726 |
| Test name | |
| Test status | |
| Simulation time | 7445412839 ps |
| CPU time | 77.23 seconds |
| Started | Aug 17 06:56:28 PM PDT 24 |
| Finished | Aug 17 06:57:46 PM PDT 24 |
| Peak memory | 574184 kb |
| Host | smart-4235d8c1-8d90-45c5-8cd5-7a5d6296cda0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466782887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_large_delays.2466782887 |
| Directory | /workspace/88.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.3655221776 |
| Short name | T2416 |
| Test name | |
| Test status | |
| Simulation time | 5872436173 ps |
| CPU time | 95.92 seconds |
| Started | Aug 17 06:56:38 PM PDT 24 |
| Finished | Aug 17 06:58:14 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-38299905-b0cc-4222-8143-95406072d5a9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655221776 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_slow_rsp.3655221776 |
| Directory | /workspace/88.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_smoke_zero_delays.1194581581 |
| Short name | T1915 |
| Test name | |
| Test status | |
| Simulation time | 46385308 ps |
| CPU time | 5.96 seconds |
| Started | Aug 17 06:56:35 PM PDT 24 |
| Finished | Aug 17 06:56:41 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-66485e11-cf34-4e2c-8ecb-61c16f8074f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194581581 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_smoke_zero_delay s.1194581581 |
| Directory | /workspace/88.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all.1266232703 |
| Short name | T1736 |
| Test name | |
| Test status | |
| Simulation time | 7575804985 ps |
| CPU time | 290.99 seconds |
| Started | Aug 17 06:56:42 PM PDT 24 |
| Finished | Aug 17 07:01:33 PM PDT 24 |
| Peak memory | 576424 kb |
| Host | smart-f4d00344-248d-4ab0-86ed-c5a0aa7484ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266232703 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all.1266232703 |
| Directory | /workspace/88.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_error.78358861 |
| Short name | T1373 |
| Test name | |
| Test status | |
| Simulation time | 847697605 ps |
| CPU time | 25.11 seconds |
| Started | Aug 17 06:56:43 PM PDT 24 |
| Finished | Aug 17 06:57:08 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-36d55fa1-077b-4d7c-a9f8-be5900fdad74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78358861 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_with_error.78358861 |
| Directory | /workspace/88.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_rand_reset.678342250 |
| Short name | T2677 |
| Test name | |
| Test status | |
| Simulation time | 49850488 ps |
| CPU time | 30.41 seconds |
| Started | Aug 17 06:56:38 PM PDT 24 |
| Finished | Aug 17 06:57:09 PM PDT 24 |
| Peak memory | 576288 kb |
| Host | smart-e22c75b5-2ec5-48bb-9fbd-e3cecb0ba6a5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678342250 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_all_ with_rand_reset.678342250 |
| Directory | /workspace/88.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_stress_all_with_reset_error.2769750854 |
| Short name | T2409 |
| Test name | |
| Test status | |
| Simulation time | 1080389948 ps |
| CPU time | 233.76 seconds |
| Started | Aug 17 06:56:39 PM PDT 24 |
| Finished | Aug 17 07:00:33 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-7f056165-695a-46a3-a7fe-f80d3848c7a7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769750854 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_stress_al l_with_reset_error.2769750854 |
| Directory | /workspace/88.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.4133434540 |
| Short name | T1831 |
| Test name | |
| Test status | |
| Simulation time | 118048970 ps |
| CPU time | 15.39 seconds |
| Started | Aug 17 06:56:38 PM PDT 24 |
| Finished | Aug 17 06:56:53 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-c8cf1c9e-3fd0-449b-b675-aa734c6cfb3c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4133434540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 88.xbar_unmapped_addr.4133434540 |
| Directory | /workspace/88.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device.2208184606 |
| Short name | T2717 |
| Test name | |
| Test status | |
| Simulation time | 2522368033 ps |
| CPU time | 111.47 seconds |
| Started | Aug 17 06:56:45 PM PDT 24 |
| Finished | Aug 17 06:58:37 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-70a14d6b-71d3-4bba-ab90-b126b4687381 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208184606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_device .2208184606 |
| Directory | /workspace/89.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_access_same_device_slow_rsp.3183659055 |
| Short name | T1897 |
| Test name | |
| Test status | |
| Simulation time | 102495292861 ps |
| CPU time | 1875.35 seconds |
| Started | Aug 17 06:56:44 PM PDT 24 |
| Finished | Aug 17 07:27:59 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-f6ab8278-e254-4bd1-b5b7-71c3a0cbc3dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183659055 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_access_same_ device_slow_rsp.3183659055 |
| Directory | /workspace/89.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_and_unmapped_addr.3681530239 |
| Short name | T1477 |
| Test name | |
| Test status | |
| Simulation time | 399558305 ps |
| CPU time | 18.08 seconds |
| Started | Aug 17 06:56:42 PM PDT 24 |
| Finished | Aug 17 06:57:00 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-909980ea-0e60-479d-81b2-b214f5db69b0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681530239 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_and_unmapped_add r.3681530239 |
| Directory | /workspace/89.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_error_random.2459440364 |
| Short name | T1975 |
| Test name | |
| Test status | |
| Simulation time | 329861782 ps |
| CPU time | 26.79 seconds |
| Started | Aug 17 06:56:45 PM PDT 24 |
| Finished | Aug 17 06:57:11 PM PDT 24 |
| Peak memory | 575496 kb |
| Host | smart-161a0ec3-0ab8-49f5-8785-e5005faaa08f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459440364 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_error_random.2459440364 |
| Directory | /workspace/89.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random.1959688830 |
| Short name | T2232 |
| Test name | |
| Test status | |
| Simulation time | 326069413 ps |
| CPU time | 13.94 seconds |
| Started | Aug 17 06:56:38 PM PDT 24 |
| Finished | Aug 17 06:56:52 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-998b6188-dc58-4c68-b26b-6828b4393fd0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959688830 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random.1959688830 |
| Directory | /workspace/89.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_large_delays.4216883656 |
| Short name | T1684 |
| Test name | |
| Test status | |
| Simulation time | 77080420384 ps |
| CPU time | 895.47 seconds |
| Started | Aug 17 06:56:40 PM PDT 24 |
| Finished | Aug 17 07:11:35 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-e7676fad-6051-48bf-ad49-98c31b6f02f3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216883656 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_large_delays.4216883656 |
| Directory | /workspace/89.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_slow_rsp.3809412987 |
| Short name | T1882 |
| Test name | |
| Test status | |
| Simulation time | 29532448472 ps |
| CPU time | 523.18 seconds |
| Started | Aug 17 06:56:48 PM PDT 24 |
| Finished | Aug 17 07:05:31 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-7a56db1f-284c-40a2-8e2e-25357b70e715 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809412987 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_slow_rsp.3809412987 |
| Directory | /workspace/89.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.125189751 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 445937835 ps |
| CPU time | 40.61 seconds |
| Started | Aug 17 06:56:36 PM PDT 24 |
| Finished | Aug 17 06:57:17 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-1d469057-8bcb-4711-8325-736cfc631392 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125189751 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_random_zero_dela ys.125189751 |
| Directory | /workspace/89.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_same_source.767326637 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 1178030820 ps |
| CPU time | 33.2 seconds |
| Started | Aug 17 06:56:47 PM PDT 24 |
| Finished | Aug 17 06:57:20 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f37d7193-ed74-4b24-a596-0c002028ad42 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767326637 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_same_source.767326637 |
| Directory | /workspace/89.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke.1349828151 |
| Short name | T1841 |
| Test name | |
| Test status | |
| Simulation time | 55957745 ps |
| CPU time | 7.02 seconds |
| Started | Aug 17 06:56:39 PM PDT 24 |
| Finished | Aug 17 06:56:47 PM PDT 24 |
| Peak memory | 574140 kb |
| Host | smart-aa10588d-17a3-4ce1-b59a-aae820767a67 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349828151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke.1349828151 |
| Directory | /workspace/89.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_large_delays.3718639744 |
| Short name | T1898 |
| Test name | |
| Test status | |
| Simulation time | 8455286609 ps |
| CPU time | 90.64 seconds |
| Started | Aug 17 06:56:39 PM PDT 24 |
| Finished | Aug 17 06:58:10 PM PDT 24 |
| Peak memory | 573552 kb |
| Host | smart-3248765e-4bc9-4894-8552-ba8fb08f83da |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718639744 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_large_delays.3718639744 |
| Directory | /workspace/89.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_slow_rsp.3012330996 |
| Short name | T2061 |
| Test name | |
| Test status | |
| Simulation time | 4250031106 ps |
| CPU time | 68.08 seconds |
| Started | Aug 17 06:56:37 PM PDT 24 |
| Finished | Aug 17 06:57:45 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-84d8ef6d-8796-462d-a63a-c2693e175a3d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3012330996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_slow_rsp.3012330996 |
| Directory | /workspace/89.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_smoke_zero_delays.751866167 |
| Short name | T2248 |
| Test name | |
| Test status | |
| Simulation time | 53677516 ps |
| CPU time | 6.63 seconds |
| Started | Aug 17 06:56:41 PM PDT 24 |
| Finished | Aug 17 06:56:47 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-f0541844-892a-4aa1-9471-153f27241b88 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751866167 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_smoke_zero_delays .751866167 |
| Directory | /workspace/89.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all.3784438997 |
| Short name | T2392 |
| Test name | |
| Test status | |
| Simulation time | 2293146934 ps |
| CPU time | 187.56 seconds |
| Started | Aug 17 06:56:42 PM PDT 24 |
| Finished | Aug 17 06:59:50 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-cc21875c-75b9-4748-b6c6-f5d9a8be38d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784438997 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all.3784438997 |
| Directory | /workspace/89.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_error.219045817 |
| Short name | T1919 |
| Test name | |
| Test status | |
| Simulation time | 2082194149 ps |
| CPU time | 159.15 seconds |
| Started | Aug 17 06:56:48 PM PDT 24 |
| Finished | Aug 17 06:59:27 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-6daf6548-e1ce-403d-b063-2fa231fff555 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219045817 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all_with_error.219045817 |
| Directory | /workspace/89.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_rand_reset.4073387531 |
| Short name | T2884 |
| Test name | |
| Test status | |
| Simulation time | 9401008387 ps |
| CPU time | 745.71 seconds |
| Started | Aug 17 06:56:45 PM PDT 24 |
| Finished | Aug 17 07:09:11 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-71a09a51-26b4-46bf-8317-f3536d9211ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073387531 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_all _with_rand_reset.4073387531 |
| Directory | /workspace/89.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_stress_all_with_reset_error.3646627580 |
| Short name | T1519 |
| Test name | |
| Test status | |
| Simulation time | 398644555 ps |
| CPU time | 159.52 seconds |
| Started | Aug 17 06:56:47 PM PDT 24 |
| Finished | Aug 17 06:59:27 PM PDT 24 |
| Peak memory | 576328 kb |
| Host | smart-f6a40873-e18b-47d9-8b82-072d43f77c94 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646627580 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_stress_al l_with_reset_error.3646627580 |
| Directory | /workspace/89.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/89.xbar_unmapped_addr.3384613872 |
| Short name | T2725 |
| Test name | |
| Test status | |
| Simulation time | 832258866 ps |
| CPU time | 36.87 seconds |
| Started | Aug 17 06:56:47 PM PDT 24 |
| Finished | Aug 17 06:57:24 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-fb039f65-cfed-4b7d-89ff-4934eb2230c9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384613872 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 89.xbar_unmapped_addr.3384613872 |
| Directory | /workspace/89.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_mem_rw_with_rand_reset.1723645286 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 12037947880 ps |
| CPU time | 710.64 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:59:47 PM PDT 24 |
| Peak memory | 652700 kb |
| Host | smart-e0a93117-a7cb-41ce-a2e7-7fcdb06e751d |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723645286 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top .vdb -cm_log /dev/null -cm_name 9.chip_csr_mem_rw_with_rand_reset.1723645286 |
| Directory | /workspace/9.chip_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_csr_rw.329343482 |
| Short name | T2112 |
| Test name | |
| Test status | |
| Simulation time | 4391607575 ps |
| CPU time | 298.77 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:52:48 PM PDT 24 |
| Peak memory | 598608 kb |
| Host | smart-b6c019cd-3dd1-49e6-94e2-16cc0ff62449 |
| User | root |
| Command | /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329343482 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_ vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_csr_rw.329343482 |
| Directory | /workspace/9.chip_csr_rw/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_same_csr_outstanding.2464641018 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 16230505208 ps |
| CPU time | 1815 seconds |
| Started | Aug 17 06:47:46 PM PDT 24 |
| Finished | Aug 17 07:18:01 PM PDT 24 |
| Peak memory | 593364 kb |
| Host | smart-5ae1e950-2df3-45b9-af34-dfc13683f992 |
| User | root |
| Command | /workspace/cover_reg_top/simv +test_timeout_ns=120_000_000 +run_same_csr_outstanding +en_scb=0 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464641018 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb - cm_log /dev/null -cm_name 9.chip_same_csr_outstanding.2464641018 |
| Directory | /workspace/9.chip_same_csr_outstanding/latest |
| Test location | /workspace/coverage/cover_reg_top/9.chip_tl_errors.2860359407 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 3198964152 ps |
| CPU time | 188.63 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:50:53 PM PDT 24 |
| Peak memory | 603828 kb |
| Host | smart-4a13bb25-7fb9-42d8-ac25-53d8c54ab440 |
| User | root |
| Command | /workspace/cover_reg_top/simv +run_tl_errors +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860359407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_common_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.chip_tl_errors.2860359407 |
| Directory | /workspace/9.chip_tl_errors/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device.1165321021 |
| Short name | T2309 |
| Test name | |
| Test status | |
| Simulation time | 3272862162 ps |
| CPU time | 116.84 seconds |
| Started | Aug 17 06:47:44 PM PDT 24 |
| Finished | Aug 17 06:49:41 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-cff63dc4-550c-4390-9f4f-c0bcca8151f0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165321021 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_device. 1165321021 |
| Directory | /workspace/9.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_access_same_device_slow_rsp.3755397425 |
| Short name | T2510 |
| Test name | |
| Test status | |
| Simulation time | 77689079914 ps |
| CPU time | 1363.71 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 07:10:36 PM PDT 24 |
| Peak memory | 575436 kb |
| Host | smart-1dc81583-66cd-4522-9a6a-f6895c8bb281 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755397425 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_access_same_d evice_slow_rsp.3755397425 |
| Directory | /workspace/9.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_and_unmapped_addr.458706353 |
| Short name | T1617 |
| Test name | |
| Test status | |
| Simulation time | 964951815 ps |
| CPU time | 41.1 seconds |
| Started | Aug 17 06:47:55 PM PDT 24 |
| Finished | Aug 17 06:48:36 PM PDT 24 |
| Peak memory | 575536 kb |
| Host | smart-324dbf9f-5587-43a4-acc5-1042d3a51d60 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=458706353 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_and_unmapped_addr. 458706353 |
| Directory | /workspace/9.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_error_random.3445066408 |
| Short name | T1700 |
| Test name | |
| Test status | |
| Simulation time | 188894762 ps |
| CPU time | 17.75 seconds |
| Started | Aug 17 06:47:57 PM PDT 24 |
| Finished | Aug 17 06:48:15 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-b051395f-bd72-4844-9efa-b0b2510ceeeb |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445066408 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_error_random.3445066408 |
| Directory | /workspace/9.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random.1155865063 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 2320581148 ps |
| CPU time | 83.42 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:49:13 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-42e5026b-927d-40e9-9bbe-1a854887831b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155865063 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random.1155865063 |
| Directory | /workspace/9.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_slow_rsp.2360154985 |
| Short name | T2132 |
| Test name | |
| Test status | |
| Simulation time | 63765869816 ps |
| CPU time | 983.4 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 07:04:14 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-68c6252e-7201-4308-a2e3-069384e3b96c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360154985 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_slow_rsp.2360154985 |
| Directory | /workspace/9.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_random_zero_delays.2703851568 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 513622364 ps |
| CPU time | 43.83 seconds |
| Started | Aug 17 06:47:50 PM PDT 24 |
| Finished | Aug 17 06:48:34 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-08bb6f2f-48e6-48f5-8eb4-8405b37030dc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703851568 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_random_zero_dela ys.2703851568 |
| Directory | /workspace/9.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_same_source.688658658 |
| Short name | T2264 |
| Test name | |
| Test status | |
| Simulation time | 2427867470 ps |
| CPU time | 68.01 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:49:00 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-5872e599-f7f1-457f-92d1-3c0704d75d91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=688658658 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_same_source.688658658 |
| Directory | /workspace/9.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke.49289597 |
| Short name | T2245 |
| Test name | |
| Test status | |
| Simulation time | 49100613 ps |
| CPU time | 6.54 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:47:52 PM PDT 24 |
| Peak memory | 574096 kb |
| Host | smart-637d6f29-f48a-488e-9d33-c30f469378ad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49289597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke.49289597 |
| Directory | /workspace/9.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_large_delays.3211944756 |
| Short name | T1981 |
| Test name | |
| Test status | |
| Simulation time | 10345558710 ps |
| CPU time | 100.98 seconds |
| Started | Aug 17 06:47:45 PM PDT 24 |
| Finished | Aug 17 06:49:27 PM PDT 24 |
| Peak memory | 573564 kb |
| Host | smart-5a185b09-f2f6-446b-97ed-babadc84eab8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211944756 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_large_delays.3211944756 |
| Directory | /workspace/9.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_slow_rsp.1660450289 |
| Short name | T2211 |
| Test name | |
| Test status | |
| Simulation time | 3468006732 ps |
| CPU time | 58.61 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:47 PM PDT 24 |
| Peak memory | 573504 kb |
| Host | smart-fb88ecdf-94c7-4822-8811-7fd95bf208b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660450289 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_slow_rsp.1660450289 |
| Directory | /workspace/9.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_smoke_zero_delays.2521547714 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 47342158 ps |
| CPU time | 6.24 seconds |
| Started | Aug 17 06:47:56 PM PDT 24 |
| Finished | Aug 17 06:48:02 PM PDT 24 |
| Peak memory | 573384 kb |
| Host | smart-8253733c-a4b7-4086-8487-ea99fdba2131 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521547714 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_smoke_zero_delays .2521547714 |
| Directory | /workspace/9.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all.4275447471 |
| Short name | T2434 |
| Test name | |
| Test status | |
| Simulation time | 18734709964 ps |
| CPU time | 663.3 seconds |
| Started | Aug 17 06:47:49 PM PDT 24 |
| Finished | Aug 17 06:58:52 PM PDT 24 |
| Peak memory | 575580 kb |
| Host | smart-b6680bbb-cda1-4421-9155-41183a59ebd6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275447471 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all.4275447471 |
| Directory | /workspace/9.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_error.3275189130 |
| Short name | T2312 |
| Test name | |
| Test status | |
| Simulation time | 1994707826 ps |
| CPU time | 136.69 seconds |
| Started | Aug 17 06:47:57 PM PDT 24 |
| Finished | Aug 17 06:50:14 PM PDT 24 |
| Peak memory | 575928 kb |
| Host | smart-4c8085b4-d707-404f-a110-786e68c3ca14 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275189130 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_with_error.3275189130 |
| Directory | /workspace/9.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_rand_reset.2786097443 |
| Short name | T2120 |
| Test name | |
| Test status | |
| Simulation time | 732598816 ps |
| CPU time | 225.61 seconds |
| Started | Aug 17 06:47:52 PM PDT 24 |
| Finished | Aug 17 06:51:37 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-79ea2cab-bd28-4076-be44-b577d2903f73 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786097443 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all_ with_rand_reset.2786097443 |
| Directory | /workspace/9.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_stress_all_with_reset_error.1667310452 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 8237702816 ps |
| CPU time | 482.06 seconds |
| Started | Aug 17 06:48:03 PM PDT 24 |
| Finished | Aug 17 06:56:06 PM PDT 24 |
| Peak memory | 576352 kb |
| Host | smart-958da195-effc-4ada-be4d-b19d06175005 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667310452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_stress_all _with_reset_error.1667310452 |
| Directory | /workspace/9.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.2193172685 |
| Short name | T2166 |
| Test name | |
| Test status | |
| Simulation time | 1067753543 ps |
| CPU time | 47.47 seconds |
| Started | Aug 17 06:47:48 PM PDT 24 |
| Finished | Aug 17 06:48:35 PM PDT 24 |
| Peak memory | 575484 kb |
| Host | smart-f6a45ff6-50ad-4a16-9cc6-0244956ad24e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2193172685 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.xbar_unmapped_addr.2193172685 |
| Directory | /workspace/9.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device.235058882 |
| Short name | T2703 |
| Test name | |
| Test status | |
| Simulation time | 62508873 ps |
| CPU time | 8.47 seconds |
| Started | Aug 17 06:56:50 PM PDT 24 |
| Finished | Aug 17 06:56:58 PM PDT 24 |
| Peak memory | 573380 kb |
| Host | smart-8a8d38f4-d9d0-4dba-9a0d-c73b7cefedad |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235058882 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_device. 235058882 |
| Directory | /workspace/90.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_access_same_device_slow_rsp.279818671 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 99323338255 ps |
| CPU time | 1860 seconds |
| Started | Aug 17 06:56:49 PM PDT 24 |
| Finished | Aug 17 07:27:49 PM PDT 24 |
| Peak memory | 575684 kb |
| Host | smart-58e4661f-bcdb-47e7-9734-721b51e06407 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279818671 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_access_same_d evice_slow_rsp.279818671 |
| Directory | /workspace/90.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_and_unmapped_addr.2988054571 |
| Short name | T2694 |
| Test name | |
| Test status | |
| Simulation time | 895303763 ps |
| CPU time | 33.48 seconds |
| Started | Aug 17 06:56:50 PM PDT 24 |
| Finished | Aug 17 06:57:24 PM PDT 24 |
| Peak memory | 575568 kb |
| Host | smart-414a42a5-2ea0-4ba7-bc0e-a996950a741e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988054571 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_and_unmapped_add r.2988054571 |
| Directory | /workspace/90.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_error_random.414537452 |
| Short name | T2467 |
| Test name | |
| Test status | |
| Simulation time | 862958277 ps |
| CPU time | 30.48 seconds |
| Started | Aug 17 06:56:52 PM PDT 24 |
| Finished | Aug 17 06:57:23 PM PDT 24 |
| Peak memory | 575376 kb |
| Host | smart-f3120107-4ec6-4fb0-9b58-fb467f3cf8fc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414537452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_error_random.414537452 |
| Directory | /workspace/90.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random.829382919 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 246965127 ps |
| CPU time | 12.33 seconds |
| Started | Aug 17 06:56:44 PM PDT 24 |
| Finished | Aug 17 06:56:56 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-bf26efed-40fc-4f0c-970e-efd33dd018d9 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829382919 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random.829382919 |
| Directory | /workspace/90.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_large_delays.446048280 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 32408293825 ps |
| CPU time | 349.34 seconds |
| Started | Aug 17 06:56:48 PM PDT 24 |
| Finished | Aug 17 07:02:38 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-9059ae54-2f3b-43cf-b639-6f335c4a00ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446048280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_large_delays.446048280 |
| Directory | /workspace/90.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_slow_rsp.1274714314 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 5321926032 ps |
| CPU time | 86.53 seconds |
| Started | Aug 17 06:56:49 PM PDT 24 |
| Finished | Aug 17 06:58:16 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-17e7a8fe-d458-4b84-97a7-c2e94558e6d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274714314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_slow_rsp.1274714314 |
| Directory | /workspace/90.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_random_zero_delays.1972787932 |
| Short name | T2063 |
| Test name | |
| Test status | |
| Simulation time | 34161614 ps |
| CPU time | 6.02 seconds |
| Started | Aug 17 06:56:44 PM PDT 24 |
| Finished | Aug 17 06:56:50 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-b2ed0c31-7393-4e7e-b793-052ec615d4fa |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1972787932 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_random_zero_del ays.1972787932 |
| Directory | /workspace/90.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_same_source.539063885 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 485771905 ps |
| CPU time | 30.65 seconds |
| Started | Aug 17 06:56:49 PM PDT 24 |
| Finished | Aug 17 06:57:20 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-28de3ac5-f430-4cb5-aabe-0ea196863e1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=539063885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_same_source.539063885 |
| Directory | /workspace/90.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke.3680947378 |
| Short name | T2760 |
| Test name | |
| Test status | |
| Simulation time | 217575614 ps |
| CPU time | 9.8 seconds |
| Started | Aug 17 06:56:43 PM PDT 24 |
| Finished | Aug 17 06:56:53 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-e01ffb1d-c8cf-4c36-91c6-01322ce6bfee |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680947378 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke.3680947378 |
| Directory | /workspace/90.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_large_delays.2060495164 |
| Short name | T1960 |
| Test name | |
| Test status | |
| Simulation time | 8512980224 ps |
| CPU time | 84.78 seconds |
| Started | Aug 17 06:56:48 PM PDT 24 |
| Finished | Aug 17 06:58:13 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-613a0448-2bcf-44b9-b001-3cbf296aa87d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060495164 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_large_delays.2060495164 |
| Directory | /workspace/90.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_slow_rsp.3795263754 |
| Short name | T1504 |
| Test name | |
| Test status | |
| Simulation time | 4840599936 ps |
| CPU time | 73.54 seconds |
| Started | Aug 17 06:56:47 PM PDT 24 |
| Finished | Aug 17 06:58:00 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-86fc140c-e767-4ead-a26d-ab03aafd8eab |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795263754 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_slow_rsp.3795263754 |
| Directory | /workspace/90.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_smoke_zero_delays.4187761237 |
| Short name | T1379 |
| Test name | |
| Test status | |
| Simulation time | 56055128 ps |
| CPU time | 6.76 seconds |
| Started | Aug 17 06:56:44 PM PDT 24 |
| Finished | Aug 17 06:56:51 PM PDT 24 |
| Peak memory | 574044 kb |
| Host | smart-92195bfc-a87d-4f39-90b0-aabc2aa5cffc |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187761237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_smoke_zero_delay s.4187761237 |
| Directory | /workspace/90.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all.2449072262 |
| Short name | T1936 |
| Test name | |
| Test status | |
| Simulation time | 3962306251 ps |
| CPU time | 167.31 seconds |
| Started | Aug 17 06:56:49 PM PDT 24 |
| Finished | Aug 17 06:59:37 PM PDT 24 |
| Peak memory | 575744 kb |
| Host | smart-266a8d39-e3dc-454e-9043-33291cc5904f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449072262 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all.2449072262 |
| Directory | /workspace/90.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_error.4200294282 |
| Short name | T2208 |
| Test name | |
| Test status | |
| Simulation time | 547183402 ps |
| CPU time | 45.92 seconds |
| Started | Aug 17 06:56:57 PM PDT 24 |
| Finished | Aug 17 06:57:43 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-55d608c5-6e48-4589-872c-2ea0a7c17727 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4200294282 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all_with_error.4200294282 |
| Directory | /workspace/90.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_stress_all_with_rand_reset.3275687264 |
| Short name | T2327 |
| Test name | |
| Test status | |
| Simulation time | 2740151392 ps |
| CPU time | 249.58 seconds |
| Started | Aug 17 06:56:52 PM PDT 24 |
| Finished | Aug 17 07:01:02 PM PDT 24 |
| Peak memory | 576064 kb |
| Host | smart-ab574fc7-7fd0-449a-b372-d24d8e299671 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275687264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_stress_all _with_rand_reset.3275687264 |
| Directory | /workspace/90.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/90.xbar_unmapped_addr.598957318 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 1230294655 ps |
| CPU time | 54.21 seconds |
| Started | Aug 17 06:56:50 PM PDT 24 |
| Finished | Aug 17 06:57:45 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-ed90b4c2-e5a3-45a9-be65-36c5d0aef051 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598957318 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 90.xbar_unmapped_addr.598957318 |
| Directory | /workspace/90.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device.2923570885 |
| Short name | T1863 |
| Test name | |
| Test status | |
| Simulation time | 2710354296 ps |
| CPU time | 102.54 seconds |
| Started | Aug 17 06:56:59 PM PDT 24 |
| Finished | Aug 17 06:58:42 PM PDT 24 |
| Peak memory | 575672 kb |
| Host | smart-4c9091af-f509-4739-a136-00d17a7133fd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923570885 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_device .2923570885 |
| Directory | /workspace/91.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_access_same_device_slow_rsp.2608341606 |
| Short name | T2579 |
| Test name | |
| Test status | |
| Simulation time | 87793668292 ps |
| CPU time | 1707.04 seconds |
| Started | Aug 17 06:56:59 PM PDT 24 |
| Finished | Aug 17 07:25:26 PM PDT 24 |
| Peak memory | 575456 kb |
| Host | smart-6f4ba546-fa1c-465e-b8e4-7b278665ed91 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608341606 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_access_same_ device_slow_rsp.2608341606 |
| Directory | /workspace/91.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_and_unmapped_addr.3510126985 |
| Short name | T1788 |
| Test name | |
| Test status | |
| Simulation time | 337907576 ps |
| CPU time | 32.83 seconds |
| Started | Aug 17 06:57:08 PM PDT 24 |
| Finished | Aug 17 06:57:41 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-02c716d3-b370-4c1f-8f62-7d5190d96c20 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510126985 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_and_unmapped_add r.3510126985 |
| Directory | /workspace/91.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_error_random.2786419730 |
| Short name | T1466 |
| Test name | |
| Test status | |
| Simulation time | 315415824 ps |
| CPU time | 31.67 seconds |
| Started | Aug 17 06:56:58 PM PDT 24 |
| Finished | Aug 17 06:57:29 PM PDT 24 |
| Peak memory | 575288 kb |
| Host | smart-466bc41a-6811-4054-879e-349177cca8ea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786419730 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_error_random.2786419730 |
| Directory | /workspace/91.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random.1787148264 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 576303670 ps |
| CPU time | 51.42 seconds |
| Started | Aug 17 06:56:59 PM PDT 24 |
| Finished | Aug 17 06:57:50 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-4ee77c20-19af-4444-ac28-edccfede0dd4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787148264 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random.1787148264 |
| Directory | /workspace/91.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_large_delays.3753908519 |
| Short name | T1512 |
| Test name | |
| Test status | |
| Simulation time | 38521302371 ps |
| CPU time | 381.96 seconds |
| Started | Aug 17 06:56:58 PM PDT 24 |
| Finished | Aug 17 07:03:20 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-b963a2f8-4da4-42a1-b4c8-63ec3f6889cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3753908519 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_large_delays.3753908519 |
| Directory | /workspace/91.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_slow_rsp.2713890162 |
| Short name | T1938 |
| Test name | |
| Test status | |
| Simulation time | 43814037095 ps |
| CPU time | 770.52 seconds |
| Started | Aug 17 06:56:58 PM PDT 24 |
| Finished | Aug 17 07:09:49 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-e86f9f60-f194-40a0-8c72-3346637d8fbc |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2713890162 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_slow_rsp.2713890162 |
| Directory | /workspace/91.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_random_zero_delays.24540241 |
| Short name | T1962 |
| Test name | |
| Test status | |
| Simulation time | 466902084 ps |
| CPU time | 40.32 seconds |
| Started | Aug 17 06:56:56 PM PDT 24 |
| Finished | Aug 17 06:57:36 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-d26f6beb-0526-43fe-b652-77ce400e6f0f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24540241 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_random_zero_delay s.24540241 |
| Directory | /workspace/91.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_same_source.3074879060 |
| Short name | T2586 |
| Test name | |
| Test status | |
| Simulation time | 2188537703 ps |
| CPU time | 70.22 seconds |
| Started | Aug 17 06:56:59 PM PDT 24 |
| Finished | Aug 17 06:58:09 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-c8d91c0e-a6c4-4d84-baee-01f877080c01 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074879060 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_same_source.3074879060 |
| Directory | /workspace/91.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke.2647848745 |
| Short name | T2753 |
| Test name | |
| Test status | |
| Simulation time | 157195086 ps |
| CPU time | 7.51 seconds |
| Started | Aug 17 06:56:59 PM PDT 24 |
| Finished | Aug 17 06:57:06 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-93d944cb-1a3d-45ec-b30f-deccc4191f0e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647848745 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke.2647848745 |
| Directory | /workspace/91.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_large_delays.264176826 |
| Short name | T2397 |
| Test name | |
| Test status | |
| Simulation time | 10990576370 ps |
| CPU time | 115.03 seconds |
| Started | Aug 17 06:56:57 PM PDT 24 |
| Finished | Aug 17 06:58:52 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-c17049ee-51f8-4ed4-b347-bf2a09673788 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264176826 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_large_delays.264176826 |
| Directory | /workspace/91.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_slow_rsp.48942564 |
| Short name | T1385 |
| Test name | |
| Test status | |
| Simulation time | 4566719940 ps |
| CPU time | 69.96 seconds |
| Started | Aug 17 06:56:59 PM PDT 24 |
| Finished | Aug 17 06:58:09 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-2a9c0aca-69ce-415c-acd5-cc950019cf6c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48942564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_slow_rsp.48942564 |
| Directory | /workspace/91.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_smoke_zero_delays.826961539 |
| Short name | T1914 |
| Test name | |
| Test status | |
| Simulation time | 40510836 ps |
| CPU time | 6.14 seconds |
| Started | Aug 17 06:56:58 PM PDT 24 |
| Finished | Aug 17 06:57:04 PM PDT 24 |
| Peak memory | 573440 kb |
| Host | smart-272f52ce-68a0-41f2-bfe9-131216b3d338 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826961539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_smoke_zero_delays .826961539 |
| Directory | /workspace/91.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all.1283857603 |
| Short name | T2595 |
| Test name | |
| Test status | |
| Simulation time | 12965204481 ps |
| CPU time | 569.82 seconds |
| Started | Aug 17 06:57:06 PM PDT 24 |
| Finished | Aug 17 07:06:36 PM PDT 24 |
| Peak memory | 576440 kb |
| Host | smart-3e245dce-96d8-42ce-89db-c54a70c5babd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283857603 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all.1283857603 |
| Directory | /workspace/91.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_error.228256476 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 1470790981 ps |
| CPU time | 111.96 seconds |
| Started | Aug 17 06:57:04 PM PDT 24 |
| Finished | Aug 17 06:58:56 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-c03aa6c9-3a00-465f-bc3b-6ef5160f7929 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=228256476 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all_with_error.228256476 |
| Directory | /workspace/91.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_stress_all_with_rand_reset.2848639066 |
| Short name | T2051 |
| Test name | |
| Test status | |
| Simulation time | 10574056960 ps |
| CPU time | 627.81 seconds |
| Started | Aug 17 06:57:05 PM PDT 24 |
| Finished | Aug 17 07:07:33 PM PDT 24 |
| Peak memory | 576360 kb |
| Host | smart-91eeba23-96ab-4729-a31c-970dd94322de |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848639066 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_stress_all _with_rand_reset.2848639066 |
| Directory | /workspace/91.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/91.xbar_unmapped_addr.1203370161 |
| Short name | T2682 |
| Test name | |
| Test status | |
| Simulation time | 1181077022 ps |
| CPU time | 47.71 seconds |
| Started | Aug 17 06:56:57 PM PDT 24 |
| Finished | Aug 17 06:57:45 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-9826ff0b-16ed-4211-bf45-2e99cd326904 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203370161 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 91.xbar_unmapped_addr.1203370161 |
| Directory | /workspace/91.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device.2452892859 |
| Short name | T1528 |
| Test name | |
| Test status | |
| Simulation time | 837689369 ps |
| CPU time | 36.58 seconds |
| Started | Aug 17 06:57:06 PM PDT 24 |
| Finished | Aug 17 06:57:43 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-c0af30d9-4e5b-4740-b45c-decc66e51ea5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452892859 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_device .2452892859 |
| Directory | /workspace/92.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_access_same_device_slow_rsp.2987041586 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 52380480347 ps |
| CPU time | 983.46 seconds |
| Started | Aug 17 06:57:08 PM PDT 24 |
| Finished | Aug 17 07:13:32 PM PDT 24 |
| Peak memory | 575524 kb |
| Host | smart-13133740-64c3-4c2f-84a8-220093f049d6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987041586 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_access_same_ device_slow_rsp.2987041586 |
| Directory | /workspace/92.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_and_unmapped_addr.1100648761 |
| Short name | T1361 |
| Test name | |
| Test status | |
| Simulation time | 277706745 ps |
| CPU time | 30 seconds |
| Started | Aug 17 06:57:12 PM PDT 24 |
| Finished | Aug 17 06:57:42 PM PDT 24 |
| Peak memory | 575388 kb |
| Host | smart-5796c7e6-19bc-4e09-b0bb-06cf2ee3349a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100648761 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_and_unmapped_add r.1100648761 |
| Directory | /workspace/92.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_error_random.300045762 |
| Short name | T2604 |
| Test name | |
| Test status | |
| Simulation time | 257162196 ps |
| CPU time | 21.37 seconds |
| Started | Aug 17 06:57:08 PM PDT 24 |
| Finished | Aug 17 06:57:30 PM PDT 24 |
| Peak memory | 575508 kb |
| Host | smart-8c79552f-6798-404f-a4e5-2eb58389d59f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300045762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_error_random.300045762 |
| Directory | /workspace/92.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random.2749098792 |
| Short name | T2757 |
| Test name | |
| Test status | |
| Simulation time | 2180668777 ps |
| CPU time | 89.03 seconds |
| Started | Aug 17 06:57:04 PM PDT 24 |
| Finished | Aug 17 06:58:33 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-a47b53a1-829c-4636-900d-f8facf2f3c87 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2749098792 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random.2749098792 |
| Directory | /workspace/92.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_large_delays.4057339540 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 9999936973 ps |
| CPU time | 108.29 seconds |
| Started | Aug 17 06:57:04 PM PDT 24 |
| Finished | Aug 17 06:58:52 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-f935d342-c921-4e04-9a73-0c84222fe582 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057339540 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_large_delays.4057339540 |
| Directory | /workspace/92.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_slow_rsp.908318320 |
| Short name | T2480 |
| Test name | |
| Test status | |
| Simulation time | 22800329497 ps |
| CPU time | 389.29 seconds |
| Started | Aug 17 06:57:07 PM PDT 24 |
| Finished | Aug 17 07:03:36 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-22275bd2-2290-42df-94b1-48ba4e9e5e63 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908318320 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_slow_rsp.908318320 |
| Directory | /workspace/92.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.1656834408 |
| Short name | T2443 |
| Test name | |
| Test status | |
| Simulation time | 374058548 ps |
| CPU time | 30.09 seconds |
| Started | Aug 17 06:57:07 PM PDT 24 |
| Finished | Aug 17 06:57:37 PM PDT 24 |
| Peak memory | 575360 kb |
| Host | smart-e5ec363c-3897-4f28-b8b2-a852690f7861 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656834408 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_random_zero_del ays.1656834408 |
| Directory | /workspace/92.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_same_source.3386374945 |
| Short name | T1397 |
| Test name | |
| Test status | |
| Simulation time | 119025078 ps |
| CPU time | 11.95 seconds |
| Started | Aug 17 06:57:05 PM PDT 24 |
| Finished | Aug 17 06:57:17 PM PDT 24 |
| Peak memory | 575572 kb |
| Host | smart-47079589-8804-4e9b-ad31-62602f148920 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3386374945 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_same_source.3386374945 |
| Directory | /workspace/92.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke.3900735327 |
| Short name | T1757 |
| Test name | |
| Test status | |
| Simulation time | 55455615 ps |
| CPU time | 6.44 seconds |
| Started | Aug 17 06:57:07 PM PDT 24 |
| Finished | Aug 17 06:57:13 PM PDT 24 |
| Peak memory | 573444 kb |
| Host | smart-73081be1-b7f5-4c19-a987-756c073b1d56 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900735327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke.3900735327 |
| Directory | /workspace/92.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_large_delays.69600191 |
| Short name | T1383 |
| Test name | |
| Test status | |
| Simulation time | 8132971323 ps |
| CPU time | 81.76 seconds |
| Started | Aug 17 06:57:06 PM PDT 24 |
| Finished | Aug 17 06:58:27 PM PDT 24 |
| Peak memory | 573516 kb |
| Host | smart-577a99c9-23d0-44a2-9411-9cffac1de864 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69600191 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_large_delays.69600191 |
| Directory | /workspace/92.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_slow_rsp.2936242174 |
| Short name | T2557 |
| Test name | |
| Test status | |
| Simulation time | 4036242096 ps |
| CPU time | 67.77 seconds |
| Started | Aug 17 06:57:07 PM PDT 24 |
| Finished | Aug 17 06:58:15 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-928a14e8-e484-421b-8099-ce6911914beb |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936242174 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_slow_rsp.2936242174 |
| Directory | /workspace/92.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_smoke_zero_delays.3776310188 |
| Short name | T2190 |
| Test name | |
| Test status | |
| Simulation time | 49367855 ps |
| CPU time | 6.64 seconds |
| Started | Aug 17 06:57:07 PM PDT 24 |
| Finished | Aug 17 06:57:14 PM PDT 24 |
| Peak memory | 573428 kb |
| Host | smart-55eab081-b3f6-41f7-97ac-6fea340f7eca |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776310188 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_smoke_zero_delay s.3776310188 |
| Directory | /workspace/92.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all.1540206075 |
| Short name | T2302 |
| Test name | |
| Test status | |
| Simulation time | 198337519 ps |
| CPU time | 8.69 seconds |
| Started | Aug 17 06:57:07 PM PDT 24 |
| Finished | Aug 17 06:57:15 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-48ad5c01-8049-40e5-af29-bc1bdff48482 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540206075 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all.1540206075 |
| Directory | /workspace/92.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_error.2547217279 |
| Short name | T1682 |
| Test name | |
| Test status | |
| Simulation time | 421832876 ps |
| CPU time | 31.22 seconds |
| Started | Aug 17 06:57:06 PM PDT 24 |
| Finished | Aug 17 06:57:37 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-356d3d56-9ffc-4309-a7cd-5319ee4f4419 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2547217279 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_with_error.2547217279 |
| Directory | /workspace/92.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_rand_reset.582170033 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2184113287 ps |
| CPU time | 497.64 seconds |
| Started | Aug 17 06:57:08 PM PDT 24 |
| Finished | Aug 17 07:05:26 PM PDT 24 |
| Peak memory | 576396 kb |
| Host | smart-7e500416-aedc-47fa-ae8a-2592e1c84b8c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582170033 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_all_ with_rand_reset.582170033 |
| Directory | /workspace/92.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_stress_all_with_reset_error.1438747144 |
| Short name | T2716 |
| Test name | |
| Test status | |
| Simulation time | 180295161 ps |
| CPU time | 70.35 seconds |
| Started | Aug 17 06:57:04 PM PDT 24 |
| Finished | Aug 17 06:58:14 PM PDT 24 |
| Peak memory | 576252 kb |
| Host | smart-f4a706c5-f253-49b2-a82c-72aa9d9776d2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438747144 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_stress_al l_with_reset_error.1438747144 |
| Directory | /workspace/92.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/92.xbar_unmapped_addr.2438891140 |
| Short name | T2039 |
| Test name | |
| Test status | |
| Simulation time | 145271514 ps |
| CPU time | 19.57 seconds |
| Started | Aug 17 06:57:11 PM PDT 24 |
| Finished | Aug 17 06:57:30 PM PDT 24 |
| Peak memory | 575452 kb |
| Host | smart-04e8dd1c-e23f-4414-bca3-18ac30d264b4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438891140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 92.xbar_unmapped_addr.2438891140 |
| Directory | /workspace/92.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device.3255903254 |
| Short name | T2227 |
| Test name | |
| Test status | |
| Simulation time | 2359071374 ps |
| CPU time | 111.54 seconds |
| Started | Aug 17 06:57:11 PM PDT 24 |
| Finished | Aug 17 06:59:03 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-c6f9cfc2-eeff-4bbc-aa46-a35b2a2a2e8f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255903254 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_device .3255903254 |
| Directory | /workspace/93.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_access_same_device_slow_rsp.1454978539 |
| Short name | T2422 |
| Test name | |
| Test status | |
| Simulation time | 37692042918 ps |
| CPU time | 689.05 seconds |
| Started | Aug 17 06:57:10 PM PDT 24 |
| Finished | Aug 17 07:08:39 PM PDT 24 |
| Peak memory | 575676 kb |
| Host | smart-90134f6f-6524-4182-a17f-500d9dbb832e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454978539 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_access_same_ device_slow_rsp.1454978539 |
| Directory | /workspace/93.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_and_unmapped_addr.3931334023 |
| Short name | T1679 |
| Test name | |
| Test status | |
| Simulation time | 1495232108 ps |
| CPU time | 52.54 seconds |
| Started | Aug 17 06:57:12 PM PDT 24 |
| Finished | Aug 17 06:58:05 PM PDT 24 |
| Peak memory | 575616 kb |
| Host | smart-993db26a-1ef1-47f8-9928-7f6f8763b58b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931334023 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_and_unmapped_add r.3931334023 |
| Directory | /workspace/93.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_error_random.4196662167 |
| Short name | T1671 |
| Test name | |
| Test status | |
| Simulation time | 477000030 ps |
| CPU time | 37.01 seconds |
| Started | Aug 17 06:57:12 PM PDT 24 |
| Finished | Aug 17 06:57:49 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-38af2436-1225-42cb-b0a5-b973c7d87f9a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196662167 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_error_random.4196662167 |
| Directory | /workspace/93.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random.1462749624 |
| Short name | T2161 |
| Test name | |
| Test status | |
| Simulation time | 137482284 ps |
| CPU time | 12.7 seconds |
| Started | Aug 17 06:57:13 PM PDT 24 |
| Finished | Aug 17 06:57:26 PM PDT 24 |
| Peak memory | 575428 kb |
| Host | smart-f08cf41c-60cb-4a37-9e12-e35470bf8b2f |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462749624 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random.1462749624 |
| Directory | /workspace/93.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_large_delays.412656532 |
| Short name | T2318 |
| Test name | |
| Test status | |
| Simulation time | 102863014017 ps |
| CPU time | 1145.03 seconds |
| Started | Aug 17 06:57:11 PM PDT 24 |
| Finished | Aug 17 07:16:17 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-6c96de0e-8f6a-48ba-a125-e9808477358e |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412656532 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_large_delays.412656532 |
| Directory | /workspace/93.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_slow_rsp.2362335931 |
| Short name | T2739 |
| Test name | |
| Test status | |
| Simulation time | 38228999577 ps |
| CPU time | 706.75 seconds |
| Started | Aug 17 06:57:10 PM PDT 24 |
| Finished | Aug 17 07:08:57 PM PDT 24 |
| Peak memory | 575628 kb |
| Host | smart-903a1a0f-9fa7-45c6-a3c8-668316ed832d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362335931 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_slow_rsp.2362335931 |
| Directory | /workspace/93.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_random_zero_delays.353623953 |
| Short name | T1557 |
| Test name | |
| Test status | |
| Simulation time | 577701481 ps |
| CPU time | 46.84 seconds |
| Started | Aug 17 06:57:11 PM PDT 24 |
| Finished | Aug 17 06:57:58 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-152fb1ed-84e4-465f-8fb5-23588ce0b06d |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353623953 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_random_zero_dela ys.353623953 |
| Directory | /workspace/93.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_same_source.898606010 |
| Short name | T1773 |
| Test name | |
| Test status | |
| Simulation time | 515952958 ps |
| CPU time | 17.25 seconds |
| Started | Aug 17 06:57:12 PM PDT 24 |
| Finished | Aug 17 06:57:29 PM PDT 24 |
| Peak memory | 575416 kb |
| Host | smart-78e9f329-90f1-435f-958e-b5889aa52b3b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898606010 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_same_source.898606010 |
| Directory | /workspace/93.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke.55490587 |
| Short name | T1724 |
| Test name | |
| Test status | |
| Simulation time | 50400231 ps |
| CPU time | 6.65 seconds |
| Started | Aug 17 06:57:04 PM PDT 24 |
| Finished | Aug 17 06:57:11 PM PDT 24 |
| Peak memory | 574064 kb |
| Host | smart-c6b7589f-cbe2-4c15-b56c-e3cc4f90a09c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55490587 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke.55490587 |
| Directory | /workspace/93.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_large_delays.2868775359 |
| Short name | T1542 |
| Test name | |
| Test status | |
| Simulation time | 5174126928 ps |
| CPU time | 52.5 seconds |
| Started | Aug 17 06:57:04 PM PDT 24 |
| Finished | Aug 17 06:57:57 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-b7a2a1da-a93f-47bf-8cf6-47b59d219085 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868775359 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_large_delays.2868775359 |
| Directory | /workspace/93.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_slow_rsp.1761205676 |
| Short name | T1851 |
| Test name | |
| Test status | |
| Simulation time | 5431727177 ps |
| CPU time | 96.42 seconds |
| Started | Aug 17 06:57:10 PM PDT 24 |
| Finished | Aug 17 06:58:47 PM PDT 24 |
| Peak memory | 573436 kb |
| Host | smart-a79bd8b4-a3cf-44f6-9436-3df699f60321 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761205676 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_slow_rsp.1761205676 |
| Directory | /workspace/93.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_smoke_zero_delays.2931734043 |
| Short name | T1635 |
| Test name | |
| Test status | |
| Simulation time | 51523396 ps |
| CPU time | 6.09 seconds |
| Started | Aug 17 06:57:06 PM PDT 24 |
| Finished | Aug 17 06:57:13 PM PDT 24 |
| Peak memory | 574052 kb |
| Host | smart-2663a71d-0bad-40e7-b36b-514820bb30e1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931734043 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_smoke_zero_delay s.2931734043 |
| Directory | /workspace/93.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_error.1196061332 |
| Short name | T2218 |
| Test name | |
| Test status | |
| Simulation time | 3379933405 ps |
| CPU time | 108.39 seconds |
| Started | Aug 17 06:57:16 PM PDT 24 |
| Finished | Aug 17 06:59:05 PM PDT 24 |
| Peak memory | 575712 kb |
| Host | smart-4ba7dff0-4472-48cb-8ca1-64fd455114cc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196061332 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all_with_error.1196061332 |
| Directory | /workspace/93.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_rand_reset.3486433803 |
| Short name | T1848 |
| Test name | |
| Test status | |
| Simulation time | 51405327 ps |
| CPU time | 54.6 seconds |
| Started | Aug 17 06:57:12 PM PDT 24 |
| Finished | Aug 17 06:58:07 PM PDT 24 |
| Peak memory | 575492 kb |
| Host | smart-ee9dca0f-d6be-4933-bb12-9c1b8da5093e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486433803 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_all _with_rand_reset.3486433803 |
| Directory | /workspace/93.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_stress_all_with_reset_error.3680784082 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 662126483 ps |
| CPU time | 197 seconds |
| Started | Aug 17 06:57:12 PM PDT 24 |
| Finished | Aug 17 07:00:29 PM PDT 24 |
| Peak memory | 576344 kb |
| Host | smart-2da7dd1a-70ee-4c6a-85ac-984705b0546c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680784082 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_stress_al l_with_reset_error.3680784082 |
| Directory | /workspace/93.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/93.xbar_unmapped_addr.308207558 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 266765709 ps |
| CPU time | 32.99 seconds |
| Started | Aug 17 06:57:12 PM PDT 24 |
| Finished | Aug 17 06:57:45 PM PDT 24 |
| Peak memory | 575584 kb |
| Host | smart-5c605b69-2b9f-4f22-b435-f4f3dafdc2bf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308207558 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 93.xbar_unmapped_addr.308207558 |
| Directory | /workspace/93.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_access_same_device_slow_rsp.3517643631 |
| Short name | T2189 |
| Test name | |
| Test status | |
| Simulation time | 10968991060 ps |
| CPU time | 191.3 seconds |
| Started | Aug 17 06:57:24 PM PDT 24 |
| Finished | Aug 17 07:00:36 PM PDT 24 |
| Peak memory | 575652 kb |
| Host | smart-cec577b3-a98b-461d-8259-66ab0ab72e54 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3517643631 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_access_same_ device_slow_rsp.3517643631 |
| Directory | /workspace/94.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_and_unmapped_addr.246692487 |
| Short name | T1993 |
| Test name | |
| Test status | |
| Simulation time | 35747936 ps |
| CPU time | 6.88 seconds |
| Started | Aug 17 06:57:19 PM PDT 24 |
| Finished | Aug 17 06:57:26 PM PDT 24 |
| Peak memory | 573508 kb |
| Host | smart-10738e2b-ed3a-4688-8e6c-fc83bb862aca |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246692487 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_and_unmapped_addr .246692487 |
| Directory | /workspace/94.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_error_random.3627042348 |
| Short name | T1367 |
| Test name | |
| Test status | |
| Simulation time | 1073321594 ps |
| CPU time | 36.2 seconds |
| Started | Aug 17 06:57:22 PM PDT 24 |
| Finished | Aug 17 06:57:58 PM PDT 24 |
| Peak memory | 575464 kb |
| Host | smart-46874045-3dcb-4d45-a02b-151a04c5dc11 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627042348 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_error_random.3627042348 |
| Directory | /workspace/94.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random.2591937230 |
| Short name | T1888 |
| Test name | |
| Test status | |
| Simulation time | 1892630988 ps |
| CPU time | 65.89 seconds |
| Started | Aug 17 06:57:17 PM PDT 24 |
| Finished | Aug 17 06:58:23 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-2e7d715e-4d12-45da-88fd-a54013e87018 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591937230 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random.2591937230 |
| Directory | /workspace/94.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_large_delays.1493180996 |
| Short name | T1532 |
| Test name | |
| Test status | |
| Simulation time | 33131741339 ps |
| CPU time | 373.62 seconds |
| Started | Aug 17 06:57:22 PM PDT 24 |
| Finished | Aug 17 07:03:36 PM PDT 24 |
| Peak memory | 575448 kb |
| Host | smart-2e429ab8-f293-4d0e-bdb1-78c1740073c5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493180996 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_large_delays.1493180996 |
| Directory | /workspace/94.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_slow_rsp.2888216201 |
| Short name | T1393 |
| Test name | |
| Test status | |
| Simulation time | 19787453747 ps |
| CPU time | 382.95 seconds |
| Started | Aug 17 06:57:22 PM PDT 24 |
| Finished | Aug 17 07:03:45 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-63371fcc-25b7-4018-8510-cddcab1375ec |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888216201 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_slow_rsp.2888216201 |
| Directory | /workspace/94.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_random_zero_delays.1849101423 |
| Short name | T1978 |
| Test name | |
| Test status | |
| Simulation time | 332457477 ps |
| CPU time | 32.42 seconds |
| Started | Aug 17 06:57:19 PM PDT 24 |
| Finished | Aug 17 06:57:51 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-c65c1e2f-26b4-455c-a426-243c094a6b9f |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849101423 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_random_zero_del ays.1849101423 |
| Directory | /workspace/94.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_same_source.916101016 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 754825415 ps |
| CPU time | 23.38 seconds |
| Started | Aug 17 06:57:24 PM PDT 24 |
| Finished | Aug 17 06:57:48 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-f1131dbe-7bd9-413d-85d3-534f20f14cf1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916101016 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_same_source.916101016 |
| Directory | /workspace/94.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke.3837711959 |
| Short name | T2685 |
| Test name | |
| Test status | |
| Simulation time | 203879599 ps |
| CPU time | 8.54 seconds |
| Started | Aug 17 06:57:20 PM PDT 24 |
| Finished | Aug 17 06:57:29 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-be9fc590-4438-473c-9307-1c9d9ba491ef |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837711959 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke.3837711959 |
| Directory | /workspace/94.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_large_delays.3670643388 |
| Short name | T1690 |
| Test name | |
| Test status | |
| Simulation time | 9476430562 ps |
| CPU time | 109.34 seconds |
| Started | Aug 17 06:57:28 PM PDT 24 |
| Finished | Aug 17 06:59:18 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-14f7ed11-8261-4852-853c-27fefcb1e5b5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670643388 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_large_delays.3670643388 |
| Directory | /workspace/94.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.653068466 |
| Short name | T2276 |
| Test name | |
| Test status | |
| Simulation time | 4213129698 ps |
| CPU time | 69.71 seconds |
| Started | Aug 17 06:57:20 PM PDT 24 |
| Finished | Aug 17 06:58:29 PM PDT 24 |
| Peak memory | 574136 kb |
| Host | smart-cc3f15f9-2048-43c0-a60b-65965a4d662f |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653068466 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_slow_rsp.653068466 |
| Directory | /workspace/94.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_smoke_zero_delays.2041256849 |
| Short name | T2745 |
| Test name | |
| Test status | |
| Simulation time | 42829878 ps |
| CPU time | 5.84 seconds |
| Started | Aug 17 06:57:20 PM PDT 24 |
| Finished | Aug 17 06:57:26 PM PDT 24 |
| Peak memory | 574028 kb |
| Host | smart-c7d74e97-b449-4de5-b5d9-df40dc91c990 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041256849 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_smoke_zero_delay s.2041256849 |
| Directory | /workspace/94.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all.299416942 |
| Short name | T1787 |
| Test name | |
| Test status | |
| Simulation time | 965299352 ps |
| CPU time | 81.83 seconds |
| Started | Aug 17 06:57:28 PM PDT 24 |
| Finished | Aug 17 06:58:50 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-43c4622c-1fae-4a36-81ce-46da719c67ac |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299416942 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all.299416942 |
| Directory | /workspace/94.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_error.350905132 |
| Short name | T2917 |
| Test name | |
| Test status | |
| Simulation time | 5176566778 ps |
| CPU time | 182.08 seconds |
| Started | Aug 17 06:57:20 PM PDT 24 |
| Finished | Aug 17 07:00:22 PM PDT 24 |
| Peak memory | 575692 kb |
| Host | smart-c06e3150-07f8-4537-97c5-87914d0ddac0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350905132 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_with_error.350905132 |
| Directory | /workspace/94.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_rand_reset.181347962 |
| Short name | T2599 |
| Test name | |
| Test status | |
| Simulation time | 5496677346 ps |
| CPU time | 637.19 seconds |
| Started | Aug 17 06:57:19 PM PDT 24 |
| Finished | Aug 17 07:07:56 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-370f97b4-0193-4df1-ad4a-1c6e34e8bd1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181347962 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_rand_reset.181347962 |
| Directory | /workspace/94.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_stress_all_with_reset_error.65598937 |
| Short name | T2262 |
| Test name | |
| Test status | |
| Simulation time | 3222775341 ps |
| CPU time | 449.96 seconds |
| Started | Aug 17 06:57:28 PM PDT 24 |
| Finished | Aug 17 07:04:59 PM PDT 24 |
| Peak memory | 576400 kb |
| Host | smart-ea285e7a-e796-45a1-96e0-b1b84b3a7a0c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65598937 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_stress_all_ with_reset_error.65598937 |
| Directory | /workspace/94.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/94.xbar_unmapped_addr.1560648549 |
| Short name | T1417 |
| Test name | |
| Test status | |
| Simulation time | 89611754 ps |
| CPU time | 12.85 seconds |
| Started | Aug 17 06:57:25 PM PDT 24 |
| Finished | Aug 17 06:57:38 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-8ae93579-8767-4118-b0a9-f669e2d46164 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560648549 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 94.xbar_unmapped_addr.1560648549 |
| Directory | /workspace/94.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device.86310307 |
| Short name | T1865 |
| Test name | |
| Test status | |
| Simulation time | 77449805 ps |
| CPU time | 7.81 seconds |
| Started | Aug 17 06:57:30 PM PDT 24 |
| Finished | Aug 17 06:57:37 PM PDT 24 |
| Peak memory | 574088 kb |
| Host | smart-07d8c3c9-84f4-46b3-bbad-acf03f773efc |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86310307 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_device.86310307 |
| Directory | /workspace/95.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_access_same_device_slow_rsp.2112640280 |
| Short name | T2365 |
| Test name | |
| Test status | |
| Simulation time | 169721630648 ps |
| CPU time | 3117.68 seconds |
| Started | Aug 17 06:57:26 PM PDT 24 |
| Finished | Aug 17 07:49:24 PM PDT 24 |
| Peak memory | 575688 kb |
| Host | smart-0b171fad-8e37-42a1-a42e-df54a9089caa |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112640280 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_access_same_ device_slow_rsp.2112640280 |
| Directory | /workspace/95.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_and_unmapped_addr.1274016477 |
| Short name | T2077 |
| Test name | |
| Test status | |
| Simulation time | 906594207 ps |
| CPU time | 31.72 seconds |
| Started | Aug 17 06:57:27 PM PDT 24 |
| Finished | Aug 17 06:57:59 PM PDT 24 |
| Peak memory | 574112 kb |
| Host | smart-df802ff2-174b-4559-af5a-bbd8254d3ee0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274016477 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_and_unmapped_add r.1274016477 |
| Directory | /workspace/95.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_error_random.1080672341 |
| Short name | T1722 |
| Test name | |
| Test status | |
| Simulation time | 370149150 ps |
| CPU time | 29.87 seconds |
| Started | Aug 17 06:57:27 PM PDT 24 |
| Finished | Aug 17 06:57:57 PM PDT 24 |
| Peak memory | 574348 kb |
| Host | smart-df88b52a-4d7c-40f9-a0c2-944c3a18767a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080672341 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_error_random.1080672341 |
| Directory | /workspace/95.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random.913556069 |
| Short name | T1697 |
| Test name | |
| Test status | |
| Simulation time | 2213680072 ps |
| CPU time | 85.49 seconds |
| Started | Aug 17 06:57:25 PM PDT 24 |
| Finished | Aug 17 06:58:50 PM PDT 24 |
| Peak memory | 575620 kb |
| Host | smart-768ecd84-6be7-4d5f-8562-92610fb438d5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913556069 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random.913556069 |
| Directory | /workspace/95.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_large_delays.2738674867 |
| Short name | T1694 |
| Test name | |
| Test status | |
| Simulation time | 16136202413 ps |
| CPU time | 165.26 seconds |
| Started | Aug 17 06:57:33 PM PDT 24 |
| Finished | Aug 17 07:00:18 PM PDT 24 |
| Peak memory | 575576 kb |
| Host | smart-4511cc18-1f40-4e23-ac64-ab44a1316835 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738674867 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_large_delays.2738674867 |
| Directory | /workspace/95.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.797591332 |
| Short name | T2052 |
| Test name | |
| Test status | |
| Simulation time | 26025927108 ps |
| CPU time | 462.61 seconds |
| Started | Aug 17 06:57:24 PM PDT 24 |
| Finished | Aug 17 07:05:07 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-6b12bde9-f0ad-4ab7-a440-f6dc95e3c51b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797591332 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_slow_rsp.797591332 |
| Directory | /workspace/95.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_random_zero_delays.360521629 |
| Short name | T2916 |
| Test name | |
| Test status | |
| Simulation time | 595227369 ps |
| CPU time | 42.5 seconds |
| Started | Aug 17 06:57:32 PM PDT 24 |
| Finished | Aug 17 06:58:15 PM PDT 24 |
| Peak memory | 575336 kb |
| Host | smart-b86d62da-2e1e-4461-a507-d50c73889d6b |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360521629 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_random_zero_dela ys.360521629 |
| Directory | /workspace/95.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_same_source.2875976202 |
| Short name | T2282 |
| Test name | |
| Test status | |
| Simulation time | 439877692 ps |
| CPU time | 15.06 seconds |
| Started | Aug 17 06:57:26 PM PDT 24 |
| Finished | Aug 17 06:57:41 PM PDT 24 |
| Peak memory | 575420 kb |
| Host | smart-dc4da4b1-2682-4a34-9610-4266ce38251c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875976202 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_same_source.2875976202 |
| Directory | /workspace/95.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke.1504855968 |
| Short name | T1747 |
| Test name | |
| Test status | |
| Simulation time | 215674357 ps |
| CPU time | 9.42 seconds |
| Started | Aug 17 06:57:21 PM PDT 24 |
| Finished | Aug 17 06:57:31 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-9333c3f0-5c85-43b7-8985-30d7cef37e39 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504855968 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke.1504855968 |
| Directory | /workspace/95.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_large_delays.3128284522 |
| Short name | T1445 |
| Test name | |
| Test status | |
| Simulation time | 7997000534 ps |
| CPU time | 90.55 seconds |
| Started | Aug 17 06:57:29 PM PDT 24 |
| Finished | Aug 17 06:59:00 PM PDT 24 |
| Peak memory | 573532 kb |
| Host | smart-fdd51dfe-55e2-4298-9507-3d9bc4d05934 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128284522 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_large_delays.3128284522 |
| Directory | /workspace/95.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_slow_rsp.38680561 |
| Short name | T1481 |
| Test name | |
| Test status | |
| Simulation time | 4430233722 ps |
| CPU time | 73.42 seconds |
| Started | Aug 17 06:57:26 PM PDT 24 |
| Finished | Aug 17 06:58:40 PM PDT 24 |
| Peak memory | 573520 kb |
| Host | smart-77710d78-fd93-4f7c-bbf1-390c6e6d6b74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38680561 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_slow_rsp.38680561 |
| Directory | /workspace/95.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_smoke_zero_delays.2068028556 |
| Short name | T2622 |
| Test name | |
| Test status | |
| Simulation time | 46802526 ps |
| CPU time | 6.38 seconds |
| Started | Aug 17 06:57:28 PM PDT 24 |
| Finished | Aug 17 06:57:35 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-dc493487-5e46-4d46-86ed-3b31507a77de |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2068028556 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_smoke_zero_delay s.2068028556 |
| Directory | /workspace/95.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all.3320082937 |
| Short name | T2271 |
| Test name | |
| Test status | |
| Simulation time | 9441461168 ps |
| CPU time | 340.9 seconds |
| Started | Aug 17 06:57:27 PM PDT 24 |
| Finished | Aug 17 07:03:08 PM PDT 24 |
| Peak memory | 575848 kb |
| Host | smart-452db3db-9d13-46af-b4e2-e0d4ff54a6cd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320082937 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all.3320082937 |
| Directory | /workspace/95.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_error.2483819265 |
| Short name | T2560 |
| Test name | |
| Test status | |
| Simulation time | 958289868 ps |
| CPU time | 65.27 seconds |
| Started | Aug 17 06:57:33 PM PDT 24 |
| Finished | Aug 17 06:58:39 PM PDT 24 |
| Peak memory | 575608 kb |
| Host | smart-98eb9ced-d895-4bad-b9c7-df707784a05e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483819265 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_all_with_error.2483819265 |
| Directory | /workspace/95.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_stress_all_with_reset_error.2291774712 |
| Short name | T1759 |
| Test name | |
| Test status | |
| Simulation time | 7261271788 ps |
| CPU time | 225.22 seconds |
| Started | Aug 17 06:57:25 PM PDT 24 |
| Finished | Aug 17 07:01:10 PM PDT 24 |
| Peak memory | 576296 kb |
| Host | smart-75facaea-6b0e-475a-a43c-50ea465db756 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2291774712 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_stress_al l_with_reset_error.2291774712 |
| Directory | /workspace/95.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/95.xbar_unmapped_addr.2845781757 |
| Short name | T1768 |
| Test name | |
| Test status | |
| Simulation time | 168287856 ps |
| CPU time | 18.51 seconds |
| Started | Aug 17 06:57:32 PM PDT 24 |
| Finished | Aug 17 06:57:51 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-ca0a4f19-b14f-49f9-b6af-4ede649d368a |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845781757 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 95.xbar_unmapped_addr.2845781757 |
| Directory | /workspace/95.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device.1837856205 |
| Short name | T1672 |
| Test name | |
| Test status | |
| Simulation time | 720582603 ps |
| CPU time | 55.71 seconds |
| Started | Aug 17 06:57:32 PM PDT 24 |
| Finished | Aug 17 06:58:28 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-62c7c4d1-37a5-4d49-a307-18cf93115456 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1837856205 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_device .1837856205 |
| Directory | /workspace/96.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_access_same_device_slow_rsp.2072403050 |
| Short name | T2050 |
| Test name | |
| Test status | |
| Simulation time | 83804172905 ps |
| CPU time | 1530.19 seconds |
| Started | Aug 17 06:57:34 PM PDT 24 |
| Finished | Aug 17 07:23:05 PM PDT 24 |
| Peak memory | 575704 kb |
| Host | smart-4af1f0f6-7cf5-4143-8f14-bc4154117201 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072403050 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_access_same_ device_slow_rsp.2072403050 |
| Directory | /workspace/96.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.3822934351 |
| Short name | T1714 |
| Test name | |
| Test status | |
| Simulation time | 476967916 ps |
| CPU time | 21.82 seconds |
| Started | Aug 17 06:57:32 PM PDT 24 |
| Finished | Aug 17 06:57:54 PM PDT 24 |
| Peak memory | 575560 kb |
| Host | smart-edde8be9-37d7-4033-914b-9493dab3006b |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822934351 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_and_unmapped_add r.3822934351 |
| Directory | /workspace/96.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_error_random.4168517207 |
| Short name | T2840 |
| Test name | |
| Test status | |
| Simulation time | 1351554891 ps |
| CPU time | 46.8 seconds |
| Started | Aug 17 06:57:31 PM PDT 24 |
| Finished | Aug 17 06:58:18 PM PDT 24 |
| Peak memory | 575364 kb |
| Host | smart-d2d9e8ca-67b1-41b1-9196-e5be229abd45 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168517207 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_error_random.4168517207 |
| Directory | /workspace/96.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random.29249140 |
| Short name | T2316 |
| Test name | |
| Test status | |
| Simulation time | 1691694425 ps |
| CPU time | 59.32 seconds |
| Started | Aug 17 06:57:24 PM PDT 24 |
| Finished | Aug 17 06:58:23 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-32a5af31-0aeb-4b38-a581-4b3a9628b432 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29249140 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random.29249140 |
| Directory | /workspace/96.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_large_delays.103638863 |
| Short name | T2437 |
| Test name | |
| Test status | |
| Simulation time | 5801108194 ps |
| CPU time | 58.65 seconds |
| Started | Aug 17 06:57:25 PM PDT 24 |
| Finished | Aug 17 06:58:24 PM PDT 24 |
| Peak memory | 574156 kb |
| Host | smart-e7d7526a-ffb9-4e02-9d1d-1cba87229b0b |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103638863 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_large_delays.103638863 |
| Directory | /workspace/96.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_slow_rsp.1205357101 |
| Short name | T2658 |
| Test name | |
| Test status | |
| Simulation time | 49491242622 ps |
| CPU time | 893.35 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 07:12:33 PM PDT 24 |
| Peak memory | 575668 kb |
| Host | smart-19cd2805-44e9-46e9-9b37-6269106ee945 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205357101 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_slow_rsp.1205357101 |
| Directory | /workspace/96.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_random_zero_delays.851186760 |
| Short name | T1760 |
| Test name | |
| Test status | |
| Simulation time | 592831154 ps |
| CPU time | 48.84 seconds |
| Started | Aug 17 06:57:31 PM PDT 24 |
| Finished | Aug 17 06:58:20 PM PDT 24 |
| Peak memory | 575552 kb |
| Host | smart-98b28e67-49e1-4b9c-8cac-46526330bfb2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851186760 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_random_zero_dela ys.851186760 |
| Directory | /workspace/96.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_same_source.1452832489 |
| Short name | T2088 |
| Test name | |
| Test status | |
| Simulation time | 2238447017 ps |
| CPU time | 62.38 seconds |
| Started | Aug 17 06:57:31 PM PDT 24 |
| Finished | Aug 17 06:58:33 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-ca1918a7-6c76-4217-ae50-6d1bc70c15a6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452832489 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_same_source.1452832489 |
| Directory | /workspace/96.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke.578543151 |
| Short name | T1360 |
| Test name | |
| Test status | |
| Simulation time | 44763641 ps |
| CPU time | 6.66 seconds |
| Started | Aug 17 06:57:25 PM PDT 24 |
| Finished | Aug 17 06:57:32 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-b6e9939a-ab2a-41a3-a0df-4a49da02ba79 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578543151 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke.578543151 |
| Directory | /workspace/96.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_large_delays.3090509024 |
| Short name | T1485 |
| Test name | |
| Test status | |
| Simulation time | 6832273830 ps |
| CPU time | 69.57 seconds |
| Started | Aug 17 06:57:24 PM PDT 24 |
| Finished | Aug 17 06:58:34 PM PDT 24 |
| Peak memory | 573496 kb |
| Host | smart-f888efa0-063d-4e84-a4b4-12b6ff50ee35 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090509024 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_large_delays.3090509024 |
| Directory | /workspace/96.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_slow_rsp.4081200286 |
| Short name | T1601 |
| Test name | |
| Test status | |
| Simulation time | 3870655862 ps |
| CPU time | 65.7 seconds |
| Started | Aug 17 06:57:25 PM PDT 24 |
| Finished | Aug 17 06:58:31 PM PDT 24 |
| Peak memory | 573536 kb |
| Host | smart-4fd5bce8-8f32-424c-bdfd-50d2582b1f0d |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081200286 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_slow_rsp.4081200286 |
| Directory | /workspace/96.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3519306684 |
| Short name | T2291 |
| Test name | |
| Test status | |
| Simulation time | 42431363 ps |
| CPU time | 6.54 seconds |
| Started | Aug 17 06:57:25 PM PDT 24 |
| Finished | Aug 17 06:57:32 PM PDT 24 |
| Peak memory | 573448 kb |
| Host | smart-e26c4313-33a7-47d0-969f-ebac38e5db33 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519306684 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_smoke_zero_delay s.3519306684 |
| Directory | /workspace/96.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all.178895597 |
| Short name | T1618 |
| Test name | |
| Test status | |
| Simulation time | 1770245710 ps |
| CPU time | 56.75 seconds |
| Started | Aug 17 06:57:30 PM PDT 24 |
| Finished | Aug 17 06:58:27 PM PDT 24 |
| Peak memory | 575656 kb |
| Host | smart-6cb0bac4-da8f-4f35-b431-73e5f92fc3d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178895597 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all.178895597 |
| Directory | /workspace/96.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_rand_reset.605919741 |
| Short name | T2488 |
| Test name | |
| Test status | |
| Simulation time | 294868859 ps |
| CPU time | 119.48 seconds |
| Started | Aug 17 06:57:34 PM PDT 24 |
| Finished | Aug 17 06:59:33 PM PDT 24 |
| Peak memory | 576172 kb |
| Host | smart-031b95b7-8ad2-4a58-b3bb-b89881ed044d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=605919741 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_res et_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_all_ with_rand_reset.605919741 |
| Directory | /workspace/96.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_stress_all_with_reset_error.3207737191 |
| Short name | T2812 |
| Test name | |
| Test status | |
| Simulation time | 7486638207 ps |
| CPU time | 739.07 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 07:10:00 PM PDT 24 |
| Peak memory | 576408 kb |
| Host | smart-b5723f19-f881-4578-9843-aa8f35ca40e2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207737191 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_stress_al l_with_reset_error.3207737191 |
| Directory | /workspace/96.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/96.xbar_unmapped_addr.2601013545 |
| Short name | T2220 |
| Test name | |
| Test status | |
| Simulation time | 1029779298 ps |
| CPU time | 43.78 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 06:58:23 PM PDT 24 |
| Peak memory | 575604 kb |
| Host | smart-6b10832e-03ec-46e1-91e4-cdcda0dabbb5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2601013545 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 96.xbar_unmapped_addr.2601013545 |
| Directory | /workspace/96.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device.877979110 |
| Short name | T2405 |
| Test name | |
| Test status | |
| Simulation time | 945619606 ps |
| CPU time | 40.52 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 06:58:21 PM PDT 24 |
| Peak memory | 575512 kb |
| Host | smart-6bbe96d6-b4b0-4ee8-a61d-686f12f08d74 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=877979110 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_device. 877979110 |
| Directory | /workspace/97.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_access_same_device_slow_rsp.1605480635 |
| Short name | T2128 |
| Test name | |
| Test status | |
| Simulation time | 85635500696 ps |
| CPU time | 1632.44 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 07:24:53 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-10d62485-1f40-4aa3-b36a-0bb890f9f8d0 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605480635 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_access_same_ device_slow_rsp.1605480635 |
| Directory | /workspace/97.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_and_unmapped_addr.3499859452 |
| Short name | T2325 |
| Test name | |
| Test status | |
| Simulation time | 52476782 ps |
| CPU time | 9.24 seconds |
| Started | Aug 17 06:57:41 PM PDT 24 |
| Finished | Aug 17 06:57:50 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-a3026e90-31a0-429e-b7db-666e8f99ba69 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499859452 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_and_unmapped_add r.3499859452 |
| Directory | /workspace/97.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_error_random.2926294993 |
| Short name | T1578 |
| Test name | |
| Test status | |
| Simulation time | 162831773 ps |
| CPU time | 14.11 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 06:57:55 PM PDT 24 |
| Peak memory | 575392 kb |
| Host | smart-813a194e-218c-4b81-90dc-17755723c7f2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2926294993 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_error_random.2926294993 |
| Directory | /workspace/97.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random.3732713126 |
| Short name | T2477 |
| Test name | |
| Test status | |
| Simulation time | 1508228110 ps |
| CPU time | 53.44 seconds |
| Started | Aug 17 06:57:42 PM PDT 24 |
| Finished | Aug 17 06:58:35 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-25988e9e-63b0-4c5e-8b4f-d8f5a9481b48 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732713126 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random.3732713126 |
| Directory | /workspace/97.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_large_delays.1697167362 |
| Short name | T1857 |
| Test name | |
| Test status | |
| Simulation time | 21441584461 ps |
| CPU time | 245.13 seconds |
| Started | Aug 17 06:57:41 PM PDT 24 |
| Finished | Aug 17 07:01:47 PM PDT 24 |
| Peak memory | 575480 kb |
| Host | smart-3da1da68-6b57-4e10-8050-8a52f2423fb3 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697167362 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_large_delays.1697167362 |
| Directory | /workspace/97.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_slow_rsp.1271542951 |
| Short name | T1610 |
| Test name | |
| Test status | |
| Simulation time | 5555710488 ps |
| CPU time | 100.32 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 06:59:20 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-1b807cbd-ec14-49e2-8d03-b47bed21cda1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271542951 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_slow_rsp.1271542951 |
| Directory | /workspace/97.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_random_zero_delays.4095429030 |
| Short name | T1820 |
| Test name | |
| Test status | |
| Simulation time | 516278416 ps |
| CPU time | 41.54 seconds |
| Started | Aug 17 06:57:42 PM PDT 24 |
| Finished | Aug 17 06:58:23 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-6fc47f5d-3bd2-49f8-8b28-590ff51178e4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4095429030 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_random_zero_del ays.4095429030 |
| Directory | /workspace/97.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_same_source.3237158564 |
| Short name | T2373 |
| Test name | |
| Test status | |
| Simulation time | 1086782034 ps |
| CPU time | 34.08 seconds |
| Started | Aug 17 06:57:39 PM PDT 24 |
| Finished | Aug 17 06:58:13 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-04e94064-c69c-46fe-964f-ecae60c8d7d8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3237158564 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_same_source.3237158564 |
| Directory | /workspace/97.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke.1071596747 |
| Short name | T1384 |
| Test name | |
| Test status | |
| Simulation time | 55187683 ps |
| CPU time | 6.51 seconds |
| Started | Aug 17 06:57:33 PM PDT 24 |
| Finished | Aug 17 06:57:40 PM PDT 24 |
| Peak memory | 573488 kb |
| Host | smart-0548ea6a-6b24-4252-8589-cddd213181ff |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071596747 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke.1071596747 |
| Directory | /workspace/97.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_large_delays.3873754673 |
| Short name | T2928 |
| Test name | |
| Test status | |
| Simulation time | 8881858378 ps |
| CPU time | 89.01 seconds |
| Started | Aug 17 06:57:43 PM PDT 24 |
| Finished | Aug 17 06:59:12 PM PDT 24 |
| Peak memory | 573556 kb |
| Host | smart-99060911-d6eb-48cb-8b7b-8df7f7d54239 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873754673 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_large_delays.3873754673 |
| Directory | /workspace/97.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_slow_rsp.1540288520 |
| Short name | T1482 |
| Test name | |
| Test status | |
| Simulation time | 4827394682 ps |
| CPU time | 83.61 seconds |
| Started | Aug 17 06:57:43 PM PDT 24 |
| Finished | Aug 17 06:59:07 PM PDT 24 |
| Peak memory | 574172 kb |
| Host | smart-c8df62b1-78e9-4983-9fb8-aa49543b2e37 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540288520 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_slow_rsp.1540288520 |
| Directory | /workspace/97.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_smoke_zero_delays.589508560 |
| Short name | T1892 |
| Test name | |
| Test status | |
| Simulation time | 42770315 ps |
| CPU time | 6.15 seconds |
| Started | Aug 17 06:57:34 PM PDT 24 |
| Finished | Aug 17 06:57:40 PM PDT 24 |
| Peak memory | 573432 kb |
| Host | smart-72917843-84fa-4535-aa6d-40f013a12b95 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589508560 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_smoke_zero_delays .589508560 |
| Directory | /workspace/97.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all.1566527978 |
| Short name | T1961 |
| Test name | |
| Test status | |
| Simulation time | 9978732863 ps |
| CPU time | 366.68 seconds |
| Started | Aug 17 06:57:42 PM PDT 24 |
| Finished | Aug 17 07:03:49 PM PDT 24 |
| Peak memory | 576456 kb |
| Host | smart-fd5f3674-effd-4617-b40a-ce4841450eea |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566527978 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all.1566527978 |
| Directory | /workspace/97.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_error.3081625449 |
| Short name | T1752 |
| Test name | |
| Test status | |
| Simulation time | 9545955259 ps |
| CPU time | 365.23 seconds |
| Started | Aug 17 06:57:39 PM PDT 24 |
| Finished | Aug 17 07:03:45 PM PDT 24 |
| Peak memory | 575708 kb |
| Host | smart-78636ce3-5c1f-4094-9a3a-e5cbcc0810dd |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3081625449 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_all_with_error.3081625449 |
| Directory | /workspace/97.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_stress_all_with_reset_error.2517545665 |
| Short name | T2761 |
| Test name | |
| Test status | |
| Simulation time | 502006163 ps |
| CPU time | 89.52 seconds |
| Started | Aug 17 06:57:38 PM PDT 24 |
| Finished | Aug 17 06:59:08 PM PDT 24 |
| Peak memory | 576256 kb |
| Host | smart-b8075f7c-974f-4f6b-b727-fb0d41799ac4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517545665 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_r eset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_stress_al l_with_reset_error.2517545665 |
| Directory | /workspace/97.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/97.xbar_unmapped_addr.2150532142 |
| Short name | T2369 |
| Test name | |
| Test status | |
| Simulation time | 1127924131 ps |
| CPU time | 46.93 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 06:58:27 PM PDT 24 |
| Peak memory | 575556 kb |
| Host | smart-3777d00f-e3d8-4bc4-a2d8-7a9bc1ee6a1d |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150532142 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 97.xbar_unmapped_addr.2150532142 |
| Directory | /workspace/97.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device.332531237 |
| Short name | T2569 |
| Test name | |
| Test status | |
| Simulation time | 3715317657 ps |
| CPU time | 144.61 seconds |
| Started | Aug 17 06:57:47 PM PDT 24 |
| Finished | Aug 17 07:00:12 PM PDT 24 |
| Peak memory | 575600 kb |
| Host | smart-08f26831-c637-4259-89fd-e4d3f5283baf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332531237 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_device. 332531237 |
| Directory | /workspace/98.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_access_same_device_slow_rsp.226660958 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 9083478259 ps |
| CPU time | 147.71 seconds |
| Started | Aug 17 06:57:50 PM PDT 24 |
| Finished | Aug 17 07:00:18 PM PDT 24 |
| Peak memory | 573524 kb |
| Host | smart-02da8acf-6e2a-490d-844a-ef08417e3db4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226660958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device _vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_access_same_d evice_slow_rsp.226660958 |
| Directory | /workspace/98.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_and_unmapped_addr.448764762 |
| Short name | T2364 |
| Test name | |
| Test status | |
| Simulation time | 114275763 ps |
| CPU time | 13.56 seconds |
| Started | Aug 17 06:57:49 PM PDT 24 |
| Finished | Aug 17 06:58:02 PM PDT 24 |
| Peak memory | 575384 kb |
| Host | smart-560ca657-0049-4d51-bd5c-c038a3ccc8e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448764762 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_and_unmapped_addr .448764762 |
| Directory | /workspace/98.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_error_random.1234929777 |
| Short name | T1840 |
| Test name | |
| Test status | |
| Simulation time | 1463573694 ps |
| CPU time | 48.83 seconds |
| Started | Aug 17 06:57:46 PM PDT 24 |
| Finished | Aug 17 06:58:35 PM PDT 24 |
| Peak memory | 575548 kb |
| Host | smart-79a214d5-2b76-43b2-b64c-734d96fff74e |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234929777 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_error_random.1234929777 |
| Directory | /workspace/98.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random.3428009499 |
| Short name | T2235 |
| Test name | |
| Test status | |
| Simulation time | 553818345 ps |
| CPU time | 49.14 seconds |
| Started | Aug 17 06:57:46 PM PDT 24 |
| Finished | Aug 17 06:58:35 PM PDT 24 |
| Peak memory | 575488 kb |
| Host | smart-23ce3fd9-ab78-44ad-b397-d0eb6200c833 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428009499 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random.3428009499 |
| Directory | /workspace/98.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_large_delays.4035945407 |
| Short name | T2790 |
| Test name | |
| Test status | |
| Simulation time | 90167667513 ps |
| CPU time | 965.43 seconds |
| Started | Aug 17 06:57:46 PM PDT 24 |
| Finished | Aug 17 07:13:51 PM PDT 24 |
| Peak memory | 575472 kb |
| Host | smart-3587969c-0ba3-4c51-98bf-2f30758d7ec2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035945407 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_large_delays.4035945407 |
| Directory | /workspace/98.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_slow_rsp.645459977 |
| Short name | T1988 |
| Test name | |
| Test status | |
| Simulation time | 6809339374 ps |
| CPU time | 110.82 seconds |
| Started | Aug 17 06:57:45 PM PDT 24 |
| Finished | Aug 17 06:59:36 PM PDT 24 |
| Peak memory | 575424 kb |
| Host | smart-daf0261d-66c1-400b-a9c4-3719a0c4ce83 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645459977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_slow_rsp.645459977 |
| Directory | /workspace/98.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_random_zero_delays.2172012977 |
| Short name | T2002 |
| Test name | |
| Test status | |
| Simulation time | 507844457 ps |
| CPU time | 45.64 seconds |
| Started | Aug 17 06:57:47 PM PDT 24 |
| Finished | Aug 17 06:58:33 PM PDT 24 |
| Peak memory | 575516 kb |
| Host | smart-0771c52e-dae3-4a5d-a8b8-3f90e243ba18 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172012977 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_random_zero_del ays.2172012977 |
| Directory | /workspace/98.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_same_source.1742736731 |
| Short name | T2097 |
| Test name | |
| Test status | |
| Simulation time | 1921356347 ps |
| CPU time | 60.05 seconds |
| Started | Aug 17 06:57:48 PM PDT 24 |
| Finished | Aug 17 06:58:48 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-080c7753-114c-4ffc-aeef-08745d903fa1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742736731 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_same_source.1742736731 |
| Directory | /workspace/98.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke.3740174958 |
| Short name | T2570 |
| Test name | |
| Test status | |
| Simulation time | 238128728 ps |
| CPU time | 10.15 seconds |
| Started | Aug 17 06:57:41 PM PDT 24 |
| Finished | Aug 17 06:57:51 PM PDT 24 |
| Peak memory | 573452 kb |
| Host | smart-980599f9-9799-4678-90c1-603cff897141 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3740174958 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke.3740174958 |
| Directory | /workspace/98.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_large_delays.3943582008 |
| Short name | T2019 |
| Test name | |
| Test status | |
| Simulation time | 7025601458 ps |
| CPU time | 74.63 seconds |
| Started | Aug 17 06:57:40 PM PDT 24 |
| Finished | Aug 17 06:58:55 PM PDT 24 |
| Peak memory | 573528 kb |
| Host | smart-a69113dd-e71e-4d06-839d-0e1b5b6cb6df |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943582008 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_large_delays.3943582008 |
| Directory | /workspace/98.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_slow_rsp.455702742 |
| Short name | T2627 |
| Test name | |
| Test status | |
| Simulation time | 5865892532 ps |
| CPU time | 97.11 seconds |
| Started | Aug 17 06:57:42 PM PDT 24 |
| Finished | Aug 17 06:59:20 PM PDT 24 |
| Peak memory | 573540 kb |
| Host | smart-6c7928b0-ac09-4c72-80b6-a82baa99586c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455702742 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_slow_rsp.455702742 |
| Directory | /workspace/98.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_smoke_zero_delays.2682457990 |
| Short name | T2487 |
| Test name | |
| Test status | |
| Simulation time | 38863724 ps |
| CPU time | 5.3 seconds |
| Started | Aug 17 06:57:42 PM PDT 24 |
| Finished | Aug 17 06:57:47 PM PDT 24 |
| Peak memory | 573360 kb |
| Host | smart-417c7951-afe5-45c0-b860-a9426e2733e6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682457990 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vs eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_smoke_zero_delay s.2682457990 |
| Directory | /workspace/98.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all.504097430 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 935704990 ps |
| CPU time | 78.47 seconds |
| Started | Aug 17 06:57:46 PM PDT 24 |
| Finished | Aug 17 06:59:05 PM PDT 24 |
| Peak memory | 575984 kb |
| Host | smart-c5c3a2fe-91b1-4b8a-a754-92bac9a76adf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504097430 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all.504097430 |
| Directory | /workspace/98.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_error.2347877536 |
| Short name | T2386 |
| Test name | |
| Test status | |
| Simulation time | 22489609906 ps |
| CPU time | 881.41 seconds |
| Started | Aug 17 06:57:46 PM PDT 24 |
| Finished | Aug 17 07:12:28 PM PDT 24 |
| Peak memory | 576420 kb |
| Host | smart-2728ed6d-6231-4862-b243-0dd44bbf8ae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347877536 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all_with_error.2347877536 |
| Directory | /workspace/98.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_rand_reset.1518266327 |
| Short name | T2810 |
| Test name | |
| Test status | |
| Simulation time | 1272988854 ps |
| CPU time | 319.6 seconds |
| Started | Aug 17 06:57:51 PM PDT 24 |
| Finished | Aug 17 07:03:10 PM PDT 24 |
| Peak memory | 576340 kb |
| Host | smart-0c0bbfef-7a25-4c7e-9a7a-f7e0d47999f4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518266327 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_rand_reset.1518266327 |
| Directory | /workspace/98.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.775957403 |
| Short name | T2617 |
| Test name | |
| Test status | |
| Simulation time | 15355104860 ps |
| CPU time | 710.47 seconds |
| Started | Aug 17 06:57:57 PM PDT 24 |
| Finished | Aug 17 07:09:47 PM PDT 24 |
| Peak memory | 576392 kb |
| Host | smart-ffecc5ec-0d60-4720-afc0-521b8bc70972 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775957403 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_stress_all _with_reset_error.775957403 |
| Directory | /workspace/98.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/98.xbar_unmapped_addr.3056028401 |
| Short name | T2101 |
| Test name | |
| Test status | |
| Simulation time | 146624616 ps |
| CPU time | 17.22 seconds |
| Started | Aug 17 06:57:50 PM PDT 24 |
| Finished | Aug 17 06:58:08 PM PDT 24 |
| Peak memory | 575696 kb |
| Host | smart-d409388a-6555-413d-acea-3092c07de357 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3056028401 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 98.xbar_unmapped_addr.3056028401 |
| Directory | /workspace/98.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device.912542326 |
| Short name | T2900 |
| Test name | |
| Test status | |
| Simulation time | 3485553868 ps |
| CPU time | 136.82 seconds |
| Started | Aug 17 06:57:52 PM PDT 24 |
| Finished | Aug 17 07:00:09 PM PDT 24 |
| Peak memory | 575680 kb |
| Host | smart-3ac4b998-5899-48f1-97e0-ed603758c1df |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912542326 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_device_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_device. 912542326 |
| Directory | /workspace/99.xbar_access_same_device/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_access_same_device_slow_rsp.2453778678 |
| Short name | T2457 |
| Test name | |
| Test status | |
| Simulation time | 58491116316 ps |
| CPU time | 1086.81 seconds |
| Started | Aug 17 06:57:56 PM PDT 24 |
| Finished | Aug 17 07:16:03 PM PDT 24 |
| Peak memory | 575596 kb |
| Host | smart-0e8c8985-6e87-4760-9ecf-74d138aee5c2 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453778678 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_access_same_devic e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_access_same_ device_slow_rsp.2453778678 |
| Directory | /workspace/99.xbar_access_same_device_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_and_unmapped_addr.2381652581 |
| Short name | T2319 |
| Test name | |
| Test status | |
| Simulation time | 962610252 ps |
| CPU time | 39.44 seconds |
| Started | Aug 17 06:57:54 PM PDT 24 |
| Finished | Aug 17 06:58:34 PM PDT 24 |
| Peak memory | 575304 kb |
| Host | smart-24989ae2-1c0b-4417-8d6b-57f5706ca91c |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2381652581 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_and_unmapped_add r.2381652581 |
| Directory | /workspace/99.xbar_error_and_unmapped_addr/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_error_random.957222947 |
| Short name | T1630 |
| Test name | |
| Test status | |
| Simulation time | 698183309 ps |
| CPU time | 20.36 seconds |
| Started | Aug 17 06:57:54 PM PDT 24 |
| Finished | Aug 17 06:58:14 PM PDT 24 |
| Peak memory | 575528 kb |
| Host | smart-40f915a5-1e41-4221-af19-a096c83585aa |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957222947 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_error_random.957222947 |
| Directory | /workspace/99.xbar_error_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random.2657386452 |
| Short name | T2326 |
| Test name | |
| Test status | |
| Simulation time | 1416220483 ps |
| CPU time | 51.84 seconds |
| Started | Aug 17 06:57:54 PM PDT 24 |
| Finished | Aug 17 06:58:46 PM PDT 24 |
| Peak memory | 575588 kb |
| Host | smart-6629cb61-daf2-48b3-8264-5ff693557224 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657386452 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random.2657386452 |
| Directory | /workspace/99.xbar_random/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_large_delays.3025882128 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 50237607967 ps |
| CPU time | 565.16 seconds |
| Started | Aug 17 06:57:53 PM PDT 24 |
| Finished | Aug 17 07:07:18 PM PDT 24 |
| Peak memory | 575648 kb |
| Host | smart-012a4d5c-a9aa-45c1-be14-d9fefd3e691c |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3025882128 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_large_delays.3025882128 |
| Directory | /workspace/99.xbar_random_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_slow_rsp.1650205314 |
| Short name | T1798 |
| Test name | |
| Test status | |
| Simulation time | 29722418084 ps |
| CPU time | 524.2 seconds |
| Started | Aug 17 06:57:58 PM PDT 24 |
| Finished | Aug 17 07:06:42 PM PDT 24 |
| Peak memory | 575632 kb |
| Host | smart-bca3a5f5-6575-44dd-adf9-879abcc71a90 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1650205314 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_slow_rsp.1650205314 |
| Directory | /workspace/99.xbar_random_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_random_zero_delays.4264802555 |
| Short name | T1596 |
| Test name | |
| Test status | |
| Simulation time | 213655763 ps |
| CPU time | 20.77 seconds |
| Started | Aug 17 06:57:53 PM PDT 24 |
| Finished | Aug 17 06:58:14 PM PDT 24 |
| Peak memory | 575476 kb |
| Host | smart-29050126-e57d-435c-936f-f322d7939403 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264802555 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_random_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_random_zero_del ays.4264802555 |
| Directory | /workspace/99.xbar_random_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_same_source.2714385908 |
| Short name | T1870 |
| Test name | |
| Test status | |
| Simulation time | 663508346 ps |
| CPU time | 22.75 seconds |
| Started | Aug 17 06:57:55 PM PDT 24 |
| Finished | Aug 17 06:58:17 PM PDT 24 |
| Peak memory | 575468 kb |
| Host | smart-bf7533a0-dd11-4f56-a9d5-a6e173fdf1a4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714385908 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_same_source_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_same_source.2714385908 |
| Directory | /workspace/99.xbar_same_source/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke.2875559257 |
| Short name | T2929 |
| Test name | |
| Test status | |
| Simulation time | 53607908 ps |
| CPU time | 7.41 seconds |
| Started | Aug 17 06:57:57 PM PDT 24 |
| Finished | Aug 17 06:58:05 PM PDT 24 |
| Peak memory | 573420 kb |
| Host | smart-53be3833-735e-4a2c-8ee5-60195565b150 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875559257 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke.2875559257 |
| Directory | /workspace/99.xbar_smoke/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_large_delays.151597887 |
| Short name | T1939 |
| Test name | |
| Test status | |
| Simulation time | 8014171312 ps |
| CPU time | 82.74 seconds |
| Started | Aug 17 06:57:59 PM PDT 24 |
| Finished | Aug 17 06:59:22 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-9d005839-218c-4c12-a36b-2de03bf2e4f8 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=1000 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=1000 +max_host_valid_ len=2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151597887 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_large_delays.151597887 |
| Directory | /workspace/99.xbar_smoke_large_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_slow_rsp.872420352 |
| Short name | T2587 |
| Test name | |
| Test status | |
| Simulation time | 4963043824 ps |
| CPU time | 89.88 seconds |
| Started | Aug 17 06:57:56 PM PDT 24 |
| Finished | Aug 17 06:59:26 PM PDT 24 |
| Peak memory | 573484 kb |
| Host | smart-8c8acbd2-e64f-4a92-8455-36b5e1cffae5 |
| User | root |
| Command | /workspace/cover_reg_top/simv +max_host_req_delay=10 +max_host_rsp_delay=1000 +max_device_req_delay=1000 +max_device_rsp_delay=10 +max_host_valid_len= 2000 +max_device_valid_len=2000 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872420352 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_slow_rsp.872420352 |
| Directory | /workspace/99.xbar_smoke_slow_rsp/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_smoke_zero_delays.66228118 |
| Short name | T2100 |
| Test name | |
| Test status | |
| Simulation time | 56987305 ps |
| CPU time | 6.98 seconds |
| Started | Aug 17 06:57:55 PM PDT 24 |
| Finished | Aug 17 06:58:02 PM PDT 24 |
| Peak memory | 574068 kb |
| Host | smart-f78c8a7b-08a9-4d54-b193-a555db08aaf6 |
| User | root |
| Command | /workspace/cover_reg_top/simv +zero_delays=1 +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do / workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66228118 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_smoke_zero_delays.66228118 |
| Directory | /workspace/99.xbar_smoke_zero_delays/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all.4240840479 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 12527911282 ps |
| CPU time | 517.9 seconds |
| Started | Aug 17 06:57:54 PM PDT 24 |
| Finished | Aug 17 07:06:33 PM PDT 24 |
| Peak memory | 576468 kb |
| Host | smart-29ca82b5-a2a1-4a8d-b65f-40d0cbe8efc7 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240840479 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all.4240840479 |
| Directory | /workspace/99.xbar_stress_all/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_error.597691087 |
| Short name | T2552 |
| Test name | |
| Test status | |
| Simulation time | 2956955059 ps |
| CPU time | 205.69 seconds |
| Started | Aug 17 06:57:54 PM PDT 24 |
| Finished | Aug 17 07:01:20 PM PDT 24 |
| Peak memory | 575968 kb |
| Host | smart-ec9c0210-b29f-49a1-9489-06bcb4ae64cf |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597691087 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all_with_error.597691087 |
| Directory | /workspace/99.xbar_stress_all_with_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_rand_reset.1534195085 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 11994828254 ps |
| CPU time | 611.86 seconds |
| Started | Aug 17 06:57:53 PM PDT 24 |
| Finished | Aug 17 07:08:05 PM PDT 24 |
| Peak memory | 575544 kb |
| Host | smart-e4f0c15c-87cc-48ad-8c0b-8134e43138b1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534195085 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_rand_reset.1534195085 |
| Directory | /workspace/99.xbar_stress_all_with_rand_reset/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_stress_all_with_reset_error.177466328 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 219525733 ps |
| CPU time | 106.37 seconds |
| Started | Aug 17 06:57:57 PM PDT 24 |
| Finished | Aug 17 06:59:44 PM PDT 24 |
| Peak memory | 576332 kb |
| Host | smart-070259eb-5628-4385-8f30-e0baecf4c6c1 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177466328 -assert nopostproc +UVM_TESTNAME=xbar_error_test +UVM_TEST_SEQ=xbar_stress_all_with_rand_re set_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_stress_all _with_reset_error.177466328 |
| Directory | /workspace/99.xbar_stress_all_with_reset_error/latest |
| Test location | /workspace/coverage/cover_reg_top/99.xbar_unmapped_addr.653001598 |
| Short name | T1994 |
| Test name | |
| Test status | |
| Simulation time | 70935258 ps |
| CPU time | 6.45 seconds |
| Started | Aug 17 06:57:55 PM PDT 24 |
| Finished | Aug 17 06:58:01 PM PDT 24 |
| Peak memory | 574148 kb |
| Host | smart-91c9f2a4-7e0d-4c11-8bf3-8581f1cac5d4 |
| User | root |
| Command | /workspace/cover_reg_top/simv +xbar_mode=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653001598 -assert nopostproc +UVM_TESTNAME=xbar_base_test +UVM_TEST_SEQ=xbar_unmapped_addr_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 99.xbar_unmapped_addr.653001598 |
| Directory | /workspace/99.xbar_unmapped_addr/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_csr_rw.2677200915 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 10277147276 ps |
| CPU time | 1510.33 seconds |
| Started | Aug 17 06:59:19 PM PDT 24 |
| Finished | Aug 17 07:24:29 PM PDT 24 |
| Peak memory | 608580 kb |
| Host | smart-fee62098-966c-478d-8bf6-a47fe414fef8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677200915 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.c hip_jtag_csr_rw.2677200915 |
| Directory | /workspace/0.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/0.chip_jtag_mem_access.1915274973 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 13555891005 ps |
| CPU time | 1780.75 seconds |
| Started | Aug 17 06:59:30 PM PDT 24 |
| Finished | Aug 17 07:29:11 PM PDT 24 |
| Peak memory | 608572 kb |
| Host | smart-8eba9b92-5078-413e-919f-e86a97537f7e |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915274973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_jtag_mem_access.1 915274973 |
| Directory | /workspace/0.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/0.chip_sival_flash_info_access.2083275595 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 3034946194 ps |
| CPU time | 309.99 seconds |
| Started | Aug 17 07:06:21 PM PDT 24 |
| Finished | Aug 17 07:11:32 PM PDT 24 |
| Peak memory | 609528 kb |
| Host | smart-e53e27ec-9ad7-467b-b6d7-9e84f671a4d5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=2083275595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sival_flash_info_access.2083275595 |
| Directory | /workspace/0.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc.3286189653 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 3278010632 ps |
| CPU time | 313.6 seconds |
| Started | Aug 17 07:06:55 PM PDT 24 |
| Finished | Aug 17 07:12:09 PM PDT 24 |
| Peak memory | 609376 kb |
| Host | smart-6b963345-0f39-4bd7-a3dd-5b72c21e7aa6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286189653 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc.3286189653 |
| Directory | /workspace/0.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2793283865 |
| Short name | T1272 |
| Test name | |
| Test status | |
| Simulation time | 2613540797 ps |
| CPU time | 237.34 seconds |
| Started | Aug 17 07:09:09 PM PDT 24 |
| Finished | Aug 17 07:13:07 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-9f80bfe2-f6d1-4118-9e5e-7d16d8922593 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2793 283865 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en.2793283865 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2284525572 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 3385721866 ps |
| CPU time | 289.58 seconds |
| Started | Aug 17 07:07:07 PM PDT 24 |
| Finished | Aug 17 07:11:57 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-7a1386aa-0932-4eb1-b596-164956c1ae59 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284525572 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_enc_jitter_en_reduced_freq.2284525572 |
| Directory | /workspace/0.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_entropy.556331288 |
| Short name | T1137 |
| Test name | |
| Test status | |
| Simulation time | 2235786336 ps |
| CPU time | 265.15 seconds |
| Started | Aug 17 07:14:26 PM PDT 24 |
| Finished | Aug 17 07:18:53 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-f38aee64-8c1b-446a-858e-b97387df622a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556331288 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_entropy.556331288 |
| Directory | /workspace/0.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_idle.3672179028 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 2537452088 ps |
| CPU time | 242.69 seconds |
| Started | Aug 17 07:14:54 PM PDT 24 |
| Finished | Aug 17 07:18:56 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-8dd6b7e7-9cf0-463b-aa44-4542bce43eaa |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672179028 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_idle.3672179028 |
| Directory | /workspace/0.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_masking_off.2464500268 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2525817458 ps |
| CPU time | 311.66 seconds |
| Started | Aug 17 07:14:19 PM PDT 24 |
| Finished | Aug 17 07:19:31 PM PDT 24 |
| Peak memory | 610488 kb |
| Host | smart-cc8d6093-4b1d-4697-876b-f3821b6f366e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464500268 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_masking_off.2464500268 |
| Directory | /workspace/0.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aes_smoketest.2784899999 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 3143185480 ps |
| CPU time | 274.98 seconds |
| Started | Aug 17 07:12:37 PM PDT 24 |
| Finished | Aug 17 07:17:12 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-dcea4d9c-0cc3-4c89-9c10-71130d8d79d8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2784899999 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aes_smoketest.2784899999 |
| Directory | /workspace/0.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_entropy.626345204 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 3843779594 ps |
| CPU time | 352.92 seconds |
| Started | Aug 17 07:08:22 PM PDT 24 |
| Finished | Aug 17 07:14:17 PM PDT 24 |
| Peak memory | 610008 kb |
| Host | smart-936708ab-622f-4e87-9399-fba3526bcf93 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=626345204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_entropy.626345204 |
| Directory | /workspace/0.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1621481896 |
| Short name | T1285 |
| Test name | |
| Test status | |
| Simulation time | 5530917778 ps |
| CPU time | 631.15 seconds |
| Started | Aug 17 07:14:41 PM PDT 24 |
| Finished | Aug 17 07:25:12 PM PDT 24 |
| Peak memory | 619224 kb |
| Host | smart-e056312b-5709-48af-b4a8-969b5d4e949e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1621481896 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_escalation.1621481896 |
| Directory | /workspace/0.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.2462301700 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 7818979518 ps |
| CPU time | 1695.78 seconds |
| Started | Aug 17 07:06:33 PM PDT 24 |
| Finished | Aug 17 07:34:49 PM PDT 24 |
| Peak memory | 610708 kb |
| Host | smart-95ef7f32-2e2e-4a88-8fd6-0ec0c15b0311 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462301700 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_reset_togg le.2462301700 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2898580645 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 10994461934 ps |
| CPU time | 1281.95 seconds |
| Started | Aug 17 07:13:47 PM PDT 24 |
| Finished | Aug 17 07:35:10 PM PDT 24 |
| Peak memory | 611632 kb |
| Host | smart-0352e3f0-7511-479f-b1c8-4a92259e23f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898580645 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_lpg_sleep_mode_pings.2898580645 |
| Directory | /workspace/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_ok.3713317585 |
| Short name | T1124 |
| Test name | |
| Test status | |
| Simulation time | 7517091524 ps |
| CPU time | 1511.19 seconds |
| Started | Aug 17 07:08:29 PM PDT 24 |
| Finished | Aug 17 07:33:40 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-6d9da7e3-14e4-409a-af74-eacae2478d76 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3713317585 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_ok.3713317585 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2017957905 |
| Short name | T1162 |
| Test name | |
| Test status | |
| Simulation time | 4839446392 ps |
| CPU time | 460.05 seconds |
| Started | Aug 17 07:09:06 PM PDT 24 |
| Finished | Aug 17 07:16:47 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-e1631189-fe35-4807-9c18-62390c3a5bf9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2017957905 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_ping_timeout.2017957905 |
| Directory | /workspace/0.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.739434539 |
| Short name | T1328 |
| Test name | |
| Test status | |
| Simulation time | 254484265764 ps |
| CPU time | 12390.7 seconds |
| Started | Aug 17 07:08:40 PM PDT 24 |
| Finished | Aug 17 10:35:12 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-0e53ceb8-e495-4b50-9182-5025fb6aa102 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=739434539 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.739434539 |
| Directory | /workspace/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/0.chip_sw_alert_test.639990247 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 3341338248 ps |
| CPU time | 386.19 seconds |
| Started | Aug 17 07:08:40 PM PDT 24 |
| Finished | Aug 17 07:15:07 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-ae724b6a-2206-4a23-944d-7b5825f94b4e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639990247 -assert nopostproc +UVM_TESTNAME=chip_bas e_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm _name 0.chip_sw_alert_test.639990247 |
| Directory | /workspace/0.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1239143318 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 7039829576 ps |
| CPU time | 456.3 seconds |
| Started | Aug 17 07:08:37 PM PDT 24 |
| Finished | Aug 17 07:16:14 PM PDT 24 |
| Peak memory | 610076 kb |
| Host | smart-86a82c0f-5a7c-4b1f-8fca-06a008646232 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1239143318 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_sleep_wdog_sleep_pause.1239143318 |
| Directory | /workspace/0.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.425645333 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 2586836404 ps |
| CPU time | 281.58 seconds |
| Started | Aug 17 07:13:13 PM PDT 24 |
| Finished | Aug 17 07:17:54 PM PDT 24 |
| Peak memory | 609384 kb |
| Host | smart-98896422-0741-44a9-be2b-ba26d8523e40 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425645333 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_aon_timer_smoketest.425645333 |
| Directory | /workspace/0.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.4028533004 |
| Short name | T1152 |
| Test name | |
| Test status | |
| Simulation time | 8257919960 ps |
| CPU time | 935.45 seconds |
| Started | Aug 17 07:14:52 PM PDT 24 |
| Finished | Aug 17 07:30:28 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-5fc7a1f8-e577-4c92-b805-30fa581e5536 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4028533004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_bite_reset.4028533004 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2737953947 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 4810802000 ps |
| CPU time | 532.76 seconds |
| Started | Aug 17 07:05:37 PM PDT 24 |
| Finished | Aug 17 07:14:30 PM PDT 24 |
| Peak memory | 610148 kb |
| Host | smart-060405f4-1d63-4225-9350-49797592bd19 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2737953947 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_aon_timer_wdog_lc_escalate.2737953947 |
| Directory | /workspace/0.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_ast_clk_outputs.2014857627 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 8433724880 ps |
| CPU time | 907.94 seconds |
| Started | Aug 17 07:07:02 PM PDT 24 |
| Finished | Aug 17 07:22:10 PM PDT 24 |
| Peak memory | 617944 kb |
| Host | smart-39aba3bd-26e5-4c48-be07-2b2bc9c2328c |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014857627 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_ast_clk_outputs.2014857627 |
| Directory | /workspace/0.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3538941556 |
| Short name | T1293 |
| Test name | |
| Test status | |
| Simulation time | 3809619412 ps |
| CPU time | 620.06 seconds |
| Started | Aug 17 07:08:37 PM PDT 24 |
| Finished | Aug 17 07:18:57 PM PDT 24 |
| Peak memory | 613860 kb |
| Host | smart-55cec172-1a53-43d9-a237-00405c040c98 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538941556 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3538941556 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1495535772 |
| Short name | T1271 |
| Test name | |
| Test status | |
| Simulation time | 4704530808 ps |
| CPU time | 587.75 seconds |
| Started | Aug 17 07:09:15 PM PDT 24 |
| Finished | Aug 17 07:19:02 PM PDT 24 |
| Peak memory | 614876 kb |
| Host | smart-75d300a4-1c72-41da-a382-a76b5eaa7b29 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495535772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.1495535772 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.4012057819 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 4813081512 ps |
| CPU time | 709.17 seconds |
| Started | Aug 17 07:10:20 PM PDT 24 |
| Finished | Aug 17 07:22:10 PM PDT 24 |
| Peak memory | 614660 kb |
| Host | smart-9b1e06e8-2073-4c9d-a096-1caa547c0e58 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012057819 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.4012057819 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2690223085 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 4472680520 ps |
| CPU time | 620.65 seconds |
| Started | Aug 17 07:08:33 PM PDT 24 |
| Finished | Aug 17 07:18:54 PM PDT 24 |
| Peak memory | 613992 kb |
| Host | smart-70467cc2-45f0-4956-95a4-8061be5a66e5 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2690223085 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2690223085 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.472459678 |
| Short name | T1274 |
| Test name | |
| Test status | |
| Simulation time | 4950989708 ps |
| CPU time | 707.68 seconds |
| Started | Aug 17 07:08:18 PM PDT 24 |
| Finished | Aug 17 07:20:06 PM PDT 24 |
| Peak memory | 613928 kb |
| Host | smart-7e0e223c-102c-465d-abb0-d7ddcb18f864 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472459678 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.472459678 |
| Directory | /workspace/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1270110884 |
| Short name | T1270 |
| Test name | |
| Test status | |
| Simulation time | 2064594894 ps |
| CPU time | 193.29 seconds |
| Started | Aug 17 07:06:54 PM PDT 24 |
| Finished | Aug 17 07:10:08 PM PDT 24 |
| Peak memory | 609900 kb |
| Host | smart-e5412bb1-fd1d-46e2-83bd-a9fb147c8f9a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1270110884 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_clkmgr_jitter.1270110884 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2779481648 |
| Short name | T1177 |
| Test name | |
| Test status | |
| Simulation time | 3828005290 ps |
| CPU time | 495.77 seconds |
| Started | Aug 17 07:08:23 PM PDT 24 |
| Finished | Aug 17 07:16:39 PM PDT 24 |
| Peak memory | 610168 kb |
| Host | smart-2b429488-ca32-449b-a586-dd0bad4a9eff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779481648 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_frequency.2779481648 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3013269725 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 2278305227 ps |
| CPU time | 177.07 seconds |
| Started | Aug 17 07:08:15 PM PDT 24 |
| Finished | Aug 17 07:11:13 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-654c2498-d792-45e7-b59f-ddacc43c042c |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013269725 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_jitter_reduced_freq.3013269725 |
| Directory | /workspace/0.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.290725926 |
| Short name | T1316 |
| Test name | |
| Test status | |
| Simulation time | 4070283810 ps |
| CPU time | 534.13 seconds |
| Started | Aug 17 07:10:23 PM PDT 24 |
| Finished | Aug 17 07:19:17 PM PDT 24 |
| Peak memory | 609860 kb |
| Host | smart-5b527fb1-98ea-41f5-b46b-c24103ba0546 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290725926 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_clkmgr_off_aes_trans.290725926 |
| Directory | /workspace/0.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2618947022 |
| Short name | T1211 |
| Test name | |
| Test status | |
| Simulation time | 4791805974 ps |
| CPU time | 447.67 seconds |
| Started | Aug 17 07:09:18 PM PDT 24 |
| Finished | Aug 17 07:16:46 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-749c644b-36ce-458b-a6b1-8dc96ed49e00 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618947022 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_hmac_trans.2618947022 |
| Directory | /workspace/0.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2300754475 |
| Short name | T1233 |
| Test name | |
| Test status | |
| Simulation time | 5270122810 ps |
| CPU time | 512.81 seconds |
| Started | Aug 17 07:09:57 PM PDT 24 |
| Finished | Aug 17 07:18:30 PM PDT 24 |
| Peak memory | 611096 kb |
| Host | smart-c34d3bfb-b018-4a29-a50e-91775df8f7c6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300754475 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_kmac_trans.2300754475 |
| Directory | /workspace/0.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3695184372 |
| Short name | T1172 |
| Test name | |
| Test status | |
| Simulation time | 4913046840 ps |
| CPU time | 378.22 seconds |
| Started | Aug 17 07:08:11 PM PDT 24 |
| Finished | Aug 17 07:14:30 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-d2096539-955b-404f-b61f-6066700bbfd1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695184372 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_clkmgr_off_otbn_trans.3695184372 |
| Directory | /workspace/0.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3050272795 |
| Short name | T1292 |
| Test name | |
| Test status | |
| Simulation time | 9399526088 ps |
| CPU time | 1211.45 seconds |
| Started | Aug 17 07:08:31 PM PDT 24 |
| Finished | Aug 17 07:28:43 PM PDT 24 |
| Peak memory | 611176 kb |
| Host | smart-40b9d0cb-2316-4b5c-9a5c-5ff6e490b7f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050272795 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_off_peri.3050272795 |
| Directory | /workspace/0.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.2694074176 |
| Short name | T1139 |
| Test name | |
| Test status | |
| Simulation time | 3474505377 ps |
| CPU time | 409.87 seconds |
| Started | Aug 17 07:07:45 PM PDT 24 |
| Finished | Aug 17 07:14:35 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-548e5a03-5182-43dd-90ff-c74bca5f4543 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694074176 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_reset_frequency.2694074176 |
| Directory | /workspace/0.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.1519570726 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 4580019440 ps |
| CPU time | 632.7 seconds |
| Started | Aug 17 07:09:10 PM PDT 24 |
| Finished | Aug 17 07:19:44 PM PDT 24 |
| Peak memory | 610900 kb |
| Host | smart-3119ec0b-d6ea-4442-8fc3-56f08ca2bcd2 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519570726 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_clkmgr_sleep_frequency.1519570726 |
| Directory | /workspace/0.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.4041798382 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 3099378224 ps |
| CPU time | 397.92 seconds |
| Started | Aug 17 07:11:00 PM PDT 24 |
| Finished | Aug 17 07:17:38 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-fcd30b1d-e6cb-4df1-be54-7addef0acf54 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041798382 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_clkmgr_smoketest.4041798382 |
| Directory | /workspace/0.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_coremark.2026568844 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 71383400136 ps |
| CPU time | 13281.4 seconds |
| Started | Aug 17 07:09:23 PM PDT 24 |
| Finished | Aug 17 10:50:46 PM PDT 24 |
| Peak memory | 611112 kb |
| Host | smart-ad018b8b-49d4-46d5-926f-8e91d95bfc83 |
| User | root |
| Command | /workspace/default/simv +en_uart_logger=1 +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=coremark_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=2026568844 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_coremark.2026568844 |
| Directory | /workspace/0.chip_sw_coremark/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1944087195 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 17558775296 ps |
| CPU time | 4166.53 seconds |
| Started | Aug 17 07:08:19 PM PDT 24 |
| Finished | Aug 17 08:17:46 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-aeb8d1db-d3be-4a3a-948a-1034869c5823 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944087195 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency.1944087195 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1509677536 |
| Short name | T1207 |
| Test name | |
| Test status | |
| Simulation time | 21598980329 ps |
| CPU time | 3861.48 seconds |
| Started | Aug 17 07:10:23 PM PDT 24 |
| Finished | Aug 17 08:14:45 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-885522aa-53e4-4ecb-81b6-c0024629492b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1509677536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_edn_concurrency_reduced_freq.1509677536 |
| Directory | /workspace/0.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_kat_test.2466850730 |
| Short name | T1305 |
| Test name | |
| Test status | |
| Simulation time | 3047188188 ps |
| CPU time | 192.41 seconds |
| Started | Aug 17 07:08:37 PM PDT 24 |
| Finished | Aug 17 07:11:49 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-a562baf0-0537-415f-9248-5708f7f58ea3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466850730 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csrng_kat_test.2466850730 |
| Directory | /workspace/0.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2637883596 |
| Short name | T1331 |
| Test name | |
| Test status | |
| Simulation time | 6994317320 ps |
| CPU time | 577.65 seconds |
| Started | Aug 17 07:06:11 PM PDT 24 |
| Finished | Aug 17 07:15:49 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-f274f183-a8ee-404f-b6cb-369ea0a3b856 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2637883596 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_csr ng_lc_hw_debug_en_test.2637883596 |
| Directory | /workspace/0.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_csrng_smoketest.501444042 |
| Short name | T1340 |
| Test name | |
| Test status | |
| Simulation time | 2790209178 ps |
| CPU time | 309.91 seconds |
| Started | Aug 17 07:12:20 PM PDT 24 |
| Finished | Aug 17 07:17:30 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-96810a73-ffad-4093-a19d-6b953c96f24a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=501444042 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_csrng_smoketest.501444042 |
| Directory | /workspace/0.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_data_integrity_escalation.1909749193 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 6255722732 ps |
| CPU time | 705.46 seconds |
| Started | Aug 17 07:05:46 PM PDT 24 |
| Finished | Aug 17 07:17:31 PM PDT 24 |
| Peak memory | 611692 kb |
| Host | smart-f3f378ce-3cd7-4a8b-b7e8-aeccb5c4549d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=1909749193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_data_integrity_escalation.1909749193 |
| Directory | /workspace/0.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_auto_mode.1212321111 |
| Short name | T1174 |
| Test name | |
| Test status | |
| Simulation time | 4926437284 ps |
| CPU time | 1063.52 seconds |
| Started | Aug 17 07:07:13 PM PDT 24 |
| Finished | Aug 17 07:24:57 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-680957d3-19ff-452a-8c8b-81f4453e06ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212321111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_ auto_mode.1212321111 |
| Directory | /workspace/0.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.1190058806 |
| Short name | T1134 |
| Test name | |
| Test status | |
| Simulation time | 5796556118 ps |
| CPU time | 1108.99 seconds |
| Started | Aug 17 07:07:14 PM PDT 24 |
| Finished | Aug 17 07:25:44 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-2a264659-69b2-44be-bd5e-a8f0fcacbe9c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=1190058806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs.1190058806 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.89858473 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 6843521672 ps |
| CPU time | 981.6 seconds |
| Started | Aug 17 07:05:37 PM PDT 24 |
| Finished | Aug 17 07:21:59 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-6f7fb48e-3503-4337-a4d9-b67cc8326465 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89858473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_entropy_reqs_jitter.89858473 |
| Directory | /workspace/0.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_kat.1911956246 |
| Short name | T1160 |
| Test name | |
| Test status | |
| Simulation time | 3636201584 ps |
| CPU time | 574.32 seconds |
| Started | Aug 17 07:05:42 PM PDT 24 |
| Finished | Aug 17 07:15:17 PM PDT 24 |
| Peak memory | 617148 kb |
| Host | smart-44e59662-805d-41bf-adc8-70f6422fa4e1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911956246 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_edn_kat.1911956246 |
| Directory | /workspace/0.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/0.chip_sw_edn_sw_mode.1151211108 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 6088884448 ps |
| CPU time | 1479.35 seconds |
| Started | Aug 17 07:07:30 PM PDT 24 |
| Finished | Aug 17 07:32:10 PM PDT 24 |
| Peak memory | 609684 kb |
| Host | smart-6e4398ed-c124-4a6f-961b-32f3c1410c50 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1151211108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 0.chip_sw_edn_sw_mode.1151211108 |
| Directory | /workspace/0.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1748215617 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 2706721868 ps |
| CPU time | 216.64 seconds |
| Started | Aug 17 07:09:47 PM PDT 24 |
| Finished | Aug 17 07:13:24 PM PDT 24 |
| Peak memory | 609292 kb |
| Host | smart-022fe570-826b-452c-bebb-b4d22ccf063e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17 48215617 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_ast_rng_req.1748215617 |
| Directory | /workspace/0.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.802132329 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 3379483840 ps |
| CPU time | 290.4 seconds |
| Started | Aug 17 07:06:28 PM PDT 24 |
| Finished | Aug 17 07:11:19 PM PDT 24 |
| Peak memory | 609944 kb |
| Host | smart-0fdbfe27-9dec-45d0-98ba-216ae3f9e90f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802132329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_kat_test.802132329 |
| Directory | /workspace/0.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3986913368 |
| Short name | T1115 |
| Test name | |
| Test status | |
| Simulation time | 3110659630 ps |
| CPU time | 482.53 seconds |
| Started | Aug 17 07:11:12 PM PDT 24 |
| Finished | Aug 17 07:19:15 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-d8712ba3-2329-44ba-954b-0b28244f6cc7 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3986913368 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_entropy_src_smoketest.3986913368 |
| Directory | /workspace/0.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_concurrency.2259347229 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 2176423560 ps |
| CPU time | 207.95 seconds |
| Started | Aug 17 07:05:14 PM PDT 24 |
| Finished | Aug 17 07:08:42 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-bda480e7-a999-41cb-8a8c-ec6d38835c70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259347229 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_example_concurrency.2259347229 |
| Directory | /workspace/0.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_flash.2319169011 |
| Short name | T1190 |
| Test name | |
| Test status | |
| Simulation time | 3495935110 ps |
| CPU time | 273.11 seconds |
| Started | Aug 17 07:05:47 PM PDT 24 |
| Finished | Aug 17 07:10:20 PM PDT 24 |
| Peak memory | 610384 kb |
| Host | smart-4f3b2ded-dce1-4b51-9ee5-8a4291d4f469 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319169011 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_flash.2319169011 |
| Directory | /workspace/0.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_manufacturer.2400540495 |
| Short name | T1147 |
| Test name | |
| Test status | |
| Simulation time | 2360542000 ps |
| CPU time | 204.6 seconds |
| Started | Aug 17 07:05:43 PM PDT 24 |
| Finished | Aug 17 07:09:09 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-07a4a2ad-3385-4a7d-8b90-61714b8c29ef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400540495 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_manufacturer.2400540495 |
| Directory | /workspace/0.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/0.chip_sw_example_rom.2569377462 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 3048218128 ps |
| CPU time | 150.42 seconds |
| Started | Aug 17 07:05:02 PM PDT 24 |
| Finished | Aug 17 07:07:34 PM PDT 24 |
| Peak memory | 609596 kb |
| Host | smart-769f6eaf-034e-4f11-a442-f14f2455dc6d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569377462 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_example_rom.2569377462 |
| Directory | /workspace/0.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3949197170 |
| Short name | T1317 |
| Test name | |
| Test status | |
| Simulation time | 59719336182 ps |
| CPU time | 10480.9 seconds |
| Started | Aug 17 07:06:00 PM PDT 24 |
| Finished | Aug 17 10:00:42 PM PDT 24 |
| Peak memory | 625528 kb |
| Host | smart-1626bc8f-f097-48b8-807b-740f766967db |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3949197170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_exit_test_unlocked_bootstrap.3949197170 |
| Directory | /workspace/0.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_crash_alert.886104772 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 5867304986 ps |
| CPU time | 619.83 seconds |
| Started | Aug 17 07:11:00 PM PDT 24 |
| Finished | Aug 17 07:21:20 PM PDT 24 |
| Peak memory | 611772 kb |
| Host | smart-9980b1ba-11d2-4df3-905f-da235eb35f95 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=886104772 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_crash_alert.886104772 |
| Directory | /workspace/0.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3392582687 |
| Short name | T1290 |
| Test name | |
| Test status | |
| Simulation time | 5674560096 ps |
| CPU time | 1091.49 seconds |
| Started | Aug 17 07:08:40 PM PDT 24 |
| Finished | Aug 17 07:26:53 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-47d11866-9a9e-494f-8f94-4a4f1d63c74b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3392582687 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 0.chip_sw_flash_ctrl_access.3392582687 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1326476623 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 6120503429 ps |
| CPU time | 1030.1 seconds |
| Started | Aug 17 07:07:28 PM PDT 24 |
| Finished | Aug 17 07:24:39 PM PDT 24 |
| Peak memory | 609976 kb |
| Host | smart-9aa4daac-cd7b-43d7-b06a-242c07e1e4b7 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326476623 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en.1326476623 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.85118183 |
| Short name | T1284 |
| Test name | |
| Test status | |
| Simulation time | 7068439118 ps |
| CPU time | 1201.89 seconds |
| Started | Aug 17 07:09:22 PM PDT 24 |
| Finished | Aug 17 07:29:25 PM PDT 24 |
| Peak memory | 609776 kb |
| Host | smart-6ee2a2e5-1d44-4ecb-9685-b276270116da |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85118183 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.85118183 |
| Directory | /workspace/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.341189522 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 5565399610 ps |
| CPU time | 1051.04 seconds |
| Started | Aug 17 07:06:21 PM PDT 24 |
| Finished | Aug 17 07:23:52 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-4e1291c5-5c82-4d65-9dee-7e07b891c9cb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341189522 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_flash_ctrl_clock_freqs.341189522 |
| Directory | /workspace/0.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.695510469 |
| Short name | T1206 |
| Test name | |
| Test status | |
| Simulation time | 3111507256 ps |
| CPU time | 337.18 seconds |
| Started | Aug 17 07:06:53 PM PDT 24 |
| Finished | Aug 17 07:12:31 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-004793d5-9b04-4e32-aef5-d4d7158796b8 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=695510469 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_idle_low_power.695510469 |
| Directory | /workspace/0.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.420063057 |
| Short name | T1129 |
| Test name | |
| Test status | |
| Simulation time | 5226887967 ps |
| CPU time | 346.57 seconds |
| Started | Aug 17 07:04:54 PM PDT 24 |
| Finished | Aug 17 07:10:40 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-f5bd5261-fc91-44a6-a2b9-1a4b71564ca6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42 0063057 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_lc_rw_en.420063057 |
| Directory | /workspace/0.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.81487950 |
| Short name | T1191 |
| Test name | |
| Test status | |
| Simulation time | 5762679930 ps |
| CPU time | 1121.58 seconds |
| Started | Aug 17 07:09:52 PM PDT 24 |
| Finished | Aug 17 07:28:34 PM PDT 24 |
| Peak memory | 609752 kb |
| Host | smart-2bb83d67-637e-4e68-a20d-a6195bfab441 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81487950 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 0.chip_sw_flash_ctrl_mem_protection.81487950 |
| Directory | /workspace/0.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1471868408 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 4892409784 ps |
| CPU time | 858.4 seconds |
| Started | Aug 17 07:05:49 PM PDT 24 |
| Finished | Aug 17 07:20:08 PM PDT 24 |
| Peak memory | 610776 kb |
| Host | smart-979e82ed-5d3d-48b8-b6e1-5543cc425a7e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1471868408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en.1471868408 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1148723972 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 4519276119 ps |
| CPU time | 650.15 seconds |
| Started | Aug 17 07:08:21 PM PDT 24 |
| Finished | Aug 17 07:19:12 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-8e0a1b14-38a0-485b-8c66-910fe5c4a111 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1148723972 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1148723972 |
| Directory | /workspace/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_ctrl_write_clear.141659130 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 2831239688 ps |
| CPU time | 374.15 seconds |
| Started | Aug 17 07:09:47 PM PDT 24 |
| Finished | Aug 17 07:16:01 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-21d2ea1e-f4df-4efa-8e6e-19751118cd6d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416591 30 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_ctrl_write_clear.141659130 |
| Directory | /workspace/0.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init.3757853948 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 22077307058 ps |
| CPU time | 1967.56 seconds |
| Started | Aug 17 07:06:16 PM PDT 24 |
| Finished | Aug 17 07:39:04 PM PDT 24 |
| Peak memory | 614116 kb |
| Host | smart-c703d9ee-1f9b-4439-b814-7ea64b33a5f2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757853948 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init.3757853948 |
| Directory | /workspace/0.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.852785824 |
| Short name | T1145 |
| Test name | |
| Test status | |
| Simulation time | 19741711301 ps |
| CPU time | 2293.64 seconds |
| Started | Aug 17 07:11:17 PM PDT 24 |
| Finished | Aug 17 07:49:32 PM PDT 24 |
| Peak memory | 613132 kb |
| Host | smart-1bcfa956-2a25-429d-8c8c-ea5bd83a2ae1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=852785824 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_init_reduced_freq.852785824 |
| Directory | /workspace/0.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3683996153 |
| Short name | T1303 |
| Test name | |
| Test status | |
| Simulation time | 2979572040 ps |
| CPU time | 218.22 seconds |
| Started | Aug 17 07:13:25 PM PDT 24 |
| Finished | Aug 17 07:17:04 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-3bf724a6-1d83-4dc3-b9f6-bbb1b75272fe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3683996153 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_flash_scrambling_smoketest.3683996153 |
| Directory | /workspace/0.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_gpio_smoketest.3466289460 |
| Short name | T1148 |
| Test name | |
| Test status | |
| Simulation time | 2914146216 ps |
| CPU time | 307.51 seconds |
| Started | Aug 17 07:09:19 PM PDT 24 |
| Finished | Aug 17 07:14:27 PM PDT 24 |
| Peak memory | 610640 kb |
| Host | smart-baae33ce-9a48-4b22-a048-f6d1b90bb8a6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3466289460 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_gpio_smoketest.3466289460 |
| Directory | /workspace/0.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc.2212089552 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 3104741284 ps |
| CPU time | 287.68 seconds |
| Started | Aug 17 07:06:34 PM PDT 24 |
| Finished | Aug 17 07:11:22 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-c601f39e-02c3-48dd-99b2-edd4ce53f859 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212089552 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_enc.2212089552 |
| Directory | /workspace/0.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_idle.214899429 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 3268007390 ps |
| CPU time | 241.25 seconds |
| Started | Aug 17 07:08:41 PM PDT 24 |
| Finished | Aug 17 07:12:43 PM PDT 24 |
| Peak memory | 609960 kb |
| Host | smart-07fdc15a-0d28-4f29-94bd-5d04010ee4f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214899429 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_hmac_enc_idle.214899429 |
| Directory | /workspace/0.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.2723273800 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 2296727947 ps |
| CPU time | 214.9 seconds |
| Started | Aug 17 07:07:56 PM PDT 24 |
| Finished | Aug 17 07:11:32 PM PDT 24 |
| Peak memory | 609468 kb |
| Host | smart-65979531-b858-40a2-87ca-2dd3958bfa0c |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2723273800 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_hmac_enc_jitter_en.2723273800 |
| Directory | /workspace/0.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_multistream.2641260724 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 7314371570 ps |
| CPU time | 1672.81 seconds |
| Started | Aug 17 07:14:19 PM PDT 24 |
| Finished | Aug 17 07:42:13 PM PDT 24 |
| Peak memory | 609760 kb |
| Host | smart-f2c9b396-671b-4aac-a956-1c2b47d6ecc3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2641260724 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 0.chip_sw_hmac_multistream.2641260724 |
| Directory | /workspace/0.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_oneshot.3077434283 |
| Short name | T1169 |
| Test name | |
| Test status | |
| Simulation time | 3159681240 ps |
| CPU time | 325.33 seconds |
| Started | Aug 17 07:10:43 PM PDT 24 |
| Finished | Aug 17 07:16:08 PM PDT 24 |
| Peak memory | 610580 kb |
| Host | smart-e30886b7-22fa-4b17-8e5a-21d42ff34cf4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077434283 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_hmac_oneshot.3077434283 |
| Directory | /workspace/0.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/0.chip_sw_hmac_smoketest.3074150203 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 3358467960 ps |
| CPU time | 276.84 seconds |
| Started | Aug 17 07:09:31 PM PDT 24 |
| Finished | Aug 17 07:14:07 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-52678a65-11bd-49cd-b84b-fd28d6ada1d5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3074150203 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_hmac_smoketest.3074150203 |
| Directory | /workspace/0.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.1531044265 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 4580253072 ps |
| CPU time | 615.07 seconds |
| Started | Aug 17 07:09:23 PM PDT 24 |
| Finished | Aug 17 07:19:40 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-e0da2a84-5ddc-45e2-aedb-c5d1b980063a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531044265 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_i2c_device_tx_rx.1531044265 |
| Directory | /workspace/0.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4118173703 |
| Short name | T1158 |
| Test name | |
| Test status | |
| Simulation time | 4750678064 ps |
| CPU time | 806.16 seconds |
| Started | Aug 17 07:05:50 PM PDT 24 |
| Finished | Aug 17 07:19:17 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-bda8aa90-2fce-4db8-9373-b72df8daba49 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118173703 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_i2c_host_tx_rx_idx1.4118173703 |
| Directory | /workspace/0.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_inject_scramble_seed.794399671 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 65810046667 ps |
| CPU time | 11467.1 seconds |
| Started | Aug 17 07:07:22 PM PDT 24 |
| Finished | Aug 17 10:18:30 PM PDT 24 |
| Peak memory | 625516 kb |
| Host | smart-17aa3d5b-1d3d-460e-8682-e692d168a99b |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=794399671 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_inject_scramble_seed.794399671 |
| Directory | /workspace/0.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.582457058 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 11382303612 ps |
| CPU time | 2810.06 seconds |
| Started | Aug 17 07:07:04 PM PDT 24 |
| Finished | Aug 17 07:53:55 PM PDT 24 |
| Peak memory | 617352 kb |
| Host | smart-78d52120-904e-4661-a51c-fdafb54f249c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5824 57058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation.582457058 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.714018103 |
| Short name | T1163 |
| Test name | |
| Test status | |
| Simulation time | 8146502217 ps |
| CPU time | 1572.94 seconds |
| Started | Aug 17 07:07:10 PM PDT 24 |
| Finished | Aug 17 07:33:23 PM PDT 24 |
| Peak memory | 616984 kb |
| Host | smart-01a04faa-affd-49ba-a558-c6eca5c8a963 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=714018103 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en.714018103 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1406961194 |
| Short name | T1321 |
| Test name | |
| Test status | |
| Simulation time | 13051456385 ps |
| CPU time | 2210.08 seconds |
| Started | Aug 17 07:09:04 PM PDT 24 |
| Finished | Aug 17 07:45:55 PM PDT 24 |
| Peak memory | 618600 kb |
| Host | smart-dff4a5a9-edd0-4202-90da-e7df718a9862 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1406961194 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.1406961194 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.3714505473 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 7763061304 ps |
| CPU time | 1563.91 seconds |
| Started | Aug 17 07:09:28 PM PDT 24 |
| Finished | Aug 17 07:35:33 PM PDT 24 |
| Peak memory | 617312 kb |
| Host | smart-9aa26054-4948-4b2d-b35f-adc5ec952ab8 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3714505473 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_key_derivation_prod.3714505473 |
| Directory | /workspace/0.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1677448864 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 10861264908 ps |
| CPU time | 2498.81 seconds |
| Started | Aug 17 07:09:28 PM PDT 24 |
| Finished | Aug 17 07:51:07 PM PDT 24 |
| Peak memory | 611624 kb |
| Host | smart-40f56c98-7e34-4127-ba45-908997d0f32a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167744 8864 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_aes.1677448864 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.1925834227 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 9438370104 ps |
| CPU time | 1817.59 seconds |
| Started | Aug 17 07:09:22 PM PDT 24 |
| Finished | Aug 17 07:39:41 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-d07473d4-bc06-4be6-ab96-442a69707fde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19258 34227 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_keymgr_sideload_kmac.1925834227 |
| Directory | /workspace/0.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_app_rom.1457310566 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2621697620 ps |
| CPU time | 197.61 seconds |
| Started | Aug 17 07:15:08 PM PDT 24 |
| Finished | Aug 17 07:18:26 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-7abf4615-ecf9-4680-a879-c0b5eeb7ecf6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457310566 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_kmac_app_rom.1457310566 |
| Directory | /workspace/0.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_entropy.176026935 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2392226266 ps |
| CPU time | 227.21 seconds |
| Started | Aug 17 07:08:20 PM PDT 24 |
| Finished | Aug 17 07:12:07 PM PDT 24 |
| Peak memory | 609916 kb |
| Host | smart-3857b63f-e2ed-409f-8537-47c80e0a7de1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176026935 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_kmac_entropy.176026935 |
| Directory | /workspace/0.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_idle.3620577174 |
| Short name | T1343 |
| Test name | |
| Test status | |
| Simulation time | 2654157092 ps |
| CPU time | 319.48 seconds |
| Started | Aug 17 07:07:34 PM PDT 24 |
| Finished | Aug 17 07:12:53 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-86c84537-972d-4218-8656-740dc9659882 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620577174 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_idle.3620577174 |
| Directory | /workspace/0.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3949791457 |
| Short name | T1254 |
| Test name | |
| Test status | |
| Simulation time | 3088100780 ps |
| CPU time | 269.23 seconds |
| Started | Aug 17 07:14:48 PM PDT 24 |
| Finished | Aug 17 07:19:18 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-d7a75c3a-e576-4dc1-ba99-b1d75023dd8a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949791457 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 0.chip_sw_kmac_mode_cshake.3949791457 |
| Directory | /workspace/0.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.1719476203 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 3817741872 ps |
| CPU time | 423.22 seconds |
| Started | Aug 17 07:14:23 PM PDT 24 |
| Finished | Aug 17 07:21:27 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-c653c57e-4d83-4534-9599-195a931f598f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719476203 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_kmac_mode_kmac.1719476203 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.2323886910 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 3190768459 ps |
| CPU time | 282.8 seconds |
| Started | Aug 17 07:06:45 PM PDT 24 |
| Finished | Aug 17 07:11:28 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-b9f844b3-70e5-4d5b-a0d0-9d3a727da751 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323886910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en.2323886910 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.508412077 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 2795062879 ps |
| CPU time | 280.06 seconds |
| Started | Aug 17 07:08:22 PM PDT 24 |
| Finished | Aug 17 07:13:03 PM PDT 24 |
| Peak memory | 610468 kb |
| Host | smart-8fe98e74-6848-4d6a-911a-30eaa89867ea |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50841207 7 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.508412077 |
| Directory | /workspace/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_kmac_smoketest.2898320249 |
| Short name | T1219 |
| Test name | |
| Test status | |
| Simulation time | 3109979976 ps |
| CPU time | 300.49 seconds |
| Started | Aug 17 07:09:05 PM PDT 24 |
| Finished | Aug 17 07:14:05 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-31722d39-9f33-4c67-a3a9-0de672229d29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898320249 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_kmac_smoketest.2898320249 |
| Directory | /workspace/0.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1887458695 |
| Short name | T1311 |
| Test name | |
| Test status | |
| Simulation time | 2874462636 ps |
| CPU time | 288.02 seconds |
| Started | Aug 17 07:05:16 PM PDT 24 |
| Finished | Aug 17 07:10:04 PM PDT 24 |
| Peak memory | 609300 kb |
| Host | smart-e0e3dfcd-0101-4b6f-a8c8-86caf876960f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887458695 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 0.chip_sw_lc_ctrl_otp_hw_cfg0.1887458695 |
| Directory | /workspace/0.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.1493318078 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 3148724468 ps |
| CPU time | 154.98 seconds |
| Started | Aug 17 07:09:15 PM PDT 24 |
| Finished | Aug 17 07:11:51 PM PDT 24 |
| Peak memory | 620740 kb |
| Host | smart-82936304-6788-433f-98aa-8b9b3d889606 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14933180 78 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rand_to_scrap.1493318078 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.312111810 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 3949633842 ps |
| CPU time | 144.72 seconds |
| Started | Aug 17 07:09:28 PM PDT 24 |
| Finished | Aug 17 07:11:54 PM PDT 24 |
| Peak memory | 620892 kb |
| Host | smart-c5c5d7ce-ba3c-481c-8cc6-f1ee88d7cde0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRaw +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=312111810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_raw_to_scrap.312111810 |
| Directory | /workspace/0.chip_sw_lc_ctrl_raw_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.609803203 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 3069624158 ps |
| CPU time | 334.04 seconds |
| Started | Aug 17 07:06:00 PM PDT 24 |
| Finished | Aug 17 07:11:35 PM PDT 24 |
| Peak memory | 622280 kb |
| Host | smart-093cc923-43ec-47e8-bef8-ffe63c2f41c5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules ,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=609803203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_rma_to_scrap.609803203 |
| Directory | /workspace/0.chip_sw_lc_ctrl_rma_to_scrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4245382307 |
| Short name | T1178 |
| Test name | |
| Test status | |
| Simulation time | 9968960644 ps |
| CPU time | 672.34 seconds |
| Started | Aug 17 07:05:29 PM PDT 24 |
| Finished | Aug 17 07:16:42 PM PDT 24 |
| Peak memory | 625500 kb |
| Host | smart-3b4a93db-805b-4412-9044-5954a6bdcc15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4245382307 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_transition.4245382307 |
| Directory | /workspace/0.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2684823508 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 2019698932 ps |
| CPU time | 110.98 seconds |
| Started | Aug 17 07:07:06 PM PDT 24 |
| Finished | Aug 17 07:08:57 PM PDT 24 |
| Peak memory | 617732 kb |
| Host | smart-7351a70c-476f-46a2-bbd8-ad40993a77d7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=2684823508 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock.2684823508 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2862603957 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 2615472269 ps |
| CPU time | 121.14 seconds |
| Started | Aug 17 07:08:12 PM PDT 24 |
| Finished | Aug 17 07:10:13 PM PDT 24 |
| Peak memory | 617324 kb |
| Host | smart-6b00f2d2-fb81-4daa-bdbd-0c4a92a1ebec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2862603957 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2862603957 |
| Directory | /workspace/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.38017259 |
| Short name | T1210 |
| Test name | |
| Test status | |
| Simulation time | 47555631678 ps |
| CPU time | 4670.33 seconds |
| Started | Aug 17 07:10:21 PM PDT 24 |
| Finished | Aug 17 08:28:13 PM PDT 24 |
| Peak memory | 624220 kb |
| Host | smart-14025cb2-a78b-4efe-9915-845cf2992609 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38017259 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_s w_lc_walkthrough_dev.38017259 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.130459292 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 47566300960 ps |
| CPU time | 6057.72 seconds |
| Started | Aug 17 07:07:53 PM PDT 24 |
| Finished | Aug 17 08:48:54 PM PDT 24 |
| Peak memory | 625560 kb |
| Host | smart-2290a80a-9284-433f-855b-575678ab6c00 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130459292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip _sw_lc_walkthrough_prod.130459292 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.874787784 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 8435812580 ps |
| CPU time | 930.52 seconds |
| Started | Aug 17 07:08:21 PM PDT 24 |
| Finished | Aug 17 07:23:53 PM PDT 24 |
| Peak memory | 625128 kb |
| Host | smart-9d3e35a3-9c2f-4e05-9f78-05e39dffa750 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=874787784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_prodend.874787784 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3292330513 |
| Short name | T1173 |
| Test name | |
| Test status | |
| Simulation time | 25672014768 ps |
| CPU time | 2468.39 seconds |
| Started | Aug 17 07:08:30 PM PDT 24 |
| Finished | Aug 17 07:49:39 PM PDT 24 |
| Peak memory | 625400 kb |
| Host | smart-95226466-cfa5-44ca-96d5-0968c196d695 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3292330513 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_lc_walkthrough_testun locks.3292330513 |
| Directory | /workspace/0.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1496594698 |
| Short name | T1318 |
| Test name | |
| Test status | |
| Simulation time | 16846369460 ps |
| CPU time | 3751.05 seconds |
| Started | Aug 17 07:08:16 PM PDT 24 |
| Finished | Aug 17 08:10:48 PM PDT 24 |
| Peak memory | 610676 kb |
| Host | smart-82590f92-16e4-4b49-b8a0-d11dc4eb6189 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=1496594698 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq.1496594698 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3277416520 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 19115395252 ps |
| CPU time | 3424.68 seconds |
| Started | Aug 17 07:09:49 PM PDT 24 |
| Finished | Aug 17 08:06:54 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-eb06302e-0673-4812-b039-6a021ff3df68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=3277416520 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3277416520 |
| Directory | /workspace/0.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2218476415 |
| Short name | T1238 |
| Test name | |
| Test status | |
| Simulation time | 3613984730 ps |
| CPU time | 455.2 seconds |
| Started | Aug 17 07:13:48 PM PDT 24 |
| Finished | Aug 17 07:21:24 PM PDT 24 |
| Peak memory | 610096 kb |
| Host | smart-cebd13b9-31c4-40df-b90e-986ba9db3518 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218476415 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_mem_scramble.2218476415 |
| Directory | /workspace/0.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_randomness.2547911932 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 5217838604 ps |
| CPU time | 1163.39 seconds |
| Started | Aug 17 07:08:32 PM PDT 24 |
| Finished | Aug 17 07:27:56 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-482f57b8-50e9-4e37-bd2d-1d22eb254aa6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2547911932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otbn_randomness.2547911932 |
| Directory | /workspace/0.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otbn_smoketest.1342704337 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 6230094760 ps |
| CPU time | 1014.99 seconds |
| Started | Aug 17 07:11:25 PM PDT 24 |
| Finished | Aug 17 07:28:20 PM PDT 24 |
| Peak memory | 610872 kb |
| Host | smart-6cfbfe48-93c4-416f-aca4-58b8c7fbba29 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342704337 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 0.chip_sw_otbn_smoketest.1342704337 |
| Directory | /workspace/0.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_dai_lock.1065588478 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 27525380040 ps |
| CPU time | 4938.44 seconds |
| Started | Aug 17 07:10:07 PM PDT 24 |
| Finished | Aug 17 08:32:26 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-01d623d0-e604-496a-a16d-38a17b4ca1e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=otp_ctrl_mem_access_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=106558 8478 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_dai_lock.1065588478 |
| Directory | /workspace/0.chip_sw_otp_ctrl_dai_lock/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2515099931 |
| Short name | T1276 |
| Test name | |
| Test status | |
| Simulation time | 3091559040 ps |
| CPU time | 360.93 seconds |
| Started | Aug 17 07:05:35 PM PDT 24 |
| Finished | Aug 17 07:11:36 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-6a64d8ee-e26e-4ee4-a42b-e16f5b01278c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515099931 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_ecc_error_vendor_test.2515099931 |
| Directory | /workspace/0.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1924190046 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 8455925208 ps |
| CPU time | 1378.03 seconds |
| Started | Aug 17 07:05:22 PM PDT 24 |
| Finished | Aug 17 07:28:21 PM PDT 24 |
| Peak memory | 611332 kb |
| Host | smart-ca9ef34f-8902-45b4-93f8-d59b81610f65 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1924190046 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_dev.1924190046 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.67239654 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 8113635640 ps |
| CPU time | 1062.15 seconds |
| Started | Aug 17 07:08:08 PM PDT 24 |
| Finished | Aug 17 07:25:51 PM PDT 24 |
| Peak memory | 611324 kb |
| Host | smart-f079fa15-7216-423f-b309-960dfd9bbbee |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=67239654 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_prod.67239654 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2854087888 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 8176785344 ps |
| CPU time | 1303.32 seconds |
| Started | Aug 17 07:06:26 PM PDT 24 |
| Finished | Aug 17 07:28:10 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-93064a06-6014-4505-9357-33129affff47 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2854087888 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_rma.2854087888 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2775736184 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 4876392520 ps |
| CPU time | 576.61 seconds |
| Started | Aug 17 07:05:57 PM PDT 24 |
| Finished | Aug 17 07:15:34 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-f63de93a-6176-43ac-8f9a-306f98419173 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=2775736184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2775736184 |
| Directory | /workspace/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.658782123 |
| Short name | T1197 |
| Test name | |
| Test status | |
| Simulation time | 2784162690 ps |
| CPU time | 270.09 seconds |
| Started | Aug 17 07:10:32 PM PDT 24 |
| Finished | Aug 17 07:15:03 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-5277b5ba-67c6-4c3d-bf06-9549eea97f8f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658782123 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_otp_ctrl_smoketest.658782123 |
| Directory | /workspace/0.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pattgen_ios.2505344539 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 2657889208 ps |
| CPU time | 225.5 seconds |
| Started | Aug 17 07:06:29 PM PDT 24 |
| Finished | Aug 17 07:10:15 PM PDT 24 |
| Peak memory | 613780 kb |
| Host | smart-51323d49-3bbb-45a4-b07f-eb05572bfcaf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505344539 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pattgen_ios.2505344539 |
| Directory | /workspace/0.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_idle_load.1585721630 |
| Short name | T1248 |
| Test name | |
| Test status | |
| Simulation time | 4859757838 ps |
| CPU time | 672.85 seconds |
| Started | Aug 17 07:12:22 PM PDT 24 |
| Finished | Aug 17 07:23:35 PM PDT 24 |
| Peak memory | 611060 kb |
| Host | smart-8e0c2c8d-1ce8-463e-bd02-349f957d4572 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585721630 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_idle_load.1585721630 |
| Directory | /workspace/0.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_sleep_load.2584749760 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 4050474698 ps |
| CPU time | 380.85 seconds |
| Started | Aug 17 07:16:04 PM PDT 24 |
| Finished | Aug 17 07:22:26 PM PDT 24 |
| Peak memory | 609832 kb |
| Host | smart-c72f6d70-7a9e-4307-bf53-8a681820486e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584749760 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 0.chip_sw_power_sleep_load.2584749760 |
| Directory | /workspace/0.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/0.chip_sw_power_virus.1705569995 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 5832622660 ps |
| CPU time | 1623.66 seconds |
| Started | Aug 17 07:15:37 PM PDT 24 |
| Finished | Aug 17 07:42:42 PM PDT 24 |
| Peak memory | 625768 kb |
| Host | smart-da903ef4-8346-4cb6-8e9f-71bb0078056e |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1705569995 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_power_virus.1705569995 |
| Directory | /workspace/0.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4075571647 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 11975007697 ps |
| CPU time | 2021.88 seconds |
| Started | Aug 17 07:08:38 PM PDT 24 |
| Finished | Aug 17 07:42:20 PM PDT 24 |
| Peak memory | 612092 kb |
| Host | smart-cb6a18f7-843d-4535-8cdd-f906116dc861 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4075 571647 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_all_reset_reqs.4075571647 |
| Directory | /workspace/0.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4102897443 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 22366106154 ps |
| CPU time | 2039 seconds |
| Started | Aug 17 07:08:15 PM PDT 24 |
| Finished | Aug 17 07:42:14 PM PDT 24 |
| Peak memory | 611272 kb |
| Host | smart-84077091-41fc-4b57-9a98-fef68cf89f1c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410 2897443 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_b2b_sleep_reset_req.4102897443 |
| Directory | /workspace/0.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.308430951 |
| Short name | T1225 |
| Test name | |
| Test status | |
| Simulation time | 16231723153 ps |
| CPU time | 1462.51 seconds |
| Started | Aug 17 07:11:53 PM PDT 24 |
| Finished | Aug 17 07:36:17 PM PDT 24 |
| Peak memory | 612068 kb |
| Host | smart-2fe7911a-8484-4bca-9f30-524785382488 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=308430951 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.308430951 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3987584361 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 21640020964 ps |
| CPU time | 1788.94 seconds |
| Started | Aug 17 07:08:43 PM PDT 24 |
| Finished | Aug 17 07:38:33 PM PDT 24 |
| Peak memory | 611336 kb |
| Host | smart-4a5adf9e-9008-45cc-98cd-2e9cfd4f6f69 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3987584361 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3987584361 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3396724869 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 10839648728 ps |
| CPU time | 911.41 seconds |
| Started | Aug 17 07:11:02 PM PDT 24 |
| Finished | Aug 17 07:26:15 PM PDT 24 |
| Peak memory | 611524 kb |
| Host | smart-d62073f7-b2df-47eb-a088-66d335988c63 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396724869 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_deep_sleep_por_reset.3396724869 |
| Directory | /workspace/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.2095405304 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 4374544080 ps |
| CPU time | 566.68 seconds |
| Started | Aug 17 07:08:02 PM PDT 24 |
| Finished | Aug 17 07:17:29 PM PDT 24 |
| Peak memory | 618188 kb |
| Host | smart-44bbd981-e88d-409d-b601-2dca17974718 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=2095405304 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_main_power_glitch_reset.2095405304 |
| Directory | /workspace/0.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2323599725 |
| Short name | T1307 |
| Test name | |
| Test status | |
| Simulation time | 11781072705 ps |
| CPU time | 1515.8 seconds |
| Started | Aug 17 07:12:04 PM PDT 24 |
| Finished | Aug 17 07:37:21 PM PDT 24 |
| Peak memory | 612100 kb |
| Host | smart-ab2f4419-e071-4cef-b0d0-b2faa7d3cf09 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323599725 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2323599725 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2455432242 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 6719872466 ps |
| CPU time | 405.7 seconds |
| Started | Aug 17 07:07:25 PM PDT 24 |
| Finished | Aug 17 07:14:11 PM PDT 24 |
| Peak memory | 611168 kb |
| Host | smart-233317c9-5f9e-4769-8bb1-5aca7d6ea288 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455432242 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2455432242 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1077145003 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 6650309748 ps |
| CPU time | 752.12 seconds |
| Started | Aug 17 07:07:12 PM PDT 24 |
| Finished | Aug 17 07:19:44 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-47f9637a-264e-48c8-aaa5-a56c4f65f7e2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077145003 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_normal_sleep_por_reset.1077145003 |
| Directory | /workspace/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1023830272 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 24452153502 ps |
| CPU time | 2594.55 seconds |
| Started | Aug 17 07:05:43 PM PDT 24 |
| Finished | Aug 17 07:48:58 PM PDT 24 |
| Peak memory | 612156 kb |
| Host | smart-7e787f7d-64b0-4026-a0dd-a12ef9446f4d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1023830272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1023830272 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2604219748 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 35697921370 ps |
| CPU time | 3322.84 seconds |
| Started | Aug 17 07:06:10 PM PDT 24 |
| Finished | Aug 17 08:01:34 PM PDT 24 |
| Peak memory | 611628 kb |
| Host | smart-644e86c2-8a57-4170-8af6-0106695a236c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_test_timeout_ns=24_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_power _glitch_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604219748 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_random_power_glit ch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_random_s leep_power_glitch_reset.2604219748 |
| Directory | /workspace/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1600058061 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3465566200 ps |
| CPU time | 257.56 seconds |
| Started | Aug 17 07:11:26 PM PDT 24 |
| Finished | Aug 17 07:15:45 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-f05e754c-c1d6-4005-a399-48cc33ebfe5c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600058061 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_disabled.1600058061 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3629997278 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 6436735900 ps |
| CPU time | 522.75 seconds |
| Started | Aug 17 07:07:31 PM PDT 24 |
| Finished | Aug 17 07:16:15 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-a14e9442-8cfd-45db-a6d9-5f44d0c673eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3629997278 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sleep_wake_5_bug.3629997278 |
| Directory | /workspace/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.128726496 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 6582872356 ps |
| CPU time | 465.96 seconds |
| Started | Aug 17 07:15:26 PM PDT 24 |
| Finished | Aug 17 07:23:12 PM PDT 24 |
| Peak memory | 610920 kb |
| Host | smart-81d5dee5-9fd2-4e07-8198-b297ee644b75 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128726496 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_smoketest.128726496 |
| Directory | /workspace/0.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4055576206 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 6670216708 ps |
| CPU time | 1005.88 seconds |
| Started | Aug 17 07:07:29 PM PDT 24 |
| Finished | Aug 17 07:24:15 PM PDT 24 |
| Peak memory | 611168 kb |
| Host | smart-af927cc4-3048-4f5a-8435-f609750f9534 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055576206 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_sysrst_ctrl_reset.4055576206 |
| Directory | /workspace/0.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1444223684 |
| Short name | T1131 |
| Test name | |
| Test status | |
| Simulation time | 4368265776 ps |
| CPU time | 611.2 seconds |
| Started | Aug 17 07:05:28 PM PDT 24 |
| Finished | Aug 17 07:15:41 PM PDT 24 |
| Peak memory | 611104 kb |
| Host | smart-89df73bc-c7e2-4763-9b71-776211b99c5a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444223684 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1444223684 |
| Directory | /workspace/0.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3842722430 |
| Short name | T1286 |
| Test name | |
| Test status | |
| Simulation time | 5726641656 ps |
| CPU time | 408.65 seconds |
| Started | Aug 17 07:15:12 PM PDT 24 |
| Finished | Aug 17 07:22:01 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-bd18837e-c0cd-4488-a9d9-3ad04f100774 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842722430 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_usbdev_smoketest.3842722430 |
| Directory | /workspace/0.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3784926122 |
| Short name | T1123 |
| Test name | |
| Test status | |
| Simulation time | 3570915762 ps |
| CPU time | 406.44 seconds |
| Started | Aug 17 07:08:16 PM PDT 24 |
| Finished | Aug 17 07:15:03 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-36571fe4-079d-44db-a8a5-961eea81026a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378 4926122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_pwrmgr_wdog_reset.3784926122 |
| Directory | /workspace/0.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.3861847310 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 8978731499 ps |
| CPU time | 612.05 seconds |
| Started | Aug 17 07:07:18 PM PDT 24 |
| Finished | Aug 17 07:17:30 PM PDT 24 |
| Peak memory | 610292 kb |
| Host | smart-381eb357-3544-46e3-8659-ebaf5c8af956 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861847310 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rom_ctrl_integrity_check.3861847310 |
| Directory | /workspace/0.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.3827109122 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 5210276652 ps |
| CPU time | 417.52 seconds |
| Started | Aug 17 07:05:54 PM PDT 24 |
| Finished | Aug 17 07:12:51 PM PDT 24 |
| Peak memory | 609904 kb |
| Host | smart-68e3e881-beaf-4991-818b-c4ff3e9dbdef |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827109122 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_rstmgr_cpu_info.3827109122 |
| Directory | /workspace/0.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.501186935 |
| Short name | T1170 |
| Test name | |
| Test status | |
| Simulation time | 5296726508 ps |
| CPU time | 666.87 seconds |
| Started | Aug 17 07:06:54 PM PDT 24 |
| Finished | Aug 17 07:18:02 PM PDT 24 |
| Peak memory | 641864 kb |
| Host | smart-81cf78e9-8a21-4d0b-b6b1-4f7de27a9ec4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 501186935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_rst_cnsty_escalation.501186935 |
| Directory | /workspace/0.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2366182290 |
| Short name | T1111 |
| Test name | |
| Test status | |
| Simulation time | 2569732140 ps |
| CPU time | 243.66 seconds |
| Started | Aug 17 07:09:01 PM PDT 24 |
| Finished | Aug 17 07:13:05 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-d91a7071-d66f-4481-b635-79da5a23c901 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366182290 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.chip_sw_rstmgr_smoketest.2366182290 |
| Directory | /workspace/0.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4022819676 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 3504836600 ps |
| CPU time | 328.31 seconds |
| Started | Aug 17 07:09:02 PM PDT 24 |
| Finished | Aug 17 07:14:31 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-640922fd-7f88-44fb-ab1c-141670e4124a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022819676 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rstmgr_sw_req.4022819676 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1230752081 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 2483311478 ps |
| CPU time | 272.72 seconds |
| Started | Aug 17 07:08:48 PM PDT 24 |
| Finished | Aug 17 07:13:22 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-2d3d9bf3-706f-4ce0-a454-9513ee7665a9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1230752081 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rstmgr_sw_rst.1230752081 |
| Directory | /workspace/0.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.3883972988 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 2809921800 ps |
| CPU time | 260.28 seconds |
| Started | Aug 17 07:10:07 PM PDT 24 |
| Finished | Aug 17 07:14:28 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-7f4a1508-8237-4f46-8e5e-1f5bac017afd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883972988 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_icache_invalidate.3883972988 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1668524902 |
| Short name | T1188 |
| Test name | |
| Test status | |
| Simulation time | 5749703902 ps |
| CPU time | 1053.62 seconds |
| Started | Aug 17 07:13:49 PM PDT 24 |
| Finished | Aug 17 07:31:24 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-4268c351-c360-4529-973d-040c39b56c86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1668524902 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_core_ibex_rnd.1668524902 |
| Directory | /workspace/0.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1724210273 |
| Short name | T1180 |
| Test name | |
| Test status | |
| Simulation time | 5108432330 ps |
| CPU time | 457.47 seconds |
| Started | Aug 17 07:15:00 PM PDT 24 |
| Finished | Aug 17 07:22:38 PM PDT 24 |
| Peak memory | 620016 kb |
| Host | smart-ff91183b-8dab-4aa2-979a-a19a12dcb89c |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724210273 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_access_after_wakeup.1724210273 |
| Directory | /workspace/0.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2919851754 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 4479995180 ps |
| CPU time | 489.73 seconds |
| Started | Aug 17 07:07:09 PM PDT 24 |
| Finished | Aug 17 07:15:19 PM PDT 24 |
| Peak memory | 624968 kb |
| Host | smart-656cf486-db47-4214-9569-8624a4329171 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291985 1754 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2919851754 |
| Directory | /workspace/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1546086770 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 2529636216 ps |
| CPU time | 280.88 seconds |
| Started | Aug 17 07:15:35 PM PDT 24 |
| Finished | Aug 17 07:20:16 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-f263d6b0-0036-4042-bc7f-73fb224767e6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1546086770 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 0.chip_sw_rv_plic_smoketest.1546086770 |
| Directory | /workspace/0.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_irq.1172923867 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2515829902 ps |
| CPU time | 237.78 seconds |
| Started | Aug 17 07:10:24 PM PDT 24 |
| Finished | Aug 17 07:14:22 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-622f40f5-42ba-44fe-b830-cb240c8c5f11 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172923867 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_irq.1172923867 |
| Directory | /workspace/0.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1129773387 |
| Short name | T1153 |
| Test name | |
| Test status | |
| Simulation time | 3001944756 ps |
| CPU time | 260.27 seconds |
| Started | Aug 17 07:10:02 PM PDT 24 |
| Finished | Aug 17 07:14:24 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-80d4d998-d9b1-42ba-8854-7f2e30a36da6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129773387 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 0.chip_sw_rv_timer_smoketest.1129773387 |
| Directory | /workspace/0.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1901955962 |
| Short name | T1247 |
| Test name | |
| Test status | |
| Simulation time | 3172052990 ps |
| CPU time | 233.2 seconds |
| Started | Aug 17 07:07:15 PM PDT 24 |
| Finished | Aug 17 07:11:09 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-ac684d51-8fd4-4637-835e-2acaac155ac4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901955 962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sensor_ctrl_status.1901955962 |
| Directory | /workspace/0.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_retention.4067894490 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 5003254024 ps |
| CPU time | 370.4 seconds |
| Started | Aug 17 07:08:08 PM PDT 24 |
| Finished | Aug 17 07:14:19 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-f98051e2-7a8d-4151-b645-77816d0488ad |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067894490 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_retention.4067894490 |
| Directory | /workspace/0.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pin_wake.2344627044 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2668328000 ps |
| CPU time | 233.95 seconds |
| Started | Aug 17 07:07:53 PM PDT 24 |
| Finished | Aug 17 07:11:47 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-e8cfef5b-4b0f-4f31-af04-34f528fd5227 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +sw_build_device=sim_dv +sw_images=sleep_pin_wake_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344627044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_wake_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_pin_wake.2344627044 |
| Directory | /workspace/0.chip_sw_sleep_pin_wake/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.2852045665 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 8675876220 ps |
| CPU time | 1564.22 seconds |
| Started | Aug 17 07:05:53 PM PDT 24 |
| Finished | Aug 17 07:31:57 PM PDT 24 |
| Peak memory | 611232 kb |
| Host | smart-61afce08-4819-4eb7-881a-8839d3129df3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852045665 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 0.chip_sw_sleep_pwm_pulses.2852045665 |
| Directory | /workspace/0.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.382611205 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 6640789318 ps |
| CPU time | 501.94 seconds |
| Started | Aug 17 07:14:57 PM PDT 24 |
| Finished | Aug 17 07:23:19 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-70cae239-7a0c-4dd7-95c8-95c4d17b4379 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382611205 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sle ep_sram_ret_contents_no_scramble.382611205 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.384069363 |
| Short name | T1314 |
| Test name | |
| Test status | |
| Simulation time | 7626934846 ps |
| CPU time | 854.86 seconds |
| Started | Aug 17 07:08:39 PM PDT 24 |
| Finished | Aug 17 07:22:54 PM PDT 24 |
| Peak memory | 611408 kb |
| Host | smart-757c827d-a489-4956-a9e7-29f219c0a3a3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384069363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sleep_ sram_ret_contents_scramble.384069363 |
| Directory | /workspace/0.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through.3158919310 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 6750238535 ps |
| CPU time | 846.53 seconds |
| Started | Aug 17 07:07:36 PM PDT 24 |
| Finished | Aug 17 07:21:43 PM PDT 24 |
| Peak memory | 625560 kb |
| Host | smart-83e6796e-757c-4d7b-a379-922359df984f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3158919310 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through.3158919310 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4252982871 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 4217810526 ps |
| CPU time | 444.74 seconds |
| Started | Aug 17 07:05:59 PM PDT 24 |
| Finished | Aug 17 07:13:25 PM PDT 24 |
| Peak memory | 625496 kb |
| Host | smart-0a5ddf38-1578-4b28-afa4-d31fd111033d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252982871 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_pass_through_collision.4252982871 |
| Directory | /workspace/0.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/0.chip_sw_spi_device_tpm.2799147539 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 3374502365 ps |
| CPU time | 296.76 seconds |
| Started | Aug 17 07:06:01 PM PDT 24 |
| Finished | Aug 17 07:10:57 PM PDT 24 |
| Peak memory | 620296 kb |
| Host | smart-ae462363-482d-48ff-98af-f6bdc30d09ff |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799147539 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default .vdb -cm_log /dev/null -cm_name 0.chip_sw_spi_device_tpm.2799147539 |
| Directory | /workspace/0.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1219168655 |
| Short name | T1326 |
| Test name | |
| Test status | |
| Simulation time | 5070719019 ps |
| CPU time | 614.37 seconds |
| Started | Aug 17 07:08:35 PM PDT 24 |
| Finished | Aug 17 07:18:51 PM PDT 24 |
| Peak memory | 611744 kb |
| Host | smart-aad80253-1737-4056-9788-ea97f3055175 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219168655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1219168655 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.449882420 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 5609222503 ps |
| CPU time | 593.39 seconds |
| Started | Aug 17 07:09:01 PM PDT 24 |
| Finished | Aug 17 07:18:55 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-7357a43b-f03c-4355-b4c2-17b55f4f13d7 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449882420 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.449882420 |
| Directory | /workspace/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3485798628 |
| Short name | T1265 |
| Test name | |
| Test status | |
| Simulation time | 3115247318 ps |
| CPU time | 281.14 seconds |
| Started | Aug 17 07:08:28 PM PDT 24 |
| Finished | Aug 17 07:13:10 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-7c38e7ba-e8ba-44f6-b9a8-1c807ebb9977 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485798628 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 0.chip_sw_sram_ctrl_smoketest.3485798628 |
| Directory | /workspace/0.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3204638265 |
| Short name | T1344 |
| Test name | |
| Test status | |
| Simulation time | 20889394367 ps |
| CPU time | 3555.39 seconds |
| Started | Aug 17 07:07:13 PM PDT 24 |
| Finished | Aug 17 08:06:29 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-c5715a1f-3f4d-40a3-8908-71937a01df0a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204638265 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ec_rst_l.3204638265 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.3112099979 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 4979266738 ps |
| CPU time | 824.9 seconds |
| Started | Aug 17 07:08:12 PM PDT 24 |
| Finished | Aug 17 07:22:00 PM PDT 24 |
| Peak memory | 614452 kb |
| Host | smart-f8e1bfee-7149-44fa-9caa-58100ee67c12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112099979 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_in_irq.3112099979 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_outputs.2525281725 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 4093608264 ps |
| CPU time | 351.85 seconds |
| Started | Aug 17 07:07:47 PM PDT 24 |
| Finished | Aug 17 07:13:40 PM PDT 24 |
| Peak memory | 609744 kb |
| Host | smart-5794eb11-745c-4bee-936b-ad916eb7d541 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525281725 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_outputs.2525281725 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.494796414 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 23841410516 ps |
| CPU time | 1864.54 seconds |
| Started | Aug 17 07:10:26 PM PDT 24 |
| Finished | Aug 17 07:41:33 PM PDT 24 |
| Peak memory | 614580 kb |
| Host | smart-ca63b647-a3d4-4b24-83b6-4517f8494685 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49479641 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_reset.494796414 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.755067383 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 6665672258 ps |
| CPU time | 515.32 seconds |
| Started | Aug 17 07:06:24 PM PDT 24 |
| Finished | Aug 17 07:15:01 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-c2991912-fa76-4fc9-b4f5-833e65fd654e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755067383 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.755067383 |
| Directory | /workspace/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.856141720 |
| Short name | T1150 |
| Test name | |
| Test status | |
| Simulation time | 4176204816 ps |
| CPU time | 578.48 seconds |
| Started | Aug 17 07:05:44 PM PDT 24 |
| Finished | Aug 17 07:15:24 PM PDT 24 |
| Peak memory | 625128 kb |
| Host | smart-27828741-10e5-4c89-bc0d-1d33458249cc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=856141720 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_rand_baudrate.856141720 |
| Directory | /workspace/0.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_smoketest.2281819616 |
| Short name | T1258 |
| Test name | |
| Test status | |
| Simulation time | 2539504292 ps |
| CPU time | 198.89 seconds |
| Started | Aug 17 07:14:36 PM PDT 24 |
| Finished | Aug 17 07:17:55 PM PDT 24 |
| Peak memory | 611708 kb |
| Host | smart-667e837d-f7b0-428e-97b5-c39dc6c16570 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281819616 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 0.chip_sw_uart_smoketest.2281819616 |
| Directory | /workspace/0.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.1889361465 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 8320806325 ps |
| CPU time | 1704.49 seconds |
| Started | Aug 17 07:09:29 PM PDT 24 |
| Finished | Aug 17 07:37:56 PM PDT 24 |
| Peak memory | 618680 kb |
| Host | smart-372f8d58-a9dd-4bc0-b835-cdbba4a8e0cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889361465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq.1889361465 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1258489232 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 4820120966 ps |
| CPU time | 521.44 seconds |
| Started | Aug 17 07:07:24 PM PDT 24 |
| Finished | Aug 17 07:16:06 PM PDT 24 |
| Peak memory | 623876 kb |
| Host | smart-fd7a2cdf-58bd-4bf1-99ac-2ce53ae52ffe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258489232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.1258489232 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.294519363 |
| Short name | T1304 |
| Test name | |
| Test status | |
| Simulation time | 77968113357 ps |
| CPU time | 13295.3 seconds |
| Started | Aug 17 07:04:39 PM PDT 24 |
| Finished | Aug 17 10:46:16 PM PDT 24 |
| Peak memory | 636748 kb |
| Host | smart-3ee7ad53-4831-456c-adb6-21bc6e6e8f93 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=294519363 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_bootstrap.294519363 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.1115361399 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3963861576 ps |
| CPU time | 595.24 seconds |
| Started | Aug 17 07:07:14 PM PDT 24 |
| Finished | Aug 17 07:17:09 PM PDT 24 |
| Peak memory | 623144 kb |
| Host | smart-07f62c6d-e9e7-4b65-b2d3-01a9d44102c3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115361399 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx1.1115361399 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.2154608060 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 5042091832 ps |
| CPU time | 775.91 seconds |
| Started | Aug 17 07:05:47 PM PDT 24 |
| Finished | Aug 17 07:18:43 PM PDT 24 |
| Peak memory | 620668 kb |
| Host | smart-b8432b15-ddd2-4853-9690-55a35e0b72e9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2154608060 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_uart_tx_rx_idx3.2154608060 |
| Directory | /workspace/0.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.3328088075 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 3251902126 ps |
| CPU time | 304.28 seconds |
| Started | Aug 17 07:08:01 PM PDT 24 |
| Finished | Aug 17 07:13:07 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-ef4af610-0324-46c4-ac2e-3b468b3830d7 |
| User | root |
| Command | /workspace/default/simv +usb_max_drift=1 +usb_fast_sof=1 +sw_build_device=sim_dv +sw_images=ast_usb_clk_calib:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328088075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usb_ast_clk_calib_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usb_ast_clk_calib.3328088075 |
| Directory | /workspace/0.chip_sw_usb_ast_clk_calib/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_config_host.3426749952 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 8082241264 ps |
| CPU time | 1987.8 seconds |
| Started | Aug 17 07:05:00 PM PDT 24 |
| Finished | Aug 17 07:38:09 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-9156a44a-3722-4124-aec8-8d042f9ac9d9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_config_host_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34267 49952 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_config_host.3426749952 |
| Directory | /workspace/0.chip_sw_usbdev_config_host/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3948072589 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 31803389940 ps |
| CPU time | 6879.48 seconds |
| Started | Aug 17 07:08:07 PM PDT 24 |
| Finished | Aug 17 09:02:48 PM PDT 24 |
| Peak memory | 610064 kb |
| Host | smart-a8752ef6-27b6-45e3-a908-ccebe91c5ed5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=100_000_000 +sw_build_device=sim_dv +sw_images=usbdev_pincfg_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3948072589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pincfg.3948072589 |
| Directory | /workspace/0.chip_sw_usbdev_pincfg/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_pullup.1550115717 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 3424801088 ps |
| CPU time | 348.96 seconds |
| Started | Aug 17 07:06:24 PM PDT 24 |
| Finished | Aug 17 07:12:13 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-b885a247-b87e-4182-934e-06e7f0b0ff70 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_pullup_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550115717 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_pullup.1550115717 |
| Directory | /workspace/0.chip_sw_usbdev_pullup/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3107054008 |
| Short name | T1327 |
| Test name | |
| Test status | |
| Simulation time | 3556678880 ps |
| CPU time | 565.27 seconds |
| Started | Aug 17 07:05:16 PM PDT 24 |
| Finished | Aug 17 07:14:43 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-9662c0c4-ed54-492c-b652-7d9eb9b9c591 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_setuprx_test:1:new_rules,test_rom:0 +cdc_instrument ation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310705400 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_setuprx.3107054008 |
| Directory | /workspace/0.chip_sw_usbdev_setuprx/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_stream.2852928503 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 18965408108 ps |
| CPU time | 4148.79 seconds |
| Started | Aug 17 07:10:01 PM PDT 24 |
| Finished | Aug 17 08:19:11 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-c4d6723c-4514-47c4-a8e6-8d7d7b3cea39 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_test_timeout_ns=60_000_000 +sw_build_device=sim_dv +sw_images=usbdev_stream_test:1:new_ru les,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim. tcl +ntb_random_seed=2852928503 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_stream_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_stream.2852928503 |
| Directory | /workspace/0.chip_sw_usbdev_stream/latest |
| Test location | /workspace/coverage/default/0.chip_sw_usbdev_vbus.530122262 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2770216796 ps |
| CPU time | 193.49 seconds |
| Started | Aug 17 07:07:59 PM PDT 24 |
| Finished | Aug 17 07:11:13 PM PDT 24 |
| Peak memory | 609936 kb |
| Host | smart-5836722f-6498-440a-8e82-8f21dd24b959 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=usbdev_vbus_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530122262 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_usbdev_dpi_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_sw_usbdev_vbus.530122262 |
| Directory | /workspace/0.chip_sw_usbdev_vbus/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_dev.3843982332 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2908159752 ps |
| CPU time | 200.32 seconds |
| Started | Aug 17 07:06:18 PM PDT 24 |
| Finished | Aug 17 07:09:39 PM PDT 24 |
| Peak memory | 625356 kb |
| Host | smart-36972630-6623-4389-a705-7ed9927ba943 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3843982332 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_dev.3843982332 |
| Directory | /workspace/0.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_prod.2167560609 |
| Short name | T1243 |
| Test name | |
| Test status | |
| Simulation time | 16898938288 ps |
| CPU time | 1875.32 seconds |
| Started | Aug 17 07:06:47 PM PDT 24 |
| Finished | Aug 17 07:38:02 PM PDT 24 |
| Peak memory | 625676 kb |
| Host | smart-a19d29d3-7b36-4a27-a188-916b59bbfb2c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167560609 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_prod.2167560609 |
| Directory | /workspace/0.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_rma.4289156776 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 5493922620 ps |
| CPU time | 439.13 seconds |
| Started | Aug 17 07:06:30 PM PDT 24 |
| Finished | Aug 17 07:13:49 PM PDT 24 |
| Peak memory | 625716 kb |
| Host | smart-d0427f82-e7c1-4516-ad70-c48d5f7229b3 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289156776 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_rma.4289156776 |
| Directory | /workspace/0.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/0.chip_tap_straps_testunlock0.697889411 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 5507277299 ps |
| CPU time | 472.35 seconds |
| Started | Aug 17 07:07:12 PM PDT 24 |
| Finished | Aug 17 07:15:04 PM PDT 24 |
| Peak memory | 634028 kb |
| Host | smart-383f3aa4-79f8-4272-8b18-4450f5bf44e6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=697889411 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.chip_tap_straps_testunlock0.697889411 |
| Directory | /workspace/0.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_dev.4229225081 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 15486372001 ps |
| CPU time | 4504.8 seconds |
| Started | Aug 17 07:12:40 PM PDT 24 |
| Finished | Aug 17 08:27:45 PM PDT 24 |
| Peak memory | 610348 kb |
| Host | smart-1adfc151-c9d2-4b58-8a2f-e813f9b316f5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229225081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_dev.4229225081 |
| Directory | /workspace/0.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod.4104576852 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 16171312880 ps |
| CPU time | 3707 seconds |
| Started | Aug 17 07:16:32 PM PDT 24 |
| Finished | Aug 17 08:18:19 PM PDT 24 |
| Peak memory | 610896 kb |
| Host | smart-a9bbb0ce-41d0-4609-ba62-dd00146621f7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104576852 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_prod.4104576852 |
| Directory | /workspace/0.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.3336703125 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 15575873769 ps |
| CPU time | 4669.03 seconds |
| Started | Aug 17 07:15:51 PM PDT 24 |
| Finished | Aug 17 08:33:41 PM PDT 24 |
| Peak memory | 610944 kb |
| Host | smart-90f50c44-7924-411c-bb9d-f123999d9046 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336703125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 0.rom_e2e_asm_init_prod_end.3336703125 |
| Directory | /workspace/0.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_rma.4041037215 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 14992021864 ps |
| CPU time | 3343.81 seconds |
| Started | Aug 17 07:14:09 PM PDT 24 |
| Finished | Aug 17 08:09:54 PM PDT 24 |
| Peak memory | 610280 kb |
| Host | smart-750b4852-ed69-490a-933f-2830ed529de1 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4041037215 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_asm_init_rma.4041037215 |
| Directory | /workspace/0.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.334176630 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 11136582872 ps |
| CPU time | 2875.97 seconds |
| Started | Aug 17 07:11:51 PM PDT 24 |
| Finished | Aug 17 07:59:47 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-c6cd1538-d205-4d89-8e58-932686a30240 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334176630 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 0.rom_e2e_asm_init_test_unlocked0.334176630 |
| Directory | /workspace/0.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3322843930 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 24374978328 ps |
| CPU time | 6306.89 seconds |
| Started | Aug 17 07:17:10 PM PDT 24 |
| Finished | Aug 17 09:02:18 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-e2454618-919d-421c-b95d-fc2b3d3836f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3322843930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.3322843930 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1104792294 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 24743114408 ps |
| CPU time | 6899.44 seconds |
| Started | Aug 17 07:14:50 PM PDT 24 |
| Finished | Aug 17 09:09:50 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-73be93eb-644d-4724-b1e1-5616ee33fb7d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=1104792294 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.1104792294 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.468825460 |
| Short name | T1194 |
| Test name | |
| Test status | |
| Simulation time | 23567659814 ps |
| CPU time | 5942.09 seconds |
| Started | Aug 17 07:12:11 PM PDT 24 |
| Finished | Aug 17 08:51:14 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-7e9dcefe-88d8-4a21-9745-1b8e36c66bd1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=468825460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.468825460 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1676679314 |
| Short name | T1113 |
| Test name | |
| Test status | |
| Simulation time | 18238164190 ps |
| CPU time | 4615.66 seconds |
| Started | Aug 17 07:14:46 PM PDT 24 |
| Finished | Aug 17 08:31:42 PM PDT 24 |
| Peak memory | 610520 kb |
| Host | smart-f620c47c-5000-4604-9e0d-80df5ba97e43 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676679314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.1676679314 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2186787038 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 15561825240 ps |
| CPU time | 4363.38 seconds |
| Started | Aug 17 07:17:12 PM PDT 24 |
| Finished | Aug 17 08:29:58 PM PDT 24 |
| Peak memory | 610772 kb |
| Host | smart-79d183af-e94f-4adb-a3dc-520288b7816c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2186787038 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.2186787038 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3478420781 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 15241500760 ps |
| CPU time | 4087.22 seconds |
| Started | Aug 17 07:22:46 PM PDT 24 |
| Finished | Aug 17 08:30:54 PM PDT 24 |
| Peak memory | 610784 kb |
| Host | smart-9b96707a-edea-4ebd-88d8-6a0ba0723c1b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3478420781 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.3478420781 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2404695176 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 15049220860 ps |
| CPU time | 3704.39 seconds |
| Started | Aug 17 07:13:16 PM PDT 24 |
| Finished | Aug 17 08:15:01 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-270025c7-cdf5-42e7-ac14-ad74b7d78fc4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_prod_end:4,mask_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2404695176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2404695176 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1367228337 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 15059626492 ps |
| CPU time | 3516.27 seconds |
| Started | Aug 17 07:12:22 PM PDT 24 |
| Finished | Aug 17 08:10:59 PM PDT 24 |
| Peak memory | 609768 kb |
| Host | smart-a18413a2-a433-4c9e-9d8f-3a74190abfc1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1367228337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1367228337 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1533016521 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 11411560888 ps |
| CPU time | 2658.43 seconds |
| Started | Aug 17 07:12:12 PM PDT 24 |
| Finished | Aug 17 07:56:31 PM PDT 24 |
| Peak memory | 610600 kb |
| Host | smart-a6a6a0c7-2d97-45b4-b7df-d1fc1b48e1a8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_boot_policy_valid_test_unlocked0:4, mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533016521 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1533016521 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.98331762 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 15407777540 ps |
| CPU time | 3983.16 seconds |
| Started | Aug 17 07:15:04 PM PDT 24 |
| Finished | Aug 17 08:21:28 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-438834c4-2935-4a91-b4f6-9b75a4987ef7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_dev:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98331762 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_dev.98331762 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1283183512 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 15325043112 ps |
| CPU time | 3830.04 seconds |
| Started | Aug 17 07:13:27 PM PDT 24 |
| Finished | Aug 17 08:17:18 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-c4cb40b5-325d-4423-992f-8774093f37ca |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod:4,mask_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283183512 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1283183512 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.678101529 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 15766134498 ps |
| CPU time | 3295.74 seconds |
| Started | Aug 17 07:14:26 PM PDT 24 |
| Finished | Aug 17 08:09:22 PM PDT 24 |
| Peak memory | 609848 kb |
| Host | smart-03e24ecd-0e42-498a-8a4c-8df63cde1000 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_prod_end:4,mask_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678101 529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.678101529 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4268042514 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 14306229444 ps |
| CPU time | 3784.13 seconds |
| Started | Aug 17 07:16:50 PM PDT 24 |
| Finished | Aug 17 08:19:56 PM PDT 24 |
| Peak memory | 610856 kb |
| Host | smart-cabd8de7-bfe0-474a-87b2-1c436110a33d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_rma:4,mask_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4268042514 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_rma.4268042514 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2898021091 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 11896083752 ps |
| CPU time | 3205.36 seconds |
| Started | Aug 17 07:16:46 PM PDT 24 |
| Finished | Aug 17 08:10:12 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-f23bbd7c-8485-44c8-92d1-b55d73eeacba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,empty_test_slot_b_fake_ecdsa_prod_key_0:2:ot_flash_binary,otp_img_boot_policy_valid_test_unlocked0:4,mask_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2898021091 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2898021091 |
| Directory | /workspace/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_dev.3688532632 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 11538282134 ps |
| CPU time | 2079.57 seconds |
| Started | Aug 17 07:13:35 PM PDT 24 |
| Finished | Aug 17 07:48:16 PM PDT 24 |
| Peak memory | 624788 kb |
| Host | smart-fb00312d-5f1c-48d5-9145-7890cf3139dd |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_disabled:4,mask_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36885 32632 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_dev.3688532632 |
| Directory | /workspace/0.rom_e2e_jtag_debug_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3660673491 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 9946731445 ps |
| CPU time | 2306.31 seconds |
| Started | Aug 17 07:12:36 PM PDT 24 |
| Finished | Aug 17 07:51:03 PM PDT 24 |
| Peak memory | 624968 kb |
| Host | smart-8787151d-9a2a-469b-9945-a26e32504057 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlocked0_exec_disabled:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3660673491 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_debug_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_debug_test_unlocked0.3660673491 |
| Directory | /workspace/0.rom_e2e_jtag_debug_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.560284885 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 24797970849 ps |
| CPU time | 2468.44 seconds |
| Started | Aug 17 07:09:47 PM PDT 24 |
| Finished | Aug 17 07:50:56 PM PDT 24 |
| Peak memory | 619128 kb |
| Host | smart-7aa57679-b22e-4111-83f2-715d53c9d3ef |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_dev_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=560284885 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_dev.560284885 |
| Directory | /workspace/0.rom_e2e_jtag_inject_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_rma.3826567765 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 24772019366 ps |
| CPU time | 2407.08 seconds |
| Started | Aug 17 07:12:00 PM PDT 24 |
| Finished | Aug 17 07:52:08 PM PDT 24 |
| Peak memory | 619116 kb |
| Host | smart-c4f77de2-f49b-4e7c-a721-fc21c8ca2d86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_rma_exec_di sabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3826567765 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject_rma.3826567765 |
| Directory | /workspace/0.rom_e2e_jtag_inject_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_jtag_inject_test_unlocked0.1041470633 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 25059274988 ps |
| CPU time | 1800.96 seconds |
| Started | Aug 17 07:16:48 PM PDT 24 |
| Finished | Aug 17 07:46:49 PM PDT 24 |
| Peak memory | 623588 kb |
| Host | smart-89a95e20-f6ac-4099-a727-4b23f3e8587b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_jtag_dmi=1 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=img_test_unlock ed0_exec_disabled:4,sram_program:5,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041470633 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_jtag_ inject_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_jtag_inject _test_unlocked0.1041470633 |
| Directory | /workspace/0.rom_e2e_jtag_inject_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_invalid_meas.2792783028 |
| Short name | T1166 |
| Test name | |
| Test status | |
| Simulation time | 15212047084 ps |
| CPU time | 3605.59 seconds |
| Started | Aug 17 07:13:24 PM PDT 24 |
| Finished | Aug 17 08:13:31 PM PDT 24 |
| Peak memory | 610840 kb |
| Host | smart-7970e51d-3590-432a-b10f-bb0bc9389b22 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2792783028 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_in it_rom_ext_invalid_meas.2792783028 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_meas.3018772025 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 15136321128 ps |
| CPU time | 3244.41 seconds |
| Started | Aug 17 07:18:52 PM PDT 24 |
| Finished | Aug 17 08:12:56 PM PDT 24 |
| Peak memory | 610812 kb |
| Host | smart-7d3f8df7-ee86-4d87-a533-31e222224c67 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3018772025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext_meas.3018772025 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_keymgr_init_rom_ext_no_meas.2710517887 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 15181059810 ps |
| CPU time | 3187.56 seconds |
| Started | Aug 17 07:18:48 PM PDT 24 |
| Finished | Aug 17 08:11:56 PM PDT 24 |
| Peak memory | 610220 kb |
| Host | smart-d15fdef3-25a6-459d-852c-095e181c79c8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710517887 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_keymgr_init_rom_ext _no_meas.2710517887 |
| Directory | /workspace/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2402589794 |
| Short name | T1325 |
| Test name | |
| Test status | |
| Simulation time | 15110487956 ps |
| CPU time | 3704.7 seconds |
| Started | Aug 17 07:14:00 PM PDT 24 |
| Finished | Aug 17 08:15:45 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-3e8419c3-dd68-412c-973d-ba7e6243e4ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2402589794 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_ shutdown_exception_c.2402589794 |
| Directory | /workspace/0.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_shutdown_output.3900207447 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 27173193305 ps |
| CPU time | 3356.3 seconds |
| Started | Aug 17 07:16:33 PM PDT 24 |
| Finished | Aug 17 08:12:31 PM PDT 24 |
| Peak memory | 611964 kb |
| Host | smart-d700f411-e2ad-4974-a024-0d85a2fe934c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900207447 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_shutdown_output.3900207447 |
| Directory | /workspace/0.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.411179770 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 23410067372 ps |
| CPU time | 5142.38 seconds |
| Started | Aug 17 07:15:29 PM PDT 24 |
| Finished | Aug 17 08:41:12 PM PDT 24 |
| Peak memory | 609872 kb |
| Host | smart-0380da22-baf4-4ab8-bc9a-7ee9bd0bee09 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev :4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=411179770 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.411179770 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.2864683048 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 23198637100 ps |
| CPU time | 5748.87 seconds |
| Started | Aug 17 07:13:36 PM PDT 24 |
| Finished | Aug 17 08:49:25 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-222ced85-2867-478a-97d3-c410d3da71ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=2864683048 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_ b_bad_prod.2864683048 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2300614141 |
| Short name | T1164 |
| Test name | |
| Test status | |
| Simulation time | 23682524372 ps |
| CPU time | 5261.45 seconds |
| Started | Aug 17 07:23:16 PM PDT 24 |
| Finished | Aug 17 08:50:59 PM PDT 24 |
| Peak memory | 611124 kb |
| Host | smart-ede519e0-426d-4b4c-aee4-92301231cf7f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_p rod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2300614141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_ bad_b_bad_prod_end.2300614141 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.2195135630 |
| Short name | T1136 |
| Test name | |
| Test status | |
| Simulation time | 22867138598 ps |
| CPU time | 6238.12 seconds |
| Started | Aug 17 07:14:38 PM PDT 24 |
| Finished | Aug 17 08:58:37 PM PDT 24 |
| Peak memory | 610196 kb |
| Host | smart-0e09042d-5c71-4509-ae44-22dd674c57a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_r ma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=2195135630 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b _bad_rma.2195135630 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3557172076 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 17766293527 ps |
| CPU time | 5057.07 seconds |
| Started | Aug 17 07:18:23 PM PDT 24 |
| Finished | Aug 17 08:42:40 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-dda32554-f235-405e-a348-ebaf1811d8a0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=600_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,empty_test_slot_b_corrupted:2:ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_t est_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=3557172076 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b _bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_alw ays_a_bad_b_bad_test_unlocked0.3557172076 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2493552686 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 14193774276 ps |
| CPU time | 4072.82 seconds |
| Started | Aug 17 07:16:55 PM PDT 24 |
| Finished | Aug 17 08:24:49 PM PDT 24 |
| Peak memory | 610864 kb |
| Host | smart-1b0990cd-e770-4921-abff-0845f4493359 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493552686 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.2493552686 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.316846654 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 14093425551 ps |
| CPU time | 3831.65 seconds |
| Started | Aug 17 07:12:41 PM PDT 24 |
| Finished | Aug 17 08:16:33 PM PDT 24 |
| Peak memory | 611044 kb |
| Host | smart-d87bba7f-1658-4961-84bc-eca0a1a2bcde |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO SITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=316846654 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.316846654 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1790213877 |
| Short name | T1301 |
| Test name | |
| Test status | |
| Simulation time | 14075365826 ps |
| CPU time | 4044.41 seconds |
| Started | Aug 17 07:22:52 PM PDT 24 |
| Finished | Aug 17 08:30:18 PM PDT 24 |
| Peak memory | 611152 kb |
| Host | smart-a80bf1fa-47be-474e-8846-183079e1afd0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1790213877 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1790213877 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4213385335 |
| Short name | T1176 |
| Test name | |
| Test status | |
| Simulation time | 14286284528 ps |
| CPU time | 3514.03 seconds |
| Started | Aug 17 07:15:08 PM PDT 24 |
| Finished | Aug 17 08:13:43 PM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-49e88292-6ba1-4e88-b3fa-3f9c77ad4e3e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213385335 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4213385335 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3038156755 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 10905489004 ps |
| CPU time | 2808.9 seconds |
| Started | Aug 17 07:12:37 PM PDT 24 |
| Finished | Aug 17 07:59:26 PM PDT 24 |
| Peak memory | 611400 kb |
| Host | smart-09ffd0e2-1145-444c-b3a0-5b9fd6b2bcba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0:new_rules,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038156755 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3038156755 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2935335542 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 14331759891 ps |
| CPU time | 3306.56 seconds |
| Started | Aug 17 07:18:14 PM PDT 24 |
| Finished | Aug 17 08:13:21 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-26c3588b-8c45-46b1-aaf1-3bb9815d224e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_dev_key_0,otp_img_sigverify_always_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSI TY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935335542 -assert nopostproc +UVM_TESTNAME=chip_base_ test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.2935335542 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2974762696 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 14316308202 ps |
| CPU time | 3505.33 seconds |
| Started | Aug 17 07:13:17 PM PDT 24 |
| Finished | Aug 17 08:11:42 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-8295815d-3c08-49e5-9765-2c537fd0f20b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974762696 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2974762696 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2843483066 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 13649999774 ps |
| CPU time | 3016.06 seconds |
| Started | Aug 17 07:13:40 PM PDT 24 |
| Finished | Aug 17 08:03:57 PM PDT 24 |
| Peak memory | 611424 kb |
| Host | smart-11955ad2-ec10-411b-9b3b-3de62e2d805f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=100_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_prod_key_0,otp_img_sigverify_always_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOS ITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843483066 -assert nopostproc +UVM_TESTNAME=chip_base _test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2843483066 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1486574705 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 10998180482 ps |
| CPU time | 3285.64 seconds |
| Started | Aug 17 07:15:41 PM PDT 24 |
| Finished | Aug 17 08:10:27 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-4ba1bd68-6a54-4048-b09e-10a9b0c62365 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=410_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_b_corrupted:1: ot_flash_binary:signed:fake_ecdsa_test_key_0,otp_img_sigverify_always_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486574705 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_sigverify_always_a_bad_b_bad_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1486574705 |
| Directory | /workspace/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_smoke.2045883272 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 14779689120 ps |
| CPU time | 4059.65 seconds |
| Started | Aug 17 07:18:00 PM PDT 24 |
| Finished | Aug 17 08:25:40 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-e2c50b53-1079-478d-98aa-163fbf05e33c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=2045883272 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_smoke.2045883272 |
| Directory | /workspace/0.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/0.rom_e2e_static_critical.423971642 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 16874771012 ps |
| CPU time | 4382.46 seconds |
| Started | Aug 17 07:14:33 PM PDT 24 |
| Finished | Aug 17 08:27:36 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-a4fde34b-c683-49a1-bcf4-a7a47cef2eb0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423971642 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_e2e_static_critical.423971642 |
| Directory | /workspace/0.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/0.rom_keymgr_functest.2993147171 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 4446326540 ps |
| CPU time | 606.55 seconds |
| Started | Aug 17 07:13:02 PM PDT 24 |
| Finished | Aug 17 07:23:09 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-53a94550-3d52-4ea0-a940-3a96aef93ef9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993147171 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 0.rom_keymgr_functest.2993147171 |
| Directory | /workspace/0.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/0.rom_raw_unlock.493172787 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 6021561286 ps |
| CPU time | 313.42 seconds |
| Started | Aug 17 07:08:37 PM PDT 24 |
| Finished | Aug 17 07:13:50 PM PDT 24 |
| Peak memory | 619100 kb |
| Host | smart-3519b7f6-3277-4fc9-a355-2a0dd506ebc8 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=493172787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rom_raw_unlock.493172787 |
| Directory | /workspace/0.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/0.rom_volatile_raw_unlock.1342949938 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 2444209094 ps |
| CPU time | 115.3 seconds |
| Started | Aug 17 07:14:00 PM PDT 24 |
| Finished | Aug 17 07:15:55 PM PDT 24 |
| Peak memory | 617164 kb |
| Host | smart-ea94048a-938a-4ecb-9dd8-1bd71b7936a6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342949938 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 0.rom_volatile_raw_unlock.1342949938 |
| Directory | /workspace/0.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_csr_rw.3071718358 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 10085219800 ps |
| CPU time | 1353.42 seconds |
| Started | Aug 17 07:07:38 PM PDT 24 |
| Finished | Aug 17 07:30:11 PM PDT 24 |
| Peak memory | 608500 kb |
| Host | smart-ce17116c-30b1-425d-8c4d-ae9784de3183 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071718358 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.c hip_jtag_csr_rw.3071718358 |
| Directory | /workspace/1.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/1.chip_jtag_mem_access.4057147151 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 13931706425 ps |
| CPU time | 1365.32 seconds |
| Started | Aug 17 07:07:24 PM PDT 24 |
| Finished | Aug 17 07:30:10 PM PDT 24 |
| Peak memory | 608568 kb |
| Host | smart-f57a7482-9f65-49fd-bfd0-abc4a1aff4eb |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057147151 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_ mem_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_jtag_mem_access.4 057147151 |
| Directory | /workspace/1.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.2682410623 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 4515879508 ps |
| CPU time | 320.97 seconds |
| Started | Aug 17 07:19:37 PM PDT 24 |
| Finished | Aug 17 07:24:58 PM PDT 24 |
| Peak memory | 621128 kb |
| Host | smart-a9b087a9-085c-4b55-91b7-066bc61ea04e |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 682410623 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_rv_dm_ndm_reset_req.2682410623 |
| Directory | /workspace/1.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sival_flash_info_access.637758522 |
| Short name | T1116 |
| Test name | |
| Test status | |
| Simulation time | 3321807412 ps |
| CPU time | 281.35 seconds |
| Started | Aug 17 07:12:44 PM PDT 24 |
| Finished | Aug 17 07:17:25 PM PDT 24 |
| Peak memory | 610464 kb |
| Host | smart-2bd0b4f1-bda2-4c94-b49f-bb486c844780 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=637758522 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sival_flash_info_access.637758522 |
| Directory | /workspace/1.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2747765438 |
| Short name | T1146 |
| Test name | |
| Test status | |
| Simulation time | 19451512332 ps |
| CPU time | 529.93 seconds |
| Started | Aug 17 07:10:35 PM PDT 24 |
| Finished | Aug 17 07:19:25 PM PDT 24 |
| Peak memory | 619448 kb |
| Host | smart-f757f57e-025c-4ac6-be5c-1d87a425717f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=2747765438 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2747765438 |
| Directory | /workspace/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc.4215315496 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2666874378 ps |
| CPU time | 262.51 seconds |
| Started | Aug 17 07:12:53 PM PDT 24 |
| Finished | Aug 17 07:17:16 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-b01109c6-8e43-450e-9253-6177262fe01f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215315496 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc.4215315496 |
| Directory | /workspace/1.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.1689316025 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 2499130275 ps |
| CPU time | 270.26 seconds |
| Started | Aug 17 07:12:02 PM PDT 24 |
| Finished | Aug 17 07:16:32 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-867303d6-6f58-461b-aac6-8848733cf6d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1689 316025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work space/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en.1689316025 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3655709018 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 2644904563 ps |
| CPU time | 211.12 seconds |
| Started | Aug 17 07:16:49 PM PDT 24 |
| Finished | Aug 17 07:20:20 PM PDT 24 |
| Peak memory | 610416 kb |
| Host | smart-5acef9cc-bcb9-44af-bb5c-04658ee667c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655709018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_enc_jitter_en_reduced_freq.3655709018 |
| Directory | /workspace/1.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_entropy.1243909275 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 3081236090 ps |
| CPU time | 183.66 seconds |
| Started | Aug 17 07:15:20 PM PDT 24 |
| Finished | Aug 17 07:18:24 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-4096846b-9b89-4e69-bfee-640e666c7832 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243909275 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_entropy.1243909275 |
| Directory | /workspace/1.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_idle.1163886018 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 3073592840 ps |
| CPU time | 259.21 seconds |
| Started | Aug 17 07:13:42 PM PDT 24 |
| Finished | Aug 17 07:18:01 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-02c08638-069e-44e3-ac66-227cf947b9f6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163886018 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_idle.1163886018 |
| Directory | /workspace/1.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_masking_off.892529345 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2734506078 ps |
| CPU time | 337.22 seconds |
| Started | Aug 17 07:15:34 PM PDT 24 |
| Finished | Aug 17 07:21:12 PM PDT 24 |
| Peak memory | 609696 kb |
| Host | smart-3a191e31-0f59-4395-a357-77c79bc484a3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=892529345 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_masking_off.892529345 |
| Directory | /workspace/1.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aes_smoketest.1050697813 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 2916339760 ps |
| CPU time | 358.3 seconds |
| Started | Aug 17 07:18:37 PM PDT 24 |
| Finished | Aug 17 07:24:36 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-83931c75-cca2-4293-b690-f0f43dc2f8b9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050697813 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aes_smoketest.1050697813 |
| Directory | /workspace/1.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_escalation.2802329667 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 5006369196 ps |
| CPU time | 722.48 seconds |
| Started | Aug 17 07:13:33 PM PDT 24 |
| Finished | Aug 17 07:25:36 PM PDT 24 |
| Peak memory | 620256 kb |
| Host | smart-aa608206-3a24-4a66-9b6a-3f2d1d9997ab |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2802329667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_escalation.2802329667 |
| Directory | /workspace/1.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3840235089 |
| Short name | T1204 |
| Test name | |
| Test status | |
| Simulation time | 6695345138 ps |
| CPU time | 1279.07 seconds |
| Started | Aug 17 07:12:52 PM PDT 24 |
| Finished | Aug 17 07:34:11 PM PDT 24 |
| Peak memory | 610804 kb |
| Host | smart-fca21474-89ab-4e69-a845-ec860f82250b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=3840235089 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+ fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_clkoff.3840235089 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.891922414 |
| Short name | T1289 |
| Test name | |
| Test status | |
| Simulation time | 7163553674 ps |
| CPU time | 1806.64 seconds |
| Started | Aug 17 07:12:44 PM PDT 24 |
| Finished | Aug 17 07:42:51 PM PDT 24 |
| Peak memory | 610492 kb |
| Host | smart-f852d930-6d03-4961-b099-7bf5f799c8d8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891922414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_reset_toggle.891922414 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3509196405 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 10098152132 ps |
| CPU time | 1288.9 seconds |
| Started | Aug 17 07:15:46 PM PDT 24 |
| Finished | Aug 17 07:37:15 PM PDT 24 |
| Peak memory | 611296 kb |
| Host | smart-6c1258da-9174-43b9-85a8-61659b94399a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3509196405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_lpg_sleep_mode_pings.3509196405 |
| Directory | /workspace/1.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_ok.1308030274 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 7962110712 ps |
| CPU time | 1407.64 seconds |
| Started | Aug 17 07:12:52 PM PDT 24 |
| Finished | Aug 17 07:36:20 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-61e89fdb-d9cf-4067-8cd5-1712bb6377c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=1308030274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_ok.1308030274 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.574721203 |
| Short name | T1119 |
| Test name | |
| Test status | |
| Simulation time | 3614918380 ps |
| CPU time | 336.29 seconds |
| Started | Aug 17 07:11:11 PM PDT 24 |
| Finished | Aug 17 07:16:47 PM PDT 24 |
| Peak memory | 610192 kb |
| Host | smart-e7005ff7-b614-45dd-940c-c629e17ec9d2 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=574721203 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_ping_timeout.574721203 |
| Directory | /workspace/1.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1901445689 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 254455076238 ps |
| CPU time | 12651.8 seconds |
| Started | Aug 17 07:17:04 PM PDT 24 |
| Finished | Aug 17 10:47:57 PM PDT 24 |
| Peak memory | 611088 kb |
| Host | smart-4fc3aaea-9342-4972-aa68-0acbefdb5347 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1901445689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1901445689 |
| Directory | /workspace/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_irq.2260710157 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 4498136872 ps |
| CPU time | 410.97 seconds |
| Started | Aug 17 07:11:21 PM PDT 24 |
| Finished | Aug 17 07:18:12 PM PDT 24 |
| Peak memory | 609656 kb |
| Host | smart-2884eb20-2f92-4b99-945d-cce4f19a602b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260710157 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_irq.2260710157 |
| Directory | /workspace/1.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1222963677 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 7300543128 ps |
| CPU time | 494.37 seconds |
| Started | Aug 17 07:11:50 PM PDT 24 |
| Finished | Aug 17 07:20:05 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-5f054924-3342-413b-a798-a0bfb8e665d5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=1222963677 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1222963677 |
| Directory | /workspace/1.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2099725229 |
| Short name | T1181 |
| Test name | |
| Test status | |
| Simulation time | 2594388090 ps |
| CPU time | 235.97 seconds |
| Started | Aug 17 07:18:41 PM PDT 24 |
| Finished | Aug 17 07:22:38 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-cd7f9a07-65ec-4a91-b2c7-4fc3048a47d1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2099725229 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_aon_timer_smoketest.2099725229 |
| Directory | /workspace/1.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1936578928 |
| Short name | T1132 |
| Test name | |
| Test status | |
| Simulation time | 8557439072 ps |
| CPU time | 695.67 seconds |
| Started | Aug 17 07:14:29 PM PDT 24 |
| Finished | Aug 17 07:26:07 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-7f4433e7-4c1d-4781-bfdb-a6807f62f7fe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1936578928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_bite_reset.1936578928 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.656094058 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 6178414920 ps |
| CPU time | 647.92 seconds |
| Started | Aug 17 07:11:14 PM PDT 24 |
| Finished | Aug 17 07:22:02 PM PDT 24 |
| Peak memory | 611252 kb |
| Host | smart-a437508c-a790-4116-96ed-9ed22d6b1345 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =656094058 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_aon_timer_wdog_lc_escalate.656094058 |
| Directory | /workspace/1.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_outputs.150219169 |
| Short name | T1202 |
| Test name | |
| Test status | |
| Simulation time | 6651144168 ps |
| CPU time | 1061.58 seconds |
| Started | Aug 17 07:17:43 PM PDT 24 |
| Finished | Aug 17 07:35:25 PM PDT 24 |
| Peak memory | 617904 kb |
| Host | smart-9a95dea4-8511-46b8-bddd-2d2a5ede43e2 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150219169 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_outputs.150219169 |
| Directory | /workspace/1.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_ast_clk_rst_inputs.363002139 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 22768329195 ps |
| CPU time | 3608.45 seconds |
| Started | Aug 17 07:17:59 PM PDT 24 |
| Finished | Aug 17 08:18:09 PM PDT 24 |
| Peak memory | 611344 kb |
| Host | smart-aef36491-8a6f-48ec-9dd8-8833472bf313 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363002139 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_ast_clk_rst_inputs.363002139 |
| Directory | /workspace/1.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.642551910 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 5155983213 ps |
| CPU time | 495.7 seconds |
| Started | Aug 17 07:14:28 PM PDT 24 |
| Finished | Aug 17 07:22:44 PM PDT 24 |
| Peak memory | 622404 kb |
| Host | smart-b7ec12b5-a9ee-416b-a986-7dc1945a3af1 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=642551910 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_external_clk_src_for_lc.642551910 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3071253943 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 3976323496 ps |
| CPU time | 593.47 seconds |
| Started | Aug 17 07:15:02 PM PDT 24 |
| Finished | Aug 17 07:24:56 PM PDT 24 |
| Peak memory | 614796 kb |
| Host | smart-359144b7-a3c2-4c50-96e0-85fca8a9e340 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3071253943 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_dev.3071253943 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3292652023 |
| Short name | T1330 |
| Test name | |
| Test status | |
| Simulation time | 3407139844 ps |
| CPU time | 594.3 seconds |
| Started | Aug 17 07:15:43 PM PDT 24 |
| Finished | Aug 17 07:25:38 PM PDT 24 |
| Peak memory | 614936 kb |
| Host | smart-2b028303-4e08-4e33-9eda-4daace72a0c8 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3292652023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_fast_rma.3292652023 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.851395232 |
| Short name | T1154 |
| Test name | |
| Test status | |
| Simulation time | 3566796804 ps |
| CPU time | 822.85 seconds |
| Started | Aug 17 07:14:49 PM PDT 24 |
| Finished | Aug 17 07:28:32 PM PDT 24 |
| Peak memory | 614712 kb |
| Host | smart-13d4efa9-b566-40c0-b3be-9f5345950ea0 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851395232 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1. chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.851395232 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2155337920 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 5375134500 ps |
| CPU time | 694.86 seconds |
| Started | Aug 17 07:16:04 PM PDT 24 |
| Finished | Aug 17 07:27:39 PM PDT 24 |
| Peak memory | 614644 kb |
| Host | smart-e5c51540-fdaf-4e15-b429-2596c0c73f4b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155337920 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_dev.2155337920 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2551318626 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3990095560 ps |
| CPU time | 633.12 seconds |
| Started | Aug 17 07:14:39 PM PDT 24 |
| Finished | Aug 17 07:25:12 PM PDT 24 |
| Peak memory | 613864 kb |
| Host | smart-0d4d296f-1d8e-4bec-9460-a193c5cbc325 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551318626 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.2551318626 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2409621159 |
| Short name | T1297 |
| Test name | |
| Test status | |
| Simulation time | 4711640960 ps |
| CPU time | 529.92 seconds |
| Started | Aug 17 07:16:51 PM PDT 24 |
| Finished | Aug 17 07:25:41 PM PDT 24 |
| Peak memory | 614896 kb |
| Host | smart-0354ab14-3189-4e0b-9efe-b40492982c51 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409621159 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2409621159 |
| Directory | /workspace/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter.2073092498 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 3279825286 ps |
| CPU time | 253.05 seconds |
| Started | Aug 17 07:16:35 PM PDT 24 |
| Finished | Aug 17 07:20:49 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-a17a16d1-9370-421c-96fc-779dee59638d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073092498 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_clkmgr_jitter.2073092498 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.743692634 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 3749102156 ps |
| CPU time | 526.36 seconds |
| Started | Aug 17 07:14:42 PM PDT 24 |
| Finished | Aug 17 07:23:29 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-2069bd20-4556-4f83-8366-5e63c0eda307 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=743692634 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_frequency.743692634 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2173445948 |
| Short name | T1114 |
| Test name | |
| Test status | |
| Simulation time | 3405337977 ps |
| CPU time | 250.72 seconds |
| Started | Aug 17 07:17:17 PM PDT 24 |
| Finished | Aug 17 07:21:28 PM PDT 24 |
| Peak memory | 609312 kb |
| Host | smart-baca4701-19ab-4bb1-bbd1-3c467440ec46 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173445948 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_jitter_reduced_freq.2173445948 |
| Directory | /workspace/1.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1985636264 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 6025580596 ps |
| CPU time | 503.91 seconds |
| Started | Aug 17 07:13:05 PM PDT 24 |
| Finished | Aug 17 07:21:30 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-f6d7bbff-f859-412d-bf54-55f487012f8e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985636264 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_clkmgr_off_aes_trans.1985636264 |
| Directory | /workspace/1.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1101121543 |
| Short name | T1189 |
| Test name | |
| Test status | |
| Simulation time | 5461714254 ps |
| CPU time | 582.91 seconds |
| Started | Aug 17 07:14:35 PM PDT 24 |
| Finished | Aug 17 07:24:18 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-dd3e4702-54f0-4411-a01f-6d1169f098dc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101121543 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_hmac_trans.1101121543 |
| Directory | /workspace/1.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4043141129 |
| Short name | T1296 |
| Test name | |
| Test status | |
| Simulation time | 4656442568 ps |
| CPU time | 373.32 seconds |
| Started | Aug 17 07:13:11 PM PDT 24 |
| Finished | Aug 17 07:19:25 PM PDT 24 |
| Peak memory | 611140 kb |
| Host | smart-d9b7f630-7a6e-43e8-8646-e224bb04ebe0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043141129 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_kmac_trans.4043141129 |
| Directory | /workspace/1.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.4290863130 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 4136316150 ps |
| CPU time | 413.12 seconds |
| Started | Aug 17 07:14:16 PM PDT 24 |
| Finished | Aug 17 07:21:09 PM PDT 24 |
| Peak memory | 609920 kb |
| Host | smart-319bcabb-cc2a-4071-a119-d884d3a3aa45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4290863130 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_clkmgr_off_otbn_trans.4290863130 |
| Directory | /workspace/1.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1844789114 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 11474835500 ps |
| CPU time | 1450.23 seconds |
| Started | Aug 17 07:14:32 PM PDT 24 |
| Finished | Aug 17 07:38:42 PM PDT 24 |
| Peak memory | 611192 kb |
| Host | smart-2eb11446-ae09-4ecc-be6a-331ee121cdad |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844789114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_off_peri.1844789114 |
| Directory | /workspace/1.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.414748636 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 3339058635 ps |
| CPU time | 407.16 seconds |
| Started | Aug 17 07:16:26 PM PDT 24 |
| Finished | Aug 17 07:23:14 PM PDT 24 |
| Peak memory | 610588 kb |
| Host | smart-7ce143a7-077a-4122-97e2-19fa6fc15632 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=414748636 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_reset_frequency.414748636 |
| Directory | /workspace/1.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.4121571521 |
| Short name | T1128 |
| Test name | |
| Test status | |
| Simulation time | 4582115776 ps |
| CPU time | 776.68 seconds |
| Started | Aug 17 07:15:04 PM PDT 24 |
| Finished | Aug 17 07:28:00 PM PDT 24 |
| Peak memory | 610876 kb |
| Host | smart-6af7b54c-4332-4bbf-b45d-450776ce4baa |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121571521 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_clkmgr_sleep_frequency.4121571521 |
| Directory | /workspace/1.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1346653401 |
| Short name | T1186 |
| Test name | |
| Test status | |
| Simulation time | 3650541058 ps |
| CPU time | 308.52 seconds |
| Started | Aug 17 07:18:07 PM PDT 24 |
| Finished | Aug 17 07:23:15 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-a8ffa3ca-fa40-4497-8521-de3a828dd088 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346653401 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 1.chip_sw_clkmgr_smoketest.1346653401 |
| Directory | /workspace/1.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1470582044 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 3813470416 ps |
| CPU time | 509.44 seconds |
| Started | Aug 17 07:12:40 PM PDT 24 |
| Finished | Aug 17 07:21:10 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-a3e83091-fb42-4f65-a225-f99029115e86 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14705 82044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_fuse_en_sw_app_read_test.1470582044 |
| Directory | /workspace/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_kat_test.2857032609 |
| Short name | T1140 |
| Test name | |
| Test status | |
| Simulation time | 2846401000 ps |
| CPU time | 242.6 seconds |
| Started | Aug 17 07:13:10 PM PDT 24 |
| Finished | Aug 17 07:17:13 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-85da074c-01c2-492c-87b0-e95683586081 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857032609 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csrng_kat_test.2857032609 |
| Directory | /workspace/1.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_lc_hw_debug_en_test.3731735025 |
| Short name | T1149 |
| Test name | |
| Test status | |
| Simulation time | 6790113932 ps |
| CPU time | 605.86 seconds |
| Started | Aug 17 07:16:38 PM PDT 24 |
| Finished | Aug 17 07:26:44 PM PDT 24 |
| Peak memory | 611280 kb |
| Host | smart-ac003b13-3e1c-4c27-a523-752cfa1f849e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731735025 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_csr ng_lc_hw_debug_en_test.3731735025 |
| Directory | /workspace/1.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_csrng_smoketest.2605205794 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 2196429024 ps |
| CPU time | 217.2 seconds |
| Started | Aug 17 07:18:09 PM PDT 24 |
| Finished | Aug 17 07:21:47 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-6d1ffda9-3e60-4b1a-9c19-f729268cf9d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605205794 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_csrng_smoketest.2605205794 |
| Directory | /workspace/1.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_auto_mode.4117242806 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 4774955864 ps |
| CPU time | 1094.23 seconds |
| Started | Aug 17 07:18:03 PM PDT 24 |
| Finished | Aug 17 07:36:18 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-f09890a6-e692-400e-aece-9d2deb60e2f4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117242806 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ auto_mode.4117242806 |
| Directory | /workspace/1.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_boot_mode.3940456213 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 3118898256 ps |
| CPU time | 605.68 seconds |
| Started | Aug 17 07:12:48 PM PDT 24 |
| Finished | Aug 17 07:22:54 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-551af02b-9e2d-4e24-9e66-3f2ee1f69b68 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940456213 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_ boot_mode.3940456213 |
| Directory | /workspace/1.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3111463552 |
| Short name | T1226 |
| Test name | |
| Test status | |
| Simulation time | 6237228290 ps |
| CPU time | 965.77 seconds |
| Started | Aug 17 07:12:01 PM PDT 24 |
| Finished | Aug 17 07:28:07 PM PDT 24 |
| Peak memory | 610532 kb |
| Host | smart-bae77ec2-1075-4a2a-9950-b82441b4a7b3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=3111463552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs.3111463552 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3154289501 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 5181268321 ps |
| CPU time | 1010.63 seconds |
| Started | Aug 17 07:14:01 PM PDT 24 |
| Finished | Aug 17 07:30:52 PM PDT 24 |
| Peak memory | 611268 kb |
| Host | smart-46ece798-e71d-42d3-b924-352d16f15c12 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154289501 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_entropy_reqs_jitter.3154289501 |
| Directory | /workspace/1.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_kat.4103952017 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 3784609364 ps |
| CPU time | 632.2 seconds |
| Started | Aug 17 07:14:54 PM PDT 24 |
| Finished | Aug 17 07:25:28 PM PDT 24 |
| Peak memory | 617140 kb |
| Host | smart-175c9185-6de2-4fe7-85b8-8e365d35a7dd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103952017 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_edn_kat.4103952017 |
| Directory | /workspace/1.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/1.chip_sw_edn_sw_mode.1585793564 |
| Short name | T1144 |
| Test name | |
| Test status | |
| Simulation time | 8780850200 ps |
| CPU time | 2002.82 seconds |
| Started | Aug 17 07:13:42 PM PDT 24 |
| Finished | Aug 17 07:47:05 PM PDT 24 |
| Peak memory | 609680 kb |
| Host | smart-20b7d767-8023-4c73-9741-130600a0a059 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1585793564 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_edn_sw_mode.1585793564 |
| Directory | /workspace/1.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.2584495407 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 3603708444 ps |
| CPU time | 302.5 seconds |
| Started | Aug 17 07:16:08 PM PDT 24 |
| Finished | Aug 17 07:21:11 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-68333e3a-b96b-4593-8f7a-6a2fa2246495 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25 84495407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_ast_rng_req.2584495407 |
| Directory | /workspace/1.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_csrng.113080407 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 5903664788 ps |
| CPU time | 1334.6 seconds |
| Started | Aug 17 07:13:59 PM PDT 24 |
| Finished | Aug 17 07:36:14 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-26471608-091f-4980-ba79-38217b19da5d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=113080407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm li ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_csrng.113080407 |
| Directory | /workspace/1.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3624442106 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 3299826100 ps |
| CPU time | 203.12 seconds |
| Started | Aug 17 07:14:40 PM PDT 24 |
| Finished | Aug 17 07:18:04 PM PDT 24 |
| Peak memory | 609516 kb |
| Host | smart-a891a4e7-fdb7-4fe7-a4cc-6a4b8bddf793 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624442106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_kat_test.3624442106 |
| Directory | /workspace/1.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1044443170 |
| Short name | T1298 |
| Test name | |
| Test status | |
| Simulation time | 3249562720 ps |
| CPU time | 539.18 seconds |
| Started | Aug 17 07:19:19 PM PDT 24 |
| Finished | Aug 17 07:28:18 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-719b16b9-b559-4bff-8c76-46e4297423dd |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1044443170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_entropy_src_smoketest.1044443170 |
| Directory | /workspace/1.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_concurrency.1981927589 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 2625197476 ps |
| CPU time | 223.76 seconds |
| Started | Aug 17 07:10:05 PM PDT 24 |
| Finished | Aug 17 07:13:49 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-2a03bdf9-4002-401d-bb68-6723507fcec5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981927589 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_example_concurrency.1981927589 |
| Directory | /workspace/1.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_flash.3129322333 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 2352248360 ps |
| CPU time | 148.53 seconds |
| Started | Aug 17 07:09:44 PM PDT 24 |
| Finished | Aug 17 07:12:13 PM PDT 24 |
| Peak memory | 609352 kb |
| Host | smart-cbc48a0a-1922-41c9-8c24-353ae23dbc75 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129322333 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_flash.3129322333 |
| Directory | /workspace/1.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_manufacturer.4146118600 |
| Short name | T1288 |
| Test name | |
| Test status | |
| Simulation time | 2749221624 ps |
| CPU time | 315.63 seconds |
| Started | Aug 17 07:11:18 PM PDT 24 |
| Finished | Aug 17 07:16:33 PM PDT 24 |
| Peak memory | 609308 kb |
| Host | smart-4f8fa64f-1cf3-4d63-85e8-7b7a536dcb4f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146118600 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_manufacturer.4146118600 |
| Directory | /workspace/1.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/1.chip_sw_example_rom.1723209843 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 1787613448 ps |
| CPU time | 110.61 seconds |
| Started | Aug 17 07:07:36 PM PDT 24 |
| Finished | Aug 17 07:09:27 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-2dd139ae-cc69-4289-bb55-8177ca458705 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723209843 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_example_rom.1723209843 |
| Directory | /workspace/1.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.4281221064 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 58661451960 ps |
| CPU time | 10366.8 seconds |
| Started | Aug 17 07:09:58 PM PDT 24 |
| Finished | Aug 17 10:02:46 PM PDT 24 |
| Peak memory | 625452 kb |
| Host | smart-c8054e08-505a-47e5-833b-22bd993ce8b0 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=4281221064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_exit_test_unlocked_bootstrap.4281221064 |
| Directory | /workspace/1.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_crash_alert.10319941 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 4243605838 ps |
| CPU time | 575.8 seconds |
| Started | Aug 17 07:16:49 PM PDT 24 |
| Finished | Aug 17 07:26:25 PM PDT 24 |
| Peak memory | 611684 kb |
| Host | smart-939471d4-3257-43f5-8e0e-126995983c70 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=10319941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -c m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_crash_alert.10319941 |
| Directory | /workspace/1.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access.1299370807 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 6438080696 ps |
| CPU time | 1182.77 seconds |
| Started | Aug 17 07:11:12 PM PDT 24 |
| Finished | Aug 17 07:30:55 PM PDT 24 |
| Peak memory | 609712 kb |
| Host | smart-661fd1e9-486e-420f-954a-d602ff11dc2c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299370807 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_flash_ctrl_access.1299370807 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1513648914 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 5715548114 ps |
| CPU time | 1189.5 seconds |
| Started | Aug 17 07:16:09 PM PDT 24 |
| Finished | Aug 17 07:35:59 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-985294c9-b80e-4453-be05-1d9bf48d2887 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513648914 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en.1513648914 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3635495688 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 7083978625 ps |
| CPU time | 1165.57 seconds |
| Started | Aug 17 07:16:50 PM PDT 24 |
| Finished | Aug 17 07:36:16 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-cc96ad7d-dc80-4e00-86d3-ab4791f110a0 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635495688 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3635495688 |
| Directory | /workspace/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.91390380 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 6243444456 ps |
| CPU time | 1078.1 seconds |
| Started | Aug 17 07:10:58 PM PDT 24 |
| Finished | Aug 17 07:28:57 PM PDT 24 |
| Peak memory | 609716 kb |
| Host | smart-bc4bc335-7a20-4374-9f97-3958179efa86 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91390380 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_flash_ctrl_clock_freqs.91390380 |
| Directory | /workspace/1.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1261998297 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 3188664894 ps |
| CPU time | 365.59 seconds |
| Started | Aug 17 07:12:09 PM PDT 24 |
| Finished | Aug 17 07:18:15 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-229e5279-7317-4d1a-9d8e-db2c7cbca401 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261998297 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_idle_low_power.1261998297 |
| Directory | /workspace/1.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.1810234960 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 5856997896 ps |
| CPU time | 1187.79 seconds |
| Started | Aug 17 07:16:26 PM PDT 24 |
| Finished | Aug 17 07:36:14 PM PDT 24 |
| Peak memory | 609812 kb |
| Host | smart-b9bd2618-576f-4c5e-acaa-7cfe75aa0b62 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1810234960 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_mem_protection.1810234960 |
| Directory | /workspace/1.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4044016452 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 4595022175 ps |
| CPU time | 666.34 seconds |
| Started | Aug 17 07:17:07 PM PDT 24 |
| Finished | Aug 17 07:28:14 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-b0b65fd3-492c-4d13-851c-2f06ed45a47e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=4044016452 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4044016452 |
| Directory | /workspace/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_ctrl_write_clear.282533933 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 3452584498 ps |
| CPU time | 307.93 seconds |
| Started | Aug 17 07:14:34 PM PDT 24 |
| Finished | Aug 17 07:19:42 PM PDT 24 |
| Peak memory | 609416 kb |
| Host | smart-247df46b-21ae-4c30-beca-59eedb1c968f |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825339 33 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_ctrl_write_clear.282533933 |
| Directory | /workspace/1.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_init.3728174490 |
| Short name | T1267 |
| Test name | |
| Test status | |
| Simulation time | 26284803000 ps |
| CPU time | 2292.45 seconds |
| Started | Aug 17 07:11:16 PM PDT 24 |
| Finished | Aug 17 07:49:29 PM PDT 24 |
| Peak memory | 613812 kb |
| Host | smart-993cf538-a495-44e4-8f6c-3ab03b862dcf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728174490 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_init.3728174490 |
| Directory | /workspace/1.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.923820435 |
| Short name | T1151 |
| Test name | |
| Test status | |
| Simulation time | 2454084152 ps |
| CPU time | 211.15 seconds |
| Started | Aug 17 07:20:39 PM PDT 24 |
| Finished | Aug 17 07:24:10 PM PDT 24 |
| Peak memory | 610116 kb |
| Host | smart-5528bcf0-22b1-4c3a-b143-c9fef8f404b2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=923820435 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+co nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_flash_scrambling_smoketest.923820435 |
| Directory | /workspace/1.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_gpio_smoketest.1026566767 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 2866534250 ps |
| CPU time | 231.95 seconds |
| Started | Aug 17 07:19:24 PM PDT 24 |
| Finished | Aug 17 07:23:16 PM PDT 24 |
| Peak memory | 609640 kb |
| Host | smart-54348ad9-942c-4679-8ff7-2151b0009d56 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026566767 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 1.chip_sw_gpio_smoketest.1026566767 |
| Directory | /workspace/1.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc.2376361508 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 3156091416 ps |
| CPU time | 255.12 seconds |
| Started | Aug 17 07:14:02 PM PDT 24 |
| Finished | Aug 17 07:18:18 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-7d52c916-5c27-4e3b-b015-9ba42d42bbe1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376361508 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc.2376361508 |
| Directory | /workspace/1.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2016870659 |
| Short name | T1216 |
| Test name | |
| Test status | |
| Simulation time | 3014795662 ps |
| CPU time | 238.65 seconds |
| Started | Aug 17 07:13:54 PM PDT 24 |
| Finished | Aug 17 07:17:53 PM PDT 24 |
| Peak memory | 609424 kb |
| Host | smart-3b018688-7ae6-424e-9b2d-cae3f0dcea15 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2016870659 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_hmac_enc_idle.2016870659 |
| Directory | /workspace/1.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.722093128 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 2746152496 ps |
| CPU time | 303.19 seconds |
| Started | Aug 17 07:11:34 PM PDT 24 |
| Finished | Aug 17 07:16:38 PM PDT 24 |
| Peak memory | 609476 kb |
| Host | smart-acdab9ad-0534-4042-9413-7b1cf87f1018 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722093128 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en.722093128 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2906647914 |
| Short name | T1228 |
| Test name | |
| Test status | |
| Simulation time | 2792617297 ps |
| CPU time | 210.08 seconds |
| Started | Aug 17 07:17:45 PM PDT 24 |
| Finished | Aug 17 07:21:15 PM PDT 24 |
| Peak memory | 609456 kb |
| Host | smart-3a77b532-9bdb-478b-89c2-89eaee1d4e71 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906647914 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_enc_jitter_en_reduced_freq.2906647914 |
| Directory | /workspace/1.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_multistream.863535916 |
| Short name | T1268 |
| Test name | |
| Test status | |
| Simulation time | 7744070996 ps |
| CPU time | 2209.19 seconds |
| Started | Aug 17 07:13:40 PM PDT 24 |
| Finished | Aug 17 07:50:30 PM PDT 24 |
| Peak memory | 609824 kb |
| Host | smart-91700377-351e-4a92-b818-40f4cc279002 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863535916 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_hmac_multistream.863535916 |
| Directory | /workspace/1.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_oneshot.1328446858 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 2758654560 ps |
| CPU time | 286.55 seconds |
| Started | Aug 17 07:13:43 PM PDT 24 |
| Finished | Aug 17 07:18:30 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-e4ff156d-d895-4845-ab7f-24911e375e50 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328446858 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_hmac_oneshot.1328446858 |
| Directory | /workspace/1.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/1.chip_sw_hmac_smoketest.3335132513 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 2485176126 ps |
| CPU time | 323.73 seconds |
| Started | Aug 17 07:17:50 PM PDT 24 |
| Finished | Aug 17 07:23:14 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-3d99264a-6b6e-4eb5-a94b-9ef7acca7e14 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335132513 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_hmac_smoketest.3335132513 |
| Directory | /workspace/1.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.596598447 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 3732974010 ps |
| CPU time | 637.03 seconds |
| Started | Aug 17 07:16:12 PM PDT 24 |
| Finished | Aug 17 07:26:50 PM PDT 24 |
| Peak memory | 611476 kb |
| Host | smart-186aa8b4-335b-4f3c-8d9a-e9a67899de31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=i2c_device_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=596598447 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_device_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_i2c_device_tx_rx.596598447 |
| Directory | /workspace/1.chip_sw_i2c_device_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1432029753 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 5748079354 ps |
| CPU time | 939.59 seconds |
| Started | Aug 17 07:09:05 PM PDT 24 |
| Finished | Aug 17 07:24:45 PM PDT 24 |
| Peak memory | 610300 kb |
| Host | smart-40c96776-220e-4d46-901b-2091d7e81961 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432029753 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx.1432029753 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3143019809 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 5211010404 ps |
| CPU time | 949.46 seconds |
| Started | Aug 17 07:15:33 PM PDT 24 |
| Finished | Aug 17 07:31:24 PM PDT 24 |
| Peak memory | 611000 kb |
| Host | smart-277a765b-dddc-485c-845a-ed017b448afd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143019809 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx1.3143019809 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2269144177 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 5427266120 ps |
| CPU time | 967.77 seconds |
| Started | Aug 17 07:14:08 PM PDT 24 |
| Finished | Aug 17 07:30:19 PM PDT 24 |
| Peak memory | 610260 kb |
| Host | smart-de6cef01-47f3-4f01-ad97-12a1dc98d352 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269144177 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_i2c_host_tx_rx_idx2.2269144177 |
| Directory | /workspace/1.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation.820568283 |
| Short name | T1130 |
| Test name | |
| Test status | |
| Simulation time | 6744558494 ps |
| CPU time | 1382.96 seconds |
| Started | Aug 17 07:13:22 PM PDT 24 |
| Finished | Aug 17 07:36:25 PM PDT 24 |
| Peak memory | 617576 kb |
| Host | smart-a8479950-20f6-42e3-9c3f-44e7d5159073 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8205 68283 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation.820568283 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.1483284660 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 7916436975 ps |
| CPU time | 1731.2 seconds |
| Started | Aug 17 07:15:30 PM PDT 24 |
| Finished | Aug 17 07:44:21 PM PDT 24 |
| Peak memory | 617264 kb |
| Host | smart-cdf67359-16ae-4314-8c72-7f91cf80a905 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1483284660 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en.1483284660 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.86339426 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 10261700542 ps |
| CPU time | 1571.91 seconds |
| Started | Aug 17 07:17:35 PM PDT 24 |
| Finished | Aug 17 07:43:47 PM PDT 24 |
| Peak memory | 617328 kb |
| Host | smart-a005b171-a043-4d04-98f1-6c8ee23f6b6e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=86339426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_jitter_en_r educed_freq.86339426 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3351897529 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 10178797504 ps |
| CPU time | 2085.53 seconds |
| Started | Aug 17 07:13:50 PM PDT 24 |
| Finished | Aug 17 07:48:37 PM PDT 24 |
| Peak memory | 617228 kb |
| Host | smart-3e49229e-d1c4-4ec5-b321-21c38eb3029a |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3351897529 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+ tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_key_derivation_prod.3351897529 |
| Directory | /workspace/1.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2477542039 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 12881105212 ps |
| CPU time | 2546.75 seconds |
| Started | Aug 17 07:14:01 PM PDT 24 |
| Finished | Aug 17 07:56:28 PM PDT 24 |
| Peak memory | 610760 kb |
| Host | smart-1b6cbc2a-d454-4684-9b7f-8654eed3f680 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24775 42039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_kmac.2477542039 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.3100559166 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 16886037800 ps |
| CPU time | 3985.88 seconds |
| Started | Aug 17 07:12:40 PM PDT 24 |
| Finished | Aug 17 08:19:06 PM PDT 24 |
| Peak memory | 610500 kb |
| Host | smart-21134caa-6f67-4ac5-ba34-76f0f05b18af |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31005 59166 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_keymgr_sideload_otbn.3100559166 |
| Directory | /workspace/1.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_app_rom.1188935277 |
| Short name | T1273 |
| Test name | |
| Test status | |
| Simulation time | 2557732032 ps |
| CPU time | 242.7 seconds |
| Started | Aug 17 07:15:40 PM PDT 24 |
| Finished | Aug 17 07:19:43 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-e7ad806d-c263-4f3e-96ce-268ec8868baa |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1188935277 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_app_rom.1188935277 |
| Directory | /workspace/1.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_entropy.2256662950 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2886017544 ps |
| CPU time | 288.34 seconds |
| Started | Aug 17 07:12:05 PM PDT 24 |
| Finished | Aug 17 07:16:53 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-b88d163e-729f-46c2-a6df-e2247c1b4046 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256662950 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_kmac_entropy.2256662950 |
| Directory | /workspace/1.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_idle.1364354371 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 3355381156 ps |
| CPU time | 241.62 seconds |
| Started | Aug 17 07:13:41 PM PDT 24 |
| Finished | Aug 17 07:17:43 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-45b80e76-44bc-4d3e-9e8c-2ef8cf8b0281 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1364354371 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_idle.1364354371 |
| Directory | /workspace/1.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3958743403 |
| Short name | T1350 |
| Test name | |
| Test status | |
| Simulation time | 2776153528 ps |
| CPU time | 204.54 seconds |
| Started | Aug 17 07:13:25 PM PDT 24 |
| Finished | Aug 17 07:16:50 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-28707006-e727-44f9-a343-437b83041d3e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958743403 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 1.chip_sw_kmac_mode_cshake.3958743403 |
| Directory | /workspace/1.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac.572406822 |
| Short name | T1141 |
| Test name | |
| Test status | |
| Simulation time | 3876703500 ps |
| CPU time | 355.57 seconds |
| Started | Aug 17 07:14:03 PM PDT 24 |
| Finished | Aug 17 07:19:59 PM PDT 24 |
| Peak memory | 609372 kb |
| Host | smart-76236d08-4032-4296-a530-e7e3faebd496 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572406822 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_kmac_mode_kmac.572406822 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1423437635 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3369928886 ps |
| CPU time | 355.01 seconds |
| Started | Aug 17 07:13:57 PM PDT 24 |
| Finished | Aug 17 07:19:53 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-61e789b0-99cd-4292-9d3e-07a3b74acce5 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1423437635 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en.1423437635 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2568633870 |
| Short name | T1291 |
| Test name | |
| Test status | |
| Simulation time | 3584631163 ps |
| CPU time | 294.1 seconds |
| Started | Aug 17 07:16:57 PM PDT 24 |
| Finished | Aug 17 07:21:52 PM PDT 24 |
| Peak memory | 609448 kb |
| Host | smart-36298a23-a64a-4926-bd7d-b6a80bbe7309 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25686338 70 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2568633870 |
| Directory | /workspace/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_kmac_smoketest.4078955047 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 2898107624 ps |
| CPU time | 271.79 seconds |
| Started | Aug 17 07:19:42 PM PDT 24 |
| Finished | Aug 17 07:24:14 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-19c43e73-e935-47d7-aced-3a74b22a64be |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078955047 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_kmac_smoketest.4078955047 |
| Directory | /workspace/1.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.2330180643 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 2742161160 ps |
| CPU time | 274.44 seconds |
| Started | Aug 17 07:12:16 PM PDT 24 |
| Finished | Aug 17 07:16:51 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-e1d5c047-b99f-4d1f-96ac-8fdcc87f1239 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330180643 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 1.chip_sw_lc_ctrl_otp_hw_cfg0.2330180643 |
| Directory | /workspace/1.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_program_error.2308897839 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 4702187780 ps |
| CPU time | 476.55 seconds |
| Started | Aug 17 07:16:08 PM PDT 24 |
| Finished | Aug 17 07:24:05 PM PDT 24 |
| Peak memory | 611168 kb |
| Host | smart-7c5c7959-1cf0-4e00-aee2-1d6263760985 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2308897839 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_program_error.2308897839 |
| Directory | /workspace/1.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2295260702 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 3280107128 ps |
| CPU time | 171.94 seconds |
| Started | Aug 17 07:13:17 PM PDT 24 |
| Finished | Aug 17 07:16:09 PM PDT 24 |
| Peak memory | 620736 kb |
| Host | smart-c728d6b8-21c6-45a2-a2d7-05701b2da846 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22952607 02 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_rand_to_scrap.2295260702 |
| Directory | /workspace/1.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1460140163 |
| Short name | T1195 |
| Test name | |
| Test status | |
| Simulation time | 2561766992 ps |
| CPU time | 96.94 seconds |
| Started | Aug 17 07:14:01 PM PDT 24 |
| Finished | Aug 17 07:15:38 PM PDT 24 |
| Peak memory | 617948 kb |
| Host | smart-7df30e37-c818-4129-bf49-92206d72d5f0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=1460140163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock.1460140163 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1147042079 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 2694087289 ps |
| CPU time | 111.94 seconds |
| Started | Aug 17 07:12:08 PM PDT 24 |
| Finished | Aug 17 07:14:00 PM PDT 24 |
| Peak memory | 617768 kb |
| Host | smart-f017205d-895b-4fd7-8c7a-fb6d9f3472ed |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147042079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1147042079 |
| Directory | /workspace/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.2417468183 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 48184645083 ps |
| CPU time | 5663.4 seconds |
| Started | Aug 17 07:12:50 PM PDT 24 |
| Finished | Aug 17 08:47:15 PM PDT 24 |
| Peak memory | 623940 kb |
| Host | smart-26816840-e2ea-49a2-ac7e-a1bd776c5ecf |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417468183 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip _sw_lc_walkthrough_dev.2417468183 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2578577784 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 11199767416 ps |
| CPU time | 1193.3 seconds |
| Started | Aug 17 07:11:12 PM PDT 24 |
| Finished | Aug 17 07:31:06 PM PDT 24 |
| Peak memory | 625416 kb |
| Host | smart-b38e6d48-0778-4549-bccb-b6f204d4a7fe |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=2578577784 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_prodend.2578577784 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.514073470 |
| Short name | T1339 |
| Test name | |
| Test status | |
| Simulation time | 45907621840 ps |
| CPU time | 4879.74 seconds |
| Started | Aug 17 07:12:40 PM PDT 24 |
| Finished | Aug 17 08:34:01 PM PDT 24 |
| Peak memory | 622244 kb |
| Host | smart-d12f1e32-d7ea-43d6-80fd-8f4501a6fa6e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514073470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_ sw_lc_walkthrough_rma.514073470 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.929098204 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 22225716415 ps |
| CPU time | 2028.8 seconds |
| Started | Aug 17 07:14:46 PM PDT 24 |
| Finished | Aug 17 07:48:35 PM PDT 24 |
| Peak memory | 625432 kb |
| Host | smart-42ce80ab-2b78-4118-8ffe-773777c42438 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=929098204 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_lc_walkthrough_testunl ocks.929098204 |
| Directory | /workspace/1.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.3848849500 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 17055551512 ps |
| CPU time | 3213.7 seconds |
| Started | Aug 17 07:14:52 PM PDT 24 |
| Finished | Aug 17 08:08:27 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-ba82d701-9798-4e0a-9ef8-39cfc72d39c0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=3848849500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq.3848849500 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.833380446 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 18247508337 ps |
| CPU time | 4880.95 seconds |
| Started | Aug 17 07:15:21 PM PDT 24 |
| Finished | Aug 17 08:36:43 PM PDT 24 |
| Peak memory | 611040 kb |
| Host | smart-281d2a13-f5ff-4bdc-933a-83811ada9d48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=833380446 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en.833380446 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2083733125 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 24423841995 ps |
| CPU time | 4532.27 seconds |
| Started | Aug 17 07:20:22 PM PDT 24 |
| Finished | Aug 17 08:35:55 PM PDT 24 |
| Peak memory | 610164 kb |
| Host | smart-60fbea23-8e8e-4720-9fe9-d694deec790b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083733125 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.2083733125 |
| Directory | /workspace/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_mem_scramble.3581051815 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 3673653560 ps |
| CPU time | 507.03 seconds |
| Started | Aug 17 07:11:35 PM PDT 24 |
| Finished | Aug 17 07:20:03 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-f49b2d23-f9e4-4c8a-95f3-e96d69c7c2d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581051815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_mem_scramble.3581051815 |
| Directory | /workspace/1.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_randomness.2237190990 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 5352606712 ps |
| CPU time | 1002.18 seconds |
| Started | Aug 17 07:15:02 PM PDT 24 |
| Finished | Aug 17 07:31:46 PM PDT 24 |
| Peak memory | 610672 kb |
| Host | smart-a6ce4285-f615-48bc-b3f5-99e68a4441f1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2237190990 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otbn_randomness.2237190990 |
| Directory | /workspace/1.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otbn_smoketest.2653903385 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 5686251012 ps |
| CPU time | 847.38 seconds |
| Started | Aug 17 07:19:32 PM PDT 24 |
| Finished | Aug 17 07:33:40 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-25a4dea2-6a85-4556-862f-5899e3e51c6b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653903385 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 1.chip_sw_otbn_smoketest.2653903385 |
| Directory | /workspace/1.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_ecc_error_vendor_test.3422616670 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 2464823899 ps |
| CPU time | 236.5 seconds |
| Started | Aug 17 07:11:09 PM PDT 24 |
| Finished | Aug 17 07:15:05 PM PDT 24 |
| Peak memory | 609452 kb |
| Host | smart-cf030c72-626e-464c-bbe1-27e48980fbdc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3422616670 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_ecc_error_vendor_test.3422616670 |
| Directory | /workspace/1.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.3520628387 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 8403627338 ps |
| CPU time | 1542.7 seconds |
| Started | Aug 17 07:11:02 PM PDT 24 |
| Finished | Aug 17 07:36:45 PM PDT 24 |
| Peak memory | 611004 kb |
| Host | smart-4910659c-863b-4720-9b7f-3341fc9cb7fe |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=3520628387 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_dev.3520628387 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2787691955 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 7072742590 ps |
| CPU time | 1215.08 seconds |
| Started | Aug 17 07:16:55 PM PDT 24 |
| Finished | Aug 17 07:37:10 PM PDT 24 |
| Peak memory | 611032 kb |
| Host | smart-53df8c4b-c6b5-4a3a-bdff-c4086ab1b368 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2787691955 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_prod.2787691955 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.4024699425 |
| Short name | T1121 |
| Test name | |
| Test status | |
| Simulation time | 9000241982 ps |
| CPU time | 1358.8 seconds |
| Started | Aug 17 07:11:07 PM PDT 24 |
| Finished | Aug 17 07:33:46 PM PDT 24 |
| Peak memory | 611304 kb |
| Host | smart-8f6d766d-bfb9-4016-8b6e-b5deccfcb3db |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=4024699425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_rma.4024699425 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.273765273 |
| Short name | T1117 |
| Test name | |
| Test status | |
| Simulation time | 4346380040 ps |
| CPU time | 729.42 seconds |
| Started | Aug 17 07:14:02 PM PDT 24 |
| Finished | Aug 17 07:26:12 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-18f96686-6c93-449b-a84f-d612657957eb |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=273765273 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.273765273 |
| Directory | /workspace/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3080252715 |
| Short name | T1234 |
| Test name | |
| Test status | |
| Simulation time | 2580327500 ps |
| CPU time | 213.86 seconds |
| Started | Aug 17 07:19:17 PM PDT 24 |
| Finished | Aug 17 07:22:51 PM PDT 24 |
| Peak memory | 610396 kb |
| Host | smart-e7e10779-cd5b-4672-9b9d-59a52850e60e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080252715 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_otp_ctrl_smoketest.3080252715 |
| Directory | /workspace/1.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_plic_sw_irq.872022073 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2765043140 ps |
| CPU time | 188.72 seconds |
| Started | Aug 17 07:14:40 PM PDT 24 |
| Finished | Aug 17 07:17:49 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-ba22cea8-f545-4b3b-a1ff-1c3c02a4f115 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872022073 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_plic_sw_irq.872022073 |
| Directory | /workspace/1.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_idle_load.2786402205 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 3818603500 ps |
| CPU time | 606.78 seconds |
| Started | Aug 17 07:20:50 PM PDT 24 |
| Finished | Aug 17 07:30:57 PM PDT 24 |
| Peak memory | 610536 kb |
| Host | smart-8bd27ec7-f9c1-4aa4-b41f-42365a5e63eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786402205 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_idle_load.2786402205 |
| Directory | /workspace/1.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_sleep_load.3510267423 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 4737786600 ps |
| CPU time | 497.27 seconds |
| Started | Aug 17 07:17:00 PM PDT 24 |
| Finished | Aug 17 07:25:17 PM PDT 24 |
| Peak memory | 611132 kb |
| Host | smart-1f3ea556-cb62-4836-8a66-d74e9bb880ed |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510267423 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 1.chip_sw_power_sleep_load.3510267423 |
| Directory | /workspace/1.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/1.chip_sw_power_virus.1667960377 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 5959747920 ps |
| CPU time | 1548.54 seconds |
| Started | Aug 17 07:21:16 PM PDT 24 |
| Finished | Aug 17 07:47:05 PM PDT 24 |
| Peak memory | 625756 kb |
| Host | smart-f0e38831-c0ff-4295-a50f-50bec8139eb3 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_test_timeout_ns=400_000_000 +use_otp_image=OtpTypeCustom +sw_build_device= sim_dv +sw_images=power_virus_systemtest:1:new_rules,power_virus_systemtest_otp_img_rma:4,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_ regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/d v/tools/sim.tcl +ntb_random_seed=1667960377 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_virus_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_power_virus.1667960377 |
| Directory | /workspace/1.chip_sw_power_virus/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1161164228 |
| Short name | T1109 |
| Test name | |
| Test status | |
| Simulation time | 10753048171 ps |
| CPU time | 1767.85 seconds |
| Started | Aug 17 07:12:14 PM PDT 24 |
| Finished | Aug 17 07:41:42 PM PDT 24 |
| Peak memory | 611780 kb |
| Host | smart-3f80c743-f2ab-4171-ae99-5fec264d4655 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161 164228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_all_reset_reqs.1161164228 |
| Directory | /workspace/1.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.11608661 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 31504332944 ps |
| CPU time | 2326.3 seconds |
| Started | Aug 17 07:14:30 PM PDT 24 |
| Finished | Aug 17 07:53:17 PM PDT 24 |
| Peak memory | 611548 kb |
| Host | smart-8e93bbc8-108c-4726-bb05-5c0499c23738 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=116 08661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_b2b_sleep_reset_req.11608661 |
| Directory | /workspace/1.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2196779329 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 13902634085 ps |
| CPU time | 1288.67 seconds |
| Started | Aug 17 07:12:48 PM PDT 24 |
| Finished | Aug 17 07:34:17 PM PDT 24 |
| Peak memory | 612108 kb |
| Host | smart-e1c6a2d5-15a1-4977-b22f-842659b184a7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2196779329 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2196779329 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.504625640 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 25033262358 ps |
| CPU time | 1700.55 seconds |
| Started | Aug 17 07:19:07 PM PDT 24 |
| Finished | Aug 17 07:47:28 PM PDT 24 |
| Peak memory | 611440 kb |
| Host | smart-bda37968-9fcc-4496-b3ba-95ec7c7f0799 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 504625640 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.504625640 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.2696483470 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 9153213180 ps |
| CPU time | 693.07 seconds |
| Started | Aug 17 07:10:22 PM PDT 24 |
| Finished | Aug 17 07:21:56 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-cc52bc8a-ba1a-465d-a6e8-25356c537680 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696483470 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_por_reset.2696483470 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1616757862 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 7185960454 ps |
| CPU time | 474.1 seconds |
| Started | Aug 17 07:20:13 PM PDT 24 |
| Finished | Aug 17 07:28:07 PM PDT 24 |
| Peak memory | 617012 kb |
| Host | smart-8979886d-cd83-4126-8d22-24db410f809e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1616757862 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1616757862 |
| Directory | /workspace/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4074576808 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 8949219016 ps |
| CPU time | 477.05 seconds |
| Started | Aug 17 07:14:53 PM PDT 24 |
| Finished | Aug 17 07:22:50 PM PDT 24 |
| Peak memory | 611532 kb |
| Host | smart-97c6e886-8a1e-4b93-9052-5f9b7c35259c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074576808 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 1.chip_sw_pwrmgr_full_aon_reset.4074576808 |
| Directory | /workspace/1.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1799755036 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 3970560628 ps |
| CPU time | 429.18 seconds |
| Started | Aug 17 07:16:30 PM PDT 24 |
| Finished | Aug 17 07:23:41 PM PDT 24 |
| Peak memory | 610012 kb |
| Host | smart-a2169f45-6923-4cd3-93d1-8342b25f7388 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_lowpower_cancel_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799755036 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_pwrmgr_lowpower_cancel.1799755036 |
| Directory | /workspace/1.chip_sw_pwrmgr_lowpower_cancel/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3987467479 |
| Short name | T1282 |
| Test name | |
| Test status | |
| Simulation time | 4461126512 ps |
| CPU time | 333.71 seconds |
| Started | Aug 17 07:10:35 PM PDT 24 |
| Finished | Aug 17 07:16:08 PM PDT 24 |
| Peak memory | 618176 kb |
| Host | smart-a844a630-15ca-4e80-b938-539a14c4c3ee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=3987467479 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_main_power_glitch_reset.3987467479 |
| Directory | /workspace/1.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3238676095 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 10920019122 ps |
| CPU time | 1440.43 seconds |
| Started | Aug 17 07:20:40 PM PDT 24 |
| Finished | Aug 17 07:44:41 PM PDT 24 |
| Peak memory | 612092 kb |
| Host | smart-6995dad3-a5e2-44f4-872f-89e879cfceab |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238676095 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp ace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3238676095 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1311768989 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 8104493132 ps |
| CPU time | 580.53 seconds |
| Started | Aug 17 07:16:18 PM PDT 24 |
| Finished | Aug 17 07:25:59 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-35877835-c926-4408-8f55-ac19a465290b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311768989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1311768989 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.2185630698 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 8018746583 ps |
| CPU time | 601.2 seconds |
| Started | Aug 17 07:12:38 PM PDT 24 |
| Finished | Aug 17 07:22:39 PM PDT 24 |
| Peak memory | 611548 kb |
| Host | smart-401f4620-1c41-48b1-be4e-3bec1975590c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185630698 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_normal_sleep_por_reset.2185630698 |
| Directory | /workspace/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4089291511 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 26633129823 ps |
| CPU time | 2045.55 seconds |
| Started | Aug 17 07:12:36 PM PDT 24 |
| Finished | Aug 17 07:46:42 PM PDT 24 |
| Peak memory | 612124 kb |
| Host | smart-435ae99e-496b-4fae-8285-55273956e986 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=4089291511 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4089291511 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.154252079 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 22843793290 ps |
| CPU time | 1470.36 seconds |
| Started | Aug 17 07:15:59 PM PDT 24 |
| Finished | Aug 17 07:40:30 PM PDT 24 |
| Peak memory | 611364 kb |
| Host | smart-6dd96c23-4e05-4b8c-b244-515bb4c0435b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=154252079 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_random_sleep_all_wake_ups.154252079 |
| Directory | /workspace/1.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3212175023 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 6169861080 ps |
| CPU time | 514.96 seconds |
| Started | Aug 17 07:17:25 PM PDT 24 |
| Finished | Aug 17 07:26:01 PM PDT 24 |
| Peak memory | 611384 kb |
| Host | smart-c1e889d8-f4ac-49a1-8775-5aeeab559898 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3212175023 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3212175023 |
| Directory | /workspace/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.479634105 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2975196216 ps |
| CPU time | 280.82 seconds |
| Started | Aug 17 07:19:54 PM PDT 24 |
| Finished | Aug 17 07:24:35 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-090404d3-63ca-40a4-9399-93dc83d5ee38 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479634105 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_disabled.479634105 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2896138359 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 5013298488 ps |
| CPU time | 355.43 seconds |
| Started | Aug 17 07:13:54 PM PDT 24 |
| Finished | Aug 17 07:19:50 PM PDT 24 |
| Peak memory | 609536 kb |
| Host | smart-82f68619-f30b-46a3-999b-bfda99ccf5b9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28961383 59 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2896138359 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2004011308 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 6319597300 ps |
| CPU time | 658.98 seconds |
| Started | Aug 17 07:17:46 PM PDT 24 |
| Finished | Aug 17 07:28:45 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-74d74cb3-6484-40f5-8375-fb347ec8f61c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=2004011308 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sleep_wake_5_bug.2004011308 |
| Directory | /workspace/1.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.949383475 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 6081804320 ps |
| CPU time | 393.93 seconds |
| Started | Aug 17 07:17:43 PM PDT 24 |
| Finished | Aug 17 07:24:17 PM PDT 24 |
| Peak memory | 611184 kb |
| Host | smart-7f423e3e-c707-4463-89d4-edc5df3d3812 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949383475 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_smoketest.949383475 |
| Directory | /workspace/1.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1412804664 |
| Short name | T1315 |
| Test name | |
| Test status | |
| Simulation time | 8260927020 ps |
| CPU time | 1036.13 seconds |
| Started | Aug 17 07:19:43 PM PDT 24 |
| Finished | Aug 17 07:37:00 PM PDT 24 |
| Peak memory | 611144 kb |
| Host | smart-36026352-2d31-43f6-8ddb-21d13b0b1bd3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412804664 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_sysrst_ctrl_reset.1412804664 |
| Directory | /workspace/1.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4156546607 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 3746320666 ps |
| CPU time | 358.75 seconds |
| Started | Aug 17 07:14:25 PM PDT 24 |
| Finished | Aug 17 07:20:24 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-e1e6482e-9fcc-4907-8de8-716429190e31 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156546607 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usb_clk_disabled_when_active.4156546607 |
| Directory | /workspace/1.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3879169356 |
| Short name | T1185 |
| Test name | |
| Test status | |
| Simulation time | 5321458080 ps |
| CPU time | 359.83 seconds |
| Started | Aug 17 07:18:06 PM PDT 24 |
| Finished | Aug 17 07:24:06 PM PDT 24 |
| Peak memory | 610124 kb |
| Host | smart-13ef0d45-676f-4f1b-abff-aa9554fc60d0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879169356 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_usbdev_smoketest.3879169356 |
| Directory | /workspace/1.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2015675928 |
| Short name | T1335 |
| Test name | |
| Test status | |
| Simulation time | 4353571818 ps |
| CPU time | 423.81 seconds |
| Started | Aug 17 07:10:46 PM PDT 24 |
| Finished | Aug 17 07:17:50 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-c4bad92d-6a17-44f2-9254-f9bd0fa9d935 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201 5675928 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_pwrmgr_wdog_reset.2015675928 |
| Directory | /workspace/1.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3655625201 |
| Short name | T1257 |
| Test name | |
| Test status | |
| Simulation time | 10299048880 ps |
| CPU time | 629.57 seconds |
| Started | Aug 17 07:17:53 PM PDT 24 |
| Finished | Aug 17 07:28:24 PM PDT 24 |
| Peak memory | 610316 kb |
| Host | smart-26f3b586-ef7c-469d-9b71-15fc78222384 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655625201 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rom_ctrl_integrity_check.3655625201 |
| Directory | /workspace/1.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2254701060 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 11009723640 ps |
| CPU time | 1822.86 seconds |
| Started | Aug 17 07:13:58 PM PDT 24 |
| Finished | Aug 17 07:44:21 PM PDT 24 |
| Peak memory | 611564 kb |
| Host | smart-d2fe7548-c898-48e0-ba9c-e79782004f0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +sw_images=rstmgr_alert_info_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=2254701060 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_alert_info.2254701060 |
| Directory | /workspace/1.chip_sw_rstmgr_alert_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.251998492 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 6300906876 ps |
| CPU time | 761.21 seconds |
| Started | Aug 17 07:11:38 PM PDT 24 |
| Finished | Aug 17 07:24:19 PM PDT 24 |
| Peak memory | 610060 kb |
| Host | smart-fa0d6ad1-9bfb-49e5-9bf4-73650f671e9a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_cpu_info_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=251998492 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_rstmgr_cpu_info.251998492 |
| Directory | /workspace/1.chip_sw_rstmgr_cpu_info/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1941472106 |
| Short name | T1215 |
| Test name | |
| Test status | |
| Simulation time | 5023522232 ps |
| CPU time | 543.49 seconds |
| Started | Aug 17 07:11:43 PM PDT 24 |
| Finished | Aug 17 07:20:47 PM PDT 24 |
| Peak memory | 642160 kb |
| Host | smart-d5af0f46-2109-466a-83f4-17a6dc75635b |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1941472106 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_rst_cnsty_escalation.1941472106 |
| Directory | /workspace/1.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.353396215 |
| Short name | T1275 |
| Test name | |
| Test status | |
| Simulation time | 2638307792 ps |
| CPU time | 215.85 seconds |
| Started | Aug 17 07:22:27 PM PDT 24 |
| Finished | Aug 17 07:26:03 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-d47191d4-9f65-4752-bef9-ed2b7f4e708d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353396215 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 1.chip_sw_rstmgr_smoketest.353396215 |
| Directory | /workspace/1.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.348706670 |
| Short name | T1236 |
| Test name | |
| Test status | |
| Simulation time | 3668463820 ps |
| CPU time | 382.98 seconds |
| Started | Aug 17 07:10:39 PM PDT 24 |
| Finished | Aug 17 07:17:02 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-1e7eea05-d763-478c-af8c-89733752cf82 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348706670 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rstmgr_sw_req.348706670 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2170943577 |
| Short name | T1277 |
| Test name | |
| Test status | |
| Simulation time | 2946620256 ps |
| CPU time | 319.42 seconds |
| Started | Aug 17 07:11:41 PM PDT 24 |
| Finished | Aug 17 07:17:01 PM PDT 24 |
| Peak memory | 609328 kb |
| Host | smart-70dd978a-cc2b-46a1-ad03-db23a32d29b2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170943577 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rstmgr_sw_rst.2170943577 |
| Directory | /workspace/1.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.3664703407 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 2968404184 ps |
| CPU time | 310.96 seconds |
| Started | Aug 17 07:23:22 PM PDT 24 |
| Finished | Aug 17 07:28:35 PM PDT 24 |
| Peak memory | 610380 kb |
| Host | smart-81f3510a-9eb8-4eef-af0b-8b88a2f7d3e6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3664703407 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_address_translation.3664703407 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.3833205636 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 2496112537 ps |
| CPU time | 187.43 seconds |
| Started | Aug 17 07:16:22 PM PDT 24 |
| Finished | Aug 17 07:19:30 PM PDT 24 |
| Peak memory | 609952 kb |
| Host | smart-55803ac7-ae5d-4399-b517-b5e77ef7b60e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833205636 -assert nopostp roc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_icache_invalidate.3833205636 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2485438127 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 5016733452 ps |
| CPU time | 787.75 seconds |
| Started | Aug 17 07:12:08 PM PDT 24 |
| Finished | Aug 17 07:25:16 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-eea478e0-afa3-4c3d-9e05-2fe1eecbd419 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24854 38127 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_nmi_irq.2485438127 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2438733108 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 5669977284 ps |
| CPU time | 1158.08 seconds |
| Started | Aug 17 07:12:14 PM PDT 24 |
| Finished | Aug 17 07:31:33 PM PDT 24 |
| Peak memory | 610108 kb |
| Host | smart-097dac7e-0ab9-4bb9-9327-d4fc2ebaf6ec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=2438733108 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_core_ibex_rnd.2438733108 |
| Directory | /workspace/1.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1004240486 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 5490061146 ps |
| CPU time | 575.94 seconds |
| Started | Aug 17 07:16:20 PM PDT 24 |
| Finished | Aug 17 07:25:56 PM PDT 24 |
| Peak memory | 624972 kb |
| Host | smart-f2b0cecf-72c5-43c7-a4a5-007356ab4db2 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004240486 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_escalation_reset.1004240486 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.4001476356 |
| Short name | T1278 |
| Test name | |
| Test status | |
| Simulation time | 4965311920 ps |
| CPU time | 566.87 seconds |
| Started | Aug 17 07:23:06 PM PDT 24 |
| Finished | Aug 17 07:32:35 PM PDT 24 |
| Peak memory | 620264 kb |
| Host | smart-da0e9497-8977-44ff-9f45-a0686546d46b |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001476356 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_access_after_wakeup.4001476356 |
| Directory | /workspace/1.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1886642809 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 3869684544 ps |
| CPU time | 462.32 seconds |
| Started | Aug 17 07:21:26 PM PDT 24 |
| Finished | Aug 17 07:29:10 PM PDT 24 |
| Peak memory | 620248 kb |
| Host | smart-dce299a1-4a35-4f8d-92ab-f6f476a814cf |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188664 2809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1886642809 |
| Directory | /workspace/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2467351586 |
| Short name | T1322 |
| Test name | |
| Test status | |
| Simulation time | 2954294958 ps |
| CPU time | 265.77 seconds |
| Started | Aug 17 07:19:49 PM PDT 24 |
| Finished | Aug 17 07:24:16 PM PDT 24 |
| Peak memory | 609400 kb |
| Host | smart-fc92bb39-bb13-408a-85d2-fb95240da065 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2467351586 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_plic_smoketest.2467351586 |
| Directory | /workspace/1.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_irq.3520370386 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 2808716348 ps |
| CPU time | 235.62 seconds |
| Started | Aug 17 07:10:08 PM PDT 24 |
| Finished | Aug 17 07:14:04 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-58b185c4-cdba-4b6c-a5a3-abdcfc2f61cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520370386 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 1.chip_sw_rv_timer_irq.3520370386 |
| Directory | /workspace/1.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_rv_timer_smoketest.716766648 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 3235588344 ps |
| CPU time | 294.16 seconds |
| Started | Aug 17 07:19:33 PM PDT 24 |
| Finished | Aug 17 07:24:28 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-4f31e191-16da-46f0-bcc1-18070568829b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716766648 -assert nopostproc +UVM_TESTNAME= chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.chip_sw_rv_timer_smoketest.716766648 |
| Directory | /workspace/1.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1653034836 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 7984935400 ps |
| CPU time | 496.82 seconds |
| Started | Aug 17 07:13:23 PM PDT 24 |
| Finished | Aug 17 07:21:40 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-9999761a-22c0-425a-a9bb-4d3e2409d97c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16530348 36 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_alert.1653034836 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1366238397 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 2441398807 ps |
| CPU time | 173.15 seconds |
| Started | Aug 17 07:13:26 PM PDT 24 |
| Finished | Aug 17 07:16:20 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-61c27852-e75e-466a-8288-d0549c1d1614 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1366238 397 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sensor_ctrl_status.1366238397 |
| Directory | /workspace/1.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pin_retention.2659905457 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 4044661470 ps |
| CPU time | 309.39 seconds |
| Started | Aug 17 07:09:55 PM PDT 24 |
| Finished | Aug 17 07:15:06 PM PDT 24 |
| Peak memory | 610608 kb |
| Host | smart-af0b13c8-e221-4ea9-8ef1-a10d07591dc5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pin_retention_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659905457 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_pin_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep_pin_retention.2659905457 |
| Directory | /workspace/1.chip_sw_sleep_pin_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4116598872 |
| Short name | T1108 |
| Test name | |
| Test status | |
| Simulation time | 9216899200 ps |
| CPU time | 1320.52 seconds |
| Started | Aug 17 07:09:40 PM PDT 24 |
| Finished | Aug 17 07:31:41 PM PDT 24 |
| Peak memory | 611464 kb |
| Host | smart-ec28964a-b4c2-4c4c-9d42-1e21a0458a24 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116598872 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 1.chip_sw_sleep_pwm_pulses.4116598872 |
| Directory | /workspace/1.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.3651079807 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 7303127184 ps |
| CPU time | 733.26 seconds |
| Started | Aug 17 07:16:48 PM PDT 24 |
| Finished | Aug 17 07:29:02 PM PDT 24 |
| Peak memory | 610356 kb |
| Host | smart-bb6162aa-9a6a-4cd0-b113-fba502a25123 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651079807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sl eep_sram_ret_contents_no_scramble.3651079807 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.1842159980 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 8948502696 ps |
| CPU time | 693.01 seconds |
| Started | Aug 17 07:13:38 PM PDT 24 |
| Finished | Aug 17 07:25:11 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-4651889e-48cf-4c15-99ee-81ee06f84577 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842159980 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sleep _sram_ret_contents_scramble.1842159980 |
| Directory | /workspace/1.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2486844387 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 6596094426 ps |
| CPU time | 687.54 seconds |
| Started | Aug 17 07:09:18 PM PDT 24 |
| Finished | Aug 17 07:20:47 PM PDT 24 |
| Peak memory | 625552 kb |
| Host | smart-910b2e7a-2e57-44a4-b3b8-fbab2c69cc46 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2486844387 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through.2486844387 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2978084138 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 4461396413 ps |
| CPU time | 496.24 seconds |
| Started | Aug 17 07:11:02 PM PDT 24 |
| Finished | Aug 17 07:19:19 PM PDT 24 |
| Peak memory | 625516 kb |
| Host | smart-e551ba40-6362-44b7-83d0-ef3c9dbbabf2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978084138 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_collision_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pass_through_collision.2978084138 |
| Directory | /workspace/1.chip_sw_spi_device_pass_through_collision/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_pinmux_sleep_retention.3477520651 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2959287464 ps |
| CPU time | 212.05 seconds |
| Started | Aug 17 07:10:03 PM PDT 24 |
| Finished | Aug 17 07:13:35 PM PDT 24 |
| Peak memory | 618512 kb |
| Host | smart-044f1afb-2fb8-4973-a578-151903467fcf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477520651 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_pinmux_sleep_retention.3477520651 |
| Directory | /workspace/1.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_device_tpm.989542975 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 2718479535 ps |
| CPU time | 352.94 seconds |
| Started | Aug 17 07:10:36 PM PDT 24 |
| Finished | Aug 17 07:16:29 PM PDT 24 |
| Peak memory | 619856 kb |
| Host | smart-59f9625a-bb64-47c1-a7c0-d64b1ec1b55c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=989542975 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 1.chip_sw_spi_device_tpm.989542975 |
| Directory | /workspace/1.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/1.chip_sw_spi_host_tx_rx.885348975 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 3218367080 ps |
| CPU time | 258.09 seconds |
| Started | Aug 17 07:11:01 PM PDT 24 |
| Finished | Aug 17 07:15:20 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-4b3381b3-dba1-4ad6-80dd-1769499968ba |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885348975 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 1.chip_sw_spi_host_tx_rx.885348975 |
| Directory | /workspace/1.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_execution_main.765692246 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 6729900588 ps |
| CPU time | 835.13 seconds |
| Started | Aug 17 07:14:46 PM PDT 24 |
| Finished | Aug 17 07:28:41 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-d7b9fea7-c754-4d63-bf0c-ea99588cc09e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=765692246 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_execution_main.765692246 |
| Directory | /workspace/1.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.3070637933 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 4869278712 ps |
| CPU time | 589.69 seconds |
| Started | Aug 17 07:14:10 PM PDT 24 |
| Finished | Aug 17 07:24:00 PM PDT 24 |
| Peak memory | 611432 kb |
| Host | smart-4ac10186-218f-4780-abfa-bcb534abddd1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070637933 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw _sram_ctrl_scrambled_access.3070637933 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1701871836 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 4678584594 ps |
| CPU time | 739.7 seconds |
| Started | Aug 17 07:15:14 PM PDT 24 |
| Finished | Aug 17 07:27:35 PM PDT 24 |
| Peak memory | 611340 kb |
| Host | smart-07f8270b-5dfa-4321-86af-c4618a4430ba |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701871836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_n ame 1.chip_sw_sram_ctrl_scrambled_access_jitter_en.1701871836 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3469496084 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 5417759989 ps |
| CPU time | 533.34 seconds |
| Started | Aug 17 07:17:31 PM PDT 24 |
| Finished | Aug 17 07:26:25 PM PDT 24 |
| Peak memory | 611436 kb |
| Host | smart-84fa6e1b-9754-496b-bbb6-8a290d8fc176 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469496084 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3469496084 |
| Directory | /workspace/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2266008635 |
| Short name | T1240 |
| Test name | |
| Test status | |
| Simulation time | 2935081814 ps |
| CPU time | 232.95 seconds |
| Started | Aug 17 07:19:19 PM PDT 24 |
| Finished | Aug 17 07:23:12 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-5828a1fa-e579-48e2-9384-25b7c03957d2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266008635 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_sram_ctrl_smoketest.2266008635 |
| Directory | /workspace/1.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1785554018 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 20209985535 ps |
| CPU time | 3239.7 seconds |
| Started | Aug 17 07:11:51 PM PDT 24 |
| Finished | Aug 17 08:05:51 PM PDT 24 |
| Peak memory | 610172 kb |
| Host | smart-4ca826f5-5c3d-49e1-9756-f2ffda696ab5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785554018 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ec_rst_l.1785554018 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2730909685 |
| Short name | T1168 |
| Test name | |
| Test status | |
| Simulation time | 3879414442 ps |
| CPU time | 624.1 seconds |
| Started | Aug 17 07:12:58 PM PDT 24 |
| Finished | Aug 17 07:23:25 PM PDT 24 |
| Peak memory | 614144 kb |
| Host | smart-091f7d78-7ff9-4fbc-b9c3-48982f526833 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730909685 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_in_irq.2730909685 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.391214298 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 3385003185 ps |
| CPU time | 307.94 seconds |
| Started | Aug 17 07:10:23 PM PDT 24 |
| Finished | Aug 17 07:15:32 PM PDT 24 |
| Peak memory | 614052 kb |
| Host | smart-307f2712-c2a4-4e98-8d8f-996157d3054d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391214298 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_inputs.391214298 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_outputs.3580334417 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 4003036808 ps |
| CPU time | 400.54 seconds |
| Started | Aug 17 07:10:17 PM PDT 24 |
| Finished | Aug 17 07:16:59 PM PDT 24 |
| Peak memory | 609748 kb |
| Host | smart-30e1ee46-d1f3-4fbc-8b59-427aa8df4cb3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580334417 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_outputs.3580334417 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.513280618 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 21949753112 ps |
| CPU time | 1132.58 seconds |
| Started | Aug 17 07:10:18 PM PDT 24 |
| Finished | Aug 17 07:29:10 PM PDT 24 |
| Peak memory | 615576 kb |
| Host | smart-d6e99b28-6e24-446a-9f4f-172978e79fe1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=36_000_000 +sw_build_device=sim_dv +sw_images=sysrst_ctrl_reset_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51328061 8 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_reset.513280618 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4100016698 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 5569499532 ps |
| CPU time | 559.2 seconds |
| Started | Aug 17 07:12:23 PM PDT 24 |
| Finished | Aug 17 07:21:43 PM PDT 24 |
| Peak memory | 610336 kb |
| Host | smart-f38beca4-94b8-4c07-bd85-f32e0431cc9b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100016698 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4100016698 |
| Directory | /workspace/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1553648314 |
| Short name | T1203 |
| Test name | |
| Test status | |
| Simulation time | 8493170760 ps |
| CPU time | 1717.48 seconds |
| Started | Aug 17 07:12:52 PM PDT 24 |
| Finished | Aug 17 07:41:30 PM PDT 24 |
| Peak memory | 625156 kb |
| Host | smart-cfa6c2df-a0fd-41eb-b24c-109c283c5684 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1553648314 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_rand_baudrate.1553648314 |
| Directory | /workspace/1.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_smoketest.805694443 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 2620591600 ps |
| CPU time | 178.19 seconds |
| Started | Aug 17 07:18:35 PM PDT 24 |
| Finished | Aug 17 07:21:33 PM PDT 24 |
| Peak memory | 611688 kb |
| Host | smart-7f7f3aca-fe0a-4558-8b1c-69ae9ab82549 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805694443 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 1.chip_sw_uart_smoketest.805694443 |
| Directory | /workspace/1.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx.2288005363 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 5003676812 ps |
| CPU time | 619.2 seconds |
| Started | Aug 17 07:09:05 PM PDT 24 |
| Finished | Aug 17 07:19:24 PM PDT 24 |
| Peak memory | 620704 kb |
| Host | smart-20daa017-964b-4164-842f-8b44b031ff05 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288005363 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx.2288005363 |
| Directory | /workspace/1.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.2114639299 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 8585237977 ps |
| CPU time | 1834.55 seconds |
| Started | Aug 17 07:10:17 PM PDT 24 |
| Finished | Aug 17 07:40:53 PM PDT 24 |
| Peak memory | 618516 kb |
| Host | smart-c994e59c-9aa7-4a56-8e9a-d13fcc7a64f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114639299 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq.2114639299 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3094150391 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 8990457659 ps |
| CPU time | 1178.17 seconds |
| Started | Aug 17 07:09:38 PM PDT 24 |
| Finished | Aug 17 07:29:17 PM PDT 24 |
| Peak memory | 623840 kb |
| Host | smart-5552a0a9-a319-4df9-9bce-44a235a0aabf |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094150391 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.3094150391 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.495041409 |
| Short name | T1264 |
| Test name | |
| Test status | |
| Simulation time | 79100115256 ps |
| CPU time | 12541 seconds |
| Started | Aug 17 07:15:29 PM PDT 24 |
| Finished | Aug 17 10:44:32 PM PDT 24 |
| Peak memory | 634660 kb |
| Host | smart-f4116ec2-aa59-43ef-9747-46e1f306c02d |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=495041409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_bootstrap.495041409 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.170831829 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 4526917136 ps |
| CPU time | 610.28 seconds |
| Started | Aug 17 07:13:00 PM PDT 24 |
| Finished | Aug 17 07:23:11 PM PDT 24 |
| Peak memory | 620660 kb |
| Host | smart-840e95d9-d363-477a-9bbd-e6c885506378 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=170831829 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx1.170831829 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2373924540 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 4395649810 ps |
| CPU time | 687.89 seconds |
| Started | Aug 17 07:10:35 PM PDT 24 |
| Finished | Aug 17 07:22:03 PM PDT 24 |
| Peak memory | 620372 kb |
| Host | smart-bc275a80-e5c6-4706-aa40-0e3acd535718 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373924540 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx2.2373924540 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.3846895038 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 4062517878 ps |
| CPU time | 793.17 seconds |
| Started | Aug 17 07:13:06 PM PDT 24 |
| Finished | Aug 17 07:26:19 PM PDT 24 |
| Peak memory | 620416 kb |
| Host | smart-a706e3d3-bbf8-4b1e-958e-8b64ea0b0e3a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846895038 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_sw_uart_tx_rx_idx3.3846895038 |
| Directory | /workspace/1.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_dev.1081112465 |
| Short name | T1235 |
| Test name | |
| Test status | |
| Simulation time | 4618104856 ps |
| CPU time | 295.41 seconds |
| Started | Aug 17 07:20:02 PM PDT 24 |
| Finished | Aug 17 07:24:59 PM PDT 24 |
| Peak memory | 625348 kb |
| Host | smart-bf4c2a7d-db4a-427f-ac02-188636533188 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=1081112465 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_dev.1081112465 |
| Directory | /workspace/1.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_prod.739121696 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 2934409098 ps |
| CPU time | 162.87 seconds |
| Started | Aug 17 07:19:41 PM PDT 24 |
| Finished | Aug 17 07:22:25 PM PDT 24 |
| Peak memory | 625352 kb |
| Host | smart-039d4624-fc55-4e76-becc-9a19a0b16fd2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739121696 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_prod.739121696 |
| Directory | /workspace/1.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_rma.454340747 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 7563130126 ps |
| CPU time | 774.43 seconds |
| Started | Aug 17 07:15:27 PM PDT 24 |
| Finished | Aug 17 07:28:22 PM PDT 24 |
| Peak memory | 634000 kb |
| Host | smart-ec07b062-08bd-47c3-b75a-7567d2aaf4d9 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454340747 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_rma.454340747 |
| Directory | /workspace/1.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/1.chip_tap_straps_testunlock0.1244908063 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 5447105497 ps |
| CPU time | 539.98 seconds |
| Started | Aug 17 07:17:05 PM PDT 24 |
| Finished | Aug 17 07:26:05 PM PDT 24 |
| Peak memory | 625828 kb |
| Host | smart-d09d129f-67e6-4870-8ca3-a20db382a427 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1244908063 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.chip_tap_straps_testunlock0.1244908063 |
| Directory | /workspace/1.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_dev.325997045 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 15332679205 ps |
| CPU time | 3245.28 seconds |
| Started | Aug 17 07:21:56 PM PDT 24 |
| Finished | Aug 17 08:16:02 PM PDT 24 |
| Peak memory | 610284 kb |
| Host | smart-95d57083-d186-4853-bb8c-84e75eb729e4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=325997045 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SE Q=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1 .rom_e2e_asm_init_dev.325997045 |
| Directory | /workspace/1.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod.3490789518 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 15368268536 ps |
| CPU time | 3792.24 seconds |
| Started | Aug 17 07:22:14 PM PDT 24 |
| Finished | Aug 17 08:25:27 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-93e9a372-6d4d-4e09-8527-73cbfc7a7072 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490789518 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_prod.3490789518 |
| Directory | /workspace/1.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1523960510 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 15559947282 ps |
| CPU time | 4010.49 seconds |
| Started | Aug 17 07:21:20 PM PDT 24 |
| Finished | Aug 17 08:28:11 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-af6c8e28-d0f6-428d-851f-a659daedfb39 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523960510 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 1.rom_e2e_asm_init_prod_end.1523960510 |
| Directory | /workspace/1.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_rma.1965237760 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 15244772794 ps |
| CPU time | 3746.46 seconds |
| Started | Aug 17 07:21:33 PM PDT 24 |
| Finished | Aug 17 08:24:00 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-7fea8c27-402a-42b0-99ac-eb04a77bc708 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965237760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_asm_init_rma.1965237760 |
| Directory | /workspace/1.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1430471167 |
| Short name | T1323 |
| Test name | |
| Test status | |
| Simulation time | 11525928785 ps |
| CPU time | 3253.04 seconds |
| Started | Aug 17 07:22:54 PM PDT 24 |
| Finished | Aug 17 08:17:08 PM PDT 24 |
| Peak memory | 611068 kb |
| Host | smart-dd785ff2-690b-4293-81d0-8403ddde55a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1430471167 -assert nopostproc +UVM_TESTNAME=chip_base_te st +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/ null -cm_name 1.rom_e2e_asm_init_test_unlocked0.1430471167 |
| Directory | /workspace/1.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_invalid_meas.4204363716 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 14639832476 ps |
| CPU time | 3306.84 seconds |
| Started | Aug 17 07:23:08 PM PDT 24 |
| Finished | Aug 17 08:18:16 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-e446300d-c862-4260-9c10-4618486242e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4204363716 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_in it_rom_ext_invalid_meas.4204363716 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_meas.320338378 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 14851871184 ps |
| CPU time | 3590.92 seconds |
| Started | Aug 17 07:21:22 PM PDT 24 |
| Finished | Aug 17 08:21:14 PM PDT 24 |
| Peak memory | 610504 kb |
| Host | smart-7961ab10-dd55-400a-9974-b36cb2b51981 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320338378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en _cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext_meas.320338378 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_keymgr_init_rom_ext_no_meas.4116158907 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 14469590800 ps |
| CPU time | 3249.65 seconds |
| Started | Aug 17 07:24:43 PM PDT 24 |
| Finished | Aug 17 08:18:54 PM PDT 24 |
| Peak memory | 610224 kb |
| Host | smart-c42d9b40-4394-4913-bab5-732ec18b44e9 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4116158907 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_keymgr_init_rom_ext _no_meas.4116158907 |
| Directory | /workspace/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_self_hash.851677155 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 25460379352 ps |
| CPU time | 5933.2 seconds |
| Started | Aug 17 07:23:20 PM PDT 24 |
| Finished | Aug 17 09:02:14 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-13d901d9-fe54-4c57-8b37-4b044403ce1e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=851677155 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_self_hash.851677155 |
| Directory | /workspace/1.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.1255379780 |
| Short name | T1142 |
| Test name | |
| Test status | |
| Simulation time | 14647183800 ps |
| CPU time | 3075.91 seconds |
| Started | Aug 17 07:22:42 PM PDT 24 |
| Finished | Aug 17 08:13:58 PM PDT 24 |
| Peak memory | 611100 kb |
| Host | smart-5bc34581-3770-4a02-9c00-fb19aa3e824a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255379780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_ shutdown_exception_c.1255379780 |
| Directory | /workspace/1.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_shutdown_output.3080926840 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 24004918954 ps |
| CPU time | 3276.01 seconds |
| Started | Aug 17 07:24:49 PM PDT 24 |
| Finished | Aug 17 08:19:25 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-e7792a30-deb1-44c2-ac44-835c69dba84a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080926840 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_shutdown_output.3080926840 |
| Directory | /workspace/1.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_smoke.589595747 |
| Short name | T1299 |
| Test name | |
| Test status | |
| Simulation time | 15089580584 ps |
| CPU time | 3769.68 seconds |
| Started | Aug 17 07:22:44 PM PDT 24 |
| Finished | Aug 17 08:25:34 PM PDT 24 |
| Peak memory | 610248 kb |
| Host | smart-e05e14af-d6ac-4517-87fe-4fca490072a4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=589595747 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_smoke.589595747 |
| Directory | /workspace/1.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/1.rom_e2e_static_critical.2173429306 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 16893998766 ps |
| CPU time | 3813.01 seconds |
| Started | Aug 17 07:21:06 PM PDT 24 |
| Finished | Aug 17 08:24:40 PM PDT 24 |
| Peak memory | 610892 kb |
| Host | smart-f012f53a-a973-43df-824a-928160fe2927 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173429306 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_e2e_static_critical.2173429306 |
| Directory | /workspace/1.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/1.rom_keymgr_functest.2144343881 |
| Short name | T1220 |
| Test name | |
| Test status | |
| Simulation time | 5111247168 ps |
| CPU time | 697.95 seconds |
| Started | Aug 17 07:19:09 PM PDT 24 |
| Finished | Aug 17 07:30:47 PM PDT 24 |
| Peak memory | 611312 kb |
| Host | smart-77b40957-d228-4c98-9069-fb68ccb7e2b2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144343881 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 1.rom_keymgr_functest.2144343881 |
| Directory | /workspace/1.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/1.rom_raw_unlock.3627315336 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 4837937347 ps |
| CPU time | 233.51 seconds |
| Started | Aug 17 07:18:03 PM PDT 24 |
| Finished | Aug 17 07:21:57 PM PDT 24 |
| Peak memory | 624172 kb |
| Host | smart-48f4c937-b784-46f9-8b66-c4790bb131fd |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3627315336 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rom_raw_unlock.3627315336 |
| Directory | /workspace/1.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/1.rom_volatile_raw_unlock.761243040 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1831294230 ps |
| CPU time | 114.23 seconds |
| Started | Aug 17 07:20:44 PM PDT 24 |
| Finished | Aug 17 07:22:39 PM PDT 24 |
| Peak memory | 617376 kb |
| Host | smart-402e334a-f363-4918-9b2c-19bb6f40e6dc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761243040 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 1.rom_volatile_raw_unlock.761243040 |
| Directory | /workspace/1.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3772403760 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 3635939000 ps |
| CPU time | 398.44 seconds |
| Started | Aug 17 07:31:29 PM PDT 24 |
| Finished | Aug 17 07:38:08 PM PDT 24 |
| Peak memory | 650080 kb |
| Host | smart-afbdd004-e498-4513-880c-f407bf08e203 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772403760 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3772403760 |
| Directory | /workspace/10.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2981145834 |
| Short name | T1333 |
| Test name | |
| Test status | |
| Simulation time | 10682644938 ps |
| CPU time | 960.04 seconds |
| Started | Aug 17 07:32:18 PM PDT 24 |
| Finished | Aug 17 07:48:19 PM PDT 24 |
| Peak memory | 625472 kb |
| Host | smart-fe8a9aaa-a56f-47b6-a021-5a67f819b653 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2981145834 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 10.chip_sw_lc_ctrl_transition.2981145834 |
| Directory | /workspace/10.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/10.chip_sw_uart_rand_baudrate.2293731582 |
| Short name | T1122 |
| Test name | |
| Test status | |
| Simulation time | 4188605674 ps |
| CPU time | 570.99 seconds |
| Started | Aug 17 07:30:22 PM PDT 24 |
| Finished | Aug 17 07:39:53 PM PDT 24 |
| Peak memory | 619416 kb |
| Host | smart-68c5dcd7-79e6-4721-8506-f0b8cdbeb3c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2293731582 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.chip_sw_uart_rand_baudrate.2293731582 |
| Directory | /workspace/10.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1250343819 |
| Short name | T1332 |
| Test name | |
| Test status | |
| Simulation time | 5360758769 ps |
| CPU time | 640.89 seconds |
| Started | Aug 17 07:35:48 PM PDT 24 |
| Finished | Aug 17 07:46:30 PM PDT 24 |
| Peak memory | 625484 kb |
| Host | smart-92600d63-87b7-4b2e-94aa-d303125747da |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1250343819 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 11.chip_sw_lc_ctrl_transition.1250343819 |
| Directory | /workspace/11.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/11.chip_sw_uart_rand_baudrate.192523074 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 8717564552 ps |
| CPU time | 1845.7 seconds |
| Started | Aug 17 07:31:18 PM PDT 24 |
| Finished | Aug 17 08:02:04 PM PDT 24 |
| Peak memory | 619216 kb |
| Host | smart-320e609e-92e4-4410-87a3-a67375ca24f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=192523074 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.chip_sw_uart_rand_baudrate.192523074 |
| Directory | /workspace/11.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.1565244425 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 3561829528 ps |
| CPU time | 455.8 seconds |
| Started | Aug 17 07:32:35 PM PDT 24 |
| Finished | Aug 17 07:40:11 PM PDT 24 |
| Peak memory | 649184 kb |
| Host | smart-5c4d7a2d-2e83-471c-a60f-402047d45942 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1565244425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1565244425 |
| Directory | /workspace/12.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3129530865 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 6022528273 ps |
| CPU time | 397.83 seconds |
| Started | Aug 17 07:33:43 PM PDT 24 |
| Finished | Aug 17 07:40:22 PM PDT 24 |
| Peak memory | 625452 kb |
| Host | smart-f208076a-f64b-4ac8-bafc-cea9b54fae99 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3129530865 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 12.chip_sw_lc_ctrl_transition.3129530865 |
| Directory | /workspace/12.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/12.chip_sw_uart_rand_baudrate.295111453 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 4524294886 ps |
| CPU time | 560.64 seconds |
| Started | Aug 17 07:33:55 PM PDT 24 |
| Finished | Aug 17 07:43:16 PM PDT 24 |
| Peak memory | 619804 kb |
| Host | smart-666a14c9-938c-451d-8c12-c5bac3ee9702 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=295111453 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.chip_sw_uart_rand_baudrate.295111453 |
| Directory | /workspace/12.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3347716364 |
| Short name | T1205 |
| Test name | |
| Test status | |
| Simulation time | 6222399393 ps |
| CPU time | 462.05 seconds |
| Started | Aug 17 07:32:39 PM PDT 24 |
| Finished | Aug 17 07:40:21 PM PDT 24 |
| Peak memory | 622032 kb |
| Host | smart-cd48d330-7211-45de-bc58-8eca10f982fb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347716364 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 13.chip_sw_lc_ctrl_transition.3347716364 |
| Directory | /workspace/13.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3105597426 |
| Short name | T1159 |
| Test name | |
| Test status | |
| Simulation time | 3421457800 ps |
| CPU time | 484.36 seconds |
| Started | Aug 17 07:32:23 PM PDT 24 |
| Finished | Aug 17 07:40:27 PM PDT 24 |
| Peak memory | 625152 kb |
| Host | smart-22624b88-6142-4c9c-975c-1582e306dd60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3105597426 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.chip_sw_uart_rand_baudrate.3105597426 |
| Directory | /workspace/13.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2195883333 |
| Short name | T1245 |
| Test name | |
| Test status | |
| Simulation time | 7472034581 ps |
| CPU time | 338.82 seconds |
| Started | Aug 17 07:31:15 PM PDT 24 |
| Finished | Aug 17 07:36:54 PM PDT 24 |
| Peak memory | 625436 kb |
| Host | smart-f1255ebd-cd28-4a2d-9ac2-fb1f37a58909 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195883333 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 14.chip_sw_lc_ctrl_transition.2195883333 |
| Directory | /workspace/14.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3717497367 |
| Short name | T1182 |
| Test name | |
| Test status | |
| Simulation time | 4466444730 ps |
| CPU time | 539.99 seconds |
| Started | Aug 17 07:31:25 PM PDT 24 |
| Finished | Aug 17 07:40:25 PM PDT 24 |
| Peak memory | 625148 kb |
| Host | smart-b9110eb3-222b-47e3-8eea-aa86a08b58cb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3717497367 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.chip_sw_uart_rand_baudrate.3717497367 |
| Directory | /workspace/14.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.4208189543 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 4311765008 ps |
| CPU time | 343.55 seconds |
| Started | Aug 17 07:31:33 PM PDT 24 |
| Finished | Aug 17 07:37:17 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-bea2dc6d-d052-4030-820c-922eb6dded28 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208189543 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_ sw_alert_handler_lpg_sleep_mode_alerts.4208189543 |
| Directory | /workspace/15.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/15.chip_sw_all_escalation_resets.2292725975 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 5216214590 ps |
| CPU time | 716.72 seconds |
| Started | Aug 17 07:34:43 PM PDT 24 |
| Finished | Aug 17 07:46:40 PM PDT 24 |
| Peak memory | 650700 kb |
| Host | smart-b13b4768-55d0-477f-8e2d-5f80a20c87bf |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2292725975 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_all_escalation_resets.2292725975 |
| Directory | /workspace/15.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.699329039 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 3786488872 ps |
| CPU time | 580.36 seconds |
| Started | Aug 17 07:32:42 PM PDT 24 |
| Finished | Aug 17 07:42:23 PM PDT 24 |
| Peak memory | 624168 kb |
| Host | smart-40e460a0-69a8-4c64-b612-0af3d8dd28d3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=699329039 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.chip_sw_uart_rand_baudrate.699329039 |
| Directory | /workspace/15.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/16.chip_sw_uart_rand_baudrate.2852024287 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 3597246560 ps |
| CPU time | 420.8 seconds |
| Started | Aug 17 07:34:05 PM PDT 24 |
| Finished | Aug 17 07:41:06 PM PDT 24 |
| Peak memory | 625164 kb |
| Host | smart-2d22843b-c140-412e-8612-0a5bf8d8d0c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2852024287 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.chip_sw_uart_rand_baudrate.2852024287 |
| Directory | /workspace/16.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.956343384 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 4128671668 ps |
| CPU time | 348.71 seconds |
| Started | Aug 17 07:31:57 PM PDT 24 |
| Finished | Aug 17 07:37:46 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-e897e22c-530e-46a2-9670-48aa7adff3f1 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=956343384 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_s w_alert_handler_lpg_sleep_mode_alerts.956343384 |
| Directory | /workspace/17.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/17.chip_sw_all_escalation_resets.336730745 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 5717974904 ps |
| CPU time | 699 seconds |
| Started | Aug 17 07:32:23 PM PDT 24 |
| Finished | Aug 17 07:44:02 PM PDT 24 |
| Peak memory | 651104 kb |
| Host | smart-2226b8bf-2d38-4682-bea8-6797a8c2fa1e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 336730745 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_all_escalation_resets.336730745 |
| Directory | /workspace/17.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3842416822 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 7787297640 ps |
| CPU time | 1441.61 seconds |
| Started | Aug 17 07:31:11 PM PDT 24 |
| Finished | Aug 17 07:55:13 PM PDT 24 |
| Peak memory | 625220 kb |
| Host | smart-a0480a23-755a-4a8b-8bbe-8f4cdf62a5d6 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3842416822 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.chip_sw_uart_rand_baudrate.3842416822 |
| Directory | /workspace/17.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600030989 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 4300184608 ps |
| CPU time | 439.62 seconds |
| Started | Aug 17 07:31:28 PM PDT 24 |
| Finished | Aug 17 07:38:49 PM PDT 24 |
| Peak memory | 649896 kb |
| Host | smart-bafb98db-c0af-4baf-867d-cf0e91fc8c6f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600030989 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2600030989 |
| Directory | /workspace/18.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/18.chip_sw_uart_rand_baudrate.861097599 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 4508505224 ps |
| CPU time | 655.16 seconds |
| Started | Aug 17 07:32:08 PM PDT 24 |
| Finished | Aug 17 07:43:04 PM PDT 24 |
| Peak memory | 625160 kb |
| Host | smart-0edda697-b035-4d67-99df-5c53d653657b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=861097599 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.chip_sw_uart_rand_baudrate.861097599 |
| Directory | /workspace/18.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767812141 |
| Short name | T1294 |
| Test name | |
| Test status | |
| Simulation time | 3435442636 ps |
| CPU time | 391.73 seconds |
| Started | Aug 17 07:32:18 PM PDT 24 |
| Finished | Aug 17 07:38:50 PM PDT 24 |
| Peak memory | 649568 kb |
| Host | smart-20617bad-cc22-4ec8-a614-fc369558eaa8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767812141 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2767812141 |
| Directory | /workspace/19.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/19.chip_sw_all_escalation_resets.3332377427 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 5467480012 ps |
| CPU time | 664.24 seconds |
| Started | Aug 17 07:34:04 PM PDT 24 |
| Finished | Aug 17 07:45:08 PM PDT 24 |
| Peak memory | 651008 kb |
| Host | smart-cbe0c296-3e3b-4610-a944-775da9970fa1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3332377427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_all_escalation_resets.3332377427 |
| Directory | /workspace/19.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1095978176 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 4580612964 ps |
| CPU time | 657.95 seconds |
| Started | Aug 17 07:31:00 PM PDT 24 |
| Finished | Aug 17 07:41:58 PM PDT 24 |
| Peak memory | 619476 kb |
| Host | smart-cacc01f7-cd4c-4c25-a224-2aba63a2f591 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1095978176 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.chip_sw_uart_rand_baudrate.1095978176 |
| Directory | /workspace/19.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_csr_rw.1017925339 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 10724359107 ps |
| CPU time | 1162.36 seconds |
| Started | Aug 17 07:18:13 PM PDT 24 |
| Finished | Aug 17 07:37:36 PM PDT 24 |
| Peak memory | 608568 kb |
| Host | smart-fd8898eb-b293-4001-8929-b8f08a1c0c98 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +csr_rw +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017925339 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_jtag_csr_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.c hip_jtag_csr_rw.1017925339 |
| Directory | /workspace/2.chip_jtag_csr_rw/latest |
| Test location | /workspace/coverage/default/2.chip_jtag_mem_access.700766321 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 13928083901 ps |
| CPU time | 1505.58 seconds |
| Started | Aug 17 07:18:24 PM PDT 24 |
| Finished | Aug 17 07:43:31 PM PDT 24 |
| Peak memory | 608580 kb |
| Host | smart-ec9da9d5-9cae-4d29-98ad-dc3fc8899553 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700766321 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_jtag_m em_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_jtag_mem_access.700766321 |
| Directory | /workspace/2.chip_jtag_mem_access/latest |
| Test location | /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.2124401836 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 4492431976 ps |
| CPU time | 537.85 seconds |
| Started | Aug 17 07:25:54 PM PDT 24 |
| Finished | Aug 17 07:34:52 PM PDT 24 |
| Peak memory | 624824 kb |
| Host | smart-112a5443-aab6-4bed-bcf7-a8a628f43ce3 |
| User | root |
| Command | /workspace/default/simv +en_scb_tl_err_chk=0 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_rma:1:new_rules,test_rom:0 +cdc_in strumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2 124401836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_rv_dm_ndm_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_rv_dm_ndm_reset_req.2124401836 |
| Directory | /workspace/2.chip_rv_dm_ndm_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sival_flash_info_access.550963171 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 3298113190 ps |
| CPU time | 273.46 seconds |
| Started | Aug 17 07:18:24 PM PDT 24 |
| Finished | Aug 17 07:22:58 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-6729083f-4778-4001-aa35-e99f44475184 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_images=flash_ctrl_info_access_lc:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=550963171 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sival_flash_info_access.550963171 |
| Directory | /workspace/2.chip_sival_flash_info_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3222664371 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 19017902948 ps |
| CPU time | 641.5 seconds |
| Started | Aug 17 07:25:04 PM PDT 24 |
| Finished | Aug 17 07:35:47 PM PDT 24 |
| Peak memory | 619404 kb |
| Host | smart-cba1343a-0935-4131-80e0-015067f503ed |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=adc_ctrl_sleep_debug_cable_wakeup_test:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=3222664371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq +en_cov=1 -cm line +cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3222664371 |
| Directory | /workspace/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc.2732335495 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 3546923716 ps |
| CPU time | 341.79 seconds |
| Started | Aug 17 07:23:22 PM PDT 24 |
| Finished | Aug 17 07:29:04 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-3ac932fb-52a1-47f9-bee5-b0ed1da840db |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=22_000_000 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732335495 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc.2732335495 |
| Directory | /workspace/2.chip_sw_aes_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.796466340 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 2397650807 ps |
| CPU time | 282.84 seconds |
| Started | Aug 17 07:25:05 PM PDT 24 |
| Finished | Aug 17 07:29:48 PM PDT 24 |
| Peak memory | 610360 kb |
| Host | smart-e35b6b24-d839-4ffe-89d0-fa2b50486cf3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7964 66340 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en.796466340 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2088904077 |
| Short name | T1320 |
| Test name | |
| Test status | |
| Simulation time | 2886299129 ps |
| CPU time | 221.39 seconds |
| Started | Aug 17 07:28:22 PM PDT 24 |
| Finished | Aug 17 07:32:04 PM PDT 24 |
| Peak memory | 610100 kb |
| Host | smart-71c0ed01-9495-48b1-91d5-2e0e60fe09eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=26_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088904077 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_enc_jitter_en_reduced_freq.2088904077 |
| Directory | /workspace/2.chip_sw_aes_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_entropy.3829748641 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 3024290760 ps |
| CPU time | 234.03 seconds |
| Started | Aug 17 07:23:43 PM PDT 24 |
| Finished | Aug 17 07:27:37 PM PDT 24 |
| Peak memory | 609988 kb |
| Host | smart-99fed299-3f75-46ba-b476-a99ed90716ab |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=aes_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829748641 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_entropy.3829748641 |
| Directory | /workspace/2.chip_sw_aes_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_idle.2378655858 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 3137144532 ps |
| CPU time | 208.2 seconds |
| Started | Aug 17 07:25:15 PM PDT 24 |
| Finished | Aug 17 07:28:43 PM PDT 24 |
| Peak memory | 609364 kb |
| Host | smart-d7fe2c56-9cb9-421f-a123-fc9cb57d8e2e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=aes_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_en abled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378655858 -asser t nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_idle.2378655858 |
| Directory | /workspace/2.chip_sw_aes_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_masking_off.998683111 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 3815393966 ps |
| CPU time | 342.64 seconds |
| Started | Aug 17 07:23:32 PM PDT 24 |
| Finished | Aug 17 07:29:15 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-ac05576d-15c6-4864-a3f3-e3921afdc7eb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_masking_off_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=998683111 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_aes_masking_off_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_masking_off.998683111 |
| Directory | /workspace/2.chip_sw_aes_masking_off/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aes_smoketest.1107957784 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2572409480 ps |
| CPU time | 261.95 seconds |
| Started | Aug 17 07:27:43 PM PDT 24 |
| Finished | Aug 17 07:32:05 PM PDT 24 |
| Peak memory | 610376 kb |
| Host | smart-6d05b397-5998-4815-9a11-8d57e0483974 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1107957784 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aes_smoketest.1107957784 |
| Directory | /workspace/2.chip_sw_aes_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_entropy.127330724 |
| Short name | T1217 |
| Test name | |
| Test status | |
| Simulation time | 3475110274 ps |
| CPU time | 342.8 seconds |
| Started | Aug 17 07:25:31 PM PDT 24 |
| Finished | Aug 17 07:31:14 PM PDT 24 |
| Peak memory | 610208 kb |
| Host | smart-a046a378-f191-499b-a586-f64fca6b071a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_entropy_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=127330724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_entropy_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_entropy.127330724 |
| Directory | /workspace/2.chip_sw_alert_handler_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_escalation.1526680427 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 5136125232 ps |
| CPU time | 505.38 seconds |
| Started | Aug 17 07:22:34 PM PDT 24 |
| Finished | Aug 17 07:31:00 PM PDT 24 |
| Peak memory | 619968 kb |
| Host | smart-1f9b5645-e600-4d36-b24c-6506769d5803 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test _rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb _random_seed=1526680427 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_escalation_vseq +en_cov=1 -cm line+con d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_escalation.1526680427 |
| Directory | /workspace/2.chip_sw_alert_handler_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.558382328 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 8534775016 ps |
| CPU time | 1657.74 seconds |
| Started | Aug 17 07:24:09 PM PDT 24 |
| Finished | Aug 17 07:51:48 PM PDT 24 |
| Peak memory | 610816 kb |
| Host | smart-7c3bfe6e-b3b5-4ab8-aa9b-59f1d6f07628 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_clkoff_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=558382328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_lpg_clkoff_vseq +en_cov=1 -cm line+cond+f sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_clkoff.558382328 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_clkoff/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1990309515 |
| Short name | T1280 |
| Test name | |
| Test status | |
| Simulation time | 7468617780 ps |
| CPU time | 1363.08 seconds |
| Started | Aug 17 07:23:23 PM PDT 24 |
| Finished | Aug 17 07:46:07 PM PDT 24 |
| Peak memory | 611164 kb |
| Host | smart-6eafa00b-edd5-4af4-a80b-52c06eb95492 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_lpg_reset_toggle_test:1:new_rules, test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990309515 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_handler_shorten_ping_wait_cycle_vseq +en_c ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_reset_togg le.1990309515 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_reset_toggle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3154691533 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 3636225494 ps |
| CPU time | 484.91 seconds |
| Started | Aug 17 07:25:35 PM PDT 24 |
| Finished | Aug 17 07:33:40 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-8271b967-b5f6-4807-bbbd-1c6959d04915 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3154691533 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_s w_alert_handler_lpg_sleep_mode_alerts.3154691533 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3468619235 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 10012410784 ps |
| CPU time | 1023.44 seconds |
| Started | Aug 17 07:28:13 PM PDT 24 |
| Finished | Aug 17 07:45:16 PM PDT 24 |
| Peak memory | 611608 kb |
| Host | smart-d3511682-f81c-47a6-85f4-fbf19eed36ce |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=alert_handler _lpg_sleep_mode_pings_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468619235 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_alert_han dler_shorten_ping_wait_cycle_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_lpg_sleep_mode_pings.3468619235 |
| Directory | /workspace/2.chip_sw_alert_handler_lpg_sleep_mode_pings/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_ok.3813499837 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 8060823836 ps |
| CPU time | 1307.73 seconds |
| Started | Aug 17 07:23:19 PM PDT 24 |
| Finished | Aug 17 07:45:07 PM PDT 24 |
| Peak memory | 610616 kb |
| Host | smart-ff4001da-08c1-47d2-96a5-4e7198466e07 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_ok_test:1:new_rules,test_rom:0 +c dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_s eed=3813499837 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_ok.3813499837 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_ok/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3826554922 |
| Short name | T1175 |
| Test name | |
| Test status | |
| Simulation time | 5067105536 ps |
| CPU time | 435.59 seconds |
| Started | Aug 17 07:24:31 PM PDT 24 |
| Finished | Aug 17 07:31:47 PM PDT 24 |
| Peak memory | 610112 kb |
| Host | smart-294c2421-21fa-42e1-ab02-be413ff4faaa |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=24000000 +sw_build_device=sim_dv +sw_images=alert_handler_ping_timeout_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=3826554922 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_ping_timeout.3826554922 |
| Directory | /workspace/2.chip_sw_alert_handler_ping_timeout/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3341078018 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 255408159112 ps |
| CPU time | 12435.3 seconds |
| Started | Aug 17 07:23:56 PM PDT 24 |
| Finished | Aug 17 10:51:13 PM PDT 24 |
| Peak memory | 611328 kb |
| Host | smart-2e4dbdac-48f6-4d1c-93fa-11d9cb7388fd |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=300_000_000 +sw_build_device=sim_dv +sw_images=alert_handler_reverse_ping_in_deep_sleep_test:1:n ew_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=3341078018 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3341078018 |
| Directory | /workspace/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest |
| Test location | /workspace/coverage/default/2.chip_sw_alert_test.1379471082 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3147754410 ps |
| CPU time | 388.65 seconds |
| Started | Aug 17 07:25:24 PM PDT 24 |
| Finished | Aug 17 07:31:53 PM PDT 24 |
| Peak memory | 609676 kb |
| Host | smart-62b2586b-2973-4c1a-b274-aaf2837cacd9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=alert_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERB OSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1379471082 -assert nopostproc +UVM_TESTNAME=chip_ba se_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -c m_name 2.chip_sw_alert_test.1379471082 |
| Directory | /workspace/2.chip_sw_alert_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_irq.2830553380 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 3677498154 ps |
| CPU time | 532.82 seconds |
| Started | Aug 17 07:21:55 PM PDT 24 |
| Finished | Aug 17 07:30:48 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-c0e1f979-8d06-4bf0-8a85-804220b31428 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_irq_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2830553380 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_irq.2830553380 |
| Directory | /workspace/2.chip_sw_aon_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.273825506 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 8440496608 ps |
| CPU time | 596.67 seconds |
| Started | Aug 17 07:24:09 PM PDT 24 |
| Finished | Aug 17 07:34:06 PM PDT 24 |
| Peak memory | 611052 kb |
| Host | smart-3037f8c3-960d-4e1c-89f3-de884a25a40d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=273825506 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_sleep_wdog_sleep_pause.273825506 |
| Directory | /workspace/2.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2533158785 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 3312013736 ps |
| CPU time | 284.93 seconds |
| Started | Aug 17 07:27:17 PM PDT 24 |
| Finished | Aug 17 07:32:02 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-73a90ef6-0a5a-4513-8615-8b166e82ff94 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=aon_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533158785 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_aon_timer_smoketest.2533158785 |
| Directory | /workspace/2.chip_sw_aon_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.500874066 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 9874508570 ps |
| CPU time | 948.34 seconds |
| Started | Aug 17 07:23:45 PM PDT 24 |
| Finished | Aug 17 07:39:33 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-df603c31-7b7c-4522-9f09-69bbebf9ddda |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_bite_reset_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 500874066 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_bite_reset.500874066 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_bite_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2749914003 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 5805242820 ps |
| CPU time | 572.38 seconds |
| Started | Aug 17 07:24:43 PM PDT 24 |
| Finished | Aug 17 07:34:16 PM PDT 24 |
| Peak memory | 610964 kb |
| Host | smart-8758ab08-3820-4e0d-95c2-d475099c96f5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_wdog_lc_escalate_test:1:new_rules,test_rom:0 +cdc_ instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed =2749914003 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_aon_timer_wdog_lc_escalate.2749914003 |
| Directory | /workspace/2.chip_sw_aon_timer_wdog_lc_escalate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_outputs.390202423 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 8075524520 ps |
| CPU time | 1329.99 seconds |
| Started | Aug 17 07:24:37 PM PDT 24 |
| Finished | Aug 17 07:46:47 PM PDT 24 |
| Peak memory | 617872 kb |
| Host | smart-09f176e9-4c61-4155-8e06-18ebafc0dd20 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=ast_clk_outs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled= 1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390202423 -assert nopos tproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_outputs.390202423 |
| Directory | /workspace/2.chip_sw_ast_clk_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_ast_clk_rst_inputs.992095098 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 22433329897 ps |
| CPU time | 3045.68 seconds |
| Started | Aug 17 07:27:03 PM PDT 24 |
| Finished | Aug 17 08:17:50 PM PDT 24 |
| Peak memory | 611180 kb |
| Host | smart-c6d7780c-654f-4102-8c59-fce1dfe64f89 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +sw_build_device=sim_dv +sw_images=ast_clk_rst_inputs:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992095098 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_ast_clk_rst_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_ast_clk_rst_inputs.992095098 |
| Directory | /workspace/2.chip_sw_ast_clk_rst_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3808245378 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 6109833870 ps |
| CPU time | 382.85 seconds |
| Started | Aug 17 07:25:29 PM PDT 24 |
| Finished | Aug 17 07:31:53 PM PDT 24 |
| Peak memory | 625460 kb |
| Host | smart-39051744-8e42-48e5-9251-5836ec6be876 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +sw_images=clkmgr_external_clk_src_for_lc_test:1:new_r ules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim .tcl +ntb_random_seed=3808245378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_external_clk_src_for_lc.3808245378 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_lc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.383630186 |
| Short name | T1179 |
| Test name | |
| Test status | |
| Simulation time | 3783900276 ps |
| CPU time | 631.28 seconds |
| Started | Aug 17 07:25:23 PM PDT 24 |
| Finished | Aug 17 07:35:54 PM PDT 24 |
| Peak memory | 613840 kb |
| Host | smart-82477b3b-b051-4b96-80a1-163a77d95226 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383630186 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_fast_dev.383630186 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.86004408 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 4598975752 ps |
| CPU time | 681.49 seconds |
| Started | Aug 17 07:25:58 PM PDT 24 |
| Finished | Aug 17 07:37:19 PM PDT 24 |
| Peak memory | 614696 kb |
| Host | smart-0bbd09b7-cbb1-43e0-b23e-5bf196ea8f2b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86004408 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clk mgr_external_clk_src_for_sw_fast_rma.86004408 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1375317708 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 3824025292 ps |
| CPU time | 590.79 seconds |
| Started | Aug 17 07:25:58 PM PDT 24 |
| Finished | Aug 17 07:35:50 PM PDT 24 |
| Peak memory | 613924 kb |
| Host | smart-e8b09a40-b863-4851-be85-2251e862b647 |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_fast_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375317708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UV M_TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2 .chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1375317708 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.233337963 |
| Short name | T1253 |
| Test name | |
| Test status | |
| Simulation time | 4302295792 ps |
| CPU time | 611.81 seconds |
| Started | Aug 17 07:25:43 PM PDT 24 |
| Finished | Aug 17 07:35:55 PM PDT 24 |
| Peak memory | 614872 kb |
| Host | smart-c767c3f7-8330-47fe-b3c1-9ce2eba9c6ff |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStDev +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233337963 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_cl kmgr_external_clk_src_for_sw_slow_dev.233337963 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4079148540 |
| Short name | T1302 |
| Test name | |
| Test status | |
| Simulation time | 4612036840 ps |
| CPU time | 637.7 seconds |
| Started | Aug 17 07:25:50 PM PDT 24 |
| Finished | Aug 17 07:36:28 PM PDT 24 |
| Peak memory | 614616 kb |
| Host | smart-44fbe4ce-47c9-4413-9b7c-39cf5e236f8b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStRma +sw_build_device=sim_dv +sw_ima ges=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079148540 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_c lkmgr_external_clk_src_for_sw_slow_rma.4079148540 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.947359432 |
| Short name | T1252 |
| Test name | |
| Test status | |
| Simulation time | 4623159242 ps |
| CPU time | 691.85 seconds |
| Started | Aug 17 07:26:15 PM PDT 24 |
| Finished | Aug 17 07:37:47 PM PDT 24 |
| Peak memory | 614928 kb |
| Host | smart-bca0d58c-cbcc-4991-8d74-bb68e160f65b |
| User | root |
| Command | /workspace/default/simv +chip_clock_source=ChipClockSourceExternal48Mhz +calibrate_usb_clk=1 +src_dec_state=DecLcStTestUnlocked0 +sw_build_device=sim_ dv +sw_images=clkmgr_external_clk_src_for_sw_slow_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L OW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947359432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM _TEST_SEQ=chip_sw_lc_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2. chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.947359432 |
| Directory | /workspace/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter.3607265924 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 2349644872 ps |
| CPU time | 227.69 seconds |
| Started | Aug 17 07:26:13 PM PDT 24 |
| Finished | Aug 17 07:30:01 PM PDT 24 |
| Peak memory | 609356 kb |
| Host | smart-e6878375-801e-4d21-9d03-16ee0cce041a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607265924 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_clkmgr_jitter.3607265924 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3238418638 |
| Short name | T1300 |
| Test name | |
| Test status | |
| Simulation time | 3010907760 ps |
| CPU time | 440.76 seconds |
| Started | Aug 17 07:25:20 PM PDT 24 |
| Finished | Aug 17 07:32:41 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-21768bda-f906-48f3-ab2f-80fa2a28d5e4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_jitter_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3238418638 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_frequency.3238418638 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2775248021 |
| Short name | T1306 |
| Test name | |
| Test status | |
| Simulation time | 2768397945 ps |
| CPU time | 243.97 seconds |
| Started | Aug 17 07:26:59 PM PDT 24 |
| Finished | Aug 17 07:31:04 PM PDT 24 |
| Peak memory | 609280 kb |
| Host | smart-55ae6881-1c9c-41d3-b2f6-e758e8038149 |
| User | root |
| Command | /workspace/default/simv +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=clkmgr_jitter_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2775248021 -assert nop ostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_jitter_reduced_freq.2775248021 |
| Directory | /workspace/2.chip_sw_clkmgr_jitter_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3374776843 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 4764134040 ps |
| CPU time | 472.86 seconds |
| Started | Aug 17 07:26:11 PM PDT 24 |
| Finished | Aug 17 07:34:04 PM PDT 24 |
| Peak memory | 610128 kb |
| Host | smart-54e28d4c-8a3c-4da0-9081-aee5af88ba70 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_aes_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374776843 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_aes_trans.3374776843 |
| Directory | /workspace/2.chip_sw_clkmgr_off_aes_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3578085945 |
| Short name | T1262 |
| Test name | |
| Test status | |
| Simulation time | 4415091122 ps |
| CPU time | 442.48 seconds |
| Started | Aug 17 07:25:41 PM PDT 24 |
| Finished | Aug 17 07:33:03 PM PDT 24 |
| Peak memory | 609932 kb |
| Host | smart-6d0ec69d-f052-459d-81b7-68eec4c82fda |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_hmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578085945 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_hmac_trans.3578085945 |
| Directory | /workspace/2.chip_sw_clkmgr_off_hmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2818123442 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 5251862984 ps |
| CPU time | 533.83 seconds |
| Started | Aug 17 07:25:00 PM PDT 24 |
| Finished | Aug 17 07:33:54 PM PDT 24 |
| Peak memory | 611148 kb |
| Host | smart-d3ded786-f1b6-4279-af19-08098d582bcd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_kmac_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818123442 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_ log /dev/null -cm_name 2.chip_sw_clkmgr_off_kmac_trans.2818123442 |
| Directory | /workspace/2.chip_sw_clkmgr_off_kmac_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.881397831 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 4660639244 ps |
| CPU time | 511.68 seconds |
| Started | Aug 17 07:24:48 PM PDT 24 |
| Finished | Aug 17 07:33:20 PM PDT 24 |
| Peak memory | 610032 kb |
| Host | smart-c9cc5e8b-27a7-408d-9b32-a693b7155cc5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_off_otbn_trans_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881397831 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_clkmgr_off_otbn_trans.881397831 |
| Directory | /workspace/2.chip_sw_clkmgr_off_otbn_trans/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1651161359 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 9568535810 ps |
| CPU time | 1220.76 seconds |
| Started | Aug 17 07:25:01 PM PDT 24 |
| Finished | Aug 17 07:45:22 PM PDT 24 |
| Peak memory | 611196 kb |
| Host | smart-28c9f9e2-ad0f-4491-966e-ac6dd20738b7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=30_000_000 +sw_build_device=sim_dv +sw_images=clkmgr_off_peri_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651161359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_off_peri.1651161359 |
| Directory | /workspace/2.chip_sw_clkmgr_off_peri/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.567451952 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 3370672952 ps |
| CPU time | 392.16 seconds |
| Started | Aug 17 07:24:59 PM PDT 24 |
| Finished | Aug 17 07:31:31 PM PDT 24 |
| Peak memory | 610400 kb |
| Host | smart-bea56c6b-bf8e-4286-87e4-97fa891bf199 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_reset_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=567451952 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_reset_frequency.567451952 |
| Directory | /workspace/2.chip_sw_clkmgr_reset_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1300085655 |
| Short name | T1338 |
| Test name | |
| Test status | |
| Simulation time | 4580136880 ps |
| CPU time | 530.2 seconds |
| Started | Aug 17 07:25:21 PM PDT 24 |
| Finished | Aug 17 07:34:11 PM PDT 24 |
| Peak memory | 610632 kb |
| Host | smart-5d61e70f-0c3d-4361-953d-1f10b151a271 |
| User | root |
| Command | /workspace/default/simv +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=clkmgr_sleep_frequency_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1300085655 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cov erage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_clkmgr_sleep_frequency.1300085655 |
| Directory | /workspace/2.chip_sw_clkmgr_sleep_frequency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3214772063 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 2792037176 ps |
| CPU time | 201.96 seconds |
| Started | Aug 17 07:30:32 PM PDT 24 |
| Finished | Aug 17 07:33:54 PM PDT 24 |
| Peak memory | 609924 kb |
| Host | smart-2a910e0f-768d-41e2-aa04-11749356aec7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=clkmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214772063 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_clkmgr_smoketest.3214772063 |
| Directory | /workspace/2.chip_sw_clkmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.653039616 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 17433900680 ps |
| CPU time | 3972.77 seconds |
| Started | Aug 17 07:24:02 PM PDT 24 |
| Finished | Aug 17 08:30:15 PM PDT 24 |
| Peak memory | 610792 kb |
| Host | smart-b800c978-1bf7-4f37-bf8c-a8d5e5563b9b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653039616 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency.653039616 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2978470962 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 132465682167 ps |
| CPU time | 17709.9 seconds |
| Started | Aug 17 07:27:53 PM PDT 24 |
| Finished | Aug 18 12:23:05 AM PDT 24 |
| Peak memory | 610824 kb |
| Host | smart-f97a738e-a25d-4e6c-bc21-83399270909e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=360_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +cal_sys_clk_70mhz=1 +en_jitter=1 +sw_build_de vice=sim_dv +sw_images=csrng_edn_concurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=2978470962 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_edn_concurrency_reduced_freq.2978470962 |
| Directory | /workspace/2.chip_sw_csrng_edn_concurrency_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.1979406636 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 4539987156 ps |
| CPU time | 706.44 seconds |
| Started | Aug 17 07:24:22 PM PDT 24 |
| Finished | Aug 17 07:36:09 PM PDT 24 |
| Peak memory | 610392 kb |
| Host | smart-55a74e26-6422-4197-81f2-d32b04f5287f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=csrng_fuse_en_sw_app_read:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19794 06636 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_entropy_src_fuse_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_fuse_en_sw_app_read_test.1979406636 |
| Directory | /workspace/2.chip_sw_csrng_fuse_en_sw_app_read_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_kat_test.1835826415 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 2517980288 ps |
| CPU time | 260.2 seconds |
| Started | Aug 17 07:28:14 PM PDT 24 |
| Finished | Aug 17 07:32:35 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-053ef4e0-aa77-4a74-8c70-3e48d85ad764 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=csrng_kat_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835826415 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csrng_kat_test.1835826415 |
| Directory | /workspace/2.chip_sw_csrng_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_lc_hw_debug_en_test.3566772536 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 5680857540 ps |
| CPU time | 764.32 seconds |
| Started | Aug 17 07:24:33 PM PDT 24 |
| Finished | Aug 17 07:37:18 PM PDT 24 |
| Peak memory | 611840 kb |
| Host | smart-57ad61da-5bc0-4aec-8f6b-86a6e142767a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +rng_srate_value_min=15 +use_otp_image=OtpTypeLcStTestUnlocked0 +sw_build_device=sim_dv +sw_ima ges=csrng_lc_hw_debug_en_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566772536 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_csrng_ lc_hw_debug_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_csr ng_lc_hw_debug_en_test.3566772536 |
| Directory | /workspace/2.chip_sw_csrng_lc_hw_debug_en_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_csrng_smoketest.2104633025 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 2467779952 ps |
| CPU time | 300.24 seconds |
| Started | Aug 17 07:27:39 PM PDT 24 |
| Finished | Aug 17 07:32:40 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-d4258991-cfdc-4e60-b70b-41a4136aaabd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=csrng_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104633025 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_csrng_smoketest.2104633025 |
| Directory | /workspace/2.chip_sw_csrng_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_data_integrity_escalation.2063843866 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 4881177448 ps |
| CPU time | 821.08 seconds |
| Started | Aug 17 07:19:31 PM PDT 24 |
| Finished | Aug 17 07:33:12 PM PDT 24 |
| Peak memory | 611708 kb |
| Host | smart-552f165d-2325-4fa6-99e2-25f8595122f3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2063843866 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_data_integrity_escalation.2063843866 |
| Directory | /workspace/2.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_auto_mode.2488461184 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 4432801330 ps |
| CPU time | 1016.24 seconds |
| Started | Aug 17 07:24:29 PM PDT 24 |
| Finished | Aug 17 07:41:25 PM PDT 24 |
| Peak memory | 610104 kb |
| Host | smart-1527c34c-7196-4b98-8f2f-2dbc055061b5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_auto_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488461184 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ =chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_ auto_mode.2488461184 |
| Directory | /workspace/2.chip_sw_edn_auto_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_boot_mode.793466174 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 3406242296 ps |
| CPU time | 628.72 seconds |
| Started | Aug 17 07:24:03 PM PDT 24 |
| Finished | Aug 17 07:34:32 PM PDT 24 |
| Peak memory | 610264 kb |
| Host | smart-9e27f2b9-a926-42ad-ab9f-ad69a1070854 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +sw_build_device=sim_dv +sw_images=edn_boot_mode:1:new_rules,test_rom:0 +acc elerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licque ue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=793466174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_b oot_mode.793466174 |
| Directory | /workspace/2.chip_sw_edn_boot_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs.552653704 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 7367853696 ps |
| CPU time | 1272.25 seconds |
| Started | Aug 17 07:24:39 PM PDT 24 |
| Finished | Aug 17 07:45:52 PM PDT 24 |
| Peak memory | 611260 kb |
| Host | smart-53d9f48e-acf6-49a5-b045-06ea91d90d0b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ed n_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_ top/hw/dv/tools/sim.tcl +ntb_random_seed=552653704 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs.552653704 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.2487570984 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 8059354565 ps |
| CPU time | 1227.38 seconds |
| Started | Aug 17 07:30:09 PM PDT 24 |
| Finished | Aug 17 07:50:37 PM PDT 24 |
| Peak memory | 610568 kb |
| Host | smart-66d808c9-184e-4ba9-83e1-f8a57d041897 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15000000 +rng_srate_value_min=15 +rng_srate_value_max=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=e ntropy_src_edn_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487570984 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_entropy_reqs_jitter.2487570984 |
| Directory | /workspace/2.chip_sw_edn_entropy_reqs_jitter/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_kat.1178114516 |
| Short name | T1218 |
| Test name | |
| Test status | |
| Simulation time | 3436815114 ps |
| CPU time | 728.71 seconds |
| Started | Aug 17 07:23:46 PM PDT 24 |
| Finished | Aug 17 07:35:55 PM PDT 24 |
| Peak memory | 615916 kb |
| Host | smart-98fdd1b0-367c-4a10-b106-a4058f2de5ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=5 +disable_assert_edn_output_diff_from_prev=1 +sw_build_device=sim_dv +sw_imag es=edn_kat:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178114516 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_edn_kat.1178114516 |
| Directory | /workspace/2.chip_sw_edn_kat/latest |
| Test location | /workspace/coverage/default/2.chip_sw_edn_sw_mode.1509079335 |
| Short name | T1239 |
| Test name | |
| Test status | |
| Simulation time | 7046321432 ps |
| CPU time | 1269.34 seconds |
| Started | Aug 17 07:25:20 PM PDT 24 |
| Finished | Aug 17 07:46:29 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-22ec7c35-7b42-4293-b6ca-7090e13c51e3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=edn_sw_mode:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509079335 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_edn_sw_mode.1509079335 |
| Directory | /workspace/2.chip_sw_edn_sw_mode/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.1560533661 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 3002451580 ps |
| CPU time | 263.1 seconds |
| Started | Aug 17 07:25:51 PM PDT 24 |
| Finished | Aug 17 07:30:14 PM PDT 24 |
| Peak memory | 610120 kb |
| Host | smart-ba21ced9-bd72-45d2-a2b2-49b151effd5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_ast_rng_req_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15 60533661 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo rkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_ast_rng_req.1560533661 |
| Directory | /workspace/2.chip_sw_entropy_src_ast_rng_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4021869225 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 6669593940 ps |
| CPU time | 1127.93 seconds |
| Started | Aug 17 07:31:21 PM PDT 24 |
| Finished | Aug 17 07:50:10 PM PDT 24 |
| Peak memory | 610132 kb |
| Host | smart-4d5b4b42-a26c-4f6e-ad7a-38b894764946 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_ csrng_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_t op/hw/dv/tools/sim.tcl +ntb_random_seed=4021869225 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_csrng.4021869225 |
| Directory | /workspace/2.chip_sw_entropy_src_csrng/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_kat_test.3674518228 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2904102380 ps |
| CPU time | 229.7 seconds |
| Started | Aug 17 07:23:29 PM PDT 24 |
| Finished | Aug 17 07:27:19 PM PDT 24 |
| Peak memory | 609380 kb |
| Host | smart-a3a6d4db-48bc-4b91-8b2e-102afffdb59e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=entropy_src_kat_test:1:new_rules,test_rom:0 +cdc_instrumenta tion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674518228 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_kat_test.3674518228 |
| Directory | /workspace/2.chip_sw_entropy_src_kat_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1568124043 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 3141831720 ps |
| CPU time | 475.55 seconds |
| Started | Aug 17 07:27:55 PM PDT 24 |
| Finished | Aug 17 07:35:50 PM PDT 24 |
| Peak memory | 609404 kb |
| Host | smart-9270dbcc-2542-4a6a-b641-7683d714fd52 |
| User | root |
| Command | /workspace/default/simv +rng_srate_value_min=15 +rng_srate_value_max=30 +sw_build_device=sim_dv +sw_images=entropy_src_smoketest:1:new_rules,test_rom: 0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rand om_seed=1568124043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert - cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_entropy_src_smoketest.1568124043 |
| Directory | /workspace/2.chip_sw_entropy_src_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_concurrency.1142746577 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2704736824 ps |
| CPU time | 250.05 seconds |
| Started | Aug 17 07:19:58 PM PDT 24 |
| Finished | Aug 17 07:24:08 PM PDT 24 |
| Peak memory | 609956 kb |
| Host | smart-a0e1adb8-64df-4449-ab1c-706351a79608 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_concurrency_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1142746577 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_lo g /dev/null -cm_name 2.chip_sw_example_concurrency.1142746577 |
| Directory | /workspace/2.chip_sw_example_concurrency/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_flash.1796814898 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 2992097648 ps |
| CPU time | 281.24 seconds |
| Started | Aug 17 07:22:37 PM PDT 24 |
| Finished | Aug 17 07:27:19 PM PDT 24 |
| Peak memory | 609368 kb |
| Host | smart-59f5422e-3c86-4dca-8213-7d81b17cd257 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_flash:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796814898 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_flash.1796814898 |
| Directory | /workspace/2.chip_sw_example_flash/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_manufacturer.2217317044 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 2679455224 ps |
| CPU time | 220.64 seconds |
| Started | Aug 17 07:18:42 PM PDT 24 |
| Finished | Aug 17 07:22:23 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-add9dca9-1594-47f9-9915-6c25a7eb018c |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VE RBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2217317044 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_manufacturer.2217317044 |
| Directory | /workspace/2.chip_sw_example_manufacturer/latest |
| Test location | /workspace/coverage/default/2.chip_sw_example_rom.2056315843 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2326951016 ps |
| CPU time | 106.23 seconds |
| Started | Aug 17 07:18:02 PM PDT 24 |
| Finished | Aug 17 07:19:48 PM PDT 24 |
| Peak memory | 609800 kb |
| Host | smart-b2a9a337-dedc-4c5c-a38a-368e89d4cf7f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOT ES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056315843 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_example_rom.2056315843 |
| Directory | /workspace/2.chip_sw_example_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.3025667323 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 57263753415 ps |
| CPU time | 10742.4 seconds |
| Started | Aug 17 07:19:52 PM PDT 24 |
| Finished | Aug 17 10:18:56 PM PDT 24 |
| Peak memory | 625524 kb |
| Host | smart-f4b266a2-a5d4-4147-ad09-85c007d07497 |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=exit_test_unlocked_bootstrap:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=3025667323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_exit_test_unlocked_bootstrap_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_exit_test_unlocked_bootstrap.3025667323 |
| Directory | /workspace/2.chip_sw_exit_test_unlocked_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_crash_alert.2250956458 |
| Short name | T1250 |
| Test name | |
| Test status | |
| Simulation time | 5874697024 ps |
| CPU time | 728.28 seconds |
| Started | Aug 17 07:26:05 PM PDT 24 |
| Finished | Aug 17 07:38:14 PM PDT 24 |
| Peak memory | 611736 kb |
| Host | smart-0e27bf7c-18b4-4a37-9dc5-17169d437c62 |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1: new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tool s/sim.tcl +ntb_random_seed=2250956458 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_host_gnt_err_inj_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_crash_alert.2250956458 |
| Directory | /workspace/2.chip_sw_flash_crash_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3548117005 |
| Short name | T1196 |
| Test name | |
| Test status | |
| Simulation time | 5764715598 ps |
| CPU time | 1168.66 seconds |
| Started | Aug 17 07:22:01 PM PDT 24 |
| Finished | Aug 17 07:41:29 PM PDT 24 |
| Peak memory | 609756 kb |
| Host | smart-d4fbc96d-6c85-4ff3-bb58-4550a9d499c3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM _VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548117005 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_flash_ctrl_access.3548117005 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1216011329 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 6555262959 ps |
| CPU time | 1045.69 seconds |
| Started | Aug 17 07:20:31 PM PDT 24 |
| Finished | Aug 17 07:37:58 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-2fa1a90c-d203-4b2c-8eef-c7efc9dd970e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216011329 -assert nopostproc +UV M_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c m_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en.1216011329 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1339716477 |
| Short name | T1155 |
| Test name | |
| Test status | |
| Simulation time | 7743525336 ps |
| CPU time | 1133.08 seconds |
| Started | Aug 17 07:26:17 PM PDT 24 |
| Finished | Aug 17 07:45:10 PM PDT 24 |
| Peak memory | 609736 kb |
| Host | smart-eed4a473-135c-4d5f-9c6d-3559f71b6540 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentati on_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339716477 - assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1339716477 |
| Directory | /workspace/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2526015837 |
| Short name | T1241 |
| Test name | |
| Test status | |
| Simulation time | 5201949312 ps |
| CPU time | 1028.68 seconds |
| Started | Aug 17 07:22:17 PM PDT 24 |
| Finished | Aug 17 07:39:26 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-0d01f37e-2048-40e4-b841-98b122ba98a0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_clock_freqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_R ELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526015837 -assert nopostproc +UVM _TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_flash_ctrl_clock_freqs.2526015837 |
| Directory | /workspace/2.chip_sw_flash_ctrl_clock_freqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2807801194 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 3940977880 ps |
| CPU time | 340.65 seconds |
| Started | Aug 17 07:21:49 PM PDT 24 |
| Finished | Aug 17 07:27:30 PM PDT 24 |
| Peak memory | 610516 kb |
| Host | smart-2fff8561-cf7c-4feb-b965-a084a67495a2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_idle_low_power_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807801194 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_idle_low_power.2807801194 |
| Directory | /workspace/2.chip_sw_flash_ctrl_idle_low_power/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.884562280 |
| Short name | T1260 |
| Test name | |
| Test status | |
| Simulation time | 4821043240 ps |
| CPU time | 492.12 seconds |
| Started | Aug 17 07:21:12 PM PDT 24 |
| Finished | Aug 17 07:29:24 PM PDT 24 |
| Peak memory | 610484 kb |
| Host | smart-31db9d81-ee9e-4ffb-b972-6d30cbd52908 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_lc_rw_en_test:1:new_rules,test_rom:0 +cdc_ins trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88 4562280 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_ctrl_lc_rw_en_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_lc_rw_en.884562280 |
| Directory | /workspace/2.chip_sw_flash_ctrl_lc_rw_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.2537807672 |
| Short name | T1165 |
| Test name | |
| Test status | |
| Simulation time | 5890502704 ps |
| CPU time | 1050.47 seconds |
| Started | Aug 17 07:27:48 PM PDT 24 |
| Finished | Aug 17 07:45:18 PM PDT 24 |
| Peak memory | 609884 kb |
| Host | smart-6cfdff2c-33b6-4df5-900b-2a7c2223da45 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=flash_ctrl_mem_protection_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537807672 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_mem_protection.2537807672 |
| Directory | /workspace/2.chip_sw_flash_ctrl_mem_protection/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2620930163 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 4928763776 ps |
| CPU time | 724.04 seconds |
| Started | Aug 17 07:20:06 PM PDT 24 |
| Finished | Aug 17 07:32:10 PM PDT 24 |
| Peak memory | 609820 kb |
| Host | smart-c8f80971-a451-4929-bdb1-e3a0b75710cd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc_instrumentat ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620930163 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops.2620930163 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1098405337 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 4315214758 ps |
| CPU time | 806.79 seconds |
| Started | Aug 17 07:20:56 PM PDT 24 |
| Finished | Aug 17 07:34:23 PM PDT 24 |
| Peak memory | 610744 kb |
| Host | smart-f43390f6-1e6a-409a-9794-196f308b81ee |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_rules,test_rom:0 +cdc _instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_see d=1098405337 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en.1098405337 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1484761859 |
| Short name | T1209 |
| Test name | |
| Test status | |
| Simulation time | 4313453804 ps |
| CPU time | 691.01 seconds |
| Started | Aug 17 07:27:23 PM PDT 24 |
| Finished | Aug 17 07:38:55 PM PDT 24 |
| Peak memory | 610636 kb |
| Host | smart-031ad7e5-2fe2-41a7-960f-cf4642363f6a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_ctrl_ops_test:1:new_ rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/si m.tcl +ntb_random_seed=1484761859 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+ branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1484761859 |
| Directory | /workspace/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_ctrl_write_clear.354198765 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 3818541662 ps |
| CPU time | 366.68 seconds |
| Started | Aug 17 07:26:50 PM PDT 24 |
| Finished | Aug 17 07:32:57 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-1cbf8089-c120-41c0-81c8-4e5aefc01a8d |
| User | root |
| Command | /workspace/default/simv +test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=flash_ctrl_write_clear_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541987 65 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_ctrl_write_clear.354198765 |
| Directory | /workspace/2.chip_sw_flash_ctrl_write_clear/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init.1304717105 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 17303670936 ps |
| CPU time | 2043.99 seconds |
| Started | Aug 17 07:21:17 PM PDT 24 |
| Finished | Aug 17 07:55:22 PM PDT 24 |
| Peak memory | 612100 kb |
| Host | smart-f3b080c2-267b-4f8b-9829-009df7b1407e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304717105 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init.1304717105 |
| Directory | /workspace/2.chip_sw_flash_init/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3947242485 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 20541833817 ps |
| CPU time | 1768.57 seconds |
| Started | Aug 17 07:28:05 PM PDT 24 |
| Finished | Aug 17 07:57:34 PM PDT 24 |
| Peak memory | 613080 kb |
| Host | smart-1d4375a0-069d-413f-a3e9-24978ad3a381 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=25_000_000 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=flash_init_test:0:test_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=3947242485 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_flash_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_init_reduced_freq.3947242485 |
| Directory | /workspace/2.chip_sw_flash_init_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1807112293 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 2674072056 ps |
| CPU time | 224.7 seconds |
| Started | Aug 17 07:33:24 PM PDT 24 |
| Finished | Aug 17 07:37:09 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-314483d6-4c80-44e9-b000-3d3f63a56d23 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=flash_scrambling_smoketest:1:new_rules,flash_scrambling_smoket est_otp_img_rma:4,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=1807112293 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+c ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_flash_scrambling_smoketest.1807112293 |
| Directory | /workspace/2.chip_sw_flash_scrambling_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_gpio_smoketest.3989732291 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 3062780209 ps |
| CPU time | 269.93 seconds |
| Started | Aug 17 07:29:25 PM PDT 24 |
| Finished | Aug 17 07:33:55 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-40174f48-5fdd-4f65-83a7-861934cc135e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=gpio_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989732291 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_gpio_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_gpio_smoketest.3989732291 |
| Directory | /workspace/2.chip_sw_gpio_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc.350548307 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 2777165350 ps |
| CPU time | 189.93 seconds |
| Started | Aug 17 07:31:49 PM PDT 24 |
| Finished | Aug 17 07:34:59 PM PDT 24 |
| Peak memory | 609984 kb |
| Host | smart-1fab4342-81f6-43ee-9dfb-9f4a332007b5 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350548307 -assert nopostproc +UVM_TESTNAME=chip_ base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc.350548307 |
| Directory | /workspace/2.chip_sw_hmac_enc/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_idle.1705381 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 2844491510 ps |
| CPU time | 232.27 seconds |
| Started | Aug 17 07:31:11 PM PDT 24 |
| Finished | Aug 17 07:35:04 PM PDT 24 |
| Peak memory | 610460 kb |
| Host | smart-1a5cae58-a1c4-43b5-b089-e2c71104248f |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_enc_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705381 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nu ll -cm_name 2.chip_sw_hmac_enc_idle.1705381 |
| Directory | /workspace/2.chip_sw_hmac_enc_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.380465625 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 2733756088 ps |
| CPU time | 302.8 seconds |
| Started | Aug 17 07:23:51 PM PDT 24 |
| Finished | Aug 17 07:28:54 PM PDT 24 |
| Peak memory | 610476 kb |
| Host | smart-7346eb8b-51e0-49c3-b50d-707202c3cb98 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=380465625 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en.380465625 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2066124815 |
| Short name | T1184 |
| Test name | |
| Test status | |
| Simulation time | 2398619778 ps |
| CPU time | 214.51 seconds |
| Started | Aug 17 07:27:49 PM PDT 24 |
| Finished | Aug 17 07:31:23 PM PDT 24 |
| Peak memory | 609636 kb |
| Host | smart-7a88078b-f0c5-4204-a39e-ffdbccc5e8ac |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=hmac_enc_test:1:new_rules,test_rom:0 +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066124815 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cove rage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_enc_jitter_en_reduced_freq.2066124815 |
| Directory | /workspace/2.chip_sw_hmac_enc_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_multistream.2155871874 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 7477458550 ps |
| CPU time | 1538.15 seconds |
| Started | Aug 17 07:23:31 PM PDT 24 |
| Finished | Aug 17 07:49:10 PM PDT 24 |
| Peak memory | 610788 kb |
| Host | smart-f0918b87-010a-4eb1-b7b4-6e51ac5e1203 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_multistream_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155871874 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_hmac_multistream.2155871874 |
| Directory | /workspace/2.chip_sw_hmac_multistream/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_oneshot.1265933476 |
| Short name | T1313 |
| Test name | |
| Test status | |
| Simulation time | 3327579400 ps |
| CPU time | 265.93 seconds |
| Started | Aug 17 07:26:32 PM PDT 24 |
| Finished | Aug 17 07:30:58 PM PDT 24 |
| Peak memory | 609980 kb |
| Host | smart-42b24140-94c1-45ff-aae1-3b0e5117a8b3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_functest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265933476 -assert nopostproc +UVM_TESTNAME=chip _base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_hmac_oneshot.1265933476 |
| Directory | /workspace/2.chip_sw_hmac_oneshot/latest |
| Test location | /workspace/coverage/default/2.chip_sw_hmac_smoketest.4055555117 |
| Short name | T1249 |
| Test name | |
| Test status | |
| Simulation time | 3486190552 ps |
| CPU time | 334.12 seconds |
| Started | Aug 17 07:28:04 PM PDT 24 |
| Finished | Aug 17 07:33:39 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-9399cb18-fb21-4f2f-ac65-96b3b1ba9fc2 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=hmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4055555117 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_hmac_smoketest.4055555117 |
| Directory | /workspace/2.chip_sw_hmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.840589114 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 4420549472 ps |
| CPU time | 887.87 seconds |
| Started | Aug 17 07:21:08 PM PDT 24 |
| Finished | Aug 17 07:35:57 PM PDT 24 |
| Peak memory | 609912 kb |
| Host | smart-777cc945-8ee7-474f-a82c-89fa751e56fd |
| User | root |
| Command | /workspace/default/simv +i2c_idx=0 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840589114 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx.840589114 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.2631236836 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 4570954828 ps |
| CPU time | 726.02 seconds |
| Started | Aug 17 07:20:57 PM PDT 24 |
| Finished | Aug 17 07:33:03 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-32f80e93-8a8a-4f81-a767-23f25eb214b7 |
| User | root |
| Command | /workspace/default/simv +i2c_idx=1 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631236836 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx1.2631236836 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.3626942737 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 5305762602 ps |
| CPU time | 880.73 seconds |
| Started | Aug 17 07:21:19 PM PDT 24 |
| Finished | Aug 17 07:36:00 PM PDT 24 |
| Peak memory | 611072 kb |
| Host | smart-05f56fcb-8b94-45b8-aab1-f4f24358d4ca |
| User | root |
| Command | /workspace/default/simv +i2c_idx=2 +sw_build_device=sim_dv +sw_images=i2c_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626942737 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_i2c_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_i2c_host_tx_rx_idx2.3626942737 |
| Directory | /workspace/2.chip_sw_i2c_host_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_inject_scramble_seed.632301111 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 65080654744 ps |
| CPU time | 11175.3 seconds |
| Started | Aug 17 07:20:08 PM PDT 24 |
| Finished | Aug 17 10:26:24 PM PDT 24 |
| Peak memory | 625552 kb |
| Host | smart-e20ebde4-497a-42fa-8731-3cd237616e64 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +flash_program_latency=5 +sw_test_timeout_ns=150_000_000 +sw_build_device=sim_dv +sw_images=inject_scramble_seed :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=632301111 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_inject_scramble_seed_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_inject_scramble_seed.632301111 |
| Directory | /workspace/2.chip_sw_inject_scramble_seed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2144328009 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 8505386342 ps |
| CPU time | 1624.66 seconds |
| Started | Aug 17 07:29:14 PM PDT 24 |
| Finished | Aug 17 07:56:19 PM PDT 24 |
| Peak memory | 617280 kb |
| Host | smart-991dceb3-f93f-4ecf-9849-c6fd4d8327b4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144 328009 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass ert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation.2144328009 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2025481763 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 8030608293 ps |
| CPU time | 1503.61 seconds |
| Started | Aug 17 07:24:11 PM PDT 24 |
| Finished | Aug 17 07:49:15 PM PDT 24 |
| Peak memory | 617328 kb |
| Host | smart-7acc26f7-2afd-44fc-b3fc-70bc4cf7ab6b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=2025481763 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en.2025481763 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4043944432 |
| Short name | T1221 |
| Test name | |
| Test status | |
| Simulation time | 9470356663 ps |
| CPU time | 1491.08 seconds |
| Started | Aug 17 07:27:45 PM PDT 24 |
| Finished | Aug 17 07:52:37 PM PDT 24 |
| Peak memory | 617368 kb |
| Host | smart-ef5d6036-e0f8-41fe-8e2d-a100fd6b646a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=4043944432 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov= 1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_jitter_en _reduced_freq.4043944432 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.686174538 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 6902206220 ps |
| CPU time | 1178.81 seconds |
| Started | Aug 17 07:31:40 PM PDT 24 |
| Finished | Aug 17 07:51:19 PM PDT 24 |
| Peak memory | 617640 kb |
| Host | smart-d61dffea-254a-43cc-bc67-f4aaf01167b7 |
| User | root |
| Command | /workspace/default/simv +lc_at_prod=1 +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_key_derivation_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=686174538 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_key_derivation_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_key_derivation_prod.686174538 |
| Directory | /workspace/2.chip_sw_keymgr_key_derivation_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2631444313 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 9249236312 ps |
| CPU time | 1479.45 seconds |
| Started | Aug 17 07:24:18 PM PDT 24 |
| Finished | Aug 17 07:48:58 PM PDT 24 |
| Peak memory | 611648 kb |
| Host | smart-7ee690a5-b14d-4029-bb7e-22db1c905eec |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_aes_test:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263144 4313 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_aes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_aes.2631444313 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_aes/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.4282527605 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 10568061202 ps |
| CPU time | 1777.93 seconds |
| Started | Aug 17 07:24:15 PM PDT 24 |
| Finished | Aug 17 07:53:53 PM PDT 24 |
| Peak memory | 610572 kb |
| Host | smart-63cfbf6e-9aae-4a08-b510-ee7bae09d79d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_kmac_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42825 27605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_keymgr_sideload_kmac_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_kmac.4282527605 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2023082328 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 17644561536 ps |
| CPU time | 3847.48 seconds |
| Started | Aug 17 07:24:27 PM PDT 24 |
| Finished | Aug 17 08:28:35 PM PDT 24 |
| Peak memory | 610304 kb |
| Host | smart-305bb866-6b8a-43e7-a1aa-ece8b5934c05 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +sw_build_device=sim_dv +sw_images=keymgr_sideload_otbn_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230 82328 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_keymgr_sideload_otbn.2023082328 |
| Directory | /workspace/2.chip_sw_keymgr_sideload_otbn/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_app_rom.758312928 |
| Short name | T1255 |
| Test name | |
| Test status | |
| Simulation time | 2557303696 ps |
| CPU time | 222.5 seconds |
| Started | Aug 17 07:26:29 PM PDT 24 |
| Finished | Aug 17 07:30:12 PM PDT 24 |
| Peak memory | 609320 kb |
| Host | smart-bc654a93-ba58-4d42-bb96-1999f94bb6fc |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_app_rom_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=758312928 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_app_rom.758312928 |
| Directory | /workspace/2.chip_sw_kmac_app_rom/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_entropy.514877210 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 2708876210 ps |
| CPU time | 228.78 seconds |
| Started | Aug 17 07:21:09 PM PDT 24 |
| Finished | Aug 17 07:24:58 PM PDT 24 |
| Peak memory | 609392 kb |
| Host | smart-54f740b2-6ed1-4cd3-9ec4-0801eddb2004 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_entropy_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514877210 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_kmac_entropy.514877210 |
| Directory | /workspace/2.chip_sw_kmac_entropy/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_idle.1075832262 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 2809465720 ps |
| CPU time | 332.08 seconds |
| Started | Aug 17 07:25:01 PM PDT 24 |
| Finished | Aug 17 07:30:33 PM PDT 24 |
| Peak memory | 609388 kb |
| Host | smart-31d05e58-0ba8-4f65-b032-980d2b6f451b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_idle_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075832262 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_idle.1075832262 |
| Directory | /workspace/2.chip_sw_kmac_idle/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2539409733 |
| Short name | T1312 |
| Test name | |
| Test status | |
| Simulation time | 2247138112 ps |
| CPU time | 157.97 seconds |
| Started | Aug 17 07:23:47 PM PDT 24 |
| Finished | Aug 17 07:26:25 PM PDT 24 |
| Peak memory | 609972 kb |
| Host | smart-0cd13121-8662-4b6b-aa35-168c056b89bd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_cshake_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539409733 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_kmac_mode_cshake.2539409733 |
| Directory | /workspace/2.chip_sw_kmac_mode_cshake/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.946672009 |
| Short name | T1230 |
| Test name | |
| Test status | |
| Simulation time | 3201066760 ps |
| CPU time | 290.43 seconds |
| Started | Aug 17 07:24:09 PM PDT 24 |
| Finished | Aug 17 07:28:59 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-cd73b9ff-c384-4ecc-8db3-22a35ae53059 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946672009 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_kmac_mode_kmac.946672009 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1605776481 |
| Short name | T1133 |
| Test name | |
| Test status | |
| Simulation time | 3562751678 ps |
| CPU time | 373.27 seconds |
| Started | Aug 17 07:25:21 PM PDT 24 |
| Finished | Aug 17 07:31:34 PM PDT 24 |
| Peak memory | 609544 kb |
| Host | smart-a83c4618-29a2-47ee-857f-7a991f9c762e |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605776481 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en.1605776481 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.353130374 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 2688888561 ps |
| CPU time | 288.62 seconds |
| Started | Aug 17 07:26:11 PM PDT 24 |
| Finished | Aug 17 07:31:00 PM PDT 24 |
| Peak memory | 609420 kb |
| Host | smart-106fa8fa-128c-4ba4-abfb-ca3690524524 |
| User | root |
| Command | /workspace/default/simv +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=kmac_mode_kmac_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35313037 4 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.353130374 |
| Directory | /workspace/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_kmac_smoketest.2698789034 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 2845055758 ps |
| CPU time | 306.68 seconds |
| Started | Aug 17 07:30:29 PM PDT 24 |
| Finished | Aug 17 07:35:36 PM PDT 24 |
| Peak memory | 610364 kb |
| Host | smart-76921221-667f-42b5-bf35-1e9affa86179 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=kmac_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2698789034 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_kmac_smoketest.2698789034 |
| Directory | /workspace/2.chip_sw_kmac_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.878841829 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 3299591360 ps |
| CPU time | 285.98 seconds |
| Started | Aug 17 07:21:43 PM PDT 24 |
| Finished | Aug 17 07:26:29 PM PDT 24 |
| Peak memory | 610388 kb |
| Host | smart-206773aa-1c6d-415e-994d-80843076ebeb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_otp_hw_cfg0_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878841829 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_otp_hw_cfg0.878841829 |
| Directory | /workspace/2.chip_sw_lc_ctrl_otp_hw_cfg0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_program_error.1748014808 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 4479558100 ps |
| CPU time | 426.69 seconds |
| Started | Aug 17 07:26:42 PM PDT 24 |
| Finished | Aug 17 07:33:49 PM PDT 24 |
| Peak memory | 610408 kb |
| Host | smart-727f5650-e5ba-4f38-9134-c3fdc3d22302 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_program_error:1:new_rules,test_rom:0 + cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_ seed=1748014808 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_program_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_program_error.1748014808 |
| Directory | /workspace/2.chip_sw_lc_ctrl_program_error/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2692007621 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 3273180369 ps |
| CPU time | 262.25 seconds |
| Started | Aug 17 07:23:19 PM PDT 24 |
| Finished | Aug 17 07:27:41 PM PDT 24 |
| Peak memory | 621244 kb |
| Host | smart-ee715dae-0b75-4888-9f14-1e8b84222e08 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=lc_ctrl_scrap_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26920076 21 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_scrap_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_rand_to_scrap.2692007621 |
| Directory | /workspace/2.chip_sw_lc_ctrl_rand_to_scrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_transition.471945527 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 13152840229 ps |
| CPU time | 1156.48 seconds |
| Started | Aug 17 07:20:27 PM PDT 24 |
| Finished | Aug 17 07:39:44 PM PDT 24 |
| Peak memory | 622048 kb |
| Host | smart-6ee85ac1-086e-429c-9d90-6e0c9b9ea1f1 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471945527 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_transition.471945527 |
| Directory | /workspace/2.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.440397689 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 2063896994 ps |
| CPU time | 121.17 seconds |
| Started | Aug 17 07:21:03 PM PDT 24 |
| Finished | Aug 17 07:23:04 PM PDT 24 |
| Peak memory | 617292 kb |
| Host | smart-0a7c12c7-905a-443e-a391-8c04132ec0a2 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +exp_volatile_raw_unlock_en=0 +sw_build_device=sim_dv +sw_images=lc_ctrl_volatile_raw_unlock_tes t:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/ tools/sim.tcl +ntb_random_seed=440397689 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock.440397689 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.899035199 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 2413886584 ps |
| CPU time | 116.99 seconds |
| Started | Aug 17 07:24:20 PM PDT 24 |
| Finished | Aug 17 07:26:17 PM PDT 24 |
| Peak memory | 617800 kb |
| Host | smart-8bceb843-93bb-4d36-a02a-e42be4ee28ae |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +exp_volatile_raw_unlock_en=0 +sw_build_device=s im_dv +sw_images=lc_ctrl_volatile_raw_unlock_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -l icqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=899035199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST _SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null - cm_name 2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.899035199 |
| Directory | /workspace/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3311511043 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 51399505289 ps |
| CPU time | 5008.46 seconds |
| Started | Aug 17 07:21:51 PM PDT 24 |
| Finished | Aug 17 08:45:21 PM PDT 24 |
| Peak memory | 624260 kb |
| Host | smart-43d5ca6e-904f-459f-b456-103b9708290c |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStDev +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311511043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=c hip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip _sw_lc_walkthrough_dev.3311511043 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2134352695 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 48987926114 ps |
| CPU time | 4672.68 seconds |
| Started | Aug 17 07:23:15 PM PDT 24 |
| Finished | Aug 17 08:41:08 PM PDT 24 |
| Peak memory | 625280 kb |
| Host | smart-66a7da2c-0247-409f-90e2-43471bfd604e |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProd +sw_test_timeout_ns=200_000_000 +sw_build_d evice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134352695 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chi p_sw_lc_walkthrough_prod.2134352695 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1913881639 |
| Short name | T1192 |
| Test name | |
| Test status | |
| Simulation time | 7989478743 ps |
| CPU time | 947.89 seconds |
| Started | Aug 17 07:23:10 PM PDT 24 |
| Finished | Aug 17 07:38:58 PM PDT 24 |
| Peak memory | 623100 kb |
| Host | smart-9eada2b8-d2b4-4f74-a655-a6fd0121a62f |
| User | root |
| Command | /workspace/default/simv +flash_program_latency=5 +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStProdEnd +sw_build_device=sim_dv +sw_images=lc_wa lkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/re po_top/hw/dv/tools/sim.tcl +ntb_random_seed=1913881639 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_vseq + en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_prodend.1913881639 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_prodend/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.854440500 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 48662179374 ps |
| CPU time | 4712.52 seconds |
| Started | Aug 17 07:20:28 PM PDT 24 |
| Finished | Aug 17 08:39:02 PM PDT 24 |
| Peak memory | 624292 kb |
| Host | smart-438d144f-65c3-4248-9007-275fbf738ad3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStRma +flash_program_latency=5 +sw_test_timeout_ns=200_000_000 +sw_build_de vice=sim_dv +sw_images=lc_walkthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=854440500 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=ch ip_sw_lc_walkthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_ sw_lc_walkthrough_rma.854440500 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3587860815 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 31583828014 ps |
| CPU time | 2085.62 seconds |
| Started | Aug 17 07:20:53 PM PDT 24 |
| Finished | Aug 17 07:55:39 PM PDT 24 |
| Peak memory | 625316 kb |
| Host | smart-9bc0bb4f-fbda-4eda-aaef-b2df90b2e732 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRaw +dest_dec_state=DecLcStTestUnlock7 +sw_build_device=sim_dv +sw_images=lc_walkthrough_testunlocks _test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw /dv/tools/sim.tcl +ntb_random_seed=3587860815 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_walkthrough_testunlocks_vse q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_lc_walkthrough_testun locks.3587860815 |
| Directory | /workspace/2.chip_sw_lc_walkthrough_testunlocks/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.2153120724 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 16590123668 ps |
| CPU time | 3703.5 seconds |
| Started | Aug 17 07:23:01 PM PDT 24 |
| Finished | Aug 17 08:24:45 PM PDT 24 |
| Peak memory | 610692 kb |
| Host | smart-c58b2962-f532-46bf-92ca-e391d07b7a4b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=28_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:new_rules,test_ rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ random_seed=2153120724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq.2153120724 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1597371878 |
| Short name | T1227 |
| Test name | |
| Test status | |
| Simulation time | 18846290581 ps |
| CPU time | 3662.01 seconds |
| Started | Aug 17 07:24:53 PM PDT 24 |
| Finished | Aug 17 08:25:56 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-c4f3631c-8a21-4628-9bb2-025ae40f1625 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +sw_build_device=sim_dv +sw_images=otbn_ecdsa_op_irq_test:1:ne w_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/ sim.tcl +ntb_random_seed=1597371878 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1597371878 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1826366068 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 25019017546 ps |
| CPU time | 3197.36 seconds |
| Started | Aug 17 07:26:33 PM PDT 24 |
| Finished | Aug 17 08:19:51 PM PDT 24 |
| Peak memory | 610988 kb |
| Host | smart-a7ba8930-173e-47bc-8fa1-0df85420ff91 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=33_000_000 +rng_srate_value=30 +en_jitter=1 +cal_sys_clk_70mhz=1 +sw_build_device=sim_dv +sw_images=otbn_e cdsa_op_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/ repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1826366068 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_ecdsa_op_irq_jitter_en_redu ced_freq.1826366068 |
| Directory | /workspace/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_mem_scramble.1025659941 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 4248030516 ps |
| CPU time | 548.04 seconds |
| Started | Aug 17 07:24:48 PM PDT 24 |
| Finished | Aug 17 07:33:57 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-2c394f83-8c9a-4eeb-929f-e0be61be8350 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=15_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=otbn _mem_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mn t/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025659941 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov =1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_mem_scramble.1025659941 |
| Directory | /workspace/2.chip_sw_otbn_mem_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_randomness.3348944043 |
| Short name | T1256 |
| Test name | |
| Test status | |
| Simulation time | 5923400488 ps |
| CPU time | 956.89 seconds |
| Started | Aug 17 07:23:15 PM PDT 24 |
| Finished | Aug 17 07:39:12 PM PDT 24 |
| Peak memory | 610924 kb |
| Host | smart-967579d8-5e4f-4770-86e5-7a2a95718f60 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +rng_srate_value=30 +sw_build_device=sim_dv +sw_images=otbn_randomness_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=3348944043 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otbn_randomness.3348944043 |
| Directory | /workspace/2.chip_sw_otbn_randomness/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otbn_smoketest.2956209143 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 8456264850 ps |
| CPU time | 1566.04 seconds |
| Started | Aug 17 07:28:20 PM PDT 24 |
| Finished | Aug 17 07:54:26 PM PDT 24 |
| Peak memory | 609840 kb |
| Host | smart-27cb99c2-8563-4911-89bc-bf3b2097f851 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otbn_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956209143 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/nul l -cm_name 2.chip_sw_otbn_smoketest.2956209143 |
| Directory | /workspace/2.chip_sw_otbn_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.376284370 |
| Short name | T1199 |
| Test name | |
| Test status | |
| Simulation time | 3311039984 ps |
| CPU time | 298.94 seconds |
| Started | Aug 17 07:21:38 PM PDT 24 |
| Finished | Aug 17 07:26:37 PM PDT 24 |
| Peak memory | 609692 kb |
| Host | smart-a01a03ff-bcec-4719-b30c-a9d8676d455b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_vendor_test_ecc_error_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376284370 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_otp_ctrl_vendor_test_ecc_error_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_ecc_error_vendor_test.376284370 |
| Directory | /workspace/2.chip_sw_otp_ctrl_ecc_error_vendor_test/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.2431082809 |
| Short name | T1346 |
| Test name | |
| Test status | |
| Simulation time | 7965893880 ps |
| CPU time | 1138.38 seconds |
| Started | Aug 17 07:22:11 PM PDT 24 |
| Finished | Aug 17 07:41:10 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-f90cf224-ac83-4154-a283-fddb232f329e |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=2431082809 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_dev.2431082809 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_dev/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1299720098 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 8328354600 ps |
| CPU time | 1300.38 seconds |
| Started | Aug 17 07:20:27 PM PDT 24 |
| Finished | Aug 17 07:42:07 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-a798f057-4db8-4d72-b057-065a157f8531 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=1299720098 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_prod.1299720098 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_prod/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1925046904 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 7856303144 ps |
| CPU time | 1209.32 seconds |
| Started | Aug 17 07:20:58 PM PDT 24 |
| Finished | Aug 17 07:41:08 PM PDT 24 |
| Peak memory | 611320 kb |
| Host | smart-75cf93ad-bc57-4192-9f98-c4c9c9b7a3d6 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStRma +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new_rules,tes t_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +nt b_random_seed=1925046904 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_rma.1925046904 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_rma/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1202300044 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 4486877458 ps |
| CPU time | 700.2 seconds |
| Started | Aug 17 07:21:22 PM PDT 24 |
| Finished | Aug 17 07:33:02 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-228b0ea4-f9a8-4d09-a06a-65ef4690dd85 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +otp_clear_secret2=1 +sw_build_device=sim_dv +sw_images=otp_ctrl_lc_signals_test:1:new _rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/s im.tcl +ntb_random_seed=1202300044 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1202300044 |
| Directory | /workspace/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1938094409 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 2636700000 ps |
| CPU time | 202.61 seconds |
| Started | Aug 17 07:27:48 PM PDT 24 |
| Finished | Aug 17 07:31:11 PM PDT 24 |
| Peak memory | 609340 kb |
| Host | smart-326f5acb-1528-4ee6-8cc4-8df05b0aaccb |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=otp_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938094409 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_otp_ctrl_smoketest.1938094409 |
| Directory | /workspace/2.chip_sw_otp_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pattgen_ios.4269620858 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 2482376444 ps |
| CPU time | 185.5 seconds |
| Started | Aug 17 07:18:35 PM PDT 24 |
| Finished | Aug 17 07:21:41 PM PDT 24 |
| Peak memory | 613792 kb |
| Host | smart-768c91a9-c96c-44ec-a6e3-ca282c2cd82d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=5_000_000 +sw_build_device=sim_dv +sw_images=pattgen_ios_test:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269620858 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_patt_ios_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pattgen_ios.4269620858 |
| Directory | /workspace/2.chip_sw_pattgen_ios/latest |
| Test location | /workspace/coverage/default/2.chip_sw_plic_sw_irq.1060234665 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 2436838536 ps |
| CPU time | 303.48 seconds |
| Started | Aug 17 07:23:57 PM PDT 24 |
| Finished | Aug 17 07:29:01 PM PDT 24 |
| Peak memory | 609940 kb |
| Host | smart-c15affd9-676b-4a33-bc68-62515458f86d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=plic_sw_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060234665 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_plic_sw_irq.1060234665 |
| Directory | /workspace/2.chip_sw_plic_sw_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_idle_load.1073658368 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 5033697104 ps |
| CPU time | 634.96 seconds |
| Started | Aug 17 07:28:49 PM PDT 24 |
| Finished | Aug 17 07:39:24 PM PDT 24 |
| Peak memory | 611064 kb |
| Host | smart-1ea121d1-6f4f-4975-807c-ca62eeea6d12 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_idle_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073658368 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_idle_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_power_idle_load.1073658368 |
| Directory | /workspace/2.chip_sw_power_idle_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_power_sleep_load.4084051630 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 11160013014 ps |
| CPU time | 585.63 seconds |
| Started | Aug 17 07:28:22 PM PDT 24 |
| Finished | Aug 17 07:38:08 PM PDT 24 |
| Peak memory | 611620 kb |
| Host | smart-b5242af2-6852-44fc-beb9-3b4b25ffd707 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=chip_power_sleep_load:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084051630 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_power_sleep_load_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.v db -cm_log /dev/null -cm_name 2.chip_sw_power_sleep_load.4084051630 |
| Directory | /workspace/2.chip_sw_power_sleep_load/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2208029545 |
| Short name | T1310 |
| Test name | |
| Test status | |
| Simulation time | 14124402897 ps |
| CPU time | 2021.54 seconds |
| Started | Aug 17 07:22:31 PM PDT 24 |
| Finished | Aug 17 07:56:13 PM PDT 24 |
| Peak memory | 612060 kb |
| Host | smart-e28f3aa8-350d-4485-9c30-18582dfc57d7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instr umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208 029545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse rt -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_all_reset_reqs.2208029545 |
| Directory | /workspace/2.chip_sw_pwrmgr_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2846122175 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 32443434701 ps |
| CPU time | 2746.51 seconds |
| Started | Aug 17 07:25:38 PM PDT 24 |
| Finished | Aug 17 08:11:25 PM PDT 24 |
| Peak memory | 611568 kb |
| Host | smart-7bd4cf31-2cd1-4b44-9994-95334c7b4f5e |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=35_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_b2b_sleep_reset_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284 6122175 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_repeat_reset_wkup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_b2b_sleep_reset_req.2846122175 |
| Directory | /workspace/2.chip_sw_pwrmgr_b2b_sleep_reset_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2292940012 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 25679479996 ps |
| CPU time | 2041.96 seconds |
| Started | Aug 17 07:26:25 PM PDT 24 |
| Finished | Aug 17 08:00:28 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-b0680ec2-7ab1-4744-8343-9ada6f874bbb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_all_wake_ups:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2292940012 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2292940012 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2111416323 |
| Short name | T1287 |
| Test name | |
| Test status | |
| Simulation time | 8271803272 ps |
| CPU time | 880.61 seconds |
| Started | Aug 17 07:21:44 PM PDT 24 |
| Finished | Aug 17 07:36:25 PM PDT 24 |
| Peak memory | 610496 kb |
| Host | smart-893b1116-4716-4802-8eea-4c706ca6417b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111416323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage /default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_por_reset.2111416323 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1920001934 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 6046068156 ps |
| CPU time | 497.73 seconds |
| Started | Aug 17 07:21:56 PM PDT 24 |
| Finished | Aug 17 07:30:14 PM PDT 24 |
| Peak memory | 616980 kb |
| Host | smart-c83cd0a0-6efd-44d0-8d28-8c1713c78f41 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_deep_sleep_power_glitch_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1920001934 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+b ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1920001934 |
| Directory | /workspace/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.632984055 |
| Short name | T1213 |
| Test name | |
| Test status | |
| Simulation time | 7906442986 ps |
| CPU time | 521.25 seconds |
| Started | Aug 17 07:21:01 PM PDT 24 |
| Finished | Aug 17 07:29:42 PM PDT 24 |
| Peak memory | 611452 kb |
| Host | smart-c157d50f-d81b-4ca0-ad77-13fab01d8992 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=632984055 -assert nopostproc +UVM_TESTNAME=ch ip_base_test +UVM_TEST_SEQ=chip_sw_full_aon_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_full_aon_reset.632984055 |
| Directory | /workspace/2.chip_sw_pwrmgr_full_aon_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1475103371 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 4559480698 ps |
| CPU time | 595.24 seconds |
| Started | Aug 17 07:22:20 PM PDT 24 |
| Finished | Aug 17 07:32:16 PM PDT 24 |
| Peak memory | 617188 kb |
| Host | smart-27da8e6d-eed3-4d42-becf-24b01d550ea6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=pwrmgr_main_power_glitch_test:1:new_rules,test_rom:0 +cd c_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_se ed=1475103371 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_main_power_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_main_power_glitch_reset.1475103371 |
| Directory | /workspace/2.chip_sw_pwrmgr_main_power_glitch_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.600123585 |
| Short name | T1125 |
| Test name | |
| Test status | |
| Simulation time | 10631741726 ps |
| CPU time | 1621.86 seconds |
| Started | Aug 17 07:22:35 PM PDT 24 |
| Finished | Aug 17 07:49:37 PM PDT 24 |
| Peak memory | 612096 kb |
| Host | smart-af8d806e-7098-4cb1-be40-2c63889a2b2b |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_all_reset_reqs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled =1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600123585 -assert nopo stproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.600123585 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1785777903 |
| Short name | T1261 |
| Test name | |
| Test status | |
| Simulation time | 5375037650 ps |
| CPU time | 420.27 seconds |
| Started | Aug 17 07:23:23 PM PDT 24 |
| Finished | Aug 17 07:30:23 PM PDT 24 |
| Peak memory | 611552 kb |
| Host | smart-b8b69a22-8d7e-41e0-a7fd-9d570f3c2517 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_normal_sleep_por_reset_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +U VM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785777903 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sleep_por_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_normal_sleep_por_reset.1785777903 |
| Directory | /workspace/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1299393884 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 27702507124 ps |
| CPU time | 2468.79 seconds |
| Started | Aug 17 07:21:43 PM PDT 24 |
| Finished | Aug 17 08:02:52 PM PDT 24 |
| Peak memory | 612208 kb |
| Host | smart-3e615760-7357-4393-ad15-af97e95e21f8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=50_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_reset_reqs_test:1:new_rules,test_rom :0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ran dom_seed=1299393884 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_deep_sleep_all_reset_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1299393884 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.543757930 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 20062858684 ps |
| CPU time | 1285.53 seconds |
| Started | Aug 17 07:26:57 PM PDT 24 |
| Finished | Aug 17 07:48:24 PM PDT 24 |
| Peak memory | 611612 kb |
| Host | smart-81651b4c-788f-4a50-b44f-d49a6e0ef8eb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_random_sleep_all_wake_ups:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=543757930 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_deep_sleep_all_wake_ups_vseq +en_cov=1 -cm l ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_random_sleep_all_wake_ups.543757930 |
| Directory | /workspace/2.chip_sw_pwrmgr_random_sleep_all_wake_ups/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3781346563 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 4923984440 ps |
| CPU time | 503.74 seconds |
| Started | Aug 17 07:26:22 PM PDT 24 |
| Finished | Aug 17 07:34:46 PM PDT 24 |
| Peak memory | 611924 kb |
| Host | smart-5777448c-cda8-4858-8d79-20973c6f8831 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sensor_ctrl_deep_sleep_wake_up:1:new_rul es,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t cl +ntb_random_seed=3781346563 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sensor_ctrl_deep_s leep_wake_up.3781346563 |
| Directory | /workspace/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.203054037 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2649556326 ps |
| CPU time | 227.48 seconds |
| Started | Aug 17 07:24:30 PM PDT 24 |
| Finished | Aug 17 07:28:18 PM PDT 24 |
| Peak memory | 610404 kb |
| Host | smart-97b2703b-ba69-4344-ad30-9433d9ae6019 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_disabled_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203054037 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_l og /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_disabled.203054037 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_disabled/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.317846819 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5396774158 ps |
| CPU time | 456.09 seconds |
| Started | Aug 17 07:25:14 PM PDT 24 |
| Finished | Aug 17 07:32:50 PM PDT 24 |
| Peak memory | 609480 kb |
| Host | smart-c1525c37-f64d-4b71-a5d4-7e1d3f6e26d0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=8_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31784681 9 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace /coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.317846819 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.12209150 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 5820296806 ps |
| CPU time | 641.9 seconds |
| Started | Aug 17 07:25:34 PM PDT 24 |
| Finished | Aug 17 07:36:17 PM PDT 24 |
| Peak memory | 611360 kb |
| Host | smart-562dfb89-b9e4-4dab-8159-db3f610ce691 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +do_random=1 +sw_build_device=sim_dv +sw_images=pwrmgr_sleep_wake_5_bug_test:1:new_rules,test_r om:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_r andom_seed=12209150 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sleep_wake_5_bug.12209150 |
| Directory | /workspace/2.chip_sw_pwrmgr_sleep_wake_5_bug/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1772626307 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 4961872176 ps |
| CPU time | 440.94 seconds |
| Started | Aug 17 07:28:23 PM PDT 24 |
| Finished | Aug 17 07:35:44 PM PDT 24 |
| Peak memory | 610036 kb |
| Host | smart-8f1b15dd-abb8-4f0d-b4e0-3971542cc43a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10000000 +sw_build_device=sim_dv +sw_images=pwrmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772626307 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/covera ge/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_smoketest.1772626307 |
| Directory | /workspace/2.chip_sw_pwrmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3291945136 |
| Short name | T1244 |
| Test name | |
| Test status | |
| Simulation time | 7270677336 ps |
| CPU time | 1274.2 seconds |
| Started | Aug 17 07:22:45 PM PDT 24 |
| Finished | Aug 17 07:43:59 PM PDT 24 |
| Peak memory | 611132 kb |
| Host | smart-2c90635d-0877-4c0d-b841-6aefa28890fd |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_sysrst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291945136 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_sysrst_ctrl_reset.3291945136 |
| Directory | /workspace/2.chip_sw_pwrmgr_sysrst_ctrl_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1268009038 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 5462078100 ps |
| CPU time | 705.58 seconds |
| Started | Aug 17 07:22:57 PM PDT 24 |
| Finished | Aug 17 07:34:42 PM PDT 24 |
| Peak memory | 610140 kb |
| Host | smart-1de774b6-a4f5-420d-ae20-176d144d5b92 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usb_clk_disabled_when_active_test:1:new_rules,test_rom:0 +cdc_instrumentation_enable d=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268009038 -assert no postproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de fault.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usb_clk_disabled_when_active.1268009038 |
| Directory | /workspace/2.chip_sw_pwrmgr_usb_clk_disabled_when_active/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.3449143407 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 5250961676 ps |
| CPU time | 559.91 seconds |
| Started | Aug 17 07:29:33 PM PDT 24 |
| Finished | Aug 17 07:38:53 PM PDT 24 |
| Peak memory | 609996 kb |
| Host | smart-9ea72c46-1d40-4150-96ed-9f2531466a71 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=pwrmgr_usbdev_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449143407 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_usbdev_smoketest.3449143407 |
| Directory | /workspace/2.chip_sw_pwrmgr_usbdev_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2981476144 |
| Short name | T1224 |
| Test name | |
| Test status | |
| Simulation time | 4226237460 ps |
| CPU time | 497.97 seconds |
| Started | Aug 17 07:24:39 PM PDT 24 |
| Finished | Aug 17 07:32:58 PM PDT 24 |
| Peak memory | 610780 kb |
| Host | smart-22e4c2e6-8aa8-4f25-914b-478a1b5f186f |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=pwrmgr_wdog_reset_reqs_test:1:new_rules,test_rom:0 +cdc_inst rumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298 1476144 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor kspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_pwrmgr_wdog_reset.2981476144 |
| Directory | /workspace/2.chip_sw_pwrmgr_wdog_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1016584221 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 8868208045 ps |
| CPU time | 463.17 seconds |
| Started | Aug 17 07:25:18 PM PDT 24 |
| Finished | Aug 17 07:33:02 PM PDT 24 |
| Peak memory | 610440 kb |
| Host | smart-f7ce28df-3d0e-48af-a59a-be2d8a9a0fb3 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rom_ctrl_integrity_check_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1016584221 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_ctrl_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rom_ctrl_integrity_check.1016584221 |
| Directory | /workspace/2.chip_sw_rom_ctrl_integrity_check/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.2371904475 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 6215295450 ps |
| CPU time | 783.07 seconds |
| Started | Aug 17 07:19:16 PM PDT 24 |
| Finished | Aug 17 07:32:19 PM PDT 24 |
| Peak memory | 642096 kb |
| Host | smart-a8fe4cdb-162c-4c26-ac90-39a8548cff1e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2371904475 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rstmgr_cnsty_fault_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rstmgr_rst_cnsty_escalation.2371904475 |
| Directory | /workspace/2.chip_sw_rstmgr_rst_cnsty_escalation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2623877616 |
| Short name | T1283 |
| Test name | |
| Test status | |
| Simulation time | 2513128404 ps |
| CPU time | 249.27 seconds |
| Started | Aug 17 07:27:43 PM PDT 24 |
| Finished | Aug 17 07:31:53 PM PDT 24 |
| Peak memory | 609360 kb |
| Host | smart-8cd721a1-20b6-434f-b283-8b10d30920a4 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623877616 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rstmgr_smoketest.2623877616 |
| Directory | /workspace/2.chip_sw_rstmgr_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2289950309 |
| Short name | T1336 |
| Test name | |
| Test status | |
| Simulation time | 3544088928 ps |
| CPU time | 397.4 seconds |
| Started | Aug 17 07:22:48 PM PDT 24 |
| Finished | Aug 17 07:29:25 PM PDT 24 |
| Peak memory | 609828 kb |
| Host | smart-3dcda4c1-a8c0-4e6b-9d4d-d9f09759d623 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_req_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2289950309 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rstmgr_sw_req.2289950309 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_req/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.81102534 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 2429098040 ps |
| CPU time | 248.03 seconds |
| Started | Aug 17 07:21:19 PM PDT 24 |
| Finished | Aug 17 07:25:27 PM PDT 24 |
| Peak memory | 609396 kb |
| Host | smart-64216a46-68d1-4a63-ac87-e414f6c0e144 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rstmgr_sw_rst_ctrl_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81102534 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log / dev/null -cm_name 2.chip_sw_rstmgr_sw_rst.81102534 |
| Directory | /workspace/2.chip_sw_rstmgr_sw_rst/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.507017413 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 2630291784 ps |
| CPU time | 265.23 seconds |
| Started | Aug 17 07:28:33 PM PDT 24 |
| Finished | Aug 17 07:32:59 PM PDT 24 |
| Peak memory | 609408 kb |
| Host | smart-dd1dbe9e-4aea-4cbf-ac28-29df9bd90144 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=7_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_address_translation_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=507017413 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_address_translation.507017413 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_address_translation/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.600570225 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 3488793224 ps |
| CPU time | 280.34 seconds |
| Started | Aug 17 07:26:49 PM PDT 24 |
| Finished | Aug 17 07:31:32 PM PDT 24 |
| Peak memory | 609628 kb |
| Host | smart-223e1dc3-9eb5-43b5-a336-ba6d6078f5f6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_core_ibex_icache_invalidate_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 + UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600570225 -assert nopostpr oc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_icache_invalidate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w orkspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_icache_invalidate.600570225 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_icache_invalidate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2542059731 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 2546434508 ps |
| CPU time | 297.77 seconds |
| Started | Aug 17 07:26:39 PM PDT 24 |
| Finished | Aug 17 07:31:37 PM PDT 24 |
| Peak memory | 617300 kb |
| Host | smart-a6c00663-63db-4387-b0fd-dbfd382e8d14 |
| User | root |
| Command | /workspace/default/simv +disable_assert_final_checks +sw_build_device=sim_dv +sw_images=aes_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enab led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542059731 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_core_ibex_lockstep_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_lockstep_glitch.2542059731 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_lockstep_glitch/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3828971789 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 4563985750 ps |
| CPU time | 746.48 seconds |
| Started | Aug 17 07:24:29 PM PDT 24 |
| Finished | Aug 17 07:36:55 PM PDT 24 |
| Peak memory | 609968 kb |
| Host | smart-b67be904-78ce-4af4-a625-e636b856514c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=rv_core_ibex_nmi_irq_test:1:new_rules,test_rom:0 +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38289 71789 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works pace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_nmi_irq.3828971789 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_nmi_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.670445690 |
| Short name | T1334 |
| Test name | |
| Test status | |
| Simulation time | 5793936714 ps |
| CPU time | 1029.47 seconds |
| Started | Aug 17 07:22:50 PM PDT 24 |
| Finished | Aug 17 07:40:00 PM PDT 24 |
| Peak memory | 610684 kb |
| Host | smart-6abfb95d-711b-43f6-ba17-b9557c794be3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +rng_srate_value_max=32 +sw_build_device=sim_dv +sw_images=rv_core_ibex_rnd_test:1:new_rules,te st_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +n tb_random_seed=670445690 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as sert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_core_ibex_rnd.670445690 |
| Directory | /workspace/2.chip_sw_rv_core_ibex_rnd/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2736270129 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 4777756389 ps |
| CPU time | 514.07 seconds |
| Started | Aug 17 07:26:33 PM PDT 24 |
| Finished | Aug 17 07:35:07 PM PDT 24 |
| Peak memory | 624940 kb |
| Host | smart-be261f32-09b2-4625-a4c9-4964ed4c5340 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=alert_handler_escalation_test:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736270129 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_escalation_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_escalation_reset.2736270129 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_escalation_reset/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.1791477001 |
| Short name | T1349 |
| Test name | |
| Test status | |
| Simulation time | 6876253460 ps |
| CPU time | 486.37 seconds |
| Started | Aug 17 07:27:40 PM PDT 24 |
| Finished | Aug 17 07:35:47 PM PDT 24 |
| Peak memory | 619308 kb |
| Host | smart-526cf892-90f8-41b0-b8e4-4fde66b3f652 |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_access_after_wakeup_rma:1:new_rules,test_rom:0 +cdc_instrumentation_e nabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791477001 -asse rt nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_access_after_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_ dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_access_after_wakeup.1791477001 |
| Directory | /workspace/2.chip_sw_rv_dm_access_after_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3975229532 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 4336278568 ps |
| CPU time | 584.7 seconds |
| Started | Aug 17 07:25:31 PM PDT 24 |
| Finished | Aug 17 07:35:16 PM PDT 24 |
| Peak memory | 624952 kb |
| Host | smart-f31431d7-9a44-4fd7-97bb-fd2801aa2afd |
| User | root |
| Command | /workspace/default/simv +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=rv_dm_ndm_reset_req_when_cpu_halted_rma:1:new_rules,test_rom:0 +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397522 9532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rv_dm_ndm_reset_when_cpu_halted_vseq +en_cov=1 -cm line+cond+fsm+tgl+br anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3975229532 |
| Directory | /workspace/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.827880762 |
| Short name | T1161 |
| Test name | |
| Test status | |
| Simulation time | 3071670688 ps |
| CPU time | 264.74 seconds |
| Started | Aug 17 07:27:34 PM PDT 24 |
| Finished | Aug 17 07:32:00 PM PDT 24 |
| Peak memory | 609336 kb |
| Host | smart-100d6141-9c6d-45ca-aef3-f695fd848bd0 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_plic_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +U VM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827880762 -assert nopostproc +UVM_TESTNAME=c hip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.chip_sw_rv_plic_smoketest.827880762 |
| Directory | /workspace/2.chip_sw_rv_plic_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_irq.1969855328 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2672027522 ps |
| CPU time | 367.52 seconds |
| Started | Aug 17 07:21:53 PM PDT 24 |
| Finished | Aug 17 07:28:01 PM PDT 24 |
| Peak memory | 609964 kb |
| Host | smart-0747f4e1-60fd-4d9f-ad24-aab443cb9185 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969855328 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_irq.1969855328 |
| Directory | /workspace/2.chip_sw_rv_timer_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3112285779 |
| Short name | T1281 |
| Test name | |
| Test status | |
| Simulation time | 3166499554 ps |
| CPU time | 272.11 seconds |
| Started | Aug 17 07:29:29 PM PDT 24 |
| Finished | Aug 17 07:34:01 PM PDT 24 |
| Peak memory | 609348 kb |
| Host | smart-ff9ffafd-944b-4388-bc58-f3517a53cfce |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=rv_timer_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES + UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112285779 -assert nopostproc +UVM_TESTNAME =chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev /null -cm_name 2.chip_sw_rv_timer_smoketest.3112285779 |
| Directory | /workspace/2.chip_sw_rv_timer_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3162456755 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 7769211672 ps |
| CPU time | 735.58 seconds |
| Started | Aug 17 07:24:16 PM PDT 24 |
| Finished | Aug 17 07:36:32 PM PDT 24 |
| Peak memory | 610236 kb |
| Host | smart-c303a116-ac02-4ad4-bbc6-2ea8f3676e79 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_alert_test:1:new_rules,test_rom:0 +cdc_instrumen tation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31624567 55 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_alert.3162456755 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_alert/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.728386995 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2269553989 ps |
| CPU time | 381.15 seconds |
| Started | Aug 17 07:28:59 PM PDT 24 |
| Finished | Aug 17 07:35:21 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-ca2ff121-abd5-4167-aa5a-26b7a3643118 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +sw_build_device=sim_dv +sw_images=sensor_ctrl_status_test:1:new_rules,test_rom:0 +cdc_instrume ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7283869 95 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sensor_ctrl_status_intr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sensor_ctrl_status.728386995 |
| Directory | /workspace/2.chip_sw_sensor_ctrl_status/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.3596462063 |
| Short name | T1143 |
| Test name | |
| Test status | |
| Simulation time | 8715723608 ps |
| CPU time | 1630.92 seconds |
| Started | Aug 17 07:19:33 PM PDT 24 |
| Finished | Aug 17 07:46:45 PM PDT 24 |
| Peak memory | 611188 kb |
| Host | smart-3935b679-293c-4cd6-a338-81e7ac6fcaa7 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sleep_pwm_pulses_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596462063 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_pwm_pulses_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm _log /dev/null -cm_name 2.chip_sw_sleep_pwm_pulses.3596462063 |
| Directory | /workspace/2.chip_sw_sleep_pwm_pulses/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1460625589 |
| Short name | T1201 |
| Test name | |
| Test status | |
| Simulation time | 8846130068 ps |
| CPU time | 837.24 seconds |
| Started | Aug 17 07:24:59 PM PDT 24 |
| Finished | Aug 17 07:38:56 PM PDT 24 |
| Peak memory | 611288 kb |
| Host | smart-31d0c1fe-a551-4797-81bd-6e85bedf463d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_no_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460625589 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sl eep_sram_ret_contents_no_scramble.1460625589 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_no_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2478885188 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 8810531524 ps |
| CPU time | 790.31 seconds |
| Started | Aug 17 07:24:39 PM PDT 24 |
| Finished | Aug 17 07:37:49 PM PDT 24 |
| Peak memory | 611308 kb |
| Host | smart-e9fda089-03c1-4bf8-98db-c257d35778fb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_sleep_sram_ret_contents_scramble_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueu e -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478885188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ= chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sleep _sram_ret_contents_scramble.2478885188 |
| Directory | /workspace/2.chip_sw_sleep_sram_ret_contents_scramble/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pass_through.376878694 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 7034160593 ps |
| CPU time | 1005 seconds |
| Started | Aug 17 07:21:04 PM PDT 24 |
| Finished | Aug 17 07:37:50 PM PDT 24 |
| Peak memory | 625488 kb |
| Host | smart-09ff1ce6-5777-42cb-a93e-997b2e5119d9 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_passthrough_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376878694 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_passthrough_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pass_through.376878694 |
| Directory | /workspace/2.chip_sw_spi_device_pass_through/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_pinmux_sleep_retention.2993649072 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 2935867656 ps |
| CPU time | 230.2 seconds |
| Started | Aug 17 07:20:12 PM PDT 24 |
| Finished | Aug 17 07:24:02 PM PDT 24 |
| Peak memory | 618420 kb |
| Host | smart-757d8950-d280-487b-b012-5390c69fb091 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_sleep_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993649072 -assert nopostproc +UVM_TESTN AME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_pinmux_sleep_retention_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_pinmux_sleep_retention.2993649072 |
| Directory | /workspace/2.chip_sw_spi_device_pinmux_sleep_retention/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_device_tpm.364852337 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 3426929121 ps |
| CPU time | 328.78 seconds |
| Started | Aug 17 07:20:12 PM PDT 24 |
| Finished | Aug 17 07:25:41 PM PDT 24 |
| Peak memory | 619860 kb |
| Host | smart-2745bc24-7b84-41a5-9968-53ec131bbf55 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_device_tpm_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364852337 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_device_tpm_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default. vdb -cm_log /dev/null -cm_name 2.chip_sw_spi_device_tpm.364852337 |
| Directory | /workspace/2.chip_sw_spi_device_tpm/latest |
| Test location | /workspace/coverage/default/2.chip_sw_spi_host_tx_rx.3896782295 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 3287757940 ps |
| CPU time | 284.55 seconds |
| Started | Aug 17 07:21:00 PM PDT 24 |
| Finished | Aug 17 07:25:45 PM PDT 24 |
| Peak memory | 609908 kb |
| Host | smart-e95c8028-e4a5-4be1-9402-7664ad03dd78 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=spi_host_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896782295 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_spi_host_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb - cm_log /dev/null -cm_name 2.chip_sw_spi_host_tx_rx.3896782295 |
| Directory | /workspace/2.chip_sw_spi_host_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.3522428420 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 8472665753 ps |
| CPU time | 964.33 seconds |
| Started | Aug 17 07:25:00 PM PDT 24 |
| Finished | Aug 17 07:41:05 PM PDT 24 |
| Peak memory | 610424 kb |
| Host | smart-d8fab81c-0c4b-4556-985c-db549a5d3921 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_execution_main_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522428420 -assert nopostproc +U VM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_execution_main_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/co verage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_execution_main.3522428420 |
| Directory | /workspace/2.chip_sw_sram_ctrl_execution_main/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2598554545 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 4397351506 ps |
| CPU time | 491.73 seconds |
| Started | Aug 17 07:24:53 PM PDT 24 |
| Finished | Aug 17 07:33:05 PM PDT 24 |
| Peak memory | 611644 kb |
| Host | smart-db2bddd8-9b74-473d-b195-8f1a2f3733d4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +en_scb_tl_err_chk=0 +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=sram _ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wor kspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598554545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctr l_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw _sram_ctrl_scrambled_access.2598554545 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.452713541 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 3874202909 ps |
| CPU time | 637.01 seconds |
| Started | Aug 17 07:31:25 PM PDT 24 |
| Finished | Aug 17 07:42:03 PM PDT 24 |
| Peak memory | 610428 kb |
| Host | smart-5b3c8f45-09cf-459c-8c07-763e8f2c24c8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +sw_build_device=sim_dv +s w_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452713541 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_na me 2.chip_sw_sram_ctrl_scrambled_access_jitter_en.452713541 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2968572950 |
| Short name | T1110 |
| Test name | |
| Test status | |
| Simulation time | 3997312286 ps |
| CPU time | 583.26 seconds |
| Started | Aug 17 07:27:20 PM PDT 24 |
| Finished | Aug 17 07:37:03 PM PDT 24 |
| Peak memory | 611108 kb |
| Host | smart-0e9c00e4-55cf-4a8c-8874-93797ee174f2 |
| User | root |
| Command | /workspace/default/simv +mem_sel=main +sw_test_timeout_ns=12_000_000 +bypass_alert_ready_to_end_check=1 +en_jitter=1 +en_scb_tl_err_chk=0 +cal_sys_clk _70mhz=1 +sw_build_device=sim_dv +sw_images=sram_ctrl_scrambled_access_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968572950 -assert nopostproc +UVM_TESTNA ME=chip_base_test +UVM_TEST_SEQ=chip_sw_sram_ctrl_scrambled_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/ default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2968572950 |
| Directory | /workspace/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3963352465 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 3051994256 ps |
| CPU time | 293.14 seconds |
| Started | Aug 17 07:27:01 PM PDT 24 |
| Finished | Aug 17 07:31:54 PM PDT 24 |
| Peak memory | 609316 kb |
| Host | smart-0a6a708f-57d8-45d9-bccf-0d2fe2c74d8d |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sram_ctrl_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963352465 -assert nopostproc +UVM_TESTNAM E=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /de v/null -cm_name 2.chip_sw_sram_ctrl_smoketest.3963352465 |
| Directory | /workspace/2.chip_sw_sram_ctrl_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.1641951978 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 21035643772 ps |
| CPU time | 3219.77 seconds |
| Started | Aug 17 07:23:37 PM PDT 24 |
| Finished | Aug 17 08:17:18 PM PDT 24 |
| Peak memory | 611232 kb |
| Host | smart-7dbbf808-6d59-4171-8727-7a796204a072 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ec_rst_l_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641951978 -assert nopostproc +UVM_T ESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ec_rst_l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/d efault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ec_rst_l.1641951978 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ec_rst_l/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2033557025 |
| Short name | T1232 |
| Test name | |
| Test status | |
| Simulation time | 3975696913 ps |
| CPU time | 710.13 seconds |
| Started | Aug 17 07:22:29 PM PDT 24 |
| Finished | Aug 17 07:34:21 PM PDT 24 |
| Peak memory | 614136 kb |
| Host | smart-2b4ea6dc-2910-4969-b032-cb101cb311cf |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_in_irq_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033557025 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_in_irq_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_in_irq.2033557025 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_in_irq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1509210083 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2913923856 ps |
| CPU time | 297.26 seconds |
| Started | Aug 17 07:22:23 PM PDT 24 |
| Finished | Aug 17 07:27:21 PM PDT 24 |
| Peak memory | 614056 kb |
| Host | smart-16d426ab-c887-4436-af88-c060589dca85 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_inputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1509210083 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_inputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_inputs.1509210083 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_inputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_outputs.1449753585 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 3802514520 ps |
| CPU time | 385.12 seconds |
| Started | Aug 17 07:23:01 PM PDT 24 |
| Finished | Aug 17 07:29:27 PM PDT 24 |
| Peak memory | 609720 kb |
| Host | smart-544af853-f7ea-40d2-9f67-f92946971e43 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_outputs_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449753585 -assert nopostproc +UVM_TE STNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_outputs_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def ault.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_outputs.1449753585 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_outputs/latest |
| Test location | /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3102126199 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 5602436260 ps |
| CPU time | 534.84 seconds |
| Started | Aug 17 07:24:39 PM PDT 24 |
| Finished | Aug 17 07:33:35 PM PDT 24 |
| Peak memory | 611560 kb |
| Host | smart-e09ce2dd-a6f9-405c-bfb5-0761f2e59cd6 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=sysrst_ctrl_ulp_z3_wakeup_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_N O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102126199 -assert nopostproc + UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_sysrst_ctrl_ulp_z3_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/ coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3102126199 |
| Directory | /workspace/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3453677405 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 12840972712 ps |
| CPU time | 2466.54 seconds |
| Started | Aug 17 07:20:21 PM PDT 24 |
| Finished | Aug 17 08:01:28 PM PDT 24 |
| Peak memory | 620304 kb |
| Host | smart-e64e6fb7-45c1-467c-8df0-9d91730b21c4 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3453677405 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_rand_baudrate.3453677405 |
| Directory | /workspace/2.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_smoketest.4222428178 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 3233843640 ps |
| CPU time | 307.19 seconds |
| Started | Aug 17 07:27:15 PM PDT 24 |
| Finished | Aug 17 07:32:23 PM PDT 24 |
| Peak memory | 610004 kb |
| Host | smart-fcac3dc1-c768-458e-b809-f96b6cd62345 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=uart_smoketest:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_ VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222428178 -assert nopostproc +UVM_TESTNAME=chi p_base_test +UVM_TEST_SEQ=chip_sw_uart_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /d ev/null -cm_name 2.chip_sw_uart_smoketest.4222428178 |
| Directory | /workspace/2.chip_sw_uart_smoketest/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx.398952619 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 3872621640 ps |
| CPU time | 656.71 seconds |
| Started | Aug 17 07:20:19 PM PDT 24 |
| Finished | Aug 17 07:31:16 PM PDT 24 |
| Peak memory | 620464 kb |
| Host | smart-38465599-5e09-4a2c-b855-c2996ffe5698 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398952619 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx.398952619 |
| Directory | /workspace/2.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.1248332898 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 3772745779 ps |
| CPU time | 531.09 seconds |
| Started | Aug 17 07:20:33 PM PDT 24 |
| Finished | Aug 17 07:29:24 PM PDT 24 |
| Peak memory | 623560 kb |
| Host | smart-e01d9d69-9b80-4df2-ba24-b8e7cabf9ae2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248332898 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq.1248332898 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2827403942 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 13587361025 ps |
| CPU time | 2105.24 seconds |
| Started | Aug 17 07:20:25 PM PDT 24 |
| Finished | Aug 17 07:55:31 PM PDT 24 |
| Peak memory | 623820 kb |
| Host | smart-df16ab8a-325b-4abf-805d-f4543589c1d1 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827403942 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2827403942 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1328542400 |
| Short name | T1309 |
| Test name | |
| Test status | |
| Simulation time | 78990220640 ps |
| CPU time | 12937.2 seconds |
| Started | Aug 17 07:20:17 PM PDT 24 |
| Finished | Aug 17 10:55:56 PM PDT 24 |
| Peak memory | 636820 kb |
| Host | smart-c499948b-8355-4057-a8d5-4ece7fe721b5 |
| User | root |
| Command | /workspace/default/simv +use_spi_load_bootstrap=1 +calibrate_usb_clk=1 +test_timeout_ns=160_000_000 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test :1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/t ools/sim.tcl +ntb_random_seed=1328542400 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+ cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_bootstrap.1328542400 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_bootstrap/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1399905231 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 4828422280 ps |
| CPU time | 582.86 seconds |
| Started | Aug 17 07:19:41 PM PDT 24 |
| Finished | Aug 17 07:29:25 PM PDT 24 |
| Peak memory | 620692 kb |
| Host | smart-09b4c552-e944-4503-8155-abfd69c798e3 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1399905231 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx1.1399905231 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.446346335 |
| Short name | T1259 |
| Test name | |
| Test status | |
| Simulation time | 4151047684 ps |
| CPU time | 733.83 seconds |
| Started | Aug 17 07:21:18 PM PDT 24 |
| Finished | Aug 17 07:33:32 PM PDT 24 |
| Peak memory | 620408 kb |
| Host | smart-a6ddeb95-973d-4645-b64e-ee87b24d45d9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446346335 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx2.446346335 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1209596828 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 3820442080 ps |
| CPU time | 523.81 seconds |
| Started | Aug 17 07:19:15 PM PDT 24 |
| Finished | Aug 17 07:28:00 PM PDT 24 |
| Peak memory | 620440 kb |
| Host | smart-80e1b77c-b88d-46a0-b7be-43950d6c840a |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209596828 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_sw_uart_tx_rx_idx3.1209596828 |
| Directory | /workspace/2.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_dev.2045511783 |
| Short name | T1342 |
| Test name | |
| Test status | |
| Simulation time | 2879899378 ps |
| CPU time | 172.61 seconds |
| Started | Aug 17 07:24:57 PM PDT 24 |
| Finished | Aug 17 07:27:50 PM PDT 24 |
| Peak memory | 625328 kb |
| Host | smart-6aa1cb89-005f-4b19-957a-0fad614d689b |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=2045511783 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_dev.2045511783 |
| Directory | /workspace/2.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_prod.1662026997 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 2904969709 ps |
| CPU time | 135.94 seconds |
| Started | Aug 17 07:26:12 PM PDT 24 |
| Finished | Aug 17 07:28:28 PM PDT 24 |
| Peak memory | 622644 kb |
| Host | smart-d4f60eb1-4dc8-44c3-817c-cde202292000 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662026997 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_prod.1662026997 |
| Directory | /workspace/2.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/2.chip_tap_straps_testunlock0.1060396239 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 6233544452 ps |
| CPU time | 542.33 seconds |
| Started | Aug 17 07:25:57 PM PDT 24 |
| Finished | Aug 17 07:35:00 PM PDT 24 |
| Peak memory | 633272 kb |
| Host | smart-a9630329-650e-454a-b762-b6690b70fb25 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=1060396239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.chip_tap_straps_testunlock0.1060396239 |
| Directory | /workspace/2.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_dev.3630728860 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 15699500011 ps |
| CPU time | 4639.01 seconds |
| Started | Aug 17 07:32:03 PM PDT 24 |
| Finished | Aug 17 08:49:23 PM PDT 24 |
| Peak memory | 610288 kb |
| Host | smart-5a31a2a6-5f12-4bb8-814e-23c7cb417ec3 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_dev:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630728860 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_dev.3630728860 |
| Directory | /workspace/2.rom_e2e_asm_init_dev/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod.2301085945 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 15120046537 ps |
| CPU time | 3471.12 seconds |
| Started | Aug 17 07:31:24 PM PDT 24 |
| Finished | Aug 17 08:29:15 PM PDT 24 |
| Peak memory | 610312 kb |
| Host | smart-31d06f98-4da9-448c-97a5-fb7372f91539 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301085945 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_ SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_prod.2301085945 |
| Directory | /workspace/2.rom_e2e_asm_init_prod/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.4069676977 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 15596735086 ps |
| CPU time | 3113.64 seconds |
| Started | Aug 17 07:34:07 PM PDT 24 |
| Finished | Aug 17 08:26:01 PM PDT 24 |
| Peak memory | 610272 kb |
| Host | smart-48d52b9e-93ac-4b95-b141-21a6680508ec |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_prod_end:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069676977 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_T EST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_ name 2.rom_e2e_asm_init_prod_end.4069676977 |
| Directory | /workspace/2.rom_e2e_asm_init_prod_end/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_rma.3101240557 |
| Short name | T1193 |
| Test name | |
| Test status | |
| Simulation time | 15127462440 ps |
| CPU time | 3366.09 seconds |
| Started | Aug 17 07:31:19 PM PDT 24 |
| Finished | Aug 17 08:27:26 PM PDT 24 |
| Peak memory | 610256 kb |
| Host | smart-a7ed0b62-88b8-4b85-9d4e-872df7e4faf7 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=20000000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_prod _key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licq ueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101240557 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_S EQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_asm_init_rma.3101240557 |
| Directory | /workspace/2.rom_e2e_asm_init_rma/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.955393980 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 11573064857 ps |
| CPU time | 2767.93 seconds |
| Started | Aug 17 07:31:01 PM PDT 24 |
| Finished | Aug 17 08:17:10 PM PDT 24 |
| Peak memory | 611080 kb |
| Host | smart-137703b8-85d1-45ea-91a0-8cb9a52921d4 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeCustom +sw_test_timeout_ns=410_000_000 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_p rod_key_0:1:ot_flash_binary,otp_img_e2e_bootstrap_entry_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY =UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955393980 -assert nopostproc +UVM_TESTNAME=chip_base_tes t +UVM_TEST_SEQ=chip_sw_rom_e2e_asm_init_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/n ull -cm_name 2.rom_e2e_asm_init_test_unlocked0.955393980 |
| Directory | /workspace/2.rom_e2e_asm_init_test_unlocked0/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_invalid_meas.1895001004 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 15179230296 ps |
| CPU time | 4372.86 seconds |
| Started | Aug 17 07:32:10 PM PDT 24 |
| Finished | Aug 17 08:45:03 PM PDT 24 |
| Peak memory | 610092 kb |
| Host | smart-01ad82a9-5d7e-4119-aabf-b775dda5ac2b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_invalid _meas:1:new_rules,otp_img_keymgr_otp_invalid_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -u cli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895001004 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip _sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_in it_rom_ext_invalid_meas.1895001004 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_meas.4282176223 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 15581234446 ps |
| CPU time | 3233 seconds |
| Started | Aug 17 07:33:19 PM PDT 24 |
| Finished | Aug 17 08:27:12 PM PDT 24 |
| Peak memory | 610232 kb |
| Host | smart-0960bf3b-e091-4d2a-b8d2-381cb22a1bfb |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_meas:1: new_rules,otp_img_keymgr_otp_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspa ce/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282176223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +e n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext_meas.4282176223 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_keymgr_init_rom_ext_no_meas.3751787499 |
| Short name | T1341 |
| Test name | |
| Test status | |
| Simulation time | 14956431370 ps |
| CPU time | 3299.71 seconds |
| Started | Aug 17 07:32:19 PM PDT 24 |
| Finished | Aug 17 08:27:20 PM PDT 24 |
| Peak memory | 610240 kb |
| Host | smart-60c23a0b-a9c7-4e46-b99d-11dd42413dc2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_keymgr_init_otp_no_meas :1:new_rules,otp_img_keymgr_otp_no_meas:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751787499 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_v seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_keymgr_init_rom_ext _no_meas.3751787499 |
| Directory | /workspace/2.rom_e2e_keymgr_init_rom_ext_no_meas/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_self_hash.1919251064 |
| Short name | T1266 |
| Test name | |
| Test status | |
| Simulation time | 26533136384 ps |
| CPU time | 5140.11 seconds |
| Started | Aug 17 07:34:15 PM PDT 24 |
| Finished | Aug 17 08:59:55 PM PDT 24 |
| Peak memory | 610268 kb |
| Host | smart-66cd084a-1aa5-44b5-bf19-6c07a7a4c8b8 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_self_hash_test:1:new_r ules,otp_img_sigverify_spx_prod:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace /mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919251064 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_ cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_self_hash.1919251064 |
| Directory | /workspace/2.rom_e2e_self_hash/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.3955032459 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 14426242916 ps |
| CPU time | 3002.05 seconds |
| Started | Aug 17 07:32:57 PM PDT 24 |
| Finished | Aug 17 08:22:59 PM PDT 24 |
| Peak memory | 610340 kb |
| Host | smart-bbb38b8c-7faf-48b7-9246-a544be87d79c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_shutdown_exception_c:1:ne w_rules,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955032459 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_rom_e2e_shu tdown_exception_c_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_ shutdown_exception_c.3955032459 |
| Directory | /workspace/2.rom_e2e_shutdown_exception_c/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_shutdown_output.3538185775 |
| Short name | T1222 |
| Test name | |
| Test status | |
| Simulation time | 25568734348 ps |
| CPU time | 3487.22 seconds |
| Started | Aug 17 07:32:38 PM PDT 24 |
| Finished | Aug 17 08:30:46 PM PDT 24 |
| Peak memory | 612280 kb |
| Host | smart-a6dae12b-5e1f-4f6a-9d4e-e21473cfc03c |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=20000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=empty_test_slot_a_unsigned:1:ot_f lash_binary,otp_img_shutdown_output_test_unlocked0:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue - ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3538185775 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chi p_sw_rom_e2e_shutdown_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_shutdown_output.3538185775 |
| Directory | /workspace/2.rom_e2e_shutdown_output/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_smoke.611125167 |
| Short name | T1279 |
| Test name | |
| Test status | |
| Simulation time | 15325072280 ps |
| CPU time | 3004.55 seconds |
| Started | Aug 17 07:31:54 PM PDT 24 |
| Finished | Aug 17 08:21:59 PM PDT 24 |
| Peak memory | 610540 kb |
| Host | smart-251d68b7-99c2-498c-89e8-85a61ff8bfc7 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_smoke:1:new_rules,otp_img _secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_to p/hw/dv/tools/sim.tcl +ntb_random_seed=611125167 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm lin e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_smoke.611125167 |
| Directory | /workspace/2.rom_e2e_smoke/latest |
| Test location | /workspace/coverage/default/2.rom_e2e_static_critical.4178760180 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 17616690274 ps |
| CPU time | 3516.39 seconds |
| Started | Aug 17 07:31:32 PM PDT 24 |
| Finished | Aug 17 08:30:09 PM PDT 24 |
| Peak memory | 610848 kb |
| Host | smart-3d3c7a96-8625-470f-8b8c-e9e842f8af3b |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=40000000 +use_otp_image=OtpTypeCustom +sw_build_device=sim_dv +sw_images=rom_e2e_static_critical:1:new_rul es,otp_img_secret2_locked_rma:4,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/m nt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4178760180 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_co v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_e2e_static_critical.4178760180 |
| Directory | /workspace/2.rom_e2e_static_critical/latest |
| Test location | /workspace/coverage/default/2.rom_keymgr_functest.3411867189 |
| Short name | T1208 |
| Test name | |
| Test status | |
| Simulation time | 5684423180 ps |
| CPU time | 595.88 seconds |
| Started | Aug 17 07:29:17 PM PDT 24 |
| Finished | Aug 17 07:39:14 PM PDT 24 |
| Peak memory | 610308 kb |
| Host | smart-73717b67-afd9-40e8-be13-fa01c22e711d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=10_000_000 +sw_build_device=sim_dv +sw_images=keymgr_functest:1:new_rules,test_rom:0 +cdc_instrumentation_ enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411867189 -ass ert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/cover age/default.vdb -cm_log /dev/null -cm_name 2.rom_keymgr_functest.3411867189 |
| Directory | /workspace/2.rom_keymgr_functest/latest |
| Test location | /workspace/coverage/default/2.rom_raw_unlock.2228750894 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 6097248228 ps |
| CPU time | 259.22 seconds |
| Started | Aug 17 07:29:07 PM PDT 24 |
| Finished | Aug 17 07:33:26 PM PDT 24 |
| Peak memory | 624296 kb |
| Host | smart-1e2b0e96-7c48-487f-9bd2-47251a2faae6 |
| User | root |
| Command | /workspace/default/simv +do_creator_sw_cfg_ast_cfg=0 +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceE xternal48Mhz +rom_prod_mode=1 +use_jtag_dmi=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2228750894 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rom_raw_unlock.2228750894 |
| Directory | /workspace/2.rom_raw_unlock/latest |
| Test location | /workspace/coverage/default/2.rom_volatile_raw_unlock.3781039692 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 2571020122 ps |
| CPU time | 117.08 seconds |
| Started | Aug 17 07:27:46 PM PDT 24 |
| Finished | Aug 17 07:29:43 PM PDT 24 |
| Peak memory | 617196 kb |
| Host | smart-8287546d-580b-4ef1-aefa-cd1aa04e4cc0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=200_000_000 +use_otp_image=OtpTypeLcStRaw +chip_clock_source=ChipClockSourceExternal48Mhz +rom_prod_mode=1 +sw_build_device=sim_dv +sw_images=empty_test_slot_a_fake_ecdsa_test_key_0:1:ot_flash_binary,mask_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781039692 -assert nopostproc +UVM_ TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_volatile_raw_unlock_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverag e/default.vdb -cm_log /dev/null -cm_name 2.rom_volatile_raw_unlock.3781039692 |
| Directory | /workspace/2.rom_volatile_raw_unlock/latest |
| Test location | /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1119693445 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 3409211256 ps |
| CPU time | 346.32 seconds |
| Started | Aug 17 07:32:33 PM PDT 24 |
| Finished | Aug 17 07:38:20 PM PDT 24 |
| Peak memory | 649532 kb |
| Host | smart-93bc2ed3-90d6-4dae-9bf8-d9f71b4bbc9d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119693445 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1119693445 |
| Directory | /workspace/21.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119409954 |
| Short name | T1251 |
| Test name | |
| Test status | |
| Simulation time | 4098738306 ps |
| CPU time | 459.84 seconds |
| Started | Aug 17 07:32:24 PM PDT 24 |
| Finished | Aug 17 07:40:04 PM PDT 24 |
| Peak memory | 649568 kb |
| Host | smart-259268d6-ffe0-462c-9d3c-6a740c0d9c30 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119409954 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2119409954 |
| Directory | /workspace/23.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.206100810 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 3511991096 ps |
| CPU time | 354.8 seconds |
| Started | Aug 17 07:34:40 PM PDT 24 |
| Finished | Aug 17 07:40:36 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-54f808eb-cab1-4121-b68b-49593b43268b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206100810 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.chip_s w_alert_handler_lpg_sleep_mode_alerts.206100810 |
| Directory | /workspace/24.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/25.chip_sw_all_escalation_resets.1904416708 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 4681683496 ps |
| CPU time | 550.01 seconds |
| Started | Aug 17 07:32:52 PM PDT 24 |
| Finished | Aug 17 07:42:02 PM PDT 24 |
| Peak memory | 650308 kb |
| Host | smart-e5da6b6a-1c20-470b-bc99-89b99c15456a |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1904416708 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.chip_sw_all_escalation_resets.1904416708 |
| Directory | /workspace/25.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/26.chip_sw_all_escalation_resets.562367292 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 6068273398 ps |
| CPU time | 631.77 seconds |
| Started | Aug 17 07:32:58 PM PDT 24 |
| Finished | Aug 17 07:43:30 PM PDT 24 |
| Peak memory | 650680 kb |
| Host | smart-341f4e24-1761-4897-9fa8-09232ec33253 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 562367292 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.chip_sw_all_escalation_resets.562367292 |
| Directory | /workspace/26.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/28.chip_sw_all_escalation_resets.4133112104 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 5687739240 ps |
| CPU time | 532.55 seconds |
| Started | Aug 17 07:34:07 PM PDT 24 |
| Finished | Aug 17 07:43:00 PM PDT 24 |
| Peak memory | 650348 kb |
| Host | smart-e7bf7e17-7394-41f4-9363-e1babb2029a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4133112104 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.chip_sw_all_escalation_resets.4133112104 |
| Directory | /workspace/28.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1964070534 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 3320938440 ps |
| CPU time | 358.18 seconds |
| Started | Aug 17 07:35:48 PM PDT 24 |
| Finished | Aug 17 07:41:47 PM PDT 24 |
| Peak memory | 648064 kb |
| Host | smart-9ef1fc5c-29a3-4a6d-add5-19dffc38df75 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964070534 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1964070534 |
| Directory | /workspace/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2111492638 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 4417312256 ps |
| CPU time | 348.97 seconds |
| Started | Aug 17 07:29:12 PM PDT 24 |
| Finished | Aug 17 07:35:01 PM PDT 24 |
| Peak memory | 649776 kb |
| Host | smart-1ebf279f-7241-4440-8a44-d9cc48e3dabf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111492638 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_s w_alert_handler_lpg_sleep_mode_alerts.2111492638 |
| Directory | /workspace/3.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2431701960 |
| Short name | T1295 |
| Test name | |
| Test status | |
| Simulation time | 6317192392 ps |
| CPU time | 446.54 seconds |
| Started | Aug 17 07:27:53 PM PDT 24 |
| Finished | Aug 17 07:35:20 PM PDT 24 |
| Peak memory | 610144 kb |
| Host | smart-bbd338a5-41af-44c5-8daa-0b6fa831125a |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=2431701960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2431701960 |
| Directory | /workspace/3.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/3.chip_sw_csrng_edn_concurrency.400859935 |
| Short name | T1112 |
| Test name | |
| Test status | |
| Simulation time | 19716825572 ps |
| CPU time | 4589.63 seconds |
| Started | Aug 17 07:30:07 PM PDT 24 |
| Finished | Aug 17 08:46:37 PM PDT 24 |
| Peak memory | 610980 kb |
| Host | smart-87027775-f2da-40c8-adc5-d36fb2893476 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400859935 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_csrng_edn_concurrency.400859935 |
| Directory | /workspace/3.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2554844198 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 5571334090 ps |
| CPU time | 667.33 seconds |
| Started | Aug 17 07:32:16 PM PDT 24 |
| Finished | Aug 17 07:43:24 PM PDT 24 |
| Peak memory | 611424 kb |
| Host | smart-4ac0a127-c703-4c37-8d9f-6f386c91c79d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2554844198 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_data_integrity_escalation.2554844198 |
| Directory | /workspace/3.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.4056800127 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 8745262397 ps |
| CPU time | 872.84 seconds |
| Started | Aug 17 07:29:00 PM PDT 24 |
| Finished | Aug 17 07:43:33 PM PDT 24 |
| Peak memory | 625472 kb |
| Host | smart-fddf0af2-6502-4c50-aa10-207570514123 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056800127 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 3.chip_sw_lc_ctrl_transition.4056800127 |
| Directory | /workspace/3.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.3139942524 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 3568000500 ps |
| CPU time | 646.9 seconds |
| Started | Aug 17 07:29:07 PM PDT 24 |
| Finished | Aug 17 07:39:54 PM PDT 24 |
| Peak memory | 625140 kb |
| Host | smart-f66e1aac-fed3-477a-aa10-f295ddc37011 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3139942524 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_rand_baudrate.3139942524 |
| Directory | /workspace/3.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx.2246506178 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 4199005210 ps |
| CPU time | 554.98 seconds |
| Started | Aug 17 07:31:41 PM PDT 24 |
| Finished | Aug 17 07:40:57 PM PDT 24 |
| Peak memory | 620404 kb |
| Host | smart-f4f52d8f-3ec5-495e-a077-4ffddf201b41 |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246506178 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx.2246506178 |
| Directory | /workspace/3.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.386244466 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 8904865542 ps |
| CPU time | 864.95 seconds |
| Started | Aug 17 07:30:46 PM PDT 24 |
| Finished | Aug 17 07:45:11 PM PDT 24 |
| Peak memory | 618284 kb |
| Host | smart-8a0d0d19-9036-498b-bced-90ac58f303e0 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=386244466 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_ba udrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_ alt_clk_freq_low_speed.386244466 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1918640263 |
| Short name | T1229 |
| Test name | |
| Test status | |
| Simulation time | 3963799720 ps |
| CPU time | 575.18 seconds |
| Started | Aug 17 07:32:06 PM PDT 24 |
| Finished | Aug 17 07:41:41 PM PDT 24 |
| Peak memory | 620384 kb |
| Host | smart-3d470ed6-2bc2-48ad-ac06-94fafdb2923e |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918640263 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx1.1918640263 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1757270932 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 4216066198 ps |
| CPU time | 675.58 seconds |
| Started | Aug 17 07:29:12 PM PDT 24 |
| Finished | Aug 17 07:40:28 PM PDT 24 |
| Peak memory | 623196 kb |
| Host | smart-8f591264-47f8-45e2-963a-5d8f7d9f98f9 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1757270932 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx2.1757270932 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.562951885 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 4415819510 ps |
| CPU time | 675.65 seconds |
| Started | Aug 17 07:28:04 PM PDT 24 |
| Finished | Aug 17 07:39:20 PM PDT 24 |
| Peak memory | 620420 kb |
| Host | smart-822f0451-b1cb-45ff-9e7c-c2307e73d824 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562951885 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_sw_uart_tx_rx_idx3.562951885 |
| Directory | /workspace/3.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_dev.3041687874 |
| Short name | T1319 |
| Test name | |
| Test status | |
| Simulation time | 5921184131 ps |
| CPU time | 543.93 seconds |
| Started | Aug 17 07:28:39 PM PDT 24 |
| Finished | Aug 17 07:37:44 PM PDT 24 |
| Peak memory | 621696 kb |
| Host | smart-b843857e-ba6f-42ef-8d98-37c42b12b3a0 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3041687874 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_dev.3041687874 |
| Directory | /workspace/3.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_prod.1018854807 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 13674542640 ps |
| CPU time | 1329.39 seconds |
| Started | Aug 17 07:28:22 PM PDT 24 |
| Finished | Aug 17 07:50:32 PM PDT 24 |
| Peak memory | 634024 kb |
| Host | smart-24f09647-9e3b-4c55-bf95-7115fa29e8ef |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018854807 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_prod.1018854807 |
| Directory | /workspace/3.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_rma.2339688606 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 7663596228 ps |
| CPU time | 654.28 seconds |
| Started | Aug 17 07:29:04 PM PDT 24 |
| Finished | Aug 17 07:39:58 PM PDT 24 |
| Peak memory | 625740 kb |
| Host | smart-366e21f4-6a9b-48af-a7b8-7152e4f51792 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339688606 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_rma.2339688606 |
| Directory | /workspace/3.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/3.chip_tap_straps_testunlock0.325335170 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 6758667057 ps |
| CPU time | 616.31 seconds |
| Started | Aug 17 07:28:33 PM PDT 24 |
| Finished | Aug 17 07:38:51 PM PDT 24 |
| Peak memory | 625816 kb |
| Host | smart-07d9d0cf-105e-4a66-9ad0-dd585b2323a5 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=325335170 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm +tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.chip_tap_straps_testunlock0.325335170 |
| Directory | /workspace/3.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.399419323 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 3697037850 ps |
| CPU time | 418.46 seconds |
| Started | Aug 17 07:33:32 PM PDT 24 |
| Finished | Aug 17 07:40:31 PM PDT 24 |
| Peak memory | 649776 kb |
| Host | smart-58e8e6b8-8f77-4593-b916-33e8988cba66 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399419323 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_s w_alert_handler_lpg_sleep_mode_alerts.399419323 |
| Directory | /workspace/30.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/30.chip_sw_all_escalation_resets.2538880226 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 4871294528 ps |
| CPU time | 710.42 seconds |
| Started | Aug 17 07:32:52 PM PDT 24 |
| Finished | Aug 17 07:44:42 PM PDT 24 |
| Peak memory | 650660 kb |
| Host | smart-ce9016d5-671a-45db-8eea-a9e1edff2664 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2538880226 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.chip_sw_all_escalation_resets.2538880226 |
| Directory | /workspace/30.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/31.chip_sw_all_escalation_resets.928980152 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 4280567782 ps |
| CPU time | 550 seconds |
| Started | Aug 17 07:32:21 PM PDT 24 |
| Finished | Aug 17 07:41:32 PM PDT 24 |
| Peak memory | 650532 kb |
| Host | smart-33f5ff31-4a39-4dca-8700-84088f67d8ff |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 928980152 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.chip_sw_all_escalation_resets.928980152 |
| Directory | /workspace/31.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1068801409 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 4069603750 ps |
| CPU time | 466.19 seconds |
| Started | Aug 17 07:33:18 PM PDT 24 |
| Finished | Aug 17 07:41:04 PM PDT 24 |
| Peak memory | 649560 kb |
| Host | smart-9bffb5f1-be68-4f89-a9a4-e5ec988dc815 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068801409 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1068801409 |
| Directory | /workspace/32.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/32.chip_sw_all_escalation_resets.3464931120 |
| Short name | T1183 |
| Test name | |
| Test status | |
| Simulation time | 5049794792 ps |
| CPU time | 518.89 seconds |
| Started | Aug 17 07:35:26 PM PDT 24 |
| Finished | Aug 17 07:44:06 PM PDT 24 |
| Peak memory | 618988 kb |
| Host | smart-ee5fa876-433f-43b1-9fb8-04263e16f6ce |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3464931120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.chip_sw_all_escalation_resets.3464931120 |
| Directory | /workspace/32.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1452540148 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 3705694570 ps |
| CPU time | 307.08 seconds |
| Started | Aug 17 07:33:27 PM PDT 24 |
| Finished | Aug 17 07:38:34 PM PDT 24 |
| Peak memory | 649484 kb |
| Host | smart-a420280f-932b-4269-8d2e-98d4b17534dc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452540148 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1452540148 |
| Directory | /workspace/33.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.314267856 |
| Short name | T1212 |
| Test name | |
| Test status | |
| Simulation time | 3554131938 ps |
| CPU time | 385.17 seconds |
| Started | Aug 17 07:34:08 PM PDT 24 |
| Finished | Aug 17 07:40:34 PM PDT 24 |
| Peak memory | 619408 kb |
| Host | smart-b76bf62c-0b89-44d9-8a36-ecc5621e79c7 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314267856 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.chip_s w_alert_handler_lpg_sleep_mode_alerts.314267856 |
| Directory | /workspace/34.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2886001174 |
| Short name | T1231 |
| Test name | |
| Test status | |
| Simulation time | 3509562660 ps |
| CPU time | 333.89 seconds |
| Started | Aug 17 07:33:01 PM PDT 24 |
| Finished | Aug 17 07:38:36 PM PDT 24 |
| Peak memory | 619364 kb |
| Host | smart-1e95a45b-a96a-46da-83a7-dfd316e729df |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886001174 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2886001174 |
| Directory | /workspace/35.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/38.chip_sw_all_escalation_resets.1740840128 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 4496804238 ps |
| CPU time | 582.51 seconds |
| Started | Aug 17 07:34:56 PM PDT 24 |
| Finished | Aug 17 07:44:39 PM PDT 24 |
| Peak memory | 650564 kb |
| Host | smart-e1f74680-8670-42fc-842d-6874bd74656c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1740840128 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.chip_sw_all_escalation_resets.1740840128 |
| Directory | /workspace/38.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.1101931075 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4281210746 ps |
| CPU time | 390.5 seconds |
| Started | Aug 17 07:34:16 PM PDT 24 |
| Finished | Aug 17 07:40:47 PM PDT 24 |
| Peak memory | 649524 kb |
| Host | smart-4c0b5761-6f28-4d21-92a4-f0a9b12bd756 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1101931075 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1101931075 |
| Directory | /workspace/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/39.chip_sw_all_escalation_resets.753000552 |
| Short name | T1337 |
| Test name | |
| Test status | |
| Simulation time | 5120092112 ps |
| CPU time | 479.12 seconds |
| Started | Aug 17 07:33:57 PM PDT 24 |
| Finished | Aug 17 07:41:56 PM PDT 24 |
| Peak memory | 650576 kb |
| Host | smart-3f126944-2b12-4c5c-88a5-054c05216c25 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 753000552 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.chip_sw_all_escalation_resets.753000552 |
| Directory | /workspace/39.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_all_escalation_resets.2367365457 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 3936180914 ps |
| CPU time | 621.75 seconds |
| Started | Aug 17 07:28:12 PM PDT 24 |
| Finished | Aug 17 07:38:34 PM PDT 24 |
| Peak memory | 650392 kb |
| Host | smart-658a3349-83c1-404f-ae5f-63ba665dff4f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2367365457 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_all_escalation_resets.2367365457 |
| Directory | /workspace/4.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.223274926 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 6720521176 ps |
| CPU time | 407.4 seconds |
| Started | Aug 17 07:29:32 PM PDT 24 |
| Finished | Aug 17 07:36:20 PM PDT 24 |
| Peak memory | 610040 kb |
| Host | smart-fa0a7b49-14c9-4c5c-a56b-79931e84bebd |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=18_000_000 +sw_build_device=sim_dv +sw_images=aon_timer_sleep_wdog_sleep_pause_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_rando m_seed=223274926 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_aon_timer_sleep_wdog_sleep_pause.223274926 |
| Directory | /workspace/4.chip_sw_aon_timer_sleep_wdog_sleep_pause/latest |
| Test location | /workspace/coverage/default/4.chip_sw_csrng_edn_concurrency.2242168787 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 22521052604 ps |
| CPU time | 5003.05 seconds |
| Started | Aug 17 07:29:20 PM PDT 24 |
| Finished | Aug 17 08:52:44 PM PDT 24 |
| Peak memory | 610748 kb |
| Host | smart-2bb2ee7b-4000-4fcb-a219-92531fcbb076 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242168787 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 4.chip_sw_csrng_edn_concurrency.2242168787 |
| Directory | /workspace/4.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/4.chip_sw_data_integrity_escalation.953013575 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 6577044144 ps |
| CPU time | 906.66 seconds |
| Started | Aug 17 07:29:22 PM PDT 24 |
| Finished | Aug 17 07:44:29 PM PDT 24 |
| Peak memory | 611680 kb |
| Host | smart-0a118b63-ca73-4bd8-9a04-13637e5450e7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=953013575 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_data_integrity_escalation.953013575 |
| Directory | /workspace/4.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2584558038 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 12205950517 ps |
| CPU time | 889.06 seconds |
| Started | Aug 17 07:28:36 PM PDT 24 |
| Finished | Aug 17 07:43:25 PM PDT 24 |
| Peak memory | 625516 kb |
| Host | smart-f10f4479-f590-4942-a545-4ea71d6aaf6a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584558038 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 4.chip_sw_lc_ctrl_transition.2584558038 |
| Directory | /workspace/4.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.809226811 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 13304122978 ps |
| CPU time | 2837.4 seconds |
| Started | Aug 17 07:29:44 PM PDT 24 |
| Finished | Aug 17 08:17:02 PM PDT 24 |
| Peak memory | 620244 kb |
| Host | smart-80a51fbf-71a7-4385-b388-70f70d191480 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=809226811 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_rand_baudrate.809226811 |
| Directory | /workspace/4.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx.3452622177 |
| Short name | T1308 |
| Test name | |
| Test status | |
| Simulation time | 4041319220 ps |
| CPU time | 720.77 seconds |
| Started | Aug 17 07:29:14 PM PDT 24 |
| Finished | Aug 17 07:41:16 PM PDT 24 |
| Peak memory | 623224 kb |
| Host | smart-6c307dfb-da02-448e-9ab7-0463e23bb61f |
| User | root |
| Command | /workspace/default/simv +uart_idx=0 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452622177 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx.3452622177 |
| Directory | /workspace/4.chip_sw_uart_tx_rx/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1386889316 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 4342812993 ps |
| CPU time | 502.05 seconds |
| Started | Aug 17 07:31:38 PM PDT 24 |
| Finished | Aug 17 07:40:00 PM PDT 24 |
| Peak memory | 619752 kb |
| Host | smart-cef40aac-a559-4fd5-b721-f7f55bbf9efe |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +chip_clock_source=ChipClockSourceExternal96Mhz +calibrate_usb_clk=1 +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386889316 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq.1386889316 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2752958100 |
| Short name | T1120 |
| Test name | |
| Test status | |
| Simulation time | 8487551891 ps |
| CPU time | 1208.19 seconds |
| Started | Aug 17 07:30:14 PM PDT 24 |
| Finished | Aug 17 07:50:22 PM PDT 24 |
| Peak memory | 618296 kb |
| Host | smart-17c0b58d-d6d1-4102-826a-8ea62c94dfd3 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +chip_clock_source=ChipClockSourceExternal48Mhz +sw_build_device=sim_dv +s w_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /worksp ace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752958100 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_b audrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx _alt_clk_freq_low_speed.2752958100 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.1508665210 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 4792049648 ps |
| CPU time | 664.36 seconds |
| Started | Aug 17 07:29:40 PM PDT 24 |
| Finished | Aug 17 07:40:45 PM PDT 24 |
| Peak memory | 623768 kb |
| Host | smart-887c7ebd-84af-4d41-ae93-9cc7c5001023 |
| User | root |
| Command | /workspace/default/simv +uart_idx=1 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508665210 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx1.1508665210 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx1/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1468595578 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 3745691840 ps |
| CPU time | 514.77 seconds |
| Started | Aug 17 07:35:35 PM PDT 24 |
| Finished | Aug 17 07:44:10 PM PDT 24 |
| Peak memory | 620416 kb |
| Host | smart-cf490c60-d7bb-4366-ba67-48d9ad919eb6 |
| User | root |
| Command | /workspace/default/simv +uart_idx=2 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468595578 -a ssert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa ce/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx2.1468595578 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx2/latest |
| Test location | /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.634883058 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 4335429944 ps |
| CPU time | 563.52 seconds |
| Started | Aug 17 07:30:54 PM PDT 24 |
| Finished | Aug 17 07:40:17 PM PDT 24 |
| Peak memory | 623172 kb |
| Host | smart-de476a4c-432c-4198-8164-6f9e93f1ebc5 |
| User | root |
| Command | /workspace/default/simv +uart_idx=3 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentatio n_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634883058 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_tx_rx_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac e/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_sw_uart_tx_rx_idx3.634883058 |
| Directory | /workspace/4.chip_sw_uart_tx_rx_idx3/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_dev.3582865545 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 11764629320 ps |
| CPU time | 1429.56 seconds |
| Started | Aug 17 07:28:22 PM PDT 24 |
| Finished | Aug 17 07:52:12 PM PDT 24 |
| Peak memory | 625876 kb |
| Host | smart-9860a218-3e99-46ac-b008-8939004708ff |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStDev +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom: new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl + ntb_random_seed=3582865545 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_dev.3582865545 |
| Directory | /workspace/4.chip_tap_straps_dev/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_prod.3896673193 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 11553236428 ps |
| CPU time | 1169.3 seconds |
| Started | Aug 17 07:28:57 PM PDT 24 |
| Finished | Aug 17 07:48:27 PM PDT 24 |
| Peak memory | 621692 kb |
| Host | smart-0a7314c0-d209-4034-9483-085823db2277 |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStProd +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom :new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896673193 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_prod.3896673193 |
| Directory | /workspace/4.chip_tap_straps_prod/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_rma.2584442287 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 5143355571 ps |
| CPU time | 513.38 seconds |
| Started | Aug 17 07:29:23 PM PDT 24 |
| Finished | Aug 17 07:37:57 PM PDT 24 |
| Peak memory | 624300 kb |
| Host | smart-c4715f64-946e-47cb-bd2d-670d0715b867 |
| User | root |
| Command | /workspace/default/simv +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:test_in_rom:new_rules +cdc_instrumentation _enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2584442287 -as sert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/c overage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_rma.2584442287 |
| Directory | /workspace/4.chip_tap_straps_rma/latest |
| Test location | /workspace/coverage/default/4.chip_tap_straps_testunlock0.2540132334 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 7314620522 ps |
| CPU time | 644.83 seconds |
| Started | Aug 17 07:30:02 PM PDT 24 |
| Finished | Aug 17 07:40:47 PM PDT 24 |
| Peak memory | 634028 kb |
| Host | smart-a747cce8-e195-4793-8eca-ac5cf146659c |
| User | root |
| Command | /workspace/default/simv +use_otp_image=OtpTypeLcStTestUnlocked0 +create_jtag_riscv_map=1 +sw_build_device=sim_dv +sw_images=example_test_from_rom:0:te st_in_rom:new_rules +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools /sim.tcl +ntb_random_seed=2540132334 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_tap_straps_vseq +en_cov=1 -cm line+cond+fs m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.chip_tap_straps_testunlock0.2540132334 |
| Directory | /workspace/4.chip_tap_straps_testunlock0/latest |
| Test location | /workspace/coverage/default/40.chip_sw_all_escalation_resets.3648886651 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 4547290104 ps |
| CPU time | 529.68 seconds |
| Started | Aug 17 07:32:36 PM PDT 24 |
| Finished | Aug 17 07:41:26 PM PDT 24 |
| Peak memory | 620432 kb |
| Host | smart-7f898447-790d-4922-82ca-34d34a0de634 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3648886651 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.chip_sw_all_escalation_resets.3648886651 |
| Directory | /workspace/40.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.2060137780 |
| Short name | T1118 |
| Test name | |
| Test status | |
| Simulation time | 3635633096 ps |
| CPU time | 453.92 seconds |
| Started | Aug 17 07:34:26 PM PDT 24 |
| Finished | Aug 17 07:42:01 PM PDT 24 |
| Peak memory | 619660 kb |
| Host | smart-8b83b9da-5ab2-4380-a63e-376efe1936bc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060137780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2060137780 |
| Directory | /workspace/41.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/41.chip_sw_all_escalation_resets.959974388 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 6425937960 ps |
| CPU time | 684.91 seconds |
| Started | Aug 17 07:34:28 PM PDT 24 |
| Finished | Aug 17 07:45:54 PM PDT 24 |
| Peak memory | 650632 kb |
| Host | smart-6b4d36fa-c414-4dd7-869c-6f727bf8a8a7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 959974388 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.chip_sw_all_escalation_resets.959974388 |
| Directory | /workspace/41.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1059559738 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 3995198530 ps |
| CPU time | 332.1 seconds |
| Started | Aug 17 07:34:30 PM PDT 24 |
| Finished | Aug 17 07:40:03 PM PDT 24 |
| Peak memory | 649500 kb |
| Host | smart-0e0d0dfd-7490-4734-88e5-6d87bdd3adb0 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059559738 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1059559738 |
| Directory | /workspace/43.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1805973378 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 4233913960 ps |
| CPU time | 320.52 seconds |
| Started | Aug 17 07:34:06 PM PDT 24 |
| Finished | Aug 17 07:39:27 PM PDT 24 |
| Peak memory | 649332 kb |
| Host | smart-d8f4b6e2-69ae-4cad-b4e7-31919e477eff |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1805973378 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1805973378 |
| Directory | /workspace/44.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/44.chip_sw_all_escalation_resets.1061827114 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 4082451488 ps |
| CPU time | 490.81 seconds |
| Started | Aug 17 07:33:09 PM PDT 24 |
| Finished | Aug 17 07:41:20 PM PDT 24 |
| Peak memory | 650204 kb |
| Host | smart-e066a52d-e199-4913-bdf0-4c8ee6a748ae |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1061827114 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.chip_sw_all_escalation_resets.1061827114 |
| Directory | /workspace/44.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1901745940 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 3284096560 ps |
| CPU time | 370.77 seconds |
| Started | Aug 17 07:34:05 PM PDT 24 |
| Finished | Aug 17 07:40:16 PM PDT 24 |
| Peak memory | 648508 kb |
| Host | smart-11d1176a-f01d-482d-844d-032b337d3c0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901745940 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1901745940 |
| Directory | /workspace/45.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/45.chip_sw_all_escalation_resets.1689139460 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 4397703688 ps |
| CPU time | 470.09 seconds |
| Started | Aug 17 07:33:59 PM PDT 24 |
| Finished | Aug 17 07:41:50 PM PDT 24 |
| Peak memory | 650436 kb |
| Host | smart-4d7d9c98-cbda-48f2-92d5-00fba7095b6d |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1689139460 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.chip_sw_all_escalation_resets.1689139460 |
| Directory | /workspace/45.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.89302239 |
| Short name | T1167 |
| Test name | |
| Test status | |
| Simulation time | 4029497648 ps |
| CPU time | 394.14 seconds |
| Started | Aug 17 07:33:56 PM PDT 24 |
| Finished | Aug 17 07:40:30 PM PDT 24 |
| Peak memory | 649568 kb |
| Host | smart-47d3ccaa-4a4c-436f-80dd-bebfc23a5238 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89302239 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_ escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.chip_sw _alert_handler_lpg_sleep_mode_alerts.89302239 |
| Directory | /workspace/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.3967649034 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 3550484908 ps |
| CPU time | 325.61 seconds |
| Started | Aug 17 07:35:45 PM PDT 24 |
| Finished | Aug 17 07:41:11 PM PDT 24 |
| Peak memory | 649528 kb |
| Host | smart-61cecbcd-7ab4-40c2-bf7e-4d7111b3a1bf |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967649034 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3967649034 |
| Directory | /workspace/48.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.213872455 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 3428466760 ps |
| CPU time | 315.39 seconds |
| Started | Aug 17 07:31:08 PM PDT 24 |
| Finished | Aug 17 07:36:24 PM PDT 24 |
| Peak memory | 649488 kb |
| Host | smart-8f546ae7-e255-4219-a674-b4b313976f99 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=213872455 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw _alert_handler_lpg_sleep_mode_alerts.213872455 |
| Directory | /workspace/5.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3985260994 |
| Short name | T1246 |
| Test name | |
| Test status | |
| Simulation time | 23788677432 ps |
| CPU time | 4658.71 seconds |
| Started | Aug 17 07:30:55 PM PDT 24 |
| Finished | Aug 17 08:48:35 PM PDT 24 |
| Peak memory | 610996 kb |
| Host | smart-c8508cd6-8d6e-48f8-af0c-ec68803716c5 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985260994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 5.chip_sw_csrng_edn_concurrency.3985260994 |
| Directory | /workspace/5.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2444819615 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 5906214668 ps |
| CPU time | 780.42 seconds |
| Started | Aug 17 07:30:08 PM PDT 24 |
| Finished | Aug 17 07:43:09 PM PDT 24 |
| Peak memory | 611672 kb |
| Host | smart-b86f730f-b371-4ec6-b705-73ae76ecf070 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=data_integrity_escalation_reset_test:1:new_rules,test_ro m:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_ra ndom_seed=2444819615 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_data_integrity_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.chip_sw_data_integrity_escalation.2444819615 |
| Directory | /workspace/5.chip_sw_data_integrity_escalation/latest |
| Test location | /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2328362324 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 6295735198 ps |
| CPU time | 542.96 seconds |
| Started | Aug 17 07:29:00 PM PDT 24 |
| Finished | Aug 17 07:38:03 PM PDT 24 |
| Peak memory | 622032 kb |
| Host | smart-2f319bf0-4b98-4aac-b6f2-10cedda89142 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328362324 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 5.chip_sw_lc_ctrl_transition.2328362324 |
| Directory | /workspace/5.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.3495206692 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 3927302946 ps |
| CPU time | 354 seconds |
| Started | Aug 17 07:35:53 PM PDT 24 |
| Finished | Aug 17 07:41:47 PM PDT 24 |
| Peak memory | 649784 kb |
| Host | smart-0e80a5eb-c55d-4b2d-88d9-7f18ea5d615c |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495206692 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 50.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3495206692 |
| Directory | /workspace/50.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.390196223 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 4142216188 ps |
| CPU time | 297.56 seconds |
| Started | Aug 17 07:35:18 PM PDT 24 |
| Finished | Aug 17 07:40:16 PM PDT 24 |
| Peak memory | 649264 kb |
| Host | smart-9f815170-da5f-4508-b326-c7410c24beb9 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390196223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_s w_alert_handler_lpg_sleep_mode_alerts.390196223 |
| Directory | /workspace/51.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/51.chip_sw_all_escalation_resets.1047459801 |
| Short name | T1198 |
| Test name | |
| Test status | |
| Simulation time | 5417523600 ps |
| CPU time | 608.95 seconds |
| Started | Aug 17 07:36:13 PM PDT 24 |
| Finished | Aug 17 07:46:23 PM PDT 24 |
| Peak memory | 650744 kb |
| Host | smart-2a54b479-e4cc-485f-bf52-9071a75517bb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1047459801 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 51.chip_sw_all_escalation_resets.1047459801 |
| Directory | /workspace/51.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2903891214 |
| Short name | T1156 |
| Test name | |
| Test status | |
| Simulation time | 4051982770 ps |
| CPU time | 312.99 seconds |
| Started | Aug 17 07:35:26 PM PDT 24 |
| Finished | Aug 17 07:40:40 PM PDT 24 |
| Peak memory | 619428 kb |
| Host | smart-e696bb50-3a76-4e28-8843-c446a6ec3c0b |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903891214 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 52.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2903891214 |
| Directory | /workspace/52.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2565807312 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 3720230280 ps |
| CPU time | 375.44 seconds |
| Started | Aug 17 07:36:40 PM PDT 24 |
| Finished | Aug 17 07:42:56 PM PDT 24 |
| Peak memory | 649244 kb |
| Host | smart-6c367ad8-1ecd-43b5-9aef-28686d9cba4d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565807312 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2565807312 |
| Directory | /workspace/54.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/54.chip_sw_all_escalation_resets.2680359605 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 6096357412 ps |
| CPU time | 611.81 seconds |
| Started | Aug 17 07:36:44 PM PDT 24 |
| Finished | Aug 17 07:46:56 PM PDT 24 |
| Peak memory | 650600 kb |
| Host | smart-ec4dde01-6ce3-41fa-a70f-7aefbcffa6b4 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2680359605 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 54.chip_sw_all_escalation_resets.2680359605 |
| Directory | /workspace/54.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.2314219517 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 3807542488 ps |
| CPU time | 423 seconds |
| Started | Aug 17 07:34:16 PM PDT 24 |
| Finished | Aug 17 07:41:19 PM PDT 24 |
| Peak memory | 649908 kb |
| Host | smart-6b6f7c9c-639a-4e16-8cc4-1db0a4a60c33 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314219517 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2314219517 |
| Directory | /workspace/56.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/56.chip_sw_all_escalation_resets.3599827707 |
| Short name | T1237 |
| Test name | |
| Test status | |
| Simulation time | 5595516732 ps |
| CPU time | 567.14 seconds |
| Started | Aug 17 07:35:12 PM PDT 24 |
| Finished | Aug 17 07:44:39 PM PDT 24 |
| Peak memory | 650696 kb |
| Host | smart-a3b21323-a94b-4b7f-a3ad-47a3965e3c54 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3599827707 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 56.chip_sw_all_escalation_resets.3599827707 |
| Directory | /workspace/56.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/57.chip_sw_all_escalation_resets.2083675051 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 4184506852 ps |
| CPU time | 525.85 seconds |
| Started | Aug 17 07:34:23 PM PDT 24 |
| Finished | Aug 17 07:43:09 PM PDT 24 |
| Peak memory | 619884 kb |
| Host | smart-66f8a1d2-817f-40dd-9cfd-1770a0f015d6 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2083675051 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 57.chip_sw_all_escalation_resets.2083675051 |
| Directory | /workspace/57.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2109142188 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3916535464 ps |
| CPU time | 343.14 seconds |
| Started | Aug 17 07:36:46 PM PDT 24 |
| Finished | Aug 17 07:42:29 PM PDT 24 |
| Peak memory | 649656 kb |
| Host | smart-27f72a01-8926-4ac3-a7f6-955cf4f1809f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109142188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2109142188 |
| Directory | /workspace/58.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/58.chip_sw_all_escalation_resets.2882771223 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 5487581924 ps |
| CPU time | 450.77 seconds |
| Started | Aug 17 07:34:11 PM PDT 24 |
| Finished | Aug 17 07:41:42 PM PDT 24 |
| Peak memory | 650276 kb |
| Host | smart-9c3eab71-8ee3-4754-b6dd-4a912a561573 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2882771223 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 58.chip_sw_all_escalation_resets.2882771223 |
| Directory | /workspace/58.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.772003730 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 4171995096 ps |
| CPU time | 448.11 seconds |
| Started | Aug 17 07:30:37 PM PDT 24 |
| Finished | Aug 17 07:38:05 PM PDT 24 |
| Peak memory | 649468 kb |
| Host | smart-fa169671-5e86-46fe-8f91-2c19d0c27571 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772003730 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw _alert_handler_lpg_sleep_mode_alerts.772003730 |
| Directory | /workspace/6.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/6.chip_sw_csrng_edn_concurrency.2860454729 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 24435061400 ps |
| CPU time | 4685.92 seconds |
| Started | Aug 17 07:34:51 PM PDT 24 |
| Finished | Aug 17 08:52:57 PM PDT 24 |
| Peak memory | 610200 kb |
| Host | smart-b9b6bd13-4479-4ed3-b5bd-503fad8683fc |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860454729 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 6.chip_sw_csrng_edn_concurrency.2860454729 |
| Directory | /workspace/6.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3011805210 |
| Short name | T1214 |
| Test name | |
| Test status | |
| Simulation time | 14257788533 ps |
| CPU time | 845.04 seconds |
| Started | Aug 17 07:30:04 PM PDT 24 |
| Finished | Aug 17 07:44:10 PM PDT 24 |
| Peak memory | 622080 kb |
| Host | smart-fc699f60-e5e5-4df3-bb85-e82796a42422 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011805210 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 6.chip_sw_lc_ctrl_transition.3011805210 |
| Directory | /workspace/6.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1036875425 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 9094728542 ps |
| CPU time | 1517.43 seconds |
| Started | Aug 17 07:31:01 PM PDT 24 |
| Finished | Aug 17 07:56:20 PM PDT 24 |
| Peak memory | 625100 kb |
| Host | smart-1ff83a90-624a-4e9e-9213-c9bffcc4c578 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1036875425 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.chip_sw_uart_rand_baudrate.1036875425 |
| Directory | /workspace/6.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/60.chip_sw_all_escalation_resets.4218993897 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 5149876670 ps |
| CPU time | 559.61 seconds |
| Started | Aug 17 07:37:09 PM PDT 24 |
| Finished | Aug 17 07:46:29 PM PDT 24 |
| Peak memory | 650380 kb |
| Host | smart-59951d31-4502-4373-a4f4-b5a9eee25dd0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4218993897 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 60.chip_sw_all_escalation_resets.4218993897 |
| Directory | /workspace/60.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3736701142 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 3721926352 ps |
| CPU time | 426.19 seconds |
| Started | Aug 17 07:35:59 PM PDT 24 |
| Finished | Aug 17 07:43:05 PM PDT 24 |
| Peak memory | 649324 kb |
| Host | smart-5962de5b-aead-482d-b99b-a35fe3b9dd5f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736701142 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3736701142 |
| Directory | /workspace/61.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/61.chip_sw_all_escalation_resets.771084135 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 5646919684 ps |
| CPU time | 609.11 seconds |
| Started | Aug 17 07:37:38 PM PDT 24 |
| Finished | Aug 17 07:47:47 PM PDT 24 |
| Peak memory | 620184 kb |
| Host | smart-d0b048b5-272c-435f-a76b-ff9c862b89ab |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 771084135 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 61.chip_sw_all_escalation_resets.771084135 |
| Directory | /workspace/61.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.739379504 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 4000072332 ps |
| CPU time | 542.83 seconds |
| Started | Aug 17 07:35:31 PM PDT 24 |
| Finished | Aug 17 07:44:34 PM PDT 24 |
| Peak memory | 649664 kb |
| Host | smart-c9eefb9b-3952-47c5-828c-10b9a55128af |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739379504 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 63.chip_s w_alert_handler_lpg_sleep_mode_alerts.739379504 |
| Directory | /workspace/63.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2305346532 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 3680551950 ps |
| CPU time | 354.93 seconds |
| Started | Aug 17 07:36:08 PM PDT 24 |
| Finished | Aug 17 07:42:03 PM PDT 24 |
| Peak memory | 649564 kb |
| Host | smart-acbb9611-8709-4560-be40-fd43c7d6da0a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305346532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2305346532 |
| Directory | /workspace/64.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/64.chip_sw_all_escalation_resets.2231780740 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 4388424680 ps |
| CPU time | 468.1 seconds |
| Started | Aug 17 07:35:15 PM PDT 24 |
| Finished | Aug 17 07:43:03 PM PDT 24 |
| Peak memory | 650560 kb |
| Host | smart-a9728070-7877-4759-a9d3-f4697d1f920c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2231780740 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 64.chip_sw_all_escalation_resets.2231780740 |
| Directory | /workspace/64.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.1970365778 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 3627550882 ps |
| CPU time | 531.82 seconds |
| Started | Aug 17 07:35:59 PM PDT 24 |
| Finished | Aug 17 07:44:51 PM PDT 24 |
| Peak memory | 649596 kb |
| Host | smart-88671b66-1ef1-47af-a2e5-275fad23c03a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1970365778 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1970365778 |
| Directory | /workspace/65.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/65.chip_sw_all_escalation_resets.456954093 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 4843250198 ps |
| CPU time | 438.04 seconds |
| Started | Aug 17 07:38:10 PM PDT 24 |
| Finished | Aug 17 07:45:28 PM PDT 24 |
| Peak memory | 650692 kb |
| Host | smart-d330c013-371c-4ae9-a9d6-696f77e78aa0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 456954093 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 65.chip_sw_all_escalation_resets.456954093 |
| Directory | /workspace/65.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/66.chip_sw_all_escalation_resets.2391218655 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 5140162520 ps |
| CPU time | 498.85 seconds |
| Started | Aug 17 07:36:04 PM PDT 24 |
| Finished | Aug 17 07:44:23 PM PDT 24 |
| Peak memory | 650400 kb |
| Host | smart-d09a3810-5337-47a3-8388-ef48ad0e328e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2391218655 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 66.chip_sw_all_escalation_resets.2391218655 |
| Directory | /workspace/66.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.896653488 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 3310646712 ps |
| CPU time | 317.46 seconds |
| Started | Aug 17 07:36:14 PM PDT 24 |
| Finished | Aug 17 07:41:31 PM PDT 24 |
| Peak memory | 649536 kb |
| Host | smart-f2e73fa9-579b-4330-b755-8c336115a092 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896653488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_s w_alert_handler_lpg_sleep_mode_alerts.896653488 |
| Directory | /workspace/67.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/67.chip_sw_all_escalation_resets.937966356 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 6240574620 ps |
| CPU time | 641.95 seconds |
| Started | Aug 17 07:35:25 PM PDT 24 |
| Finished | Aug 17 07:46:07 PM PDT 24 |
| Peak memory | 620452 kb |
| Host | smart-e3d437fa-4752-41e4-bd27-5ffec501e0a7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 937966356 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 67.chip_sw_all_escalation_resets.937966356 |
| Directory | /workspace/67.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1327888268 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 3156608328 ps |
| CPU time | 367.63 seconds |
| Started | Aug 17 07:36:37 PM PDT 24 |
| Finished | Aug 17 07:42:45 PM PDT 24 |
| Peak memory | 649516 kb |
| Host | smart-412aca18-56fc-41d1-acbc-e5d5fd823fd4 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327888268 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1327888268 |
| Directory | /workspace/69.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/69.chip_sw_all_escalation_resets.2399248483 |
| Short name | T1324 |
| Test name | |
| Test status | |
| Simulation time | 6368700680 ps |
| CPU time | 733.22 seconds |
| Started | Aug 17 07:35:56 PM PDT 24 |
| Finished | Aug 17 07:48:10 PM PDT 24 |
| Peak memory | 650752 kb |
| Host | smart-0b86b476-5e29-4e31-8cf8-97a3bddaaaf3 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2399248483 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 69.chip_sw_all_escalation_resets.2399248483 |
| Directory | /workspace/69.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.215216836 |
| Short name | T1135 |
| Test name | |
| Test status | |
| Simulation time | 2922379524 ps |
| CPU time | 367.13 seconds |
| Started | Aug 17 07:31:48 PM PDT 24 |
| Finished | Aug 17 07:37:56 PM PDT 24 |
| Peak memory | 649480 kb |
| Host | smart-6e223cc2-c69d-48b3-b823-629d97fca84e |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=215216836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw _alert_handler_lpg_sleep_mode_alerts.215216836 |
| Directory | /workspace/7.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/7.chip_sw_all_escalation_resets.1665300641 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 5058523704 ps |
| CPU time | 535.65 seconds |
| Started | Aug 17 07:31:05 PM PDT 24 |
| Finished | Aug 17 07:40:01 PM PDT 24 |
| Peak memory | 650740 kb |
| Host | smart-19355157-6add-487c-a527-7c4ea6b74873 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1665300641 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_all_escalation_resets.1665300641 |
| Directory | /workspace/7.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/7.chip_sw_csrng_edn_concurrency.4170186769 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 18552922980 ps |
| CPU time | 4058.13 seconds |
| Started | Aug 17 07:31:40 PM PDT 24 |
| Finished | Aug 17 08:39:19 PM PDT 24 |
| Peak memory | 610992 kb |
| Host | smart-477a7312-e31b-40cd-966d-d380bbdc2a48 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170186769 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 7.chip_sw_csrng_edn_concurrency.4170186769 |
| Directory | /workspace/7.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3086593259 |
| Short name | T1187 |
| Test name | |
| Test status | |
| Simulation time | 13769798564 ps |
| CPU time | 1020.45 seconds |
| Started | Aug 17 07:30:31 PM PDT 24 |
| Finished | Aug 17 07:47:32 PM PDT 24 |
| Peak memory | 622056 kb |
| Host | smart-fd69f7fe-9458-4c7d-8460-df179f1da546 |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086593259 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 7.chip_sw_lc_ctrl_transition.3086593259 |
| Directory | /workspace/7.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2181697845 |
| Short name | T1200 |
| Test name | |
| Test status | |
| Simulation time | 4018701152 ps |
| CPU time | 576.3 seconds |
| Started | Aug 17 07:29:54 PM PDT 24 |
| Finished | Aug 17 07:39:31 PM PDT 24 |
| Peak memory | 624140 kb |
| Host | smart-1726343a-1608-4cf5-aabc-ab6c51928298 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=2181697845 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.chip_sw_uart_rand_baudrate.2181697845 |
| Directory | /workspace/7.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3094922836 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 3925688836 ps |
| CPU time | 386.04 seconds |
| Started | Aug 17 07:36:35 PM PDT 24 |
| Finished | Aug 17 07:43:02 PM PDT 24 |
| Peak memory | 649556 kb |
| Host | smart-e8b1ab81-70e5-47bb-8e63-c1e5cc2a73be |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094922836 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3094922836 |
| Directory | /workspace/70.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/70.chip_sw_all_escalation_resets.2713231950 |
| Short name | T1329 |
| Test name | |
| Test status | |
| Simulation time | 6094705176 ps |
| CPU time | 621.79 seconds |
| Started | Aug 17 07:36:56 PM PDT 24 |
| Finished | Aug 17 07:47:18 PM PDT 24 |
| Peak memory | 611580 kb |
| Host | smart-a1010b98-2956-4a06-8c1e-9612402972df |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2713231950 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 70.chip_sw_all_escalation_resets.2713231950 |
| Directory | /workspace/70.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3887533724 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 3370931320 ps |
| CPU time | 436.16 seconds |
| Started | Aug 17 07:36:31 PM PDT 24 |
| Finished | Aug 17 07:43:47 PM PDT 24 |
| Peak memory | 649408 kb |
| Host | smart-2d06850c-db38-440a-a4b8-d2c525425d11 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3887533724 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3887533724 |
| Directory | /workspace/71.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/71.chip_sw_all_escalation_resets.3795272160 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 6175873726 ps |
| CPU time | 516.24 seconds |
| Started | Aug 17 07:36:18 PM PDT 24 |
| Finished | Aug 17 07:44:55 PM PDT 24 |
| Peak memory | 650652 kb |
| Host | smart-f1cd87ed-32e4-47c5-b380-2f709d7a42fc |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3795272160 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 71.chip_sw_all_escalation_resets.3795272160 |
| Directory | /workspace/71.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2864872994 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 3405513112 ps |
| CPU time | 331.74 seconds |
| Started | Aug 17 07:37:11 PM PDT 24 |
| Finished | Aug 17 07:42:43 PM PDT 24 |
| Peak memory | 649420 kb |
| Host | smart-68a7f52f-b276-4265-b29b-0cc670c25075 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864872994 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2864872994 |
| Directory | /workspace/72.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/72.chip_sw_all_escalation_resets.3432524944 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 4774800696 ps |
| CPU time | 566.33 seconds |
| Started | Aug 17 07:36:18 PM PDT 24 |
| Finished | Aug 17 07:45:45 PM PDT 24 |
| Peak memory | 650796 kb |
| Host | smart-49d64fa9-f5e3-4794-8fa3-4bed5544ebda |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3432524944 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 72.chip_sw_all_escalation_resets.3432524944 |
| Directory | /workspace/72.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.1258360846 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 3931626180 ps |
| CPU time | 397.48 seconds |
| Started | Aug 17 07:36:25 PM PDT 24 |
| Finished | Aug 17 07:43:02 PM PDT 24 |
| Peak memory | 649628 kb |
| Host | smart-a1ef0841-efa7-4c18-ace5-7294444dfbdb |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258360846 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 73.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1258360846 |
| Directory | /workspace/73.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2405786697 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 3866108944 ps |
| CPU time | 324.43 seconds |
| Started | Aug 17 07:36:10 PM PDT 24 |
| Finished | Aug 17 07:41:35 PM PDT 24 |
| Peak memory | 649336 kb |
| Host | smart-0d45c1e9-45b5-4d39-a936-aef872a3ce23 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405786697 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2405786697 |
| Directory | /workspace/74.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/74.chip_sw_all_escalation_resets.32340274 |
| Short name | T1348 |
| Test name | |
| Test status | |
| Simulation time | 6204167602 ps |
| CPU time | 614.4 seconds |
| Started | Aug 17 07:36:12 PM PDT 24 |
| Finished | Aug 17 07:46:26 PM PDT 24 |
| Peak memory | 650628 kb |
| Host | smart-afaaa9e3-8a3f-4219-a5e8-2d5ddd8a2bfb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 32340274 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a ssert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 74.chip_sw_all_escalation_resets.32340274 |
| Directory | /workspace/74.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.498948049 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 4024958646 ps |
| CPU time | 380.85 seconds |
| Started | Aug 17 07:37:49 PM PDT 24 |
| Finished | Aug 17 07:44:10 PM PDT 24 |
| Peak memory | 649276 kb |
| Host | smart-37c174e5-a707-47b3-8b57-061b29325ff5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498948049 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all _escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_s w_alert_handler_lpg_sleep_mode_alerts.498948049 |
| Directory | /workspace/75.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/75.chip_sw_all_escalation_resets.2697024932 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 5001599512 ps |
| CPU time | 651.34 seconds |
| Started | Aug 17 07:37:43 PM PDT 24 |
| Finished | Aug 17 07:48:35 PM PDT 24 |
| Peak memory | 649604 kb |
| Host | smart-b26704ae-7372-487c-b58c-87392d8786c9 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2697024932 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 75.chip_sw_all_escalation_resets.2697024932 |
| Directory | /workspace/75.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.1742317120 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 3790968848 ps |
| CPU time | 305.05 seconds |
| Started | Aug 17 07:39:39 PM PDT 24 |
| Finished | Aug 17 07:44:44 PM PDT 24 |
| Peak memory | 649576 kb |
| Host | smart-03085393-6a09-44d3-b1ef-002c41aed7fc |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742317120 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1742317120 |
| Directory | /workspace/76.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/76.chip_sw_all_escalation_resets.3225424667 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 5146150840 ps |
| CPU time | 556.52 seconds |
| Started | Aug 17 07:37:13 PM PDT 24 |
| Finished | Aug 17 07:46:30 PM PDT 24 |
| Peak memory | 650832 kb |
| Host | smart-d0ab024a-1e0f-4ed3-a3e3-209a1a9112ee |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3225424667 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 76.chip_sw_all_escalation_resets.3225424667 |
| Directory | /workspace/76.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529387386 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 3752230464 ps |
| CPU time | 363.29 seconds |
| Started | Aug 17 07:36:12 PM PDT 24 |
| Finished | Aug 17 07:42:15 PM PDT 24 |
| Peak memory | 649644 kb |
| Host | smart-ce2ecee1-e700-4953-a255-d883f6f1e230 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529387386 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1529387386 |
| Directory | /workspace/77.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/77.chip_sw_all_escalation_resets.1090614668 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 5241008600 ps |
| CPU time | 599.02 seconds |
| Started | Aug 17 07:37:32 PM PDT 24 |
| Finished | Aug 17 07:47:32 PM PDT 24 |
| Peak memory | 650712 kb |
| Host | smart-cc83ea80-98ad-4f2f-9d65-2a2ae9b34c61 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1090614668 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 77.chip_sw_all_escalation_resets.1090614668 |
| Directory | /workspace/77.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.2131854595 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 3943574740 ps |
| CPU time | 388.96 seconds |
| Started | Aug 17 07:37:34 PM PDT 24 |
| Finished | Aug 17 07:44:04 PM PDT 24 |
| Peak memory | 649556 kb |
| Host | smart-d6de6bfd-716f-4246-97e5-8f24f1ae4f1d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2131854595 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 78.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2131854595 |
| Directory | /workspace/78.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1720234873 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 3929690462 ps |
| CPU time | 470.68 seconds |
| Started | Aug 17 07:37:45 PM PDT 24 |
| Finished | Aug 17 07:45:36 PM PDT 24 |
| Peak memory | 649256 kb |
| Host | smart-cdc50ae0-ad6b-4231-a0e8-915c526d6a1f |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720234873 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1720234873 |
| Directory | /workspace/79.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/79.chip_sw_all_escalation_resets.3460994373 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 4790692304 ps |
| CPU time | 690.26 seconds |
| Started | Aug 17 07:37:28 PM PDT 24 |
| Finished | Aug 17 07:48:59 PM PDT 24 |
| Peak memory | 650288 kb |
| Host | smart-79170a7c-7ccd-4a3f-98e6-5b9bcdc60deb |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3460994373 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 79.chip_sw_all_escalation_resets.3460994373 |
| Directory | /workspace/79.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3857446188 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3571476144 ps |
| CPU time | 405.99 seconds |
| Started | Aug 17 07:30:39 PM PDT 24 |
| Finished | Aug 17 07:37:25 PM PDT 24 |
| Peak memory | 649668 kb |
| Host | smart-5bdafc28-3043-40fe-84c0-8a4c6c588502 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3857446188 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_s w_alert_handler_lpg_sleep_mode_alerts.3857446188 |
| Directory | /workspace/8.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/8.chip_sw_all_escalation_resets.1668936399 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 4669174268 ps |
| CPU time | 583.96 seconds |
| Started | Aug 17 07:30:16 PM PDT 24 |
| Finished | Aug 17 07:40:00 PM PDT 24 |
| Peak memory | 650480 kb |
| Host | smart-d493868b-ba27-48ff-b272-915f0ad23cd5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1668936399 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_all_escalation_resets.1668936399 |
| Directory | /workspace/8.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/8.chip_sw_csrng_edn_concurrency.1629449026 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 17989304920 ps |
| CPU time | 3456.66 seconds |
| Started | Aug 17 07:30:23 PM PDT 24 |
| Finished | Aug 17 08:28:00 PM PDT 24 |
| Peak memory | 610808 kb |
| Host | smart-f20ffcb0-8afa-45ee-b872-d231d84184ce |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1629449026 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 8.chip_sw_csrng_edn_concurrency.1629449026 |
| Directory | /workspace/8.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.1603446511 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 6900309204 ps |
| CPU time | 400.98 seconds |
| Started | Aug 17 07:30:00 PM PDT 24 |
| Finished | Aug 17 07:36:41 PM PDT 24 |
| Peak memory | 625364 kb |
| Host | smart-0ec38999-ede2-4d06-9ecd-f06a3332846e |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603446511 -assert nopostproc +UVM_TES TNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau lt.vdb -cm_log /dev/null -cm_name 8.chip_sw_lc_ctrl_transition.1603446511 |
| Directory | /workspace/8.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.1023427780 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 13077624320 ps |
| CPU time | 2156.85 seconds |
| Started | Aug 17 07:30:18 PM PDT 24 |
| Finished | Aug 17 08:06:15 PM PDT 24 |
| Peak memory | 619176 kb |
| Host | smart-24af449b-1947-4969-8dde-8d6db67b7f6d |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=1023427780 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.chip_sw_uart_rand_baudrate.1023427780 |
| Directory | /workspace/8.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2955616019 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 3960529322 ps |
| CPU time | 397.76 seconds |
| Started | Aug 17 07:36:53 PM PDT 24 |
| Finished | Aug 17 07:43:31 PM PDT 24 |
| Peak memory | 649484 kb |
| Host | smart-a65d4a05-5fa9-40b9-a52b-da46bf78f28a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955616019 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2955616019 |
| Directory | /workspace/81.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/81.chip_sw_all_escalation_resets.3957882414 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 5200255712 ps |
| CPU time | 481.89 seconds |
| Started | Aug 17 07:37:57 PM PDT 24 |
| Finished | Aug 17 07:45:59 PM PDT 24 |
| Peak memory | 650836 kb |
| Host | smart-30fe7d23-3a23-459e-b7f7-a82dfd8334da |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3957882414 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 81.chip_sw_all_escalation_resets.3957882414 |
| Directory | /workspace/81.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3799602277 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 4221759036 ps |
| CPU time | 345.75 seconds |
| Started | Aug 17 07:37:03 PM PDT 24 |
| Finished | Aug 17 07:42:49 PM PDT 24 |
| Peak memory | 649796 kb |
| Host | smart-e734a340-3434-4805-bc7e-2c7a6a76e730 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3799602277 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3799602277 |
| Directory | /workspace/82.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/82.chip_sw_all_escalation_resets.2147048532 |
| Short name | T1263 |
| Test name | |
| Test status | |
| Simulation time | 6422740320 ps |
| CPU time | 494.03 seconds |
| Started | Aug 17 07:37:39 PM PDT 24 |
| Finished | Aug 17 07:45:54 PM PDT 24 |
| Peak memory | 650608 kb |
| Host | smart-1919339c-698f-4a02-bec9-7aaf8b52f297 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2147048532 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 82.chip_sw_all_escalation_resets.2147048532 |
| Directory | /workspace/82.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/83.chip_sw_all_escalation_resets.2399968305 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 6256197192 ps |
| CPU time | 542.28 seconds |
| Started | Aug 17 07:39:40 PM PDT 24 |
| Finished | Aug 17 07:48:42 PM PDT 24 |
| Peak memory | 650468 kb |
| Host | smart-cb6fc2aa-9be1-4ef6-b659-1b353df392a1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2399968305 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 83.chip_sw_all_escalation_resets.2399968305 |
| Directory | /workspace/83.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2972438027 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 3898427060 ps |
| CPU time | 360.85 seconds |
| Started | Aug 17 07:37:55 PM PDT 24 |
| Finished | Aug 17 07:43:56 PM PDT 24 |
| Peak memory | 649996 kb |
| Host | smart-c169a524-ea6e-4262-a40f-e3a616969bc5 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972438027 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 84.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2972438027 |
| Directory | /workspace/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2596404573 |
| Short name | T1127 |
| Test name | |
| Test status | |
| Simulation time | 4134342246 ps |
| CPU time | 274.97 seconds |
| Started | Aug 17 07:37:24 PM PDT 24 |
| Finished | Aug 17 07:41:59 PM PDT 24 |
| Peak memory | 649548 kb |
| Host | smart-5e59cf1a-c76d-4089-a66c-24a6114bd18d |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596404573 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_ sw_alert_handler_lpg_sleep_mode_alerts.2596404573 |
| Directory | /workspace/85.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/85.chip_sw_all_escalation_resets.1941458526 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 4790874500 ps |
| CPU time | 497.24 seconds |
| Started | Aug 17 07:37:31 PM PDT 24 |
| Finished | Aug 17 07:45:48 PM PDT 24 |
| Peak memory | 650820 kb |
| Host | smart-ff7592ed-4060-41d6-ab96-a906c2079677 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1941458526 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 85.chip_sw_all_escalation_resets.1941458526 |
| Directory | /workspace/85.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/86.chip_sw_all_escalation_resets.2954833359 |
| Short name | T1138 |
| Test name | |
| Test status | |
| Simulation time | 4529170680 ps |
| CPU time | 699.25 seconds |
| Started | Aug 17 07:37:02 PM PDT 24 |
| Finished | Aug 17 07:48:41 PM PDT 24 |
| Peak memory | 650780 kb |
| Host | smart-559b10a9-f2a0-4e13-b9af-633bd10c5cf7 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2954833359 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 86.chip_sw_all_escalation_resets.2954833359 |
| Directory | /workspace/86.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.3834163065 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 3587316088 ps |
| CPU time | 333.75 seconds |
| Started | Aug 17 07:37:45 PM PDT 24 |
| Finished | Aug 17 07:43:19 PM PDT 24 |
| Peak memory | 649156 kb |
| Host | smart-31c775cd-41bb-46c3-9c41-e417683edeb8 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834163065 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 87.chip_ sw_alert_handler_lpg_sleep_mode_alerts.3834163065 |
| Directory | /workspace/87.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1885118606 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 4166437240 ps |
| CPU time | 414.02 seconds |
| Started | Aug 17 07:37:23 PM PDT 24 |
| Finished | Aug 17 07:44:17 PM PDT 24 |
| Peak memory | 649628 kb |
| Host | smart-017ac885-c339-414d-ac65-3d4b01c2719a |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1885118606 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_ sw_alert_handler_lpg_sleep_mode_alerts.1885118606 |
| Directory | /workspace/89.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/89.chip_sw_all_escalation_resets.587755240 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 5105412336 ps |
| CPU time | 523.41 seconds |
| Started | Aug 17 07:39:09 PM PDT 24 |
| Finished | Aug 17 07:47:53 PM PDT 24 |
| Peak memory | 650664 kb |
| Host | smart-3bf6d061-48df-41e5-8397-d8e85e68027c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 587755240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 89.chip_sw_all_escalation_resets.587755240 |
| Directory | /workspace/89.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.3958393199 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 4159174318 ps |
| CPU time | 327.66 seconds |
| Started | Aug 17 07:31:43 PM PDT 24 |
| Finished | Aug 17 07:37:11 PM PDT 24 |
| Peak memory | 649528 kb |
| Host | smart-8dabb8d3-f91d-405d-9d29-bfa0569e2763 |
| User | root |
| Command | /workspace/default/simv +en_scb=0 +sw_test_timeout_ns=3000_000_000 +bypass_alert_ready_to_end_check=1 +avoid_inject_fatal_error_for_ips=sram_ctrl_main ,flash_ctrl,lc_ctrl*state_regs +avoid_ferr_ips_append=otp_ctrl*u_otp_ctrl_dai,rv_core_ibex*sw_fatal_err +sw_build_device=sim_dv +sw_images=alert_h andler_lpg_sleep_mode_alerts_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -d o /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958393199 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_al l_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_s w_alert_handler_lpg_sleep_mode_alerts.3958393199 |
| Directory | /workspace/9.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest |
| Test location | /workspace/coverage/default/9.chip_sw_csrng_edn_concurrency.1080750341 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 8880716296 ps |
| CPU time | 1773.87 seconds |
| Started | Aug 17 07:33:52 PM PDT 24 |
| Finished | Aug 17 08:03:27 PM PDT 24 |
| Peak memory | 610820 kb |
| Host | smart-832de50e-28cb-44b6-887a-7388371720c2 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=140_000_000 +rng_srate_value_min=15 +rng_srate_value_max=20 +sw_build_device=sim_dv +sw_images=csrng_edn_c oncurrency_test:1:new_rules,test_rom:0 +accelerate_cold_power_up_time=3 +accelerate_regulators_power_up_time=2 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080750341 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_base_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vd b -cm_log /dev/null -cm_name 9.chip_sw_csrng_edn_concurrency.1080750341 |
| Directory | /workspace/9.chip_sw_csrng_edn_concurrency/latest |
| Test location | /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.658645582 |
| Short name | T1242 |
| Test name | |
| Test status | |
| Simulation time | 12227968611 ps |
| CPU time | 805.7 seconds |
| Started | Aug 17 07:31:00 PM PDT 24 |
| Finished | Aug 17 07:44:27 PM PDT 24 |
| Peak memory | 620788 kb |
| Host | smart-99eff5cc-b697-4be2-b769-2732c6047a1a |
| User | root |
| Command | /workspace/default/simv +sw_build_device=sim_dv +sw_images=lc_ctrl_transition_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658645582 -assert nopostproc +UVM_TEST NAME=chip_base_test +UVM_TEST_SEQ=chip_sw_lc_ctrl_transition_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defaul t.vdb -cm_log /dev/null -cm_name 9.chip_sw_lc_ctrl_transition.658645582 |
| Directory | /workspace/9.chip_sw_lc_ctrl_transition/latest |
| Test location | /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3806739727 |
| Short name | T1157 |
| Test name | |
| Test status | |
| Simulation time | 3859292200 ps |
| CPU time | 583.8 seconds |
| Started | Aug 17 07:30:34 PM PDT 24 |
| Finished | Aug 17 07:40:19 PM PDT 24 |
| Peak memory | 619224 kb |
| Host | smart-e2131414-32c4-40de-8699-141e9e466343 |
| User | root |
| Command | /workspace/default/simv +sw_test_timeout_ns=80_000_000 +calibrate_usb_clk=1 +sw_build_device=sim_dv +sw_images=uart_tx_rx_test:1:new_rules,test_rom:0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random _seed=3806739727 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_uart_rand_baudrate_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.chip_sw_uart_rand_baudrate.3806739727 |
| Directory | /workspace/9.chip_sw_uart_rand_baudrate/latest |
| Test location | /workspace/coverage/default/90.chip_sw_all_escalation_resets.3609410081 |
| Short name | T1126 |
| Test name | |
| Test status | |
| Simulation time | 5064731920 ps |
| CPU time | 536.48 seconds |
| Started | Aug 17 07:38:03 PM PDT 24 |
| Finished | Aug 17 07:47:00 PM PDT 24 |
| Peak memory | 650456 kb |
| Host | smart-312b017e-7b82-49ee-91d5-ab3b94606a3e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3609410081 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 90.chip_sw_all_escalation_resets.3609410081 |
| Directory | /workspace/90.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/91.chip_sw_all_escalation_resets.1236574172 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 4217809128 ps |
| CPU time | 435.76 seconds |
| Started | Aug 17 07:37:36 PM PDT 24 |
| Finished | Aug 17 07:44:52 PM PDT 24 |
| Peak memory | 650324 kb |
| Host | smart-69d0d3f3-41cf-4dce-8d10-0afbc4c04ee1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1236574172 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 91.chip_sw_all_escalation_resets.1236574172 |
| Directory | /workspace/91.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/92.chip_sw_all_escalation_resets.1380068960 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 5770075632 ps |
| CPU time | 498.02 seconds |
| Started | Aug 17 07:36:59 PM PDT 24 |
| Finished | Aug 17 07:45:17 PM PDT 24 |
| Peak memory | 611376 kb |
| Host | smart-82c3bd3f-8a20-4f4b-846f-94a1100f9f7f |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1380068960 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 92.chip_sw_all_escalation_resets.1380068960 |
| Directory | /workspace/92.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/93.chip_sw_all_escalation_resets.4177898401 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 6057819050 ps |
| CPU time | 648.24 seconds |
| Started | Aug 17 07:36:58 PM PDT 24 |
| Finished | Aug 17 07:47:46 PM PDT 24 |
| Peak memory | 650424 kb |
| Host | smart-67da33be-3713-44c2-b5af-b939b71fab9c |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4177898401 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 93.chip_sw_all_escalation_resets.4177898401 |
| Directory | /workspace/93.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/94.chip_sw_all_escalation_resets.2182583559 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 4457283090 ps |
| CPU time | 565.02 seconds |
| Started | Aug 17 07:39:12 PM PDT 24 |
| Finished | Aug 17 07:48:37 PM PDT 24 |
| Peak memory | 611604 kb |
| Host | smart-789f1cb9-49f4-46cf-b52e-b4773873e2ad |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2182583559 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 94.chip_sw_all_escalation_resets.2182583559 |
| Directory | /workspace/94.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/95.chip_sw_all_escalation_resets.1036328324 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 5932732192 ps |
| CPU time | 445.11 seconds |
| Started | Aug 17 07:39:00 PM PDT 24 |
| Finished | Aug 17 07:46:26 PM PDT 24 |
| Peak memory | 650848 kb |
| Host | smart-e1128b23-ab5a-4b89-8bf4-fd0a6e695ed1 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 1036328324 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 95.chip_sw_all_escalation_resets.1036328324 |
| Directory | /workspace/95.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/96.chip_sw_all_escalation_resets.254271973 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 5556940748 ps |
| CPU time | 489.47 seconds |
| Started | Aug 17 07:38:08 PM PDT 24 |
| Finished | Aug 17 07:46:18 PM PDT 24 |
| Peak memory | 650796 kb |
| Host | smart-c0e991c6-b92a-48e6-bec0-45773317ecf0 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 254271973 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 96.chip_sw_all_escalation_resets.254271973 |
| Directory | /workspace/96.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/97.chip_sw_all_escalation_resets.4039341676 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 5383617272 ps |
| CPU time | 458.45 seconds |
| Started | Aug 17 07:39:15 PM PDT 24 |
| Finished | Aug 17 07:46:53 PM PDT 24 |
| Peak memory | 650672 kb |
| Host | smart-444f9ae0-b3f4-4007-8b6f-bc9e512bd76e |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 4039341676 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 97.chip_sw_all_escalation_resets.4039341676 |
| Directory | /workspace/97.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/98.chip_sw_all_escalation_resets.2494190488 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 4307073176 ps |
| CPU time | 425.17 seconds |
| Started | Aug 17 07:38:51 PM PDT 24 |
| Finished | Aug 17 07:45:56 PM PDT 24 |
| Peak memory | 650568 kb |
| Host | smart-ff734b71-b15e-4be0-9e6f-7c8cdb2c79ca |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 2494190488 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 98.chip_sw_all_escalation_resets.2494190488 |
| Directory | /workspace/98.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/default/99.chip_sw_all_escalation_resets.3096116974 |
| Short name | T1223 |
| Test name | |
| Test status | |
| Simulation time | 5817033240 ps |
| CPU time | 585.13 seconds |
| Started | Aug 17 07:38:25 PM PDT 24 |
| Finished | Aug 17 07:48:10 PM PDT 24 |
| Peak memory | 620524 kb |
| Host | smart-fb28a44e-f188-4d72-a89f-df7b648c7ee5 |
| User | root |
| Command | /workspace/default/simv +bypass_alert_ready_to_end_check=1 +sw_build_device=sim_dv +sw_images=all_escalation_resets_test:1:new_rules,test_rom:0 +cdc_i nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed= 3096116974 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TEST_SEQ=chip_sw_all_escalation_resets_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch +assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 99.chip_sw_all_escalation_resets.3096116974 |
| Directory | /workspace/99.chip_sw_all_escalation_resets/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.180490848 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 4022688436 ps |
| CPU time | 286.57 seconds |
| Started | Aug 17 07:31:12 PM PDT 24 |
| Finished | Aug 17 07:35:59 PM PDT 24 |
| Peak memory | 641500 kb |
| Host | smart-31937e8c-9d26-400a-a144-5dfdccd23708 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=180490848 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 1.chip_padctrl_attributes.180490848 |
| Directory | /workspace/1.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.3690291162 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 5697378156 ps |
| CPU time | 390.23 seconds |
| Started | Aug 17 07:31:01 PM PDT 24 |
| Finished | Aug 17 07:37:32 PM PDT 24 |
| Peak memory | 657988 kb |
| Host | smart-fae4ae0c-6e6b-4d18-98db-186219618ec0 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690291162 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 2.chip_padctrl_attributes.3690291162 |
| Directory | /workspace/2.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.964000122 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 4878408787 ps |
| CPU time | 263.02 seconds |
| Started | Aug 17 07:31:14 PM PDT 24 |
| Finished | Aug 17 07:35:37 PM PDT 24 |
| Peak memory | 651476 kb |
| Host | smart-d62e973e-d190-454a-a9a1-2cca200d55b7 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964000122 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TES T_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/n ull -cm_name 3.chip_padctrl_attributes.964000122 |
| Directory | /workspace/3.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.2875197593 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 5478291107 ps |
| CPU time | 355.31 seconds |
| Started | Aug 17 07:31:12 PM PDT 24 |
| Finished | Aug 17 07:37:07 PM PDT 24 |
| Peak memory | 657940 kb |
| Host | smart-4445d56a-46cb-4f81-8d3e-70251e0972ca |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875197593 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 4.chip_padctrl_attributes.2875197593 |
| Directory | /workspace/4.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.3774935257 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 4585609360 ps |
| CPU time | 297.13 seconds |
| Started | Aug 17 07:31:11 PM PDT 24 |
| Finished | Aug 17 07:36:08 PM PDT 24 |
| Peak memory | 641536 kb |
| Host | smart-d7d85aff-b434-4dc9-ac0c-166e0750f911 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774935257 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 5.chip_padctrl_attributes.3774935257 |
| Directory | /workspace/5.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3261889369 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 5200985352 ps |
| CPU time | 213.04 seconds |
| Started | Aug 17 07:31:25 PM PDT 24 |
| Finished | Aug 17 07:34:59 PM PDT 24 |
| Peak memory | 641584 kb |
| Host | smart-7ffab366-a0fa-46f0-b754-6ad7f8ec6323 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3261889369 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 7.chip_padctrl_attributes.3261889369 |
| Directory | /workspace/7.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2221629467 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 4917183092 ps |
| CPU time | 326.48 seconds |
| Started | Aug 17 07:31:26 PM PDT 24 |
| Finished | Aug 17 07:36:53 PM PDT 24 |
| Peak memory | 652256 kb |
| Host | smart-56ece822-c08e-4af3-af03-a924b4280784 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2221629467 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 8.chip_padctrl_attributes.2221629467 |
| Directory | /workspace/8.chip_padctrl_attributes/latest |
| Test location | /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.3921074240 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 3780867874 ps |
| CPU time | 187.13 seconds |
| Started | Aug 17 07:31:12 PM PDT 24 |
| Finished | Aug 17 07:34:19 PM PDT 24 |
| Peak memory | 641524 kb |
| Host | smart-bd41d184-c856-45fc-8c81-50107767ef56 |
| User | root |
| Command | /workspace/pad_ctrl_test_mode/simv +use_otp_image=OtpTypeLcStProd +stub_cpu=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921074240 -assert nopostproc +UVM_TESTNAME=chip_base_test +UVM_TE ST_SEQ=chip_padctrl_attributes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/pad_ctrl_test_mode.vdb -cm_log /dev/ null -cm_name 9.chip_padctrl_attributes.3921074240 |
| Directory | /workspace/9.chip_padctrl_attributes/latest |
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