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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.02 95.41 93.69 95.42 94.52 97.53 99.58


Total test records in report: 2936
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T1172 /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3695184372 Aug 17 07:08:11 PM PDT 24 Aug 17 07:14:30 PM PDT 24 4913046840 ps
T1173 /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.3292330513 Aug 17 07:08:30 PM PDT 24 Aug 17 07:49:39 PM PDT 24 25672014768 ps
T1174 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1212321111 Aug 17 07:07:13 PM PDT 24 Aug 17 07:24:57 PM PDT 24 4926437284 ps
T196 /workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.2978084138 Aug 17 07:11:02 PM PDT 24 Aug 17 07:19:19 PM PDT 24 4461396413 ps
T1175 /workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3826554922 Aug 17 07:24:31 PM PDT 24 Aug 17 07:31:47 PM PDT 24 5067105536 ps
T1176 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.4213385335 Aug 17 07:15:08 PM PDT 24 Aug 17 08:13:43 PM PDT 24 14286284528 ps
T1177 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2779481648 Aug 17 07:08:23 PM PDT 24 Aug 17 07:16:39 PM PDT 24 3828005290 ps
T36 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.755067383 Aug 17 07:06:24 PM PDT 24 Aug 17 07:15:01 PM PDT 24 6665672258 ps
T383 /workspace/coverage/default/18.chip_sw_all_escalation_resets.295228608 Aug 17 07:33:50 PM PDT 24 Aug 17 07:43:12 PM PDT 24 4882321940 ps
T1178 /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.4245382307 Aug 17 07:05:29 PM PDT 24 Aug 17 07:16:42 PM PDT 24 9968960644 ps
T1179 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.383630186 Aug 17 07:25:23 PM PDT 24 Aug 17 07:35:54 PM PDT 24 3783900276 ps
T1180 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1724210273 Aug 17 07:15:00 PM PDT 24 Aug 17 07:22:38 PM PDT 24 5108432330 ps
T1181 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2099725229 Aug 17 07:18:41 PM PDT 24 Aug 17 07:22:38 PM PDT 24 2594388090 ps
T1182 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.3717497367 Aug 17 07:31:25 PM PDT 24 Aug 17 07:40:25 PM PDT 24 4466444730 ps
T1183 /workspace/coverage/default/32.chip_sw_all_escalation_resets.3464931120 Aug 17 07:35:26 PM PDT 24 Aug 17 07:44:06 PM PDT 24 5049794792 ps
T1184 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.2066124815 Aug 17 07:27:49 PM PDT 24 Aug 17 07:31:23 PM PDT 24 2398619778 ps
T1185 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.3879169356 Aug 17 07:18:06 PM PDT 24 Aug 17 07:24:06 PM PDT 24 5321458080 ps
T1186 /workspace/coverage/default/1.chip_sw_clkmgr_smoketest.1346653401 Aug 17 07:18:07 PM PDT 24 Aug 17 07:23:15 PM PDT 24 3650541058 ps
T1187 /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.3086593259 Aug 17 07:30:31 PM PDT 24 Aug 17 07:47:32 PM PDT 24 13769798564 ps
T1188 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1668524902 Aug 17 07:13:49 PM PDT 24 Aug 17 07:31:24 PM PDT 24 5749703902 ps
T27 /workspace/coverage/default/0.chip_sw_gpio.651461202 Aug 17 07:05:23 PM PDT 24 Aug 17 07:13:32 PM PDT 24 3532341150 ps
T1189 /workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1101121543 Aug 17 07:14:35 PM PDT 24 Aug 17 07:24:18 PM PDT 24 5461714254 ps
T1190 /workspace/coverage/default/0.chip_sw_example_flash.2319169011 Aug 17 07:05:47 PM PDT 24 Aug 17 07:10:20 PM PDT 24 3495935110 ps
T674 /workspace/coverage/default/50.chip_sw_all_escalation_resets.1785419207 Aug 17 07:34:13 PM PDT 24 Aug 17 07:45:39 PM PDT 24 5411103484 ps
T374 /workspace/coverage/default/1.chip_sw_hmac_enc.2376361508 Aug 17 07:14:02 PM PDT 24 Aug 17 07:18:18 PM PDT 24 3156091416 ps
T1191 /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.81487950 Aug 17 07:09:52 PM PDT 24 Aug 17 07:28:34 PM PDT 24 5762679930 ps
T242 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3468619235 Aug 17 07:28:13 PM PDT 24 Aug 17 07:45:16 PM PDT 24 10012410784 ps
T1192 /workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1913881639 Aug 17 07:23:10 PM PDT 24 Aug 17 07:38:58 PM PDT 24 7989478743 ps
T1193 /workspace/coverage/default/2.rom_e2e_asm_init_rma.3101240557 Aug 17 07:31:19 PM PDT 24 Aug 17 08:27:26 PM PDT 24 15127462440 ps
T1194 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.468825460 Aug 17 07:12:11 PM PDT 24 Aug 17 08:51:14 PM PDT 24 23567659814 ps
T1195 /workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1460140163 Aug 17 07:14:01 PM PDT 24 Aug 17 07:15:38 PM PDT 24 2561766992 ps
T1196 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.3548117005 Aug 17 07:22:01 PM PDT 24 Aug 17 07:41:29 PM PDT 24 5764715598 ps
T797 /workspace/coverage/default/23.chip_sw_all_escalation_resets.4040688611 Aug 17 07:32:16 PM PDT 24 Aug 17 07:42:16 PM PDT 24 4952642356 ps
T1197 /workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.658782123 Aug 17 07:10:32 PM PDT 24 Aug 17 07:15:03 PM PDT 24 2784162690 ps
T727 /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1776887421 Aug 17 07:37:14 PM PDT 24 Aug 17 07:43:32 PM PDT 24 3068569696 ps
T1198 /workspace/coverage/default/51.chip_sw_all_escalation_resets.1047459801 Aug 17 07:36:13 PM PDT 24 Aug 17 07:46:23 PM PDT 24 5417523600 ps
T1199 /workspace/coverage/default/2.chip_sw_otp_ctrl_ecc_error_vendor_test.376284370 Aug 17 07:21:38 PM PDT 24 Aug 17 07:26:37 PM PDT 24 3311039984 ps
T1200 /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.2181697845 Aug 17 07:29:54 PM PDT 24 Aug 17 07:39:31 PM PDT 24 4018701152 ps
T744 /workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3664962175 Aug 17 07:33:03 PM PDT 24 Aug 17 07:39:24 PM PDT 24 3873823788 ps
T1201 /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1460625589 Aug 17 07:24:59 PM PDT 24 Aug 17 07:38:56 PM PDT 24 8846130068 ps
T1202 /workspace/coverage/default/1.chip_sw_ast_clk_outputs.150219169 Aug 17 07:17:43 PM PDT 24 Aug 17 07:35:25 PM PDT 24 6651144168 ps
T1203 /workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1553648314 Aug 17 07:12:52 PM PDT 24 Aug 17 07:41:30 PM PDT 24 8493170760 ps
T1204 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.3840235089 Aug 17 07:12:52 PM PDT 24 Aug 17 07:34:11 PM PDT 24 6695345138 ps
T1205 /workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3347716364 Aug 17 07:32:39 PM PDT 24 Aug 17 07:40:21 PM PDT 24 6222399393 ps
T1206 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.695510469 Aug 17 07:06:53 PM PDT 24 Aug 17 07:12:31 PM PDT 24 3111507256 ps
T1207 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.1509677536 Aug 17 07:10:23 PM PDT 24 Aug 17 08:14:45 PM PDT 24 21598980329 ps
T334 /workspace/coverage/default/2.chip_sw_rstmgr_alert_info.3005503281 Aug 17 07:22:22 PM PDT 24 Aug 17 07:47:31 PM PDT 24 11171472890 ps
T1208 /workspace/coverage/default/2.rom_keymgr_functest.3411867189 Aug 17 07:29:17 PM PDT 24 Aug 17 07:39:14 PM PDT 24 5684423180 ps
T1209 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1484761859 Aug 17 07:27:23 PM PDT 24 Aug 17 07:38:55 PM PDT 24 4313453804 ps
T1210 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.38017259 Aug 17 07:10:21 PM PDT 24 Aug 17 08:28:13 PM PDT 24 47555631678 ps
T337 /workspace/coverage/default/2.chip_sw_entropy_src_csrng.4021869225 Aug 17 07:31:21 PM PDT 24 Aug 17 07:50:10 PM PDT 24 6669593940 ps
T330 /workspace/coverage/default/1.chip_plic_all_irqs_0.3480323607 Aug 17 07:14:46 PM PDT 24 Aug 17 07:36:42 PM PDT 24 6088328772 ps
T364 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.50507073 Aug 17 07:06:01 PM PDT 24 Aug 17 07:23:28 PM PDT 24 5253948744 ps
T1211 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2618947022 Aug 17 07:09:18 PM PDT 24 Aug 17 07:16:46 PM PDT 24 4791805974 ps
T1212 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.314267856 Aug 17 07:34:08 PM PDT 24 Aug 17 07:40:34 PM PDT 24 3554131938 ps
T1213 /workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.632984055 Aug 17 07:21:01 PM PDT 24 Aug 17 07:29:42 PM PDT 24 7906442986 ps
T137 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.1838298982 Aug 17 07:11:03 PM PDT 24 Aug 17 07:22:02 PM PDT 24 5928806900 ps
T1214 /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.3011805210 Aug 17 07:30:04 PM PDT 24 Aug 17 07:44:10 PM PDT 24 14257788533 ps
T1215 /workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1941472106 Aug 17 07:11:43 PM PDT 24 Aug 17 07:20:47 PM PDT 24 5023522232 ps
T1216 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.2016870659 Aug 17 07:13:54 PM PDT 24 Aug 17 07:17:53 PM PDT 24 3014795662 ps
T1217 /workspace/coverage/default/2.chip_sw_alert_handler_entropy.127330724 Aug 17 07:25:31 PM PDT 24 Aug 17 07:31:14 PM PDT 24 3475110274 ps
T39 /workspace/coverage/default/0.chip_sw_spi_device_tpm.2799147539 Aug 17 07:06:01 PM PDT 24 Aug 17 07:10:57 PM PDT 24 3374502365 ps
T787 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.213872455 Aug 17 07:31:08 PM PDT 24 Aug 17 07:36:24 PM PDT 24 3428466760 ps
T1218 /workspace/coverage/default/2.chip_sw_edn_kat.1178114516 Aug 17 07:23:46 PM PDT 24 Aug 17 07:35:55 PM PDT 24 3436815114 ps
T518 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1907786416 Aug 17 07:05:27 PM PDT 24 Aug 17 07:20:15 PM PDT 24 4762786734 ps
T781 /workspace/coverage/default/84.chip_sw_all_escalation_resets.2514333895 Aug 17 07:37:53 PM PDT 24 Aug 17 07:45:17 PM PDT 24 5014257214 ps
T775 /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.1107699067 Aug 17 07:35:17 PM PDT 24 Aug 17 07:40:29 PM PDT 24 3451637176 ps
T1219 /workspace/coverage/default/0.chip_sw_kmac_smoketest.2898320249 Aug 17 07:09:05 PM PDT 24 Aug 17 07:14:05 PM PDT 24 3109979976 ps
T1220 /workspace/coverage/default/1.rom_keymgr_functest.2144343881 Aug 17 07:19:09 PM PDT 24 Aug 17 07:30:47 PM PDT 24 5111247168 ps
T768 /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1720234873 Aug 17 07:37:45 PM PDT 24 Aug 17 07:45:36 PM PDT 24 3929690462 ps
T1221 /workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4043944432 Aug 17 07:27:45 PM PDT 24 Aug 17 07:52:37 PM PDT 24 9470356663 ps
T1222 /workspace/coverage/default/2.rom_e2e_shutdown_output.3538185775 Aug 17 07:32:38 PM PDT 24 Aug 17 08:30:46 PM PDT 24 25568734348 ps
T1223 /workspace/coverage/default/99.chip_sw_all_escalation_resets.3096116974 Aug 17 07:38:25 PM PDT 24 Aug 17 07:48:10 PM PDT 24 5817033240 ps
T1224 /workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2981476144 Aug 17 07:24:39 PM PDT 24 Aug 17 07:32:58 PM PDT 24 4226237460 ps
T1225 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.308430951 Aug 17 07:11:53 PM PDT 24 Aug 17 07:36:17 PM PDT 24 16231723153 ps
T1226 /workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3111463552 Aug 17 07:12:01 PM PDT 24 Aug 17 07:28:07 PM PDT 24 6237228290 ps
T197 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.4252982871 Aug 17 07:05:59 PM PDT 24 Aug 17 07:13:25 PM PDT 24 4217810526 ps
T164 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3868089673 Aug 17 07:07:50 PM PDT 24 Aug 17 07:09:35 PM PDT 24 2787286889 ps
T1227 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1597371878 Aug 17 07:24:53 PM PDT 24 Aug 17 08:25:56 PM PDT 24 18846290581 ps
T1228 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2906647914 Aug 17 07:17:45 PM PDT 24 Aug 17 07:21:15 PM PDT 24 2792617297 ps
T1229 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.1918640263 Aug 17 07:32:06 PM PDT 24 Aug 17 07:41:41 PM PDT 24 3963799720 ps
T1230 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac.946672009 Aug 17 07:24:09 PM PDT 24 Aug 17 07:28:59 PM PDT 24 3201066760 ps
T1231 /workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2886001174 Aug 17 07:33:01 PM PDT 24 Aug 17 07:38:36 PM PDT 24 3509562660 ps
T1232 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2033557025 Aug 17 07:22:29 PM PDT 24 Aug 17 07:34:21 PM PDT 24 3975696913 ps
T138 /workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.1653034836 Aug 17 07:13:23 PM PDT 24 Aug 17 07:21:40 PM PDT 24 7984935400 ps
T1233 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.2300754475 Aug 17 07:09:57 PM PDT 24 Aug 17 07:18:30 PM PDT 24 5270122810 ps
T1234 /workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3080252715 Aug 17 07:19:17 PM PDT 24 Aug 17 07:22:51 PM PDT 24 2580327500 ps
T754 /workspace/coverage/default/71.chip_sw_all_escalation_resets.3795272160 Aug 17 07:36:18 PM PDT 24 Aug 17 07:44:55 PM PDT 24 6175873726 ps
T431 /workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.504625640 Aug 17 07:19:07 PM PDT 24 Aug 17 07:47:28 PM PDT 24 25033262358 ps
T1235 /workspace/coverage/default/1.chip_tap_straps_dev.1081112465 Aug 17 07:20:02 PM PDT 24 Aug 17 07:24:59 PM PDT 24 4618104856 ps
T1236 /workspace/coverage/default/1.chip_sw_rstmgr_sw_req.348706670 Aug 17 07:10:39 PM PDT 24 Aug 17 07:17:02 PM PDT 24 3668463820 ps
T158 /workspace/coverage/default/1.rom_raw_unlock.3627315336 Aug 17 07:18:03 PM PDT 24 Aug 17 07:21:57 PM PDT 24 4837937347 ps
T1237 /workspace/coverage/default/56.chip_sw_all_escalation_resets.3599827707 Aug 17 07:35:12 PM PDT 24 Aug 17 07:44:39 PM PDT 24 5595516732 ps
T300 /workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.600570225 Aug 17 07:26:49 PM PDT 24 Aug 17 07:31:32 PM PDT 24 3488793224 ps
T174 /workspace/coverage/default/0.chip_sw_lc_ctrl_program_error.1649898943 Aug 17 07:09:52 PM PDT 24 Aug 17 07:17:01 PM PDT 24 4093234200 ps
T771 /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.1103327217 Aug 17 07:36:41 PM PDT 24 Aug 17 07:43:40 PM PDT 24 3506128736 ps
T1238 /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.2218476415 Aug 17 07:13:48 PM PDT 24 Aug 17 07:21:24 PM PDT 24 3613984730 ps
T1239 /workspace/coverage/default/2.chip_sw_edn_sw_mode.1509079335 Aug 17 07:25:20 PM PDT 24 Aug 17 07:46:29 PM PDT 24 7046321432 ps
T1240 /workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2266008635 Aug 17 07:19:19 PM PDT 24 Aug 17 07:23:12 PM PDT 24 2935081814 ps
T708 /workspace/coverage/default/0.rom_raw_unlock.493172787 Aug 17 07:08:37 PM PDT 24 Aug 17 07:13:50 PM PDT 24 6021561286 ps
T1241 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.2526015837 Aug 17 07:22:17 PM PDT 24 Aug 17 07:39:26 PM PDT 24 5201949312 ps
T170 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1951031364 Aug 17 07:08:55 PM PDT 24 Aug 17 07:17:39 PM PDT 24 5341655204 ps
T1242 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.658645582 Aug 17 07:31:00 PM PDT 24 Aug 17 07:44:27 PM PDT 24 12227968611 ps
T265 /workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2542059731 Aug 17 07:26:39 PM PDT 24 Aug 17 07:31:37 PM PDT 24 2546434508 ps
T1243 /workspace/coverage/default/0.chip_tap_straps_prod.2167560609 Aug 17 07:06:47 PM PDT 24 Aug 17 07:38:02 PM PDT 24 16898938288 ps
T690 /workspace/coverage/default/1.chip_sw_power_sleep_load.3510267423 Aug 17 07:17:00 PM PDT 24 Aug 17 07:25:17 PM PDT 24 4737786600 ps
T801 /workspace/coverage/default/11.chip_sw_all_escalation_resets.3150695126 Aug 17 07:30:23 PM PDT 24 Aug 17 07:41:35 PM PDT 24 4579002584 ps
T765 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1115622011 Aug 17 07:32:04 PM PDT 24 Aug 17 07:38:25 PM PDT 24 2995866264 ps
T90 /workspace/coverage/default/6.chip_sw_all_escalation_resets.69576999 Aug 17 07:30:24 PM PDT 24 Aug 17 07:41:26 PM PDT 24 5177886236 ps
T1244 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.3291945136 Aug 17 07:22:45 PM PDT 24 Aug 17 07:43:59 PM PDT 24 7270677336 ps
T1245 /workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2195883333 Aug 17 07:31:15 PM PDT 24 Aug 17 07:36:54 PM PDT 24 7472034581 ps
T1246 /workspace/coverage/default/5.chip_sw_csrng_edn_concurrency.3985260994 Aug 17 07:30:55 PM PDT 24 Aug 17 08:48:35 PM PDT 24 23788677432 ps
T1247 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1901955962 Aug 17 07:07:15 PM PDT 24 Aug 17 07:11:09 PM PDT 24 3172052990 ps
T1248 /workspace/coverage/default/0.chip_sw_power_idle_load.1585721630 Aug 17 07:12:22 PM PDT 24 Aug 17 07:23:35 PM PDT 24 4859757838 ps
T371 /workspace/coverage/default/2.chip_sw_aon_timer_irq.2830553380 Aug 17 07:21:55 PM PDT 24 Aug 17 07:30:48 PM PDT 24 3677498154 ps
T1249 /workspace/coverage/default/2.chip_sw_hmac_smoketest.4055555117 Aug 17 07:28:04 PM PDT 24 Aug 17 07:33:39 PM PDT 24 3486190552 ps
T751 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1538374277 Aug 17 07:32:36 PM PDT 24 Aug 17 07:40:55 PM PDT 24 3741111600 ps
T200 /workspace/coverage/default/1.chip_jtag_csr_rw.3071718358 Aug 17 07:07:38 PM PDT 24 Aug 17 07:30:11 PM PDT 24 10085219800 ps
T1250 /workspace/coverage/default/2.chip_sw_flash_crash_alert.2250956458 Aug 17 07:26:05 PM PDT 24 Aug 17 07:38:14 PM PDT 24 5874697024 ps
T653 /workspace/coverage/default/0.chip_sw_edn_boot_mode.490261027 Aug 17 07:08:56 PM PDT 24 Aug 17 07:20:10 PM PDT 24 2939744928 ps
T1251 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2119409954 Aug 17 07:32:24 PM PDT 24 Aug 17 07:40:04 PM PDT 24 4098738306 ps
T1252 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.947359432 Aug 17 07:26:15 PM PDT 24 Aug 17 07:37:47 PM PDT 24 4623159242 ps
T1253 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.233337963 Aug 17 07:25:43 PM PDT 24 Aug 17 07:35:55 PM PDT 24 4302295792 ps
T201 /workspace/coverage/default/1.chip_jtag_mem_access.4057147151 Aug 17 07:07:24 PM PDT 24 Aug 17 07:30:10 PM PDT 24 13931706425 ps
T1254 /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3949791457 Aug 17 07:14:48 PM PDT 24 Aug 17 07:19:18 PM PDT 24 3088100780 ps
T1255 /workspace/coverage/default/2.chip_sw_kmac_app_rom.758312928 Aug 17 07:26:29 PM PDT 24 Aug 17 07:30:12 PM PDT 24 2557303696 ps
T198 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2486844387 Aug 17 07:09:18 PM PDT 24 Aug 17 07:20:47 PM PDT 24 6596094426 ps
T720 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1061827114 Aug 17 07:33:09 PM PDT 24 Aug 17 07:41:20 PM PDT 24 4082451488 ps
T1256 /workspace/coverage/default/2.chip_sw_otbn_randomness.3348944043 Aug 17 07:23:15 PM PDT 24 Aug 17 07:39:12 PM PDT 24 5923400488 ps
T1257 /workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3655625201 Aug 17 07:17:53 PM PDT 24 Aug 17 07:28:24 PM PDT 24 10299048880 ps
T432 /workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1311768989 Aug 17 07:16:18 PM PDT 24 Aug 17 07:25:59 PM PDT 24 8104493132 ps
T1258 /workspace/coverage/default/0.chip_sw_uart_smoketest.2281819616 Aug 17 07:14:36 PM PDT 24 Aug 17 07:17:55 PM PDT 24 2539504292 ps
T266 /workspace/coverage/default/78.chip_sw_all_escalation_resets.1196388720 Aug 17 07:36:53 PM PDT 24 Aug 17 07:45:57 PM PDT 24 5466780312 ps
T1259 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.446346335 Aug 17 07:21:18 PM PDT 24 Aug 17 07:33:32 PM PDT 24 4151047684 ps
T1260 /workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.884562280 Aug 17 07:21:12 PM PDT 24 Aug 17 07:29:24 PM PDT 24 4821043240 ps
T332 /workspace/coverage/default/1.chip_sw_rstmgr_alert_info.2254701060 Aug 17 07:13:58 PM PDT 24 Aug 17 07:44:21 PM PDT 24 11009723640 ps
T1261 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1785777903 Aug 17 07:23:23 PM PDT 24 Aug 17 07:30:23 PM PDT 24 5375037650 ps
T1262 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3578085945 Aug 17 07:25:41 PM PDT 24 Aug 17 07:33:03 PM PDT 24 4415091122 ps
T1263 /workspace/coverage/default/82.chip_sw_all_escalation_resets.2147048532 Aug 17 07:37:39 PM PDT 24 Aug 17 07:45:54 PM PDT 24 6422740320 ps
T1264 /workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.495041409 Aug 17 07:15:29 PM PDT 24 Aug 17 10:44:32 PM PDT 24 79100115256 ps
T199 /workspace/coverage/default/1.chip_sw_power_virus.1667960377 Aug 17 07:21:16 PM PDT 24 Aug 17 07:47:05 PM PDT 24 5959747920 ps
T1265 /workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3485798628 Aug 17 07:08:28 PM PDT 24 Aug 17 07:13:10 PM PDT 24 3115247318 ps
T53 /workspace/coverage/default/0.chip_sw_sleep_pin_retention.4067894490 Aug 17 07:08:08 PM PDT 24 Aug 17 07:14:19 PM PDT 24 5003254024 ps
T691 /workspace/coverage/default/0.chip_sw_power_sleep_load.2584749760 Aug 17 07:16:04 PM PDT 24 Aug 17 07:22:26 PM PDT 24 4050474698 ps
T1266 /workspace/coverage/default/2.rom_e2e_self_hash.1919251064 Aug 17 07:34:15 PM PDT 24 Aug 17 08:59:55 PM PDT 24 26533136384 ps
T267 /workspace/coverage/default/97.chip_sw_all_escalation_resets.4039341676 Aug 17 07:39:15 PM PDT 24 Aug 17 07:46:53 PM PDT 24 5383617272 ps
T736 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.3509196405 Aug 17 07:15:46 PM PDT 24 Aug 17 07:37:15 PM PDT 24 10098152132 ps
T745 /workspace/coverage/default/42.chip_sw_all_escalation_resets.261392524 Aug 17 07:33:54 PM PDT 24 Aug 17 07:46:16 PM PDT 24 5660121550 ps
T1267 /workspace/coverage/default/1.chip_sw_flash_init.3728174490 Aug 17 07:11:16 PM PDT 24 Aug 17 07:49:29 PM PDT 24 26284803000 ps
T1268 /workspace/coverage/default/1.chip_sw_hmac_multistream.863535916 Aug 17 07:13:40 PM PDT 24 Aug 17 07:50:30 PM PDT 24 7744070996 ps
T51 /workspace/coverage/default/0.chip_sw_alert_test.639990247 Aug 17 07:08:40 PM PDT 24 Aug 17 07:15:07 PM PDT 24 3341338248 ps
T1269 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.4949883 Aug 17 07:09:32 PM PDT 24 Aug 17 07:15:56 PM PDT 24 3359941136 ps
T1270 /workspace/coverage/default/0.chip_sw_clkmgr_jitter.1270110884 Aug 17 07:06:54 PM PDT 24 Aug 17 07:10:08 PM PDT 24 2064594894 ps
T1271 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1495535772 Aug 17 07:09:15 PM PDT 24 Aug 17 07:19:02 PM PDT 24 4704530808 ps
T1272 /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2793283865 Aug 17 07:09:09 PM PDT 24 Aug 17 07:13:07 PM PDT 24 2613540797 ps
T1273 /workspace/coverage/default/1.chip_sw_kmac_app_rom.1188935277 Aug 17 07:15:40 PM PDT 24 Aug 17 07:19:43 PM PDT 24 2557732032 ps
T1274 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.472459678 Aug 17 07:08:18 PM PDT 24 Aug 17 07:20:06 PM PDT 24 4950989708 ps
T1275 /workspace/coverage/default/1.chip_sw_rstmgr_smoketest.353396215 Aug 17 07:22:27 PM PDT 24 Aug 17 07:26:03 PM PDT 24 2638307792 ps
T23 /workspace/coverage/default/0.chip_sw_usbdev_stream.2852928503 Aug 17 07:10:01 PM PDT 24 Aug 17 08:19:11 PM PDT 24 18965408108 ps
T1276 /workspace/coverage/default/0.chip_sw_otp_ctrl_ecc_error_vendor_test.2515099931 Aug 17 07:05:35 PM PDT 24 Aug 17 07:11:36 PM PDT 24 3091559040 ps
T764 /workspace/coverage/default/25.chip_sw_all_escalation_resets.1904416708 Aug 17 07:32:52 PM PDT 24 Aug 17 07:42:02 PM PDT 24 4681683496 ps
T336 /workspace/coverage/default/0.chip_sw_entropy_src_csrng.2884132336 Aug 17 07:15:32 PM PDT 24 Aug 17 07:46:16 PM PDT 24 7653684632 ps
T1277 /workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2170943577 Aug 17 07:11:41 PM PDT 24 Aug 17 07:17:01 PM PDT 24 2946620256 ps
T1278 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.4001476356 Aug 17 07:23:06 PM PDT 24 Aug 17 07:32:35 PM PDT 24 4965311920 ps
T770 /workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.849593276 Aug 17 07:33:47 PM PDT 24 Aug 17 07:40:13 PM PDT 24 3741974260 ps
T1279 /workspace/coverage/default/2.rom_e2e_smoke.611125167 Aug 17 07:31:54 PM PDT 24 Aug 17 08:21:59 PM PDT 24 15325072280 ps
T1280 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1990309515 Aug 17 07:23:23 PM PDT 24 Aug 17 07:46:07 PM PDT 24 7468617780 ps
T310 /workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1886642809 Aug 17 07:21:26 PM PDT 24 Aug 17 07:29:10 PM PDT 24 3869684544 ps
T350 /workspace/coverage/default/1.chip_sw_pwrmgr_lowpower_cancel.1799755036 Aug 17 07:16:30 PM PDT 24 Aug 17 07:23:41 PM PDT 24 3970560628 ps
T1281 /workspace/coverage/default/2.chip_sw_rv_timer_smoketest.3112285779 Aug 17 07:29:29 PM PDT 24 Aug 17 07:34:01 PM PDT 24 3166499554 ps
T1282 /workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3987467479 Aug 17 07:10:35 PM PDT 24 Aug 17 07:16:08 PM PDT 24 4461126512 ps
T1283 /workspace/coverage/default/2.chip_sw_rstmgr_smoketest.2623877616 Aug 17 07:27:43 PM PDT 24 Aug 17 07:31:53 PM PDT 24 2513128404 ps
T1284 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.85118183 Aug 17 07:09:22 PM PDT 24 Aug 17 07:29:25 PM PDT 24 7068439118 ps
T1285 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1621481896 Aug 17 07:14:41 PM PDT 24 Aug 17 07:25:12 PM PDT 24 5530917778 ps
T1286 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.3842722430 Aug 17 07:15:12 PM PDT 24 Aug 17 07:22:01 PM PDT 24 5726641656 ps
T161 /workspace/coverage/default/2.chip_plic_all_irqs_10.2415545563 Aug 17 07:25:37 PM PDT 24 Aug 17 07:34:28 PM PDT 24 3536609208 ps
T1287 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2111416323 Aug 17 07:21:44 PM PDT 24 Aug 17 07:36:25 PM PDT 24 8271803272 ps
T1288 /workspace/coverage/default/1.chip_sw_example_manufacturer.4146118600 Aug 17 07:11:18 PM PDT 24 Aug 17 07:16:33 PM PDT 24 2749221624 ps
T779 /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.2325551934 Aug 17 07:32:41 PM PDT 24 Aug 17 07:39:19 PM PDT 24 4065201620 ps
T1289 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.891922414 Aug 17 07:12:44 PM PDT 24 Aug 17 07:42:51 PM PDT 24 7163553674 ps
T240 /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2671977538 Aug 17 07:06:33 PM PDT 24 Aug 17 08:29:57 PM PDT 24 47129974733 ps
T1290 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.3392582687 Aug 17 07:08:40 PM PDT 24 Aug 17 07:26:53 PM PDT 24 5674560096 ps
T69 /workspace/coverage/default/0.chip_sw_usbdev_pincfg.3948072589 Aug 17 07:08:07 PM PDT 24 Aug 17 09:02:48 PM PDT 24 31803389940 ps
T1291 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2568633870 Aug 17 07:16:57 PM PDT 24 Aug 17 07:21:52 PM PDT 24 3584631163 ps
T776 /workspace/coverage/default/72.chip_sw_all_escalation_resets.3432524944 Aug 17 07:36:18 PM PDT 24 Aug 17 07:45:45 PM PDT 24 4774800696 ps
T1292 /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3050272795 Aug 17 07:08:31 PM PDT 24 Aug 17 07:28:43 PM PDT 24 9399526088 ps
T1293 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3538941556 Aug 17 07:08:37 PM PDT 24 Aug 17 07:18:57 PM PDT 24 3809619412 ps
T445 /workspace/coverage/default/0.rom_e2e_jtag_inject_dev.560284885 Aug 17 07:09:47 PM PDT 24 Aug 17 07:50:56 PM PDT 24 24797970849 ps
T1294 /workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.2767812141 Aug 17 07:32:18 PM PDT 24 Aug 17 07:38:50 PM PDT 24 3435442636 ps
T1295 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2431701960 Aug 17 07:27:53 PM PDT 24 Aug 17 07:35:20 PM PDT 24 6317192392 ps
T778 /workspace/coverage/default/10.chip_sw_all_escalation_resets.990033173 Aug 17 07:30:34 PM PDT 24 Aug 17 07:42:01 PM PDT 24 6043680296 ps
T1296 /workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.4043141129 Aug 17 07:13:11 PM PDT 24 Aug 17 07:19:25 PM PDT 24 4656442568 ps
T1297 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2409621159 Aug 17 07:16:51 PM PDT 24 Aug 17 07:25:41 PM PDT 24 4711640960 ps
T1298 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.1044443170 Aug 17 07:19:19 PM PDT 24 Aug 17 07:28:18 PM PDT 24 3249562720 ps
T251 /workspace/coverage/default/2.chip_jtag_mem_access.700766321 Aug 17 07:18:24 PM PDT 24 Aug 17 07:43:31 PM PDT 24 13928083901 ps
T1299 /workspace/coverage/default/1.rom_e2e_smoke.589595747 Aug 17 07:22:44 PM PDT 24 Aug 17 08:25:34 PM PDT 24 15089580584 ps
T1300 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.3238418638 Aug 17 07:25:20 PM PDT 24 Aug 17 07:32:41 PM PDT 24 3010907760 ps
T1301 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1790213877 Aug 17 07:22:52 PM PDT 24 Aug 17 08:30:18 PM PDT 24 14075365826 ps
T1302 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4079148540 Aug 17 07:25:50 PM PDT 24 Aug 17 07:36:28 PM PDT 24 4612036840 ps
T1303 /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3683996153 Aug 17 07:13:25 PM PDT 24 Aug 17 07:17:04 PM PDT 24 2979572040 ps
T1304 /workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.294519363 Aug 17 07:04:39 PM PDT 24 Aug 17 10:46:16 PM PDT 24 77968113357 ps
T110 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.2401861253 Aug 17 07:08:24 PM PDT 24 Aug 17 07:35:38 PM PDT 24 24899463808 ps
T1305 /workspace/coverage/default/0.chip_sw_csrng_kat_test.2466850730 Aug 17 07:08:37 PM PDT 24 Aug 17 07:11:49 PM PDT 24 3047188188 ps
T1306 /workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2775248021 Aug 17 07:26:59 PM PDT 24 Aug 17 07:31:04 PM PDT 24 2768397945 ps
T785 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2909677937 Aug 17 07:33:59 PM PDT 24 Aug 17 07:39:01 PM PDT 24 3534513628 ps
T1307 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2323599725 Aug 17 07:12:04 PM PDT 24 Aug 17 07:37:21 PM PDT 24 11781072705 ps
T1308 /workspace/coverage/default/4.chip_sw_uart_tx_rx.3452622177 Aug 17 07:29:14 PM PDT 24 Aug 17 07:41:16 PM PDT 24 4041319220 ps
T1309 /workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.1328542400 Aug 17 07:20:17 PM PDT 24 Aug 17 10:55:56 PM PDT 24 78990220640 ps
T1310 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.2208029545 Aug 17 07:22:31 PM PDT 24 Aug 17 07:56:13 PM PDT 24 14124402897 ps
T718 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.1347815979 Aug 17 07:33:20 PM PDT 24 Aug 17 07:41:42 PM PDT 24 3735271800 ps
T1311 /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1887458695 Aug 17 07:05:16 PM PDT 24 Aug 17 07:10:04 PM PDT 24 2874462636 ps
T709 /workspace/coverage/default/2.rom_raw_unlock.2228750894 Aug 17 07:29:07 PM PDT 24 Aug 17 07:33:26 PM PDT 24 6097248228 ps
T1312 /workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2539409733 Aug 17 07:23:47 PM PDT 24 Aug 17 07:26:25 PM PDT 24 2247138112 ps
T260 /workspace/coverage/default/0.rom_e2e_jtag_debug_test_unlocked0.3660673491 Aug 17 07:12:36 PM PDT 24 Aug 17 07:51:03 PM PDT 24 9946731445 ps
T1313 /workspace/coverage/default/2.chip_sw_hmac_oneshot.1265933476 Aug 17 07:26:32 PM PDT 24 Aug 17 07:30:58 PM PDT 24 3327579400 ps
T241 /workspace/coverage/default/2.chip_sw_flash_init.1304717105 Aug 17 07:21:17 PM PDT 24 Aug 17 07:55:22 PM PDT 24 17303670936 ps
T1314 /workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.384069363 Aug 17 07:08:39 PM PDT 24 Aug 17 07:22:54 PM PDT 24 7626934846 ps
T1315 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1412804664 Aug 17 07:19:43 PM PDT 24 Aug 17 07:37:00 PM PDT 24 8260927020 ps
T1316 /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.290725926 Aug 17 07:10:23 PM PDT 24 Aug 17 07:19:17 PM PDT 24 4070283810 ps
T268 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.251998492 Aug 17 07:11:38 PM PDT 24 Aug 17 07:24:19 PM PDT 24 6300906876 ps
T1317 /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.3949197170 Aug 17 07:06:00 PM PDT 24 Aug 17 10:00:42 PM PDT 24 59719336182 ps
T796 /workspace/coverage/default/65.chip_sw_all_escalation_resets.456954093 Aug 17 07:38:10 PM PDT 24 Aug 17 07:45:28 PM PDT 24 4843250198 ps
T1318 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.1496594698 Aug 17 07:08:16 PM PDT 24 Aug 17 08:10:48 PM PDT 24 16846369460 ps
T1319 /workspace/coverage/default/3.chip_tap_straps_dev.3041687874 Aug 17 07:28:39 PM PDT 24 Aug 17 07:37:44 PM PDT 24 5921184131 ps
T232 /workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2023082328 Aug 17 07:24:27 PM PDT 24 Aug 17 08:28:35 PM PDT 24 17644561536 ps
T382 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3781346563 Aug 17 07:26:22 PM PDT 24 Aug 17 07:34:46 PM PDT 24 4923984440 ps
T780 /workspace/coverage/default/0.chip_sw_all_escalation_resets.2813903891 Aug 17 07:05:23 PM PDT 24 Aug 17 07:16:07 PM PDT 24 4983229588 ps
T1320 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.2088904077 Aug 17 07:28:22 PM PDT 24 Aug 17 07:32:04 PM PDT 24 2886299129 ps
T1321 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1406961194 Aug 17 07:09:04 PM PDT 24 Aug 17 07:45:55 PM PDT 24 13051456385 ps
T1322 /workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2467351586 Aug 17 07:19:49 PM PDT 24 Aug 17 07:24:16 PM PDT 24 2954294958 ps
T1323 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.1430471167 Aug 17 07:22:54 PM PDT 24 Aug 17 08:17:08 PM PDT 24 11525928785 ps
T1324 /workspace/coverage/default/69.chip_sw_all_escalation_resets.2399248483 Aug 17 07:35:56 PM PDT 24 Aug 17 07:48:10 PM PDT 24 6368700680 ps
T1325 /workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2402589794 Aug 17 07:14:00 PM PDT 24 Aug 17 08:15:45 PM PDT 24 15110487956 ps
T1326 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1219168655 Aug 17 07:08:35 PM PDT 24 Aug 17 07:18:51 PM PDT 24 5070719019 ps
T1327 /workspace/coverage/default/0.chip_sw_usbdev_setuprx.3107054008 Aug 17 07:05:16 PM PDT 24 Aug 17 07:14:43 PM PDT 24 3556678880 ps
T1328 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.739434539 Aug 17 07:08:40 PM PDT 24 Aug 17 10:35:12 PM PDT 24 254484265764 ps
T1329 /workspace/coverage/default/70.chip_sw_all_escalation_resets.2713231950 Aug 17 07:36:56 PM PDT 24 Aug 17 07:47:18 PM PDT 24 6094705176 ps
T1330 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3292652023 Aug 17 07:15:43 PM PDT 24 Aug 17 07:25:38 PM PDT 24 3407139844 ps
T140 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2896138359 Aug 17 07:13:54 PM PDT 24 Aug 17 07:19:50 PM PDT 24 5013298488 ps
T70 /workspace/coverage/default/0.chip_sw_usbdev_pullup.1550115717 Aug 17 07:06:24 PM PDT 24 Aug 17 07:12:13 PM PDT 24 3424801088 ps
T1331 /workspace/coverage/default/0.chip_sw_csrng_lc_hw_debug_en_test.2637883596 Aug 17 07:06:11 PM PDT 24 Aug 17 07:15:49 PM PDT 24 6994317320 ps
T355 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.2269144177 Aug 17 07:14:08 PM PDT 24 Aug 17 07:30:19 PM PDT 24 5427266120 ps
T1332 /workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1250343819 Aug 17 07:35:48 PM PDT 24 Aug 17 07:46:30 PM PDT 24 5360758769 ps
T1333 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.2981145834 Aug 17 07:32:18 PM PDT 24 Aug 17 07:48:19 PM PDT 24 10682644938 ps
T1334 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.670445690 Aug 17 07:22:50 PM PDT 24 Aug 17 07:40:00 PM PDT 24 5793936714 ps
T1335 /workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2015675928 Aug 17 07:10:46 PM PDT 24 Aug 17 07:17:50 PM PDT 24 4353571818 ps
T1336 /workspace/coverage/default/2.chip_sw_rstmgr_sw_req.2289950309 Aug 17 07:22:48 PM PDT 24 Aug 17 07:29:25 PM PDT 24 3544088928 ps
T799 /workspace/coverage/default/80.chip_sw_all_escalation_resets.3193046376 Aug 17 07:39:11 PM PDT 24 Aug 17 07:47:04 PM PDT 24 4091198740 ps
T1337 /workspace/coverage/default/39.chip_sw_all_escalation_resets.753000552 Aug 17 07:33:57 PM PDT 24 Aug 17 07:41:56 PM PDT 24 5120092112 ps
T766 /workspace/coverage/default/26.chip_sw_all_escalation_resets.562367292 Aug 17 07:32:58 PM PDT 24 Aug 17 07:43:30 PM PDT 24 6068273398 ps
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