Toggle Coverage for Module :
hmac
| Total | Covered | Percent |
Totals |
33 |
33 |
100.00 |
Total Bits |
316 |
316 |
100.00 |
Total Bits 0->1 |
158 |
158 |
100.00 |
Total Bits 1->0 |
158 |
158 |
100.00 |
| | | |
Ports |
33 |
33 |
100.00 |
Port Bits |
316 |
316 |
100.00 |
Port Bits 0->1 |
158 |
158 |
100.00 |
Port Bits 1->0 |
158 |
158 |
100.00 |
Port Details
Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
clk_i |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
rst_ni |
Yes |
Yes |
T46,T53,T47 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.d_ready |
Yes |
Yes |
T46,T53,T47 |
Yes |
T1,T2,T3 |
INPUT |
tl_i.a_user.data_intg[6:0] |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_user.cmd_intg[6:0] |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_user.instr_type[3:0] |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_user.rsvd[4:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_data[31:0] |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_mask[3:0] |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_address[12:0] |
Yes |
Yes |
*T98,*T100,*T185 |
Yes |
T98,T100,T185 |
INPUT |
tl_i.a_address[15:13] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[16] |
Yes |
Yes |
*T83,*T347,*T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_address[19:17] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[20] |
Yes |
Yes |
*T83,*T347,*T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_address[23:21] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[24] |
Yes |
Yes |
*T83,*T347,*T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_address[29:25] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_address[30] |
Yes |
Yes |
*T83,*T347,*T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_i.a_address[31] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_source[5:0] |
Yes |
Yes |
*T30,*T101,*T98 |
Yes |
T30,T101,T98 |
INPUT |
tl_i.a_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_size[1:0] |
Yes |
Yes |
T98,T99,T100 |
Yes |
T98,T99,T100 |
INPUT |
tl_i.a_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
INPUT |
tl_i.a_opcode[2:0] |
Yes |
Yes |
T347,T348,T667 |
Yes |
T347,T348,T667 |
INPUT |
tl_i.a_valid |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
INPUT |
tl_o.a_ready |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
OUTPUT |
tl_o.d_error |
Yes |
Yes |
T98,T99,T100 |
Yes |
T98,T99,T100 |
OUTPUT |
tl_o.d_user.data_intg[6:0] |
Yes |
Yes |
T347,T348,T667 |
Yes |
T347,T348,T667 |
OUTPUT |
tl_o.d_user.rsp_intg[6:0] |
Yes |
Yes |
T347,T348,T667 |
Yes |
T347,T348,T667 |
OUTPUT |
tl_o.d_data[31:0] |
Yes |
Yes |
T83,T347,T348 |
Yes |
T347,T348,T667 |
OUTPUT |
tl_o.d_sink |
Yes |
Yes |
T98,T99,T100 |
Yes |
T98,T99,T100 |
OUTPUT |
tl_o.d_source[5:0] |
Yes |
Yes |
*T30,*T101,*T98 |
Yes |
T30,T101,T98 |
OUTPUT |
tl_o.d_source[7:6] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_size[1:0] |
Yes |
Yes |
T98,T99,T100 |
Yes |
T98,T99,T100 |
OUTPUT |
tl_o.d_param[2:0] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_opcode[0] |
Yes |
Yes |
*T83,*T347,*T348 |
Yes |
T347,T348,T667 |
OUTPUT |
tl_o.d_opcode[2:1] |
Unreachable |
Unreachable |
|
Unreachable |
|
OUTPUT |
tl_o.d_valid |
Yes |
Yes |
T83,T347,T348 |
Yes |
T83,T347,T348 |
OUTPUT |
alert_rx_i[0].ack_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
INPUT |
alert_rx_i[0].ack_p |
Yes |
Yes |
T83,T102,T266 |
Yes |
T83,T102,T266 |
INPUT |
alert_rx_i[0].ping_n |
Yes |
Yes |
T102,T266,T103 |
Yes |
T102,T266,T103 |
INPUT |
alert_rx_i[0].ping_p |
Yes |
Yes |
T102,T266,T103 |
Yes |
T102,T266,T103 |
INPUT |
alert_tx_o[0].alert_n |
Yes |
Yes |
T1,T2,T3 |
Yes |
T1,T2,T3 |
OUTPUT |
alert_tx_o[0].alert_p |
Yes |
Yes |
T83,T102,T266 |
Yes |
T83,T102,T266 |
OUTPUT |
intr_hmac_done_o |
Yes |
Yes |
T347,T348,T344 |
Yes |
T347,T348,T344 |
OUTPUT |
intr_fifo_empty_o |
Yes |
Yes |
T344,T354,T355 |
Yes |
T344,T354,T355 |
OUTPUT |
intr_hmac_err_o |
Yes |
Yes |
T344,T354,T355 |
Yes |
T344,T354,T355 |
OUTPUT |
idle_o[3:0] |
Yes |
Yes |
T1,T2,T3 |
Yes |
T46,T53,T47 |
OUTPUT |
*Tests covering at least one bit in the range