Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : i2c
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.18 93.18

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.top_earlgrey.u_i2c0 93.10 93.10
tb.dut.top_earlgrey.u_i2c1 93.14 93.14
tb.dut.top_earlgrey.u_i2c2 93.14 93.14


Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.10 93.10


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.10 93.10


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.14 93.14


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : i2c
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 352 328 93.18
Total Bits 0->1 176 164 93.18
Total Bits 1->0 176 164 93.18

Ports 54 48 88.89
Port Bits 352 328 93.18
Port Bits 0->1 176 164 93.18
Port Bits 1->0 176 164 93.18

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T35,T34,T68 Yes T35,T34,T68 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T35,T34,T68 Yes T35,T34,T68 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T35,T34,T68 Yes T35,T34,T68 INPUT
tl_o.a_ready Yes Yes T35,T34,T68 Yes T35,T34,T68 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T35,T34,T68 Yes T35,T34,T68 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T35,T34,T68 Yes T35,T34,T68 OUTPUT
tl_o.d_data[31:0] Yes Yes T35,T34,T68 Yes T35,T34,T68 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T35,*T34,*T68 Yes T35,T34,T68 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T35,T34,T68 Yes T35,T34,T68 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T356,T102 Yes T83,T356,T102 INPUT
alert_rx_i[0].ping_n Yes Yes T356,T102,T237 Yes T102,T237,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T237,T103 Yes T356,T102,T237 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T356,T102 Yes T83,T356,T102 OUTPUT
cio_scl_i Yes Yes T35,T34,T68 Yes T35,T34,T68 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T34,T68,T71 Yes T34,T68,T71 OUTPUT
cio_sda_i Yes Yes T35,T34,T68 Yes T35,T34,T68 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T35,T34,T68 Yes T35,T34,T68 OUTPUT
intr_fmt_threshold_o Yes Yes T34,T68,T71 Yes T34,T68,T71 OUTPUT
intr_rx_threshold_o Yes Yes T34,T68,T71 Yes T34,T68,T71 OUTPUT
intr_acq_threshold_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_rx_overflow_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_controller_halt_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_scl_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_stretch_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_unstable_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_cmd_complete_o Yes Yes T35,T34,T68 Yes T35,T34,T68 OUTPUT
intr_tx_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_tx_threshold_o Yes Yes T344,T30,T354 Yes T344,T30,T354 OUTPUT
intr_acq_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_unexp_stop_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_host_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 348 324 93.10
Total Bits 0->1 174 162 93.10
Total Bits 1->0 174 162 93.10

Ports 54 48 88.89
Port Bits 348 324 93.10
Port Bits 0->1 174 162 93.10
Port Bits 1->0 174 162 93.10

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T68,T315,T344 Yes T68,T315,T344 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T68,T315,T344 Yes T68,T315,T344 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[18:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T68,T315,T83 Yes T68,T315,T83 INPUT
tl_o.a_ready Yes Yes T68,T315,T83 Yes T68,T315,T83 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T68,T344,T30 Yes T68,T344,T30 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T68,T315,T189 Yes T68,T315,T83 OUTPUT
tl_o.d_data[31:0] Yes Yes T68,T315,T189 Yes T68,T315,T83 OUTPUT
tl_o.d_sink Yes Yes T98,T100,T161 Yes T98,T100,T161 OUTPUT
tl_o.d_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T68,*T315,*T344 Yes T68,T315,T344 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T68,T315,T83 Yes T68,T315,T83 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T356,T102 Yes T83,T356,T102 INPUT
alert_rx_i[0].ping_n Yes Yes T356,T102,T237 Yes T102,T237,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T237,T103 Yes T356,T102,T237 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T356,T102 Yes T83,T356,T102 OUTPUT
cio_scl_i Yes Yes T68,T13,T69 Yes T68,T13,T69 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T68,T13,T69 Yes T68,T13,T69 OUTPUT
cio_sda_i Yes Yes T68,T13,T69 Yes T68,T13,T69 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T68,T13,T69 Yes T68,T13,T69 OUTPUT
intr_fmt_threshold_o Yes Yes T68,T344,T69 Yes T68,T344,T69 OUTPUT
intr_rx_threshold_o Yes Yes T68,T344,T69 Yes T68,T344,T69 OUTPUT
intr_acq_threshold_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_rx_overflow_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_controller_halt_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_scl_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_stretch_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_unstable_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_cmd_complete_o Yes Yes T68,T344,T69 Yes T68,T344,T69 OUTPUT
intr_tx_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_tx_threshold_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_acq_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_unexp_stop_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_host_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 350 326 93.14
Total Bits 0->1 175 163 93.14
Total Bits 1->0 175 163 93.14

Ports 54 48 88.89
Port Bits 350 326 93.14
Port Bits 0->1 175 163 93.14
Port Bits 1->0 175 163 93.14

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T34,T315,T344 Yes T34,T315,T344 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T34,T315,T344 Yes T34,T315,T344 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[15:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T34,T315,T83 Yes T34,T315,T83 INPUT
tl_o.a_ready Yes Yes T34,T315,T83 Yes T34,T315,T83 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T34,T344,T30 Yes T34,T344,T30 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T34,T315,T189 Yes T34,T315,T83 OUTPUT
tl_o.d_data[31:0] Yes Yes T34,T315,T189 Yes T34,T315,T83 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T99,T100,T185 OUTPUT
tl_o.d_source[5:0] Yes Yes *T30,*T101,*T100 Yes T30,T101,T98 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T34,*T315,*T344 Yes T34,T315,T344 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T34,T315,T83 Yes T34,T315,T83 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T237,T103 Yes T102,T237,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T237,T103 Yes T102,T237,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_scl_i Yes Yes T34,T13,T70 Yes T34,T13,T70 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T34,T13,T70 Yes T34,T13,T70 OUTPUT
cio_sda_i Yes Yes T34,T13,T70 Yes T34,T13,T70 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T34,T30,T13 Yes T34,T30,T13 OUTPUT
intr_fmt_threshold_o Yes Yes T34,T344,T30 Yes T34,T344,T30 OUTPUT
intr_rx_threshold_o Yes Yes T34,T344,T70 Yes T34,T344,T70 OUTPUT
intr_acq_threshold_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_rx_overflow_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_controller_halt_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_scl_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_stretch_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_unstable_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_cmd_complete_o Yes Yes T34,T344,T70 Yes T34,T344,T70 OUTPUT
intr_tx_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_tx_threshold_o Yes Yes T344,T354,T101 Yes T344,T354,T101 OUTPUT
intr_acq_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_unexp_stop_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_host_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2
TotalCoveredPercent
Totals 54 48 88.89
Total Bits 350 326 93.14
Total Bits 0->1 175 163 93.14
Total Bits 1->0 175 163 93.14

Ports 54 48 88.89
Port Bits 350 326 93.14
Port Bits 0->1 175 163 93.14
Port Bits 1->0 175 163 93.14

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
ram_cfg_i.rf_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.rf_cfg.cfg_en No No No INPUT
ram_cfg_i.rf_cfg.test No No No INPUT
ram_cfg_i.ram_cfg.cfg[3:0] No No No INPUT
ram_cfg_i.ram_cfg.cfg_en No No No INPUT
ram_cfg_i.ram_cfg.test No No No INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T35,T315,T71 Yes T35,T315,T71 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T35,T315,T71 Yes T35,T315,T71 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[16:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[19] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:20] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T35,T315,T71 Yes T35,T315,T71 INPUT
tl_o.a_ready Yes Yes T35,T315,T71 Yes T35,T315,T71 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T35,T71,T344 Yes T35,T71,T344 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T35,T315,T71 Yes T35,T315,T71 OUTPUT
tl_o.d_data[31:0] Yes Yes T35,T315,T71 Yes T35,T315,T71 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T35,*T315,*T71 Yes T35,T315,T71 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T35,T315,T71 Yes T35,T315,T71 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T237,T103 Yes T102,T237,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T237,T103 Yes T102,T237,T103 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_scl_i Yes Yes T35,T71,T13 Yes T35,T71,T13 INPUT
cio_scl_o Unreachable Unreachable Unreachable OUTPUT
cio_scl_en_o Yes Yes T71,T30,T13 Yes T71,T30,T13 OUTPUT
cio_sda_i Yes Yes T35,T71,T13 Yes T35,T71,T13 INPUT
cio_sda_o Unreachable Unreachable Unreachable OUTPUT
cio_sda_en_o Yes Yes T35,T71,T30 Yes T35,T71,T30 OUTPUT
intr_fmt_threshold_o Yes Yes T71,T344,T30 Yes T71,T344,T30 OUTPUT
intr_rx_threshold_o Yes Yes T71,T344,T308 Yes T71,T344,T308 OUTPUT
intr_acq_threshold_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_rx_overflow_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_controller_halt_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_scl_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_interference_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_stretch_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_sda_unstable_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_cmd_complete_o Yes Yes T35,T71,T344 Yes T35,T71,T344 OUTPUT
intr_tx_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_tx_threshold_o Yes Yes T344,T30,T354 Yes T344,T30,T354 OUTPUT
intr_acq_stretch_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_unexp_stop_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT
intr_host_timeout_o Yes Yes T344,T354,T355 Yes T344,T354,T355 OUTPUT

*Tests covering at least one bit in the range