Unified Coverage Report :: Module :: tlul_rsp_intg_gen

Module : tlul_rsp_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen	83.33	66.67					100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen	100.00	100.00					100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_plic.u_reg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3 

---

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_reg_if.u_rsp_intg_gen

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_sensor_ctrl_aon.u_reg.u_reg_if.u_rsp_intg_gen

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_rv_plic.u_reg.u_reg_if.u_rsp_intg_gen

SCORE	LINE
83.33	66.67

tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         0/1     ==>      assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3 

---

Assert Coverage for Module : tlul_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	20538	20538	0	0
PayLoadWidthCheck	20538	20538	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	20538	20538	0	0
T1	9	9	0	0
T2	9	9	0	0
T3	9	9	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T30	9	9	0	0
T68	9	9	0	0
T104	9	9	0	0
T105	9	9	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	20538	20538	0	0
T1	9	9	0	0
T2	9	9	0	0
T3	9	9	0	0
T4	9	9	0	0
T5	9	9	0	0
T6	9	9	0	0
T30	9	9	0	0
T68	9	9	0	0
T104	9	9	0	0
T105	9	9	0	0