Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_rom_ctrl.u_tl_adapter_rom.u_rsp_gen

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.92	100.00	99.68			100.00	100.00	u_reg_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.91	100.00	95.65			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
80.43	60.87					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.75	95.24	80.00			100.00		u_sim_win_rsp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	0.00	0.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	2918	2918	0	0
PayLoadWidthCheck	2918	2918	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         0/1     ==>      assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T2 T3 T4 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T2 T3 T4 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T2 T3 T4 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T2 T3 T4 

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	2918	2918	0	0
PayLoadWidthCheck	2918	2918	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00

24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_sim_win_rsp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1010	1010	0	0
PayLoadWidthCheck	1010	1010	0	0

DataWidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

PayLoadWidthCheck

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0