Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : spi_host
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.21 97.21

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_spi_host_1.0/rtl/spi_host.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.top_earlgrey.u_spi_host0 96.59 96.59
tb.dut.top_earlgrey.u_spi_host1 98.77 98.77


Module Instance : tb.dut.top_earlgrey.u_spi_host0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 96.59


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.59 96.59


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_spi_host1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.77 98.77


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.77 98.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : spi_host
TotalCoveredPercent
Totals 46 43 93.48
Total Bits 358 348 97.21
Total Bits 0->1 179 174 97.21
Total Bits 1->0 179 174 97.21

Ports 46 43 93.48
Port Bits 358 348 97.21
Port Bits 0->1 179 174 97.21
Port Bits 1->0 179 174 97.21

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_mask[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T315,*T83,*T128 Yes T315,T83,T128 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T11,T226,T229 Yes T11,T226,T229 INPUT
tl_i.a_valid Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_o.a_ready Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_data[31:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T100,*T161,*T185 Yes T98,T99,T100 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T266,T237 Yes T102,T266,T237 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T266,T237 Yes T102,T266,T237 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_sck_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sck_en_o Yes Yes T11,T12,T13 Yes T10,T11,T12 OUTPUT
cio_csb_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_csb_en_o Yes Yes T11,T12,T13 Yes T10,T11,T12 OUTPUT
cio_sd_o[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sd_en_o[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sd_i[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
passthrough_i.s_en[0] Yes Yes *T11,*T12,*T13 Yes T11,T12,T13 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T6,T14,T11 Yes T6,T14,T11 INPUT
passthrough_i.csb_en No No No INPUT
passthrough_i.csb Yes Yes T5,T6,T11 Yes T6,T11,T12 INPUT
passthrough_i.sck_en No No No INPUT
passthrough_i.sck Yes Yes T6,T14,T11 Yes T6,T14,T11 INPUT
passthrough_i.passthrough_en Yes Yes T11,T226,T229 Yes T11,T12,T13 INPUT
passthrough_o.s[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
intr_error_o Yes Yes T128,T186,T187 Yes T128,T186,T187 OUTPUT
intr_spi_event_o Yes Yes T128,T186,T187 Yes T128,T186,T187 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host0
TotalCoveredPercent
Totals 44 42 95.45
Total Bits 352 340 96.59
Total Bits 0->1 176 170 96.59
Total Bits 1->0 176 170 96.59

Ports 44 42 95.45
Port Bits 352 340 96.59
Port Bits 0->1 176 170 96.59
Port Bits 1->0 176 170 96.59

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   Exclude Annotation   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_mask[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T100,*T185 Yes T98,T100,T185 INPUT
tl_i.a_address[19:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T11,T226,T229 Yes T11,T226,T229 INPUT
tl_i.a_valid Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_o.a_ready Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_data[31:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T100,*T161,*T185 Yes T98,T99,T100 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T266,T237 Yes T102,T266,T237 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T266,T237 Yes T102,T266,T237 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_sck_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sck_en_o Yes Yes T11,T12,T13 Yes T10,T11,T12 OUTPUT
cio_csb_o Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_csb_en_o Yes Yes T11,T12,T13 Yes T10,T11,T12 OUTPUT
cio_sd_o[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
cio_sd_en_o[0] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 OUTPUT
cio_sd_en_o[3:1] No No No OUTPUT
cio_sd_i[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
passthrough_i.s_en[0] Yes Yes *T11,*T12,*T13 Yes T11,T12,T13 INPUT
passthrough_i.s_en[3:1] No No No INPUT
passthrough_i.s[3:0] Yes Yes T6,T14,T11 Yes T6,T14,T11 INPUT
passthrough_i.csb_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.csb Yes Yes T5,T6,T11 Yes T6,T11,T12 INPUT
passthrough_i.sck_en[0:0] Excluded Excluded Excluded INPUT [UNR] Tied off.
passthrough_i.sck Yes Yes T6,T14,T11 Yes T6,T14,T11 INPUT
passthrough_i.passthrough_en Yes Yes T11,T226,T229 Yes T11,T12,T13 INPUT
passthrough_o.s[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
intr_error_o Yes Yes T128,T186,T187 Yes T128,T186,T187 OUTPUT
intr_spi_event_o Yes Yes T128,T186,T187 Yes T128,T186,T187 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_spi_host1
TotalCoveredPercent
Totals 38 37 97.37
Total Bits 324 320 98.77
Total Bits 0->1 162 161 99.38
Total Bits 1->0 162 159 98.15

Ports 38 37 97.37
Port Bits 324 320 98.77
Port Bits 0->1 162 161 99.38
Port Bits 1->0 162 159 98.15

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_i.a_mask[3:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T315,*T83,*T128 Yes T315,T83,T128 INPUT
tl_i.a_address[19:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[21:20] Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_i.a_address[29:22] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T315,*T83,*T128 Yes T315,T83,T128 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_valid Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_o.a_ready Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_o.d_error Yes Yes T98,T100,T161 Yes T98,T100,T161 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T315,T128,T13 Yes T315,T128,T13 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T315,T128,T349 Yes T315,T83,T128 OUTPUT
tl_o.d_data[31:0] Yes Yes T315,T128,T13 Yes T315,T128,T13 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T99,T100,T161 OUTPUT
tl_o.d_source[5:0] Yes Yes *T100,*T185,*T281 Yes T98,T99,T100 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T315,*T128,*T349 Yes T315,T128,T349 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T266 Yes T83,T102,T266 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T266,T237 Yes T266,T237,T103 INPUT
alert_rx_i[0].ping_p Yes Yes T266,T237,T103 Yes T102,T266,T237 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T266 Yes T83,T102,T266 OUTPUT
cio_sck_o Yes Yes T13,T56,T78 Yes T13,T56,T78 OUTPUT
cio_sck_en_o Yes Yes T169,T179,T422 Yes T13,T56,T78 OUTPUT
cio_csb_o Yes Yes T13,T56,T78 Yes T13,T56,T78 OUTPUT
cio_csb_en_o Yes Yes T169,T179,T422 Yes T13,T56,T78 OUTPUT
cio_sd_o[0] Yes Yes *T56,*T57 Yes T56,T57 OUTPUT
cio_sd_o[1] No No Yes T13,T78,T130 OUTPUT
cio_sd_o[2] No No No OUTPUT
cio_sd_o[3] No No Yes T13,T78,T130 OUTPUT
cio_sd_en_o[3:0] Yes Yes T13,T56,T78 Yes T13,T56,T78 OUTPUT
cio_sd_i[3:0] Yes Yes T13,T56,T78 Yes T10,T13,T56 INPUT
passthrough_i.s_en[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.s[3:0] Unreachable Unreachable Unreachable INPUT
passthrough_i.csb_en Unreachable Unreachable Unreachable INPUT
passthrough_i.csb Unreachable Unreachable Unreachable INPUT
passthrough_i.sck_en Unreachable Unreachable Unreachable INPUT
passthrough_i.sck Unreachable Unreachable Unreachable INPUT
passthrough_i.passthrough_en Unreachable Unreachable Unreachable INPUT
passthrough_o.s[3:0] Unreachable Unreachable Unreachable OUTPUT
intr_error_o Yes Yes T128,T186,T187 Yes T128,T186,T187 OUTPUT
intr_spi_event_o Yes Yes T128,T186,T187 Yes T128,T186,T187 OUTPUT

*Tests covering at least one bit in the range