Module Definition
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Module : prim_fifo_sync
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo 75.00 50.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo 100.00 100.00 100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL44100.00
CONT_ASSIGN4411100.00
CONT_ASSIGN4511100.00
CONT_ASSIGN4811100.00
CONT_ASSIGN4911100.00
CONT_ASSIGN5300


43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;
Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00



Assertion Details

Name   Attempts   Real Successes   Failures   Incomplete   
DataKnown_A 2147483647 191401064 0 0
DepthKnown_A 2147483647 2147483647 0 0
RvalidKnown_A 2147483647 2147483647 0 0
WreadyKnown_A 2147483647 2147483647 0 0
gen_passthru_fifo.paramCheckPass 21664 21664 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 191401064 0 0
T1 337864 6234 0 0
T2 862260 28838 0 0
T3 689850 20089 0 0
T4 667030 19025 0 0
T5 739490 25383 0 0
T6 823000 27569 0 0
T7 1124370 37243 0 0
T8 295684 2 0 0
T38 800870 28122 0 0
T39 706820 21137 0 0
T106 708680 24899 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 422330 421750 0 0
T2 862260 861680 0 0
T3 689850 689300 0 0
T4 667030 666450 0 0
T5 739490 738980 0 0
T6 823000 822450 0 0
T7 1124370 1123820 0 0
T38 800870 800360 0 0
T39 706820 706240 0 0
T106 708680 708130 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 422330 421750 0 0
T2 862260 861680 0 0
T3 689850 689300 0 0
T4 667030 666450 0 0
T5 739490 738980 0 0
T6 823000 822450 0 0
T7 1124370 1123820 0 0
T38 800870 800360 0 0
T39 706820 706240 0 0
T106 708680 708130 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2147483647 2147483647 0 0
T1 422330 421750 0 0
T2 862260 861680 0 0
T3 689850 689300 0 0
T4 667030 666450 0 0
T5 739490 738980 0 0
T6 823000 822450 0 0
T7 1124370 1123820 0 0
T38 800870 800360 0 0
T39 706820 706240 0 0
T106 708680 708130 0 0

gen_passthru_fifo.paramCheckPass
NameAttemptsReal SuccessesFailuresIncomplete
Total 21664 21664 0 0
T1 10 10 0 0
T2 10 10 0 0
T3 10 10 0 0
T4 10 10 0 0
T5 10 10 0 0
T6 10 10 0 0
T7 10 10 0 0
T38 10 10 0 0
T39 10 10 0 0
T106 10 10 0 0