Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508511374	61722147	0	0
DepthKnown_A	508511374	508404287	0	0
RvalidKnown_A	508511374	508404287	0	0
WreadyKnown_A	508511374	508404287	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	61722147	0	0
T1	42233	3506	0	0
T2	86226	10530	0	0
T3	68985	6811	0	0
T4	66703	6503	0	0
T5	73949	10361	0	0
T6	82300	11448	0	0
T7	112437	13033	0	0
T38	80087	9126	0	0
T39	70682	7607	0	0
T106	70868	8364	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508511374	46863145	0	0
DepthKnown_A	508511374	508404287	0	0
RvalidKnown_A	508511374	508404287	0	0
WreadyKnown_A	508511374	508404287	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	46863145	0	0
T1	42233	1884	0	0
T2	86226	7562	0	0
T3	68985	5127	0	0
T4	66703	4819	0	0
T5	73949	6636	0	0
T6	82300	7138	0	0
T7	112437	10573	0	0
T38	80087	6705	0	0
T39	70682	5492	0	0
T106	70868	5826	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508511374	44998325	0	0
DepthKnown_A	508511374	508404287	0	0
RvalidKnown_A	508511374	508404287	0	0
WreadyKnown_A	508511374	508404287	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	44998325	0	0
T1	42233	460	0	0
T2	86226	5415	0	0
T3	68985	4106	0	0
T4	66703	3882	0	0
T5	73949	4225	0	0
T6	82300	4562	0	0
T7	112437	6862	0	0
T38	80087	5936	0	0
T39	70682	4056	0	0
T106	70868	5393	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T30 T45 T101 
49         1/1              assign full_o = rready_i;
           Tests:       T30 T45 T101 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	508511374	37453089	0	0
DepthKnown_A	508511374	508404287	0	0
RvalidKnown_A	508511374	508404287	0	0
WreadyKnown_A	508511374	508404287	0	0
gen_passthru_fifo.paramCheckPass	1021	1021	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	37453089	0	0
T1	42233	352	0	0
T2	86226	5223	0	0
T3	68985	3993	0	0
T4	66703	3769	0	0
T5	73949	4049	0	0
T6	82300	4321	0	0
T7	112437	6723	0	0
T38	80087	5679	0	0
T39	70682	3930	0	0
T106	70868	5220	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	508511374	508404287	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1021	1021	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590329365	89799	0	0
DepthKnown_A	590329365	590206011	0	0
RvalidKnown_A	590329365	590206011	0	0
WreadyKnown_A	590329365	590206011	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	89799	0	0
T1	42233	8	0	0
T2	86226	27	0	0
T3	68985	13	0	0
T4	66703	13	0	0
T5	73949	28	0	0
T6	82300	25	0	0
T7	112437	13	0	0
T38	80087	169	0	0
T39	70682	13	0	0
T106	70868	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590329365	92380	0	0
DepthKnown_A	590329365	590206011	0	0
RvalidKnown_A	590329365	590206011	0	0
WreadyKnown_A	590329365	590206011	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	92380	0	0
T1	42233	8	0	0
T2	86226	27	0	0
T3	68985	13	0	0
T4	66703	13	0	0
T5	73949	28	0	0
T6	82300	25	0	0
T7	112437	13	0	0
T38	80087	169	0	0
T39	70682	13	0	0
T106	70868	24	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590329365	52673	0	0
DepthKnown_A	590329365	590206011	0	0
RvalidKnown_A	590329365	590206011	0	0
WreadyKnown_A	590329365	590206011	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	52673	0	0
T1	42233	8	0	0
T2	86226	24	0	0
T3	68985	12	0	0
T4	66703	12	0	0
T5	73949	25	0	0
T6	82300	22	0	0
T7	112437	12	0	0
T38	80087	168	0	0
T39	70682	12	0	0
T106	70868	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590329365	52672	0	0
DepthKnown_A	590329365	590206011	0	0
RvalidKnown_A	590329365	590206011	0	0
WreadyKnown_A	590329365	590206011	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	52672	0	0
T1	42233	8	0	0
T2	86226	24	0	0
T3	68985	12	0	0
T4	66703	12	0	0
T5	73949	25	0	0
T6	82300	22	0	0
T7	112437	12	0	0
T38	80087	168	0	0
T39	70682	12	0	0
T106	70868	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590329365	37126	0	0
DepthKnown_A	590329365	590206011	0	0
RvalidKnown_A	590329365	590206011	0	0
WreadyKnown_A	590329365	590206011	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	37126	0	0
T2	86226	3	0	0
T3	68985	1	0	0
T4	66703	1	0	0
T5	73949	3	0	0
T6	82300	3	0	0
T7	112437	1	0	0
T8	147842	1	0	0
T38	80087	1	0	0
T39	70682	1	0	0
T106	70868	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	590329365	39708	0	0
DepthKnown_A	590329365	590206011	0	0
RvalidKnown_A	590329365	590206011	0	0
WreadyKnown_A	590329365	590206011	0	0
gen_passthru_fifo.paramCheckPass	2930	2930	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	39708	0	0
T2	86226	3	0	0
T3	68985	1	0	0
T4	66703	1	0	0
T5	73949	3	0	0
T6	82300	3	0	0
T7	112437	1	0	0
T8	147842	1	0	0
T38	80087	1	0	0
T39	70682	1	0	0
T106	70868	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	590329365	590206011	0	0
T1	42233	42175	0	0
T2	86226	86168	0	0
T3	68985	68930	0	0
T4	66703	66645	0	0
T5	73949	73898	0	0
T6	82300	82245	0	0
T7	112437	112382	0	0
T38	80087	80036	0	0
T39	70682	70624	0	0
T106	70868	70813	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2930	2930	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T7	1	1	0	0
T38	1	1	0	0
T39	1	1	0	0
T106	1	1	0	0