Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491226693	59413671	0	0
DataKnown_AKnownEnable	491226693	491122051	0	0
DepthKnown_A	491226693	491122051	0	0
RvalidKnown_A	491226693	491122051	0	0
WreadyKnown_A	491226693	491122051	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	59413671	0	0
T1	42275	3485	0	0
T2	91152	9245	0	0
T3	115201	75597	0	0
T4	110863	12771	0	0
T5	83840	11232	0	0
T6	116117	12981	0	0
T30	92780	10482	0	0
T68	219320	24038	0	0
T104	98538	12006	0	0
T105	67890	6643	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         0/1     ==>      assign wready_o = rready_i;
49         0/1     ==>      assign full_o = rready_i;
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491226693	44469775	0	0
DataKnown_AKnownEnable	491226693	491122051	0	0
DepthKnown_A	491226693	491122051	0	0
RvalidKnown_A	491226693	491122051	0	0
WreadyKnown_A	491226693	491122051	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	44469775	0	0
T1	42275	1880	0	0
T2	91152	6267	0	0
T3	115201	37398	0	0
T4	110863	10340	0	0
T5	83840	7068	0	0
T6	116117	10439	0	0
T30	92780	8375	0	0
T68	219320	19696	0	0
T104	98538	9467	0	0
T105	67890	4973	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491226693	42947658	0	0
DataKnown_AKnownEnable	491226693	491122051	0	0
DepthKnown_A	491226693	491122051	0	0
RvalidKnown_A	491226693	491122051	0	0
WreadyKnown_A	491226693	491122051	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	42947658	0	0
T1	42275	461	0	0
T2	91152	4463	0	0
T3	115201	7519	0	0
T4	110863	6711	0	0
T5	83840	4589	0	0
T6	116117	9987	0	0
T30	92780	6155	0	0
T68	219320	20838	0	0
T104	98538	8028	0	0
T105	67890	3996	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T35 T97 T98 
49         1/1              assign full_o = rready_i;
           Tests:       T35 T97 T98 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	491226693	35985095	0	0
DataKnown_AKnownEnable	491226693	491122051	0	0
DepthKnown_A	491226693	491122051	0	0
RvalidKnown_A	491226693	491122051	0	0
WreadyKnown_A	491226693	491122051	0	0
gen_passthru_fifo.paramCheckPass	1010	1010	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	35985095	0	0
T1	42275	353	0	0
T2	91152	4272	0	0
T3	115201	6898	0	0
T4	110863	6572	0	0
T5	83840	4354	0	0
T6	116117	9534	0	0
T30	92780	6027	0	0
T68	219320	20637	0	0
T104	98538	7853	0	0
T105	67890	3882	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	491226693	491122051	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564125052	94267	0	0
DataKnown_AKnownEnable	564125052	564004966	0	0
DepthKnown_A	564125052	564004966	0	0
RvalidKnown_A	564125052	564004966	0	0
WreadyKnown_A	564125052	564004966	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	94267	0	0
T1	42275	8	0	0
T2	91152	27	0	0
T3	115201	34	0	0
T4	110863	13	0	0
T5	83840	25	0	0
T6	116117	208	0	0
T30	92780	13	0	0
T68	219320	53	0	0
T104	98538	24	0	0
T105	67890	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564125052	95779	0	0
DataKnown_AKnownEnable	564125052	564004966	0	0
DepthKnown_A	564125052	564004966	0	0
RvalidKnown_A	564125052	564004966	0	0
WreadyKnown_A	564125052	564004966	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	95779	0	0
T1	42275	8	0	0
T2	91152	27	0	0
T3	115201	34	0	0
T4	110863	13	0	0
T5	83840	25	0	0
T6	116117	208	0	0
T30	92780	13	0	0
T68	219320	53	0	0
T104	98538	24	0	0
T105	67890	13	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564125052	51402	0	0
DataKnown_AKnownEnable	564125052	564004966	0	0
DepthKnown_A	564125052	564004966	0	0
RvalidKnown_A	564125052	564004966	0	0
WreadyKnown_A	564125052	564004966	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	51402	0	0
T1	42275	8	0	0
T2	91152	24	0	0
T3	115201	31	0	0
T4	110863	12	0	0
T5	83840	22	0	0
T6	116117	205	0	0
T30	92780	12	0	0
T68	219320	52	0	0
T104	98538	23	0	0
T105	67890	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564125052	51402	0	0
DataKnown_AKnownEnable	564125052	564004966	0	0
DepthKnown_A	564125052	564004966	0	0
RvalidKnown_A	564125052	564004966	0	0
WreadyKnown_A	564125052	564004966	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	51402	0	0
T1	42275	8	0	0
T2	91152	24	0	0
T3	115201	31	0	0
T4	110863	12	0	0
T5	83840	22	0	0
T6	116117	205	0	0
T30	92780	12	0	0
T68	219320	52	0	0
T104	98538	23	0	0
T105	67890	12	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T1 T2 T3 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T1 T2 T3 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T2 T3 T4 
49         1/1              assign full_o = rready_i;
           Tests:       T2 T3 T4 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564125052	42865	0	0
DataKnown_AKnownEnable	564125052	564004966	0	0
DepthKnown_A	564125052	564004966	0	0
RvalidKnown_A	564125052	564004966	0	0
WreadyKnown_A	564125052	564004966	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	42865	0	0
T2	91152	3	0	0
T3	115201	3	0	0
T4	110863	1	0	0
T5	83840	3	0	0
T6	116117	3	0	0
T23	75281	3	0	0
T30	92780	1	0	0
T68	219320	1	0	0
T104	98538	1	0	0
T105	67890	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

43                          // device facing
44         1/1              assign rvalid_o = wvalid_i;
           Tests:       T2 T3 T4 
45         1/1              assign rdata_o = wdata_i;
           Tests:       T2 T3 T4 
46                      
47                          // host facing
48         1/1              assign wready_o = rready_i;
           Tests:       T1 T2 T3 
49         1/1              assign full_o = rready_i;
           Tests:       T1 T2 T3 
50                      
51                          // this avoids lint warnings
52                          logic unused_clr;
53         unreachable      assign unused_clr = clr_i;

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	6	6	100.00	6	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	6	6	100.00	6	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	564125052	44377	0	0
DataKnown_AKnownEnable	564125052	564004966	0	0
DepthKnown_A	564125052	564004966	0	0
RvalidKnown_A	564125052	564004966	0	0
WreadyKnown_A	564125052	564004966	0	0
gen_passthru_fifo.paramCheckPass	2918	2918	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	44377	0	0
T2	91152	3	0	0
T3	115201	3	0	0
T4	110863	1	0	0
T5	83840	3	0	0
T6	116117	3	0	0
T23	75281	3	0	0
T30	92780	1	0	0
T68	219320	1	0	0
T104	98538	1	0	0
T105	67890	1	0	0

DataKnown_AKnownEnable

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	564125052	564004966	0	0
T1	42275	42213	0	0
T2	91152	91094	0	0
T3	115201	115146	0	0
T4	110863	110808	0	0
T5	83840	83789	0	0
T6	116117	116059	0	0
T30	92780	92722	0	0
T68	219320	219269	0	0
T104	98538	98483	0	0
T105	67890	67832	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2918	2918	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0