Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : uart
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :
NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
tb.dut.top_earlgrey.u_uart0 100.00 100.00
tb.dut.top_earlgrey.u_uart1 100.00 100.00
tb.dut.top_earlgrey.u_uart2 100.00 100.00
tb.dut.top_earlgrey.u_uart3 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children


Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Toggle Coverage for Module : uart
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T31,T131,T32 Yes T31,T131,T32 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T31,T131,T32 Yes T31,T131,T32 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T31,T131,T32 Yes T31,T131,T32 INPUT
tl_o.a_ready Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
tl_o.d_data[31:0] Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T285,*T286,*T101 Yes T285,T286,T101 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T31,*T131,*T32 Yes T31,T131,T32 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T105 Yes T102,T103,T105 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T103,T105 Yes T102,T103,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_rx_i Yes Yes T31,T46,T131 Yes T1,T2,T3 INPUT
cio_tx_o Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
intr_tx_empty_o Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
intr_rx_watermark_o Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
intr_tx_done_o Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
intr_rx_overflow_o Yes Yes T31,T131,T32 Yes T31,T131,T32 OUTPUT
intr_rx_frame_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_break_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_timeout_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_parity_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 304 304 100.00
Total Bits 0->1 152 152 100.00
Total Bits 1->0 152 152 100.00

Ports 40 40 100.00
Port Bits 304 304 100.00
Port Bits 0->1 152 152 100.00
Port Bits 1->0 152 152 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T131,T223,T346 Yes T131,T223,T346 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T131,T223,T346 Yes T131,T223,T346 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[29:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T131,T83,T223 Yes T131,T83,T223 INPUT
tl_o.a_ready Yes Yes T131,T83,T346 Yes T131,T83,T346 OUTPUT
tl_o.d_error Yes Yes T99,T100,T161 Yes T99,T100,T161 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T131,T346,T349 Yes T131,T346,T349 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T131,T346,T189 Yes T131,T83,T346 OUTPUT
tl_o.d_data[31:0] Yes Yes T131,T346,T189 Yes T131,T83,T346 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T285,*T286,*T101 Yes T285,T286,T101 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T131,*T346,*T349 Yes T131,T346,T349 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T131,T83,T346 Yes T131,T83,T346 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T105 Yes T102,T103,T105 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T103,T105 Yes T102,T103,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_rx_i Yes Yes T46,T131,T53 Yes T1,T2,T3 INPUT
cio_tx_o Yes Yes T131,T63,T64 Yes T131,T63,T64 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T131,T346,T349 Yes T131,T346,T349 OUTPUT
intr_tx_empty_o Yes Yes T131,T346,T350 Yes T131,T346,T350 OUTPUT
intr_rx_watermark_o Yes Yes T131,T346,T350 Yes T131,T346,T350 OUTPUT
intr_tx_done_o Yes Yes T131,T346,T351 Yes T131,T346,T351 OUTPUT
intr_rx_overflow_o Yes Yes T131,T346,T351 Yes T131,T346,T351 OUTPUT
intr_rx_frame_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_break_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_timeout_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_parity_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T32,T346,T13 Yes T32,T346,T13 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T32,T346,T13 Yes T32,T346,T13 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[16] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:17] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T32,T83,T346 Yes T32,T83,T346 INPUT
tl_o.a_ready Yes Yes T32,T83,T346 Yes T32,T83,T346 OUTPUT
tl_o.d_error Yes Yes T99,T100,T161 Yes T99,T100,T161 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T32,T346,T13 Yes T32,T346,T13 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T32,T346,T189 Yes T32,T83,T346 OUTPUT
tl_o.d_data[31:0] Yes Yes T32,T346,T189 Yes T32,T83,T346 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T101,*T99,*T100 Yes T101,T98,T99 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T32,*T346,*T13 Yes T32,T346,T13 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T32,T83,T346 Yes T32,T83,T346 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T105 Yes T103,T105 INPUT
alert_rx_i[0].ping_p Yes Yes T103,T105 Yes T102,T103,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_rx_i Yes Yes T32,T56,T132 Yes T10,T32,T56 INPUT
cio_tx_o Yes Yes T32,T132,T133 Yes T32,T132,T133 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T32,T346,T132 Yes T32,T346,T132 OUTPUT
intr_tx_empty_o Yes Yes T32,T346,T132 Yes T32,T346,T132 OUTPUT
intr_rx_watermark_o Yes Yes T32,T346,T132 Yes T32,T346,T132 OUTPUT
intr_tx_done_o Yes Yes T32,T346,T132 Yes T32,T346,T132 OUTPUT
intr_rx_overflow_o Yes Yes T32,T346,T132 Yes T32,T346,T132 OUTPUT
intr_rx_frame_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_break_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_timeout_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_parity_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 306 306 100.00
Total Bits 0->1 153 153 100.00
Total Bits 1->0 153 153 100.00

Ports 40 40 100.00
Port Bits 306 306 100.00
Port Bits 0->1 153 153 100.00
Port Bits 1->0 153 153 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T31,T37,T346 Yes T31,T37,T346 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T31,T37,T346 Yes T31,T37,T346 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[16:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T31,T37,T83 Yes T31,T37,T83 INPUT
tl_o.a_ready Yes Yes T31,T37,T83 Yes T31,T37,T83 OUTPUT
tl_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T31,T37,T346 Yes T31,T37,T346 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T31,T37,T346 Yes T31,T37,T83 OUTPUT
tl_o.d_data[31:0] Yes Yes T31,T37,T346 Yes T31,T37,T83 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T101,*T100,*T161 Yes T101,T98,T99 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T31,*T37,*T346 Yes T31,T37,T346 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T31,T37,T83 Yes T31,T37,T83 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T105 Yes T103,T105 INPUT
alert_rx_i[0].ping_p Yes Yes T103,T105 Yes T102,T103,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_rx_i Yes Yes T31,T37,T134 Yes T31,T37,T134 INPUT
cio_tx_o Yes Yes T31,T37,T134 Yes T31,T37,T134 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T31,T37,T346 Yes T31,T37,T346 OUTPUT
intr_tx_empty_o Yes Yes T31,T37,T346 Yes T31,T37,T346 OUTPUT
intr_rx_watermark_o Yes Yes T31,T37,T346 Yes T31,T37,T346 OUTPUT
intr_tx_done_o Yes Yes T31,T37,T346 Yes T31,T37,T346 OUTPUT
intr_rx_overflow_o Yes Yes T31,T37,T346 Yes T31,T37,T346 OUTPUT
intr_rx_frame_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_break_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_timeout_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_parity_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT

*Tests covering at least one bit in the range
Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3
TotalCoveredPercent
Totals 40 40 100.00
Total Bits 308 308 100.00
Total Bits 0->1 154 154 100.00
Total Bits 1->0 154 154 100.00

Ports 40 40 100.00
Port Bits 308 308 100.00
Port Bits 0->1 154 154 100.00
Port Bits 1->0 154 154 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T29,T72,T73 Yes T29,T72,T73 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T29,T72,T73 Yes T29,T72,T73 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_i.a_address[15:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[17:16] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:18] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_i.a_valid Yes Yes T29,T83,T72 Yes T29,T83,T72 INPUT
tl_o.a_ready Yes Yes T29,T83,T72 Yes T29,T83,T72 OUTPUT
tl_o.d_error Yes Yes T98,T100,T185 Yes T98,T100,T161 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T29,T72,T73 Yes T29,T72,T73 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T29,T72,T73 Yes T29,T83,T72 OUTPUT
tl_o.d_data[31:0] Yes Yes T29,T72,T73 Yes T29,T83,T72 OUTPUT
tl_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_o.d_source[5:0] Yes Yes *T101,*T98,*T100 Yes T101,T98,T99 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T98,T100,T161 Yes T98,T100,T185 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T29,*T72,*T73 Yes T29,T72,T73 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T29,T83,T72 Yes T29,T83,T72 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T83,T102,T189 Yes T83,T102,T189 INPUT
alert_rx_i[0].ping_n Yes Yes T102,T103,T105 Yes T102,T103,T105 INPUT
alert_rx_i[0].ping_p Yes Yes T102,T103,T105 Yes T102,T103,T105 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T83,T102,T189 Yes T83,T102,T189 OUTPUT
cio_rx_i Yes Yes T29,T72,T73 Yes T29,T72,T73 INPUT
cio_tx_o Yes Yes T29,T72,T73 Yes T29,T72,T73 OUTPUT
cio_tx_en_o Unreachable Unreachable Unreachable OUTPUT
intr_tx_watermark_o Yes Yes T29,T72,T73 Yes T29,T72,T73 OUTPUT
intr_tx_empty_o Yes Yes T29,T72,T73 Yes T29,T72,T73 OUTPUT
intr_rx_watermark_o Yes Yes T29,T72,T73 Yes T29,T72,T73 OUTPUT
intr_tx_done_o Yes Yes T29,T72,T73 Yes T29,T72,T73 OUTPUT
intr_rx_overflow_o Yes Yes T29,T72,T73 Yes T29,T72,T73 OUTPUT
intr_rx_frame_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_break_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_timeout_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT
intr_rx_parity_err_o Yes Yes T346,T352,T353 Yes T346,T352,T353 OUTPUT

*Tests covering at least one bit in the range