Unified Coverage Report :: Module :: sensor_ctrl

Module : sensor_ctrl

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.90	94.59	90.00	79.93		100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_systems_sensor_ctrl_0.1/rtl/sensor_ctrl.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_sensor_ctrl_aon	92.90	94.59	90.00	79.93		100.00	100.00

---

Module Instance : tb.dut.top_earlgrey.u_sensor_ctrl_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.90	94.59	90.00	79.93		100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.37	94.27	86.47	79.93		96.17	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_sync_assign[0].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[10].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[1].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[2].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[3].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[4].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[5].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[6].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[7].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[8].u_alert_in_buf	100.00	100.00
gen_alert_sync_assign[9].u_alert_in_buf	100.00	100.00
u_alert_n_sync	100.00	100.00				100.00
u_alert_p_sync	100.00	100.00				100.00
u_init_chg	100.00	100.00	100.00			100.00
u_init_intr	100.00	100.00	100.00			100.00	100.00
u_io_intr	100.00	100.00	100.00			100.00	100.00
u_io_status_chg	100.00	100.00				100.00
u_prim_sec_anchor_buf	100.00	100.00
u_reg	93.84	93.80	85.68			95.89	100.00
u_wake_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
TOTAL		111	105	94.59
ALWAYS	186	0	0
ALWAYS	186	2	2	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	211	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	214	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	217	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	222	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	1	100.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	225	1	0	0.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	228	1	1	100.00
CONT_ASSIGN	234	1	1	100.00
ALWAYS	244	0	0
ALWAYS	244	3	3	100.00
ALWAYS	252	0	0
ALWAYS	252	3	3	100.00
CONT_ASSIGN	261	1	1	100.00
CONT_ASSIGN	263	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	330	3	3	100.00
ALWAYS	341	3	3	100.00
ALWAYS	356	11	11	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	376	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	377	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	378	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	391	0	0

185                       always_comb begin
186        1/1              for (int i = 0; i < NumAlertEvents; i++) begin
           Tests:       T164 T143 T165 
187        1/1                event_vld[i] = alert_event_p[i] | ~alert_event_n[i];
           Tests:       T164 T143 T165 
188                         end
189                       end
190                     
191                       // Only recoverable alerts are ack'd.  Fatal alerts are captured and continuously
192                       // triggered, there is thus not a need to ever acknowledge the source.
193                       // For recoverable alerts, the ack is only sent once the alert is captured into software readable
194                       // registers
195                       logic [NumAlertEvents-1:0] alert_en, alert_en_buf;
196                       logic [NumAlertEvents-1:0] recov_event;
197                       logic [NumAlertEvents-1:0] fatal_event;
198                     
199                       prim_sec_anchor_buf #(
200                         .Width(NumAlertEvents)
201                       ) u_prim_sec_anchor_buf (
202                         .in_i(alert_en),
203                         .out_o(alert_en_buf)
204                       );
205                     
206                       for (genvar i = 0; i < NumAlertEvents; i++) begin : gen_ast_alert_events
207                     
208                         // We're using the "loose" check so that alerts are only disabled iff they are equal to the
209                         // false value. This ensures that even a value glitched to an incorrect encoding will enable
210                         // the alert.
211        11/11            assign alert_en[i] = mubi4_test_true_loose(mubi4_t'(reg2hw.alert_en[i]));
           Tests:       T164 T165 T290  | T164 T290 T381  | T164 T165 T290  | T164 T290 T381  | T164 T165 T290  | T164 T290 T381  | T164 T290 T381  | T164 T143 T290  | T164 T143 T290  | T164 T290 T381  | T164 T290 T381 
212                     
213                         // when there is a valid alert, set the alert state
214        11/11            assign recov_event[i] = alert_en_buf[i] &&
           Tests:       T164 T165 T72  | T164 T290 T381  | T164 T165 T290  | T164 T290 T381  | T164 T165 T290  | T164 T290 T381  | T164 T290 T381  | T164 T143 T290  | T164 T143 T290  | T164 T290 T381  | T164 T290 T381 
215                                                 event_vld[i] &&
216                                                 !reg2hw.fatal_alert_en[i];
217        11/11            assign fatal_event[i] = alert_en_buf[i] &&
           Tests:       T164 T165 T72  | T164 T290 T381  | T164 T165 T290  | T164 T290 T381  | T164 T165 T290  | T164 T290 T381  | T164 T290 T381  | T164 T143 T290  | T164 T143 T290  | T164 T290 T381  | T164 T290 T381 
218                                                 event_vld[i] &&
219                                                 reg2hw.fatal_alert_en[i];
220                     
221                         assign hw2reg.recov_alert[i].d  = 1'b1;
222        11/11            assign hw2reg.recov_alert[i].de = recov_event[i];
           Tests:       T164 T165 T72  | T164 T167 T168  | T164 T165 T167  | T164 T167 T168  | T164 T165 T167  | T164 T167 T168  | T164 T167 T168  | T164 T143 T167  | T164 T143 T167  | T164 T167 T168  | T164 T167 T168 
223                     
224                         assign hw2reg.fatal_alert[i].d  = 1'b1;
225        5/11    ==>      assign hw2reg.fatal_alert[i].de = fatal_event[i];
           Tests:       T165 T172 T176  | T169  | T165 T172 T173  | T165 T172 T176  | T173 
226                     
227                         // only recoverable alerts ack
228        11/11            assign event_clr[i] = recov_event[i] & reg2hw.recov_alert[i].q;
           Tests:       T164 T165 T72  | T164 T167 T168  | T164 T165 T167  | T164 T167 T168  | T164 T165 T167  | T164 T167 T168  | T164 T167 T168  | T164 T143 T167  | T164 T143 T167  | T164 T167 T168  | T164 T167 T168 
229                       end
230                     
231                       // handle internal alert events, currently only have fatals
232                       for (genvar i = NumAlertEvents; i < TotalEvents; i++) begin : gen_local_alert_events
233                         assign hw2reg.fatal_alert[i].d  = 1'b1;
234        1/1              assign hw2reg.fatal_alert[i].de = intg_err;
           Tests:       T1 T2 T3 
235                       end
236                     
237                       // Note, even though the incoming alerts are differential, they are NOT expected to be
238                       // consistent all the time.  It is more appropriate for sensor_ctrl to treat them as
239                       // independent lines.
240                       // As a result, the alert_ack is only applied if an incoming alert is set to the active polarity.
241                       //
242                     
243                       always_comb begin
244        1/1              for (int i = 0; i < NumAlertEvents; i++) begin
           Tests:       T164 T143 T165 
245        1/1                ast_alert_o.alerts_ack[i].p = alert_event_p[i] & event_clr[i];
           Tests:       T164 T143 T165 
246        1/1                ast_alert_o.alerts_ack[i].n = ~(~alert_event_n[i] & event_clr[i]);
           Tests:       T164 T143 T165 
247                         end
248                       end
249                     
250                       // alert trigger for test
251                       always_comb begin
252        1/1              for (int i = 0; i < NumAlertEvents; i++) begin
           Tests:       T164 T143 T165 
253        1/1                ast_alert_o.alerts_trig[i].p = reg2hw.alert_trig[i];
           Tests:       T164 T143 T165 
254        1/1                ast_alert_o.alerts_trig[i].n = ~reg2hw.alert_trig[i];
           Tests:       T164 T143 T165 
255                         end
256                       end
257                     
258                     
259                       // alert test connection
260                       logic [NumAlerts-1:0] alert_test;
261        1/1            assign alert_test[RecovAlert] = reg2hw.alert_test.recov_alert.qe &
           Tests:       T1 T2 T3 
262                                                       reg2hw.alert_test.recov_alert.q;
263        1/1            assign alert_test[FatalAlert] = reg2hw.alert_test.fatal_alert.qe &
           Tests:       T1 T2 T3 
264                                                       reg2hw.alert_test.fatal_alert.q;
265                     
266                       prim_alert_sender #(
267                         .AsyncOn(AlertAsyncOn[RecovAlert]),
268                         .IsFatal(0)
269                       ) u_prim_recov_alert_sender (
270                         .clk_i,
271                         .rst_ni,
272                         .alert_test_i(alert_test[RecovAlert]),
273                         .alert_req_i(|recov_event),
274                         .alert_ack_o(),
275                         .alert_state_o(),
276                         .alert_rx_i(alert_rx_i[RecovAlert]),
277                         .alert_tx_o(alert_tx_o[RecovAlert])
278                       );
279                     
280                       prim_alert_sender #(
281                         .AsyncOn(AlertAsyncOn[FatalAlert]),
282                         .IsFatal(1)
283                       ) u_prim_fatal_alert_sender (
284                         .clk_i,
285                         .rst_ni,
286                         .alert_test_i(alert_test[FatalAlert]),
287                         .alert_req_i(|reg2hw.fatal_alert),
288                         .alert_ack_o(),
289                         .alert_state_o(),
290                         .alert_rx_i(alert_rx_i[FatalAlert]),
291                         .alert_tx_o(alert_tx_o[FatalAlert])
292                       );
293                     
294                       ///////////////////////////
295                       // wakeup generation
296                       ///////////////////////////
297                     
298                       // wakeups are synchronized separately from the normal event handling.
299                       // The alert handling is not synchronized through these below because
300                       // the ack latency would be very long for no apparent gain.
301                     
302                       logic async_wake;
303                       logic unstable_wake_req;
304                     
305                       // async wake combines ast inputs as well as recoverable alerts.
306                       // This is because it is possible for alert events to arrive "right"
307                       // on the boundary of low power. In the event this happens, the
308                       // original event is immediately 'acked', making it possible for the
309                       // sync flops below to miss the event. By mixing in recov_alert,
310                       // we guarantee that if the event is caught by the regfile, it can also
311                       // be used to trigger wake from low power.
312                       // Fatal alerts are not used here because they do not ever ack, meaning
313                       // the originating event can never disappear.
314        1/1            assign async_wake = (|(async_alert_event_p & alert_en_buf))  |
           Tests:       T164 T143 T165 
315                                           (~&(async_alert_event_n | ~alert_en_buf)) |
316                                           (|reg2hw.recov_alert);
317                     
318                       prim_flop_2sync #(
319                         .Width(1),
320                         .ResetValue('0)
321                       ) u_wake_sync (
322                         .clk_i(clk_aon_i),
323                         .rst_ni(rst_aon_ni),
324                         .d_i(async_wake),
325                         .q_o(unstable_wake_req)
326                       );
327                     
328                       logic [2:0] wake_req_filter;
329                       always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
330        1/1              if (!rst_aon_ni) begin
           Tests:       T1 T2 T3 
331        1/1                wake_req_filter <= '0;
           Tests:       T1 T2 T3 
332                         end else begin
333        1/1                wake_req_filter <= {wake_req_filter[1:0], unstable_wake_req};
           Tests:       T1 T2 T3 
334                         end
335                       end
336                     
337                       // The filter is needed since the input is purely combinational
338                       // among async events.  The filter is thus used to ensure the
339                       // wake indication is real and not a glitch.
340                       always_ff @(posedge clk_aon_i or negedge rst_aon_ni) begin
341        1/1              if (!rst_aon_ni) begin
           Tests:       T1 T2 T3 
342        1/1                wkup_req_o <= '0;
           Tests:       T1 T2 T3 
343                         end else begin
344        1/1                wkup_req_o <= &wake_req_filter;
           Tests:       T1 T2 T3 
345                         end
346                       end
347                     
348                       ///////////////////////////
349                       // Attributes for manual pads
350                       ///////////////////////////
351                       logic [NumAttrPads-1:0] manual_pad_pull_en_q,
352                                               manual_pad_pull_select_q,
353                                               manual_pad_input_disable_q;
354                     
355                       always_ff @(posedge clk_i or negedge rst_ni) begin
356        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
357        1/1                manual_pad_pull_en_q       <= '0;
           Tests:       T1 T2 T3 
358        1/1                manual_pad_pull_select_q   <= '0;
           Tests:       T1 T2 T3 
359        1/1                manual_pad_input_disable_q <= '0;
           Tests:       T1 T2 T3 
360                         end else begin
361        1/1                for (int kk = 0; kk < NumAttrPads; kk++) begin
           Tests:       T1 T2 T3 
362        1/1                  if (reg2hw.manual_pad_attr[kk].pull_en.qe) begin
           Tests:       T1 T2 T3 
363        1/1                    manual_pad_pull_en_q[kk]       <= reg2hw.manual_pad_attr[kk].pull_en.q;
           Tests:       T20 T21 T22 
364                             end
                        MISSING_ELSE
365        1/1                  if (reg2hw.manual_pad_attr[kk].pull_select.qe) begin
           Tests:       T1 T2 T3 
366        1/1                    manual_pad_pull_select_q[kk]   <= reg2hw.manual_pad_attr[kk].pull_select.q;
           Tests:       T20 T21 T22 
367                             end
                        MISSING_ELSE
368        1/1                  if (reg2hw.manual_pad_attr[kk].input_disable.qe) begin
           Tests:       T1 T2 T3 
369        1/1                    manual_pad_input_disable_q[kk] <= reg2hw.manual_pad_attr[kk].input_disable.q;
           Tests:       T20 T21 T22 
370                             end
                        MISSING_ELSE
371                           end
372                         end
373                       end
374                     
375                       for (genvar k = 0; k < NumAttrPads; k++) begin : gen_manual_pad_attr
376        4/4              assign hw2reg.manual_pad_attr[k].pull_en.d       = manual_pad_pull_en_q[k];
           Tests:       T20 T21 T22  | T20 T21 T22  | T20 T21 T22  | T20 T21 T22 
377        4/4              assign hw2reg.manual_pad_attr[k].pull_select.d   = manual_pad_pull_select_q[k];
           Tests:       T20 T21 T22  | T20 T21 T22  | T20 T21 T22  | T20 T21 T22 
378        4/4              assign hw2reg.manual_pad_attr[k].input_disable.d = manual_pad_input_disable_q[k];
           Tests:       T20 T21 T22  | T20 T21 T22  | T20 T21 T22  | T20 T21 T22 
379        4/4              assign manual_pad_attr_o[k] = '{
           Tests:       T20 T21 T22  | T20 T21 T22  | T20 T21 T22  | T20 T21 T22 
380                           pull_en:       manual_pad_pull_en_q[k],
381                           pull_select:   manual_pad_pull_select_q[k],
382                           input_disable: manual_pad_input_disable_q[k],
383                           default: '0
384                         };
385                       end
386                     
387                       ///////////////////////////
388                       // pinmux feedthrough to ast
389                       ///////////////////////////
390                     
391        unreachable    assign cio_ast_debug_out_o = ast2pinmux_i;

---

Cond Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Conditions	100	90	90.00
Logical	100	90	90.00
Non-Logical	0	0
Event	0	0

 LINE       187
 EXPRESSION (alert_event_p[i] | ((~alert_event_n[i])))
             --------1-------   ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T164,T143,T165
0	1	Not Covered
1	0	Covered	T315,T382,T383

 LINE       214
 EXPRESSION (alert_en_buf[0] && event_vld[0] && ((!reg2hw.fatal_alert_en[0])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T165,T167
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T165,T172,T176
1	1	1	Covered	T164,T165,T72

 LINE       214
 EXPRESSION (alert_en_buf[1] && event_vld[1] && ((!reg2hw.fatal_alert_en[1])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T169
1	1	1	Covered	T164,T167,T168

 LINE       214
 EXPRESSION (alert_en_buf[2] && event_vld[2] && ((!reg2hw.fatal_alert_en[2])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T165,T167
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T165,T172,T173
1	1	1	Covered	T164,T165,T167

 LINE       214
 EXPRESSION (alert_en_buf[3] && event_vld[3] && ((!reg2hw.fatal_alert_en[3])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T164,T167,T168

 LINE       214
 EXPRESSION (alert_en_buf[4] && event_vld[4] && ((!reg2hw.fatal_alert_en[4])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T165,T167
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T165,T172,T176
1	1	1	Covered	T164,T165,T167

 LINE       214
 EXPRESSION (alert_en_buf[5] && event_vld[5] && ((!reg2hw.fatal_alert_en[5])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T164,T167,T168

 LINE       214
 EXPRESSION (alert_en_buf[6] && event_vld[6] && ((!reg2hw.fatal_alert_en[6])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T173
1	1	1	Covered	T164,T167,T168

 LINE       214
 EXPRESSION (alert_en_buf[7] && event_vld[7] && ((!reg2hw.fatal_alert_en[7])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T164,T143,T167

 LINE       214
 EXPRESSION (alert_en_buf[8] && event_vld[8] && ((!reg2hw.fatal_alert_en[8])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T164,T143,T167

 LINE       214
 EXPRESSION (alert_en_buf[9] && event_vld[9] && ((!reg2hw.fatal_alert_en[9])))
             -------1-------    ------2-----    --------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T164,T167,T168

 LINE       214
 EXPRESSION (alert_en_buf[10] && event_vld[10] && ((!reg2hw.fatal_alert_en[10])))
             --------1-------    ------2------    ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T164,T167,T168
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T164,T167,T168

 LINE       217
 EXPRESSION (alert_en_buf[0] && event_vld[0] && reg2hw.fatal_alert_en[0])
             -------1-------    ------2-----    ------------3-----------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T165,T172,T176
1	0	1	Not Covered
1	1	0	Covered	T164,T165,T72
1	1	1	Covered	T165,T172,T176

 LINE       228
 EXPRESSION (recov_event[0] & reg2hw.recov_alert[0].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T165,T72
1	0	Covered	T164,T165,T72
1	1	Covered	T164,T165,T72

 LINE       228
 EXPRESSION (recov_event[1] & reg2hw.recov_alert[1].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T167,T168
1	0	Covered	T164,T167,T168
1	1	Covered	T164,T167,T168

 LINE       228
 EXPRESSION (recov_event[2] & reg2hw.recov_alert[2].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T165,T167
1	0	Covered	T164,T165,T167
1	1	Covered	T164,T165,T167

 LINE       228
 EXPRESSION (recov_event[3] & reg2hw.recov_alert[3].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T167,T168
1	0	Covered	T164,T167,T168
1	1	Covered	T164,T167,T168

 LINE       228
 EXPRESSION (recov_event[4] & reg2hw.recov_alert[4].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T165,T167
1	0	Covered	T164,T165,T167
1	1	Covered	T164,T165,T167

 LINE       228
 EXPRESSION (recov_event[5] & reg2hw.recov_alert[5].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T167,T168
1	0	Covered	T164,T167,T168
1	1	Covered	T164,T167,T168

 LINE       228
 EXPRESSION (recov_event[6] & reg2hw.recov_alert[6].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T167,T168
1	0	Covered	T164,T167,T168
1	1	Covered	T164,T167,T168

 LINE       228
 EXPRESSION (recov_event[7] & reg2hw.recov_alert[7].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T143,T167
1	0	Covered	T164,T143,T167
1	1	Covered	T164,T143,T167

 LINE       228
 EXPRESSION (recov_event[8] & reg2hw.recov_alert[8].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T143,T167
1	0	Covered	T164,T143,T167
1	1	Covered	T164,T143,T167

 LINE       228
 EXPRESSION (recov_event[9] & reg2hw.recov_alert[9].q)
             -------1------   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T167,T168
1	0	Covered	T164,T167,T168
1	1	Covered	T164,T167,T168

 LINE       228
 EXPRESSION (recov_event[10] & reg2hw.recov_alert[10].q)
             -------1-------   ------------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T164,T167,T168
1	0	Covered	T164,T167,T168
1	1	Covered	T164,T167,T168

 LINE       245
 EXPRESSION (alert_event_p[i] & event_clr[i])
             --------1-------   ------2-----

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T164,T143,T165
1	1	Covered	T164,T143,T165

 LINE       246
 SUB-EXPRESSION (((~alert_event_n[i])) & event_clr[i])
                 ----------1----------   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T315,T382,T383
1	0	Covered	T164,T143,T165
1	1	Covered	T164,T143,T165

 LINE       261
 EXPRESSION (reg2hw.alert_test.recov_alert.qe & reg2hw.alert_test.recov_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T75,T76,T274
1	1	Covered	T75,T76,T98

 LINE       263
 EXPRESSION (reg2hw.alert_test.fatal_alert.qe & reg2hw.alert_test.fatal_alert.q)
             ----------------1---------------   ---------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T75,T76,T274
1	1	Covered	T75,T76,T98

 LINE       314
 EXPRESSION (((|(async_alert_event_p & alert_en_buf))) | ((~&(async_alert_event_n | (~alert_en_buf)))) | ((|reg2hw.recov_alert)))
             --------------------1--------------------   ----------------------2----------------------   -----------3-----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T164,T143,T165
0	1	0	Not Covered
1	0	0	Covered	T315,T382,T383

---

Toggle Coverage for Module : sensor_ctrl

	Total	Covered	Percent
Totals	148	106	71.62
Total Bits	568	454	79.93
Total Bits 0->1	284	227	79.93
Total Bits 1->0	284	227	79.93

Ports	148	106	71.62
Port Bits	568	454	79.93
Port Bits 0->1	284	227	79.93
Port Bits 1->0	284	227	79.93

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T29,T36,T37	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T29,T36,T37	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[6:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T88,*T35,*T97	Yes	T88,T35,T97	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T35,*T97,*T98	Yes	T35,T97,T98	INPUT
tl_i.a_opcode[1]	No	No		No		INPUT
tl_i.a_opcode[2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T179,T164,T127	Yes	T179,T164,T127	OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T179,T164,T127	Yes	T75,T179,T164	OUTPUT
tl_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[5:3]	Yes	Yes	*T20,*T21,*T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_user.rsp_intg[6]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T36,T42,T43	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T98,*T36,*T42	Yes	T98,T1,T2	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T36,*T42,*T43	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_alert_i.alerts[0].n	Yes	Yes	T164,T165,T72	Yes	T165,T72,T166	INPUT
ast_alert_i.alerts[0].p	Yes	Yes	T165,T72,T166	Yes	T164,T165,T72	INPUT
ast_alert_i.alerts[1].n	Yes	Yes	T164,T167,T168	Yes	T169	INPUT
ast_alert_i.alerts[1].p	Yes	Yes	T169	Yes	T164,T167,T168	INPUT
ast_alert_i.alerts[2].n	Yes	Yes	T164,T165,T167	Yes	T165,T172,T173	INPUT
ast_alert_i.alerts[2].p	Yes	Yes	T165,T172,T173	Yes	T164,T165,T167	INPUT
ast_alert_i.alerts[3].n	No	Yes	T164,T167,T168	No		INPUT
ast_alert_i.alerts[3].p	No	No		Yes	T164,T167,T168	INPUT
ast_alert_i.alerts[4].n	Yes	Yes	T164,T165,T167	Yes	T165,T172,T176	INPUT
ast_alert_i.alerts[4].p	Yes	Yes	T165,T172,T176	Yes	T164,T165,T167	INPUT
ast_alert_i.alerts[5].n	No	Yes	T164,T167,T168	No		INPUT
ast_alert_i.alerts[5].p	No	No		Yes	T164,T167,T168	INPUT
ast_alert_i.alerts[6].n	Yes	Yes	T164,T167,T168	Yes	T173	INPUT
ast_alert_i.alerts[6].p	Yes	Yes	T173	Yes	T164,T167,T168	INPUT
ast_alert_i.alerts[7].n	Yes	Yes	T164,T143,T167	Yes	T143,T177	INPUT
ast_alert_i.alerts[7].p	Yes	Yes	T143,T177	Yes	T164,T143,T167	INPUT
ast_alert_i.alerts[8].n	Yes	Yes	T164,T143,T167	Yes	T143,T177	INPUT
ast_alert_i.alerts[8].p	Yes	Yes	T143,T177	Yes	T164,T143,T167	INPUT
ast_alert_i.alerts[9].n	No	Yes	T164,T167,T168	No		INPUT
ast_alert_i.alerts[9].p	No	No		Yes	T164,T167,T168	INPUT
ast_alert_i.alerts[10].n	No	Yes	T164,T167,T168	No		INPUT
ast_alert_i.alerts[10].p	No	No		Yes	T164,T167,T168	INPUT
ast_alert_o.alerts_trig[0].n	Yes	Yes	T164,T165,T72	Yes	T164,T165,T72	OUTPUT
ast_alert_o.alerts_trig[0].p	Yes	Yes	T164,T165,T72	Yes	T164,T165,T72	OUTPUT
ast_alert_o.alerts_trig[1].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[1].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[2].n	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_trig[2].p	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_trig[3].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[3].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[4].n	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_trig[4].p	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_trig[5].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[5].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[6].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[6].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[7].n	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_trig[7].p	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_trig[8].n	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_trig[8].p	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_trig[9].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[9].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[10].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_trig[10].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[0].n	Yes	Yes	T164,T165,T72	Yes	T164,T165,T72	OUTPUT
ast_alert_o.alerts_ack[0].p	Yes	Yes	T164,T165,T72	Yes	T164,T165,T72	OUTPUT
ast_alert_o.alerts_ack[1].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[1].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[2].n	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_ack[2].p	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_ack[3].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[3].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[4].n	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_ack[4].p	Yes	Yes	T164,T165,T167	Yes	T164,T165,T167	OUTPUT
ast_alert_o.alerts_ack[5].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[5].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[6].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[6].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[7].n	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_ack[7].p	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_ack[8].n	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_ack[8].p	Yes	Yes	T164,T143,T167	Yes	T164,T143,T167	OUTPUT
ast_alert_o.alerts_ack[9].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[9].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[10].n	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_alert_o.alerts_ack[10].p	Yes	Yes	T164,T167,T168	Yes	T164,T167,T168	OUTPUT
ast_status_i.io_pok[1:0]	Yes	Yes	T163,T179,T180	Yes	T1,T2,T3	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T6,T36,T42	INPUT
cio_ast_debug_out_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
cio_ast_debug_out_en_o[8:0]	Unreachable	Unreachable		Unreachable		OUTPUT
intr_io_status_change_o	Yes	Yes	T179,T127,T339	Yes	T179,T127,T339	OUTPUT
intr_init_status_change_o	Yes	Yes	T127,T190,T191	Yes	T127,T190,T191	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T75,T100,T101	Yes	T75,T100,T101	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T75,T334,T100	Yes	T75,T334,T100	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T100,T101,T102	Yes	T100,T101,T102	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T75,T100,T101	Yes	T75,T100,T101	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T75,T334,T100	Yes	T75,T334,T100	OUTPUT
wkup_req_o	Yes	Yes	T164,T143,T165	Yes	T164,T143,T165	OUTPUT
manual_pad_attr_o[0].invert	No	No		No		OUTPUT
manual_pad_attr_o[0].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[0].pull_en	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[0].pull_select	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[0].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[0].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[0].od_en	No	No		No		OUTPUT
manual_pad_attr_o[0].input_disable	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[0].drive_strength[3:0]	No	No		No		OUTPUT
manual_pad_attr_o[1].invert	No	No		No		OUTPUT
manual_pad_attr_o[1].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[1].pull_en	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[1].pull_select	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[1].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[1].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[1].od_en	No	No		No		OUTPUT
manual_pad_attr_o[1].input_disable	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[1].drive_strength[3:0]	No	No		No		OUTPUT
manual_pad_attr_o[2].invert	No	No		No		OUTPUT
manual_pad_attr_o[2].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[2].pull_en	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[2].pull_select	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[2].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[2].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[2].od_en	No	No		No		OUTPUT
manual_pad_attr_o[2].input_disable	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[2].drive_strength[3:0]	No	No		No		OUTPUT
manual_pad_attr_o[3].invert	No	No		No		OUTPUT
manual_pad_attr_o[3].virt_od_en	No	No		No		OUTPUT
manual_pad_attr_o[3].pull_en	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[3].pull_select	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[3].keep_en	No	No		No		OUTPUT
manual_pad_attr_o[3].schmitt_en	No	No		No		OUTPUT
manual_pad_attr_o[3].od_en	No	No		No		OUTPUT
manual_pad_attr_o[3].input_disable	Yes	Yes	T20,T21,T22	Yes	T20,T21,T22	OUTPUT
manual_pad_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
manual_pad_attr_o[3].drive_strength[3:0]	No	No		No		OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : sensor_ctrl

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
IF	330	2	2	100.00
IF	341	2	2	100.00
IF	356	2	2	100.00

330            if (!rst_aon_ni) begin
               -1-  
331              wake_req_filter <= '0;
                 ==>
332            end else begin
333              wake_req_filter <= {wake_req_filter[1:0], unstable_wake_req};
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

341            if (!rst_aon_ni) begin
               -1-  
342              wkup_req_o <= '0;
                 ==>
343            end else begin
344              wkup_req_o <= &wake_req_filter;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

356            if (!rst_ni) begin
               -1-  
357              manual_pad_pull_en_q       <= '0;
                 ==>
358              manual_pad_pull_select_q   <= '0;
359              manual_pad_input_disable_q <= '0;
360            end else begin
361              for (int kk = 0; kk < NumAttrPads; kk++) begin
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : sensor_ctrl

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
FpvSecCmRegWeOnehotCheck_A	121064162	8	0	0
NumAlertsMatch_A	1010	1010	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121064162	8	0	0
T100	29288	0	0	0
T114	0	1	0	0
T160	22933	0	0	0
T161	23829	0	0	0
T197	109784	0	0	0
T227	58789	0	0	0
T334	37829	1	0	0
T335	56914	0	0	0
T379	0	1	0	0
T384	0	1	0	0
T385	0	1	0	0
T386	0	1	0	0
T387	0	1	0	0
T388	0	1	0	0
T389	61331	0	0	0
T390	54955	0	0	0
T391	65620	0	0	0

NumAlertsMatch_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1010	1010	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T6	1	1	0	0
T30	1	1	0	0
T68	1	1	0	0
T104	1	1	0	0
T105	1	1	0	0