Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T278,T279,T280	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T99,T278,T279	Yes	T99,T278,T279	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T192,T245,T213	Yes	T192,T245,T213	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T229,T192,T245	Yes	T229,T192,T245	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T35,T97,T98	Yes	T35,T97,T98	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T181,T96,T278	Yes	T181,T96,T278	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T181,T94,T95	Yes	T181,T94,T95	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T83,T229,T246	Yes	T83,T229,T246	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T36,T42,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T88,T35,T84	Yes	T88,T35,T84	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T36,T42,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T36,T42,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T88,T35,T84	Yes	T88,T35,T84	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T36,T42,T43	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T88,T35,T84	Yes	T88,T35,T84	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T88,T35,T84	Yes	T88,T35,T84	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T84,T97	Yes	T35,T84,T97	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T88,T35,T84	Yes	T88,T35,T84	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T88,*T35,*T84	Yes	T88,T35,T84	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T88,T35,T84	Yes	T88,T35,T84	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	T94,*T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T278,T279,T280	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	T96,T99,T248	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T88,*T54,*T55	Yes	T88,T54,T55	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T36,T42,T43	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T36,T42,T43	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T88,*T54,*T55	Yes	T88,T54,T55	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T36,T42,T43	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T88,T54,T55	Yes	T88,T54,T55	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T1,T208,T31	Yes	T1,T208,T31	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T208,T412,T97	Yes	T208,T412,T97	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T76,T274	Yes	T75,T76,T274	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T413,T289	Yes	T75,T413,T289	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T413,T289	Yes	T75,T413,T289	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T75,T76,T274	Yes	T75,T76,T274	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T75,T413,T289	Yes	T75,T413,T289	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T75,T413,T289	Yes	T75,T413,T289	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T75,T413,T289	Yes	T75,T413,T289	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T413,T289,T414	Yes	T413,T289,T414	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T75,T76,T274	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T413,T289,T414	Yes	T75,T413,T289	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	T96,T99,*T248	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T289,*T415,*T416	Yes	T413,T289,T414	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T75,T413,T289	Yes	T75,T413,T289	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T88,*T35,*T97	Yes	T88,T35,T97	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T35,T97,T98	Yes	T35,T97,T98	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T43,T229,T368	Yes	T43,T229,T368	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T88,*T35,*T97	Yes	T88,T35,T97	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T98,*T94,*T95	Yes	T98,T94,T95	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T96,T99,T248	Yes	T96,T99,T248	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T8,T232,T235	Yes	T8,T232,T235	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T98,*T95,*T96	Yes	T98,T94,T95	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T8,*T242,*T9	Yes	T8,T242,T9	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T8,T242,T9	Yes	T8,T242,T9	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T98,*T94,*T95	Yes	T98,T94,T95	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T94,T96,T248	Yes	T94,T96,T248	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T25,T242,T127	Yes	T25,T242,T127	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T25,T242,T127	Yes	T25,T242,T75	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T25,T242,T127	Yes	T25,T242,T127	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T98,*T94,*T96	Yes	T98,T94,T95	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T25,*T242,*T127	Yes	T25,T242,T127	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T25,T242,T75	Yes	T25,T242,T75	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T4,T30,T7	Yes	T4,T30,T7	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T4,T7,T16	Yes	T4,T7,T16	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T4,T30,T7	Yes	T4,T30,T7	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T4,T30,T7	Yes	T4,T30,T7	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T4,T7,T16	Yes	T4,T7,T16	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T4,T30,T7	Yes	T4,T30,T7	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T181,*T94,*T95	Yes	T181,T94,T95	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T4,T30,T7	Yes	T4,T30,T7	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T4,T30,T7	Yes	T4,T30,T7	INPUT
tl_usbdev_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T4,T7,T16	Yes	T4,T30,T7	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T4,T30,T7	Yes	T4,T7,T16	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T4,T30,T7	Yes	T4,T7,T16	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T181,*T96,*T99	Yes	T181,T94,T95	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T4,*T7,*T16	Yes	T4,T7,T16	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T4,T30,T7	Yes	T4,T30,T7	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T29,T36	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T3,T6,T23	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T95,*T96,*T99	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T278,T279,T280	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T95,T96,T99	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T95,*T96,*T99	Yes	T95,T96,T99	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T29,T36	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_hmac_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T326,T650,T327	Yes	T326,T650,T327	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	INPUT
tl_hmac_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T326,T650,T327	Yes	T326,T650,T327	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T326,T650,T327	Yes	T326,T650,T327	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T75,T326,T650	Yes	T326,T650,T327	INPUT
tl_hmac_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T94,*T96,*T99	Yes	T94,T95,T96	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T75,*T326,*T650	Yes	T326,T650,T327	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T75,T326,T650	Yes	T75,T326,T650	INPUT
tl_kmac_o.d_ready	Yes	Yes	T6,T423,T29	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T423,T75,T440	Yes	T423,T75,T440	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T423,T75,T440	Yes	T423,T75,T440	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T35,*T94,*T95	Yes	T35,T94,T95	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T423,T440,T441	Yes	T423,T440,T441	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	INPUT
tl_kmac_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T423,T42,T247	Yes	T423,T42,T207	INPUT
tl_kmac_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T35,*T95,*T96	Yes	T35,T95,T96	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T423,*T42,*T247	Yes	T423,T42,T207	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T423,T42,T247	Yes	T423,T42,T247	INPUT
tl_aes_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	INPUT
tl_aes_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	INPUT
tl_aes_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T407,*T408,*T409	Yes	T407,T408,T409	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T407,T408,T409	Yes	T407,T408,T409	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T96,T99,T248	Yes	T96,T99,T248	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T160,T161,T162	Yes	T160,T161,T162	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T36,T42	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T6,T36,T42	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T96,*T99,*T248	Yes	T94,T95,T96	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T160,*T161,*T162	Yes	T160,T161,T162	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T623,T75,T160	Yes	T623,T75,T160	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T623,T160,T162	Yes	T623,T160,T162	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T36,T42	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T6,T36,T42	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T96,*T99,*T248	Yes	T94,T95,T96	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T96,T99	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T623,*T160,*T162	Yes	T623,T160,T162	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T623,T75,T160	Yes	T623,T75,T160	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T623,T75,T160	Yes	T623,T75,T160	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T94,*T96,*T99	Yes	T94,T96,T99	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T623,T160,T162	Yes	T623,T160,T162	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T36,T42	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T6,T36,T42	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T94,*T96,*T99	Yes	T94,T96,T99	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T94,T96,T99	Yes	T94,T95,T96	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T623,*T160,*T162	Yes	T623,T160,T162	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	INPUT
tl_edn1_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T160,T162,T157	Yes	T160,T162,T157	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T162,T157,T158	Yes	T75,T160,T162	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T162,T157,T158	Yes	T75,T160,T162	INPUT
tl_edn1_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T95,*T96,*T99	Yes	T94,T95,T96	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T160,*T162,*T157	Yes	T160,T162,T157	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T75,T160,T162	Yes	T75,T160,T162	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T2,T3,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T98,*T94,*T95	Yes	T98,T94,T95	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T98,*T95,*T96	Yes	T98,T94,T95	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T5	Yes	T2,T3,T5	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_otbn_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T35,*T97,*T236	Yes	T35,T97,T236	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	INPUT
tl_otbn_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T217,T162,T157	Yes	T217,T162,T157	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T217,T162,T157	Yes	T217,T162,T157	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T217,T75,T162	Yes	T217,T162,T157	INPUT
tl_otbn_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T35,*T97,*T236	Yes	T35,T97,T236	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T217,*T75,*T162	Yes	T217,T162,T157	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T217,T75,T162	Yes	T217,T75,T162	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T42,T207,T199	Yes	T42,T207,T199	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T42,T247,T207	Yes	T42,T247,T207	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T42,T247,T207	Yes	T42,T247,T207	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T42,T207,T199	Yes	T42,T207,T199	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T42,T247,T207	Yes	T42,T247,T207	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T42,T247,T207	Yes	T42,T247,T207	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T42,T247,T207	Yes	T42,T247,T207	INPUT
tl_keymgr_i.d_error	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T42,T207,T199	Yes	T42,T207,T199	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T42,T207,T199	Yes	T42,T207,T199	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T42,T207,T199	Yes	T42,T207,T199	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T94,T96,T99	Yes	T94,T96,T99	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T96,*T99,*T248	Yes	T94,T96,T99	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T42,*T207,*T199	Yes	T42,T247,T207	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T42,T247,T207	Yes	T42,T247,T207	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T94,*T95,*T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T95,T96,T99	Yes	T95,T96,T99	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T2,T3,T5	Yes	T2,T3,T5	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T94,*T96,*T99	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T6,T29,T36	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T434,*T435,*T436	Yes	T434,T435,T436	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T95,T96,T99	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T213,T320,T98	Yes	T213,T320,T98	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T151,T210,T213	Yes	T75,T151,T210	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T151,T210,T213	Yes	T75,T151,T210	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T98,*T94,*T95	Yes	T434,T435,T436	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T151,*T210,*T213	Yes	T151,T210,T213	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T75,T151,T210	Yes	T75,T151,T210	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T6,T29,T36	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T94,T95,T96	Yes	T94,T95,T96	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range