Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : xbar_main
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_xbar_main 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
93.94 92.47 89.34 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : xbar_main
TotalCoveredPercent
Totals 550 550 100.00
Total Bits 6824 6824 100.00
Total Bits 0->1 3412 3412 100.00
Total Bits 1->0 3412 3412 100.00

Ports 550 550 100.00
Port Bits 6824 6824 100.00
Port Bits 0->1 3412 3412 100.00
Port Bits 1->0 3412 3412 100.00

Port Details
Name   Toggle   Toggle 1->0   Tests   Toggle 0->1   Tests   Direction   
clk_main_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_fixed_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_usb_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host0_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_spi_host1_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
rst_fixed_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
rst_usb_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
rst_spi_host0_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
rst_spi_host1_ni Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.d_ready Yes Yes T99,T100,T161 Yes T98,T99,T100 INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0] Yes Yes T161,T281,T282 Yes T161,T281,T282 INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_data[31:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_core_ibex__corei_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_core_ibex__corei_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_core_ibex__corei_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__corei_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_error Yes Yes T205,T94,T240 Yes T205,T94,T240 OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0] Yes Yes T88,T205,T94 Yes T88,T205,T94 OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__corei_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_i.d_ready Yes Yes T30,T45,T101 Yes T30,T45,T101 INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0] Yes Yes T231,T281,T282 Yes T231,T281,T282 INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_size[1:0] Yes Yes T231,T98,T99 Yes T231,T98,T99 INPUT
tl_rv_core_ibex__cored_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cored_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_error Yes Yes T53,T89,T241 Yes T53,T89,T241 OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cored_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_i.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0] Yes Yes T94,T30,T45 Yes T94,T30,T45 INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_data[31:0] Yes Yes T94,T30,T45 Yes T94,T30,T45 INPUT
tl_rv_dm__sba_i.a_mask[3:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_rv_dm__sba_i.a_address[31:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_source[5:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__sba_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__sba_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__sba_i.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__sba_i.a_valid Yes Yes T94,T30,T45 Yes T94,T30,T45 INPUT
tl_rv_dm__sba_o.a_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_rv_dm__sba_o.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0] Yes Yes T94,T30,T45 Yes T94,T30,T45 OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0] Yes Yes T30,T45,T63 Yes T30,T45,T63 OUTPUT
tl_rv_dm__sba_o.d_data[31:0] Yes Yes T94,T30,T45 Yes T94,T30,T45 OUTPUT
tl_rv_dm__sba_o.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__sba_o.d_source[5:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__sba_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__sba_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_opcode[0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__sba_o.d_valid Yes Yes T94,T30,T45 Yes T94,T30,T45 OUTPUT
tl_rv_dm__regs_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_data[31:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_mask[3:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_source[5:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_o.a_valid Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__regs_i.a_ready Yes Yes T99,T100,T161 Yes T98,T99,T100 INPUT
tl_rv_dm__regs_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0] Yes Yes T98,T100,T161 Yes T98,T99,T100 INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__regs_i.d_data[31:0] Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_rv_dm__regs_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__regs_i.d_source[5:0] Yes Yes T100,*T161,T185 Yes T98,T99,T100 INPUT
tl_rv_dm__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_opcode[0] Yes Yes *T98,*T99,*T100 Yes T99,T100,T161 INPUT
tl_rv_dm__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__regs_i.d_valid Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__mem_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0] Yes Yes T94,T63,T285 Yes T94,T63,T285 OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0] Yes Yes T94,T63,T285 Yes T94,T63,T285 OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0] Yes Yes T94,T63,T285 Yes T94,T63,T285 OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_data[31:0] Yes Yes T94,T63,T285 Yes T94,T63,T285 OUTPUT
tl_rv_dm__mem_o.a_mask[3:0] Yes Yes T94,T63,T285 Yes T94,T63,T285 OUTPUT
tl_rv_dm__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_source[5:0] Yes Yes *T94,*T63,*T285 Yes T94,T63,T285 OUTPUT
tl_rv_dm__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_dm__mem_o.a_valid Yes Yes T94,T63,T285 Yes T94,T63,T285 OUTPUT
tl_rv_dm__mem_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_dm__mem_i.d_error Yes Yes T1,T2,T3 Yes T46,T53,T47 INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0] Yes Yes T94,T63,T285 Yes T94,T63,T285 INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0] Yes Yes T94,T63,T285 Yes T94,T63,T285 INPUT
tl_rv_dm__mem_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T46,T53,T47 INPUT
tl_rv_dm__mem_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__mem_i.d_source[5:0] Yes Yes *T94,*T63,*T285 Yes T94,T63,T285 INPUT
tl_rv_dm__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rv_dm__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T46,T53,T47 INPUT
tl_rv_dm__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_dm__mem_i.d_valid Yes Yes T94,T63,T285 Yes T94,T63,T285 INPUT
tl_rom_ctrl__rom_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0] Yes Yes T1,T201,T95 Yes T1,T201,T95 OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0] Yes Yes T201,T437,T45 Yes T201,T437,T45 OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rom_ctrl__rom_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__rom_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rom_ctrl__rom_i.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__rom_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_rom_ctrl__rom_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_opcode[0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__rom_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rom_ctrl__regs_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0] Yes Yes T83,T438,T300 Yes T83,T438,T300 OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0] Yes Yes T83,T438,T300 Yes T83,T438,T300 OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0] Yes Yes T83,T84,T85 Yes T83,T84,T85 OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0] Yes Yes T83,T438,T300 Yes T83,T438,T300 OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rom_ctrl__regs_o.a_valid Yes Yes T83,T438,T300 Yes T83,T438,T300 OUTPUT
tl_rom_ctrl__regs_i.a_ready Yes Yes T83,T438,T300 Yes T83,T438,T300 INPUT
tl_rom_ctrl__regs_i.d_error Yes Yes T98,T99,T100 Yes T99,T100,T161 INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0] Yes Yes T438,T300,T439 Yes T438,T300,T439 INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0] Yes Yes T98,T99,T100 Yes T83,T84,T85 INPUT
tl_rom_ctrl__regs_i.d_data[31:0] Yes Yes T438,T300,T439 Yes T83,T438,T300 INPUT
tl_rom_ctrl__regs_i.d_sink Yes Yes T98,T99,T100 Yes T98,T100,T185 INPUT
tl_rom_ctrl__regs_i.d_source[5:0] Yes Yes *T100,*T185,*T236 Yes T99,T100,T161 INPUT
tl_rom_ctrl__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_size[1:0] Yes Yes T99,T100,T161 Yes T98,T99,T100 INPUT
tl_rom_ctrl__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_opcode[0] Yes Yes *T300,*T440,*T441 Yes T438,T300,T439 INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rom_ctrl__regs_i.d_valid Yes Yes T83,T438,T300 Yes T83,T438,T300 INPUT
tl_peri_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 OUTPUT
tl_peri_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_peri_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_peri_o.a_opcode[2:0] Yes Yes T30,T45,T101 Yes T30,T45,T101 OUTPUT
tl_peri_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_peri_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_error Yes Yes T357,T388,T108 Yes T357,T388,T108 INPUT
tl_peri_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_peri_i.d_source[5:0] Yes Yes *T94,*T30,*T45 Yes T94,T30,T45 INPUT
tl_peri_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_peri_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_peri_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_peri_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_spi_host0_o.d_ready Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_data[31:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_spi_host0_o.a_mask[3:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_spi_host0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_source[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 OUTPUT
tl_spi_host0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_spi_host0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host0_o.a_opcode[2:0] Yes Yes T11,T226,T229 Yes T11,T226,T229 OUTPUT
tl_spi_host0_o.a_valid Yes Yes T10,T11,T12 Yes T10,T11,T12 OUTPUT
tl_spi_host0_i.a_ready Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_spi_host0_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_spi_host0_i.d_user.data_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_spi_host0_i.d_data[31:0] Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_spi_host0_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_spi_host0_i.d_source[5:0] Yes Yes *T100,*T161,*T185 Yes T98,T99,T100 INPUT
tl_spi_host0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_spi_host0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_opcode[0] Yes Yes *T10,*T11,*T12 Yes T10,T11,T12 INPUT
tl_spi_host0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host0_i.d_valid Yes Yes T10,T11,T12 Yes T10,T11,T12 INPUT
tl_spi_host1_o.d_ready Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_data[31:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_spi_host1_o.a_mask[3:0] Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_spi_host1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_source[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 OUTPUT
tl_spi_host1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_spi_host1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_spi_host1_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_spi_host1_o.a_valid Yes Yes T315,T83,T128 Yes T315,T83,T128 OUTPUT
tl_spi_host1_i.a_ready Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_spi_host1_i.d_error Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_spi_host1_i.d_user.data_intg[6:0] Yes Yes T315,T128,T13 Yes T315,T128,T13 INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0] Yes Yes T315,T128,T349 Yes T315,T83,T128 INPUT
tl_spi_host1_i.d_data[31:0] Yes Yes T315,T128,T13 Yes T315,T128,T13 INPUT
tl_spi_host1_i.d_sink Yes Yes T98,T99,T100 Yes T99,T100,T161 INPUT
tl_spi_host1_i.d_source[5:0] Yes Yes *T100,*T185,*T281 Yes T98,T99,T100 INPUT
tl_spi_host1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_spi_host1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_opcode[0] Yes Yes *T315,*T128,*T349 Yes T315,T128,T349 INPUT
tl_spi_host1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_spi_host1_i.d_valid Yes Yes T315,T83,T128 Yes T315,T83,T128 INPUT
tl_usbdev_o.d_ready Yes Yes T38,T39,T7 Yes T38,T39,T7 OUTPUT
tl_usbdev_o.a_user.data_intg[6:0] Yes Yes T38,T7,T8 Yes T38,T7,T8 OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0] Yes Yes T38,T39,T7 Yes T38,T39,T7 OUTPUT
tl_usbdev_o.a_user.instr_type[3:0] Yes Yes T38,T39,T7 Yes T38,T39,T7 OUTPUT
tl_usbdev_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_data[31:0] Yes Yes T38,T7,T8 Yes T38,T7,T8 OUTPUT
tl_usbdev_o.a_mask[3:0] Yes Yes T38,T39,T7 Yes T38,T39,T7 OUTPUT
tl_usbdev_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_source[5:0] Yes Yes *T101,*T98,*T99 Yes T101,T98,T99 OUTPUT
tl_usbdev_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_size[1:0] Yes Yes T99,T100,T161 Yes T99,T100,T161 OUTPUT
tl_usbdev_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_usbdev_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_usbdev_o.a_valid Yes Yes T38,T39,T7 Yes T38,T39,T7 OUTPUT
tl_usbdev_i.a_ready Yes Yes T38,T39,T7 Yes T38,T39,T7 INPUT
tl_usbdev_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_usbdev_i.d_user.data_intg[6:0] Yes Yes T38,T7,T8 Yes T38,T39,T7 INPUT
tl_usbdev_i.d_user.rsp_intg[6:0] Yes Yes T38,T39,T7 Yes T38,T7,T8 INPUT
tl_usbdev_i.d_data[31:0] Yes Yes T38,T39,T7 Yes T38,T7,T8 INPUT
tl_usbdev_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_usbdev_i.d_source[5:0] Yes Yes *T101,*T100,*T185 Yes T101,T98,T99 INPUT
tl_usbdev_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_size[1:0] Yes Yes T99,T100,T161 Yes T99,T100,T161 INPUT
tl_usbdev_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_opcode[0] Yes Yes *T38,*T7,*T8 Yes T38,T7,T8 INPUT
tl_usbdev_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_usbdev_i.d_valid Yes Yes T38,T39,T7 Yes T38,T39,T7 INPUT
tl_flash_ctrl__core_o.d_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__core_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__core_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_flash_ctrl__core_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0] Yes Yes T99,T100,T185 Yes T99,T100,T185 OUTPUT
tl_flash_ctrl__core_o.a_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__core_i.a_ready Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_flash_ctrl__core_i.d_error Yes Yes T1,T2,T3 Yes T46,T53,T47 INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_flash_ctrl__core_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T5,T121,T267 INPUT
tl_flash_ctrl__core_i.d_sink Yes Yes T99,T100,T161 Yes T98,T100,T161 INPUT
tl_flash_ctrl__core_i.d_source[5:0] Yes Yes *T30,*T101,*T100 Yes T30,T101,T98 INPUT
tl_flash_ctrl__core_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T100,T161,T185 INPUT
tl_flash_ctrl__core_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_flash_ctrl__core_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__core_i.d_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_flash_ctrl__prim_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0] Yes Yes T30,T101,T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0] Yes Yes T30,T101,T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0] Yes Yes T30,T101,T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0] Yes Yes T30,T101,T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0] Yes Yes T30,T101,T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0] Yes Yes *T30,*T101,T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_flash_ctrl__prim_o.a_valid Yes Yes T30,T101,T98 Yes T30,T101,T98 OUTPUT
tl_flash_ctrl__prim_i.a_ready Yes Yes T30,T101,T99 Yes T30,T101,T98 INPUT
tl_flash_ctrl__prim_i.d_error Yes Yes T99,T100,T161 Yes T99,T100,T161 INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0] Yes Yes T101,T98,T99 Yes T101,T98,T99 INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0] Yes Yes T30,T101,T98 Yes T30,T101,T98 INPUT
tl_flash_ctrl__prim_i.d_data[31:0] Yes Yes T30,T101,T98 Yes T30,T101,T98 INPUT
tl_flash_ctrl__prim_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_flash_ctrl__prim_i.d_source[5:0] Yes Yes *T30,*T101,T100 Yes T30,T101,T98 INPUT
tl_flash_ctrl__prim_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_flash_ctrl__prim_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_opcode[0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__prim_i.d_valid Yes Yes T30,T101,T98 Yes T30,T101,T98 INPUT
tl_flash_ctrl__mem_o.d_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_flash_ctrl__mem_o.a_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_flash_ctrl__mem_i.a_ready Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_flash_ctrl__mem_i.d_error Yes Yes T1,T2,T3 Yes T46,T53,T47 INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_flash_ctrl__mem_i.d_data[31:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_flash_ctrl__mem_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_flash_ctrl__mem_i.d_source[5:0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_flash_ctrl__mem_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_flash_ctrl__mem_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_opcode[0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_flash_ctrl__mem_i.d_valid Yes Yes T2,T3,T4 Yes T2,T3,T4 INPUT
tl_hmac_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_hmac_o.a_user.data_intg[6:0] Yes Yes T83,T347,T348 Yes T83,T347,T348 OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0] Yes Yes T83,T347,T348 Yes T83,T347,T348 OUTPUT
tl_hmac_o.a_user.instr_type[3:0] Yes Yes T83,T347,T348 Yes T83,T347,T348 OUTPUT
tl_hmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_data[31:0] Yes Yes T83,T347,T348 Yes T83,T347,T348 OUTPUT
tl_hmac_o.a_mask[3:0] Yes Yes T83,T347,T348 Yes T83,T347,T348 OUTPUT
tl_hmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_hmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_hmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_hmac_o.a_opcode[2:0] Yes Yes T347,T348,T667 Yes T347,T348,T667 OUTPUT
tl_hmac_o.a_valid Yes Yes T83,T347,T348 Yes T83,T347,T348 OUTPUT
tl_hmac_i.a_ready Yes Yes T83,T347,T348 Yes T83,T347,T348 INPUT
tl_hmac_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_hmac_i.d_user.data_intg[6:0] Yes Yes T347,T348,T667 Yes T347,T348,T667 INPUT
tl_hmac_i.d_user.rsp_intg[6:0] Yes Yes T347,T348,T667 Yes T347,T348,T667 INPUT
tl_hmac_i.d_data[31:0] Yes Yes T83,T347,T348 Yes T347,T348,T667 INPUT
tl_hmac_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_hmac_i.d_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 INPUT
tl_hmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_hmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_opcode[0] Yes Yes *T83,*T347,*T348 Yes T347,T348,T667 INPUT
tl_hmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_hmac_i.d_valid Yes Yes T83,T347,T348 Yes T83,T347,T348 INPUT
tl_kmac_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_kmac_o.a_user.data_intg[6:0] Yes Yes T83,T467,T156 Yes T83,T467,T156 OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_kmac_o.a_user.instr_type[3:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_kmac_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_data[31:0] Yes Yes T83,T467,T156 Yes T83,T467,T156 OUTPUT
tl_kmac_o.a_mask[3:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_kmac_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_source[5:0] Yes Yes *T30,*T101,*T74 Yes T30,T101,T74 OUTPUT
tl_kmac_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_size[1:0] Yes Yes T99,T100,T161 Yes T99,T100,T161 OUTPUT
tl_kmac_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_kmac_o.a_opcode[2:0] Yes Yes T467,T468,T469 Yes T467,T468,T469 OUTPUT
tl_kmac_o.a_valid Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_kmac_i.a_ready Yes Yes T46,T242,T196 Yes T46,T242,T196 INPUT
tl_kmac_i.d_error Yes Yes T98,T100,T185 Yes T98,T100,T185 INPUT
tl_kmac_i.d_user.data_intg[6:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 INPUT
tl_kmac_i.d_user.rsp_intg[6:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 INPUT
tl_kmac_i.d_data[31:0] Yes Yes T46,T242,T196 Yes T46,T196,T197 INPUT
tl_kmac_i.d_sink Yes Yes T98,T100,T161 Yes T98,T99,T100 INPUT
tl_kmac_i.d_source[5:0] Yes Yes *T30,*T101,*T74 Yes T30,T101,T74 INPUT
tl_kmac_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_size[1:0] Yes Yes T99,T100,T161 Yes T99,T100,T161 INPUT
tl_kmac_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_opcode[0] Yes Yes *T46,*T242,*T196 Yes T46,T196,T197 INPUT
tl_kmac_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_kmac_i.d_valid Yes Yes T46,T242,T196 Yes T46,T242,T196 INPUT
tl_aes_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_aes_o.a_user.data_intg[6:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 OUTPUT
tl_aes_o.a_user.cmd_intg[6:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 OUTPUT
tl_aes_o.a_user.instr_type[3:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 OUTPUT
tl_aes_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_data[31:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 OUTPUT
tl_aes_o.a_mask[3:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 OUTPUT
tl_aes_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_source[5:0] Yes Yes *T98,*T99,*T100 Yes T98,T99,T100 OUTPUT
tl_aes_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_aes_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_aes_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_aes_o.a_valid Yes Yes T294,T296,T297 Yes T294,T296,T297 OUTPUT
tl_aes_i.a_ready Yes Yes T294,T296,T297 Yes T294,T296,T297 INPUT
tl_aes_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_aes_i.d_user.data_intg[6:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 INPUT
tl_aes_i.d_user.rsp_intg[6:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 INPUT
tl_aes_i.d_data[31:0] Yes Yes T294,T296,T297 Yes T294,T296,T297 INPUT
tl_aes_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_aes_i.d_source[5:0] Yes Yes *T99,*T100,*T185 Yes T98,T99,T100 INPUT
tl_aes_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_aes_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_opcode[0] Yes Yes *T294,*T296,*T297 Yes T294,T296,T297 INPUT
tl_aes_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_aes_i.d_valid Yes Yes T294,T296,T297 Yes T294,T296,T297 INPUT
tl_entropy_src_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_entropy_src_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_entropy_src_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_entropy_src_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_entropy_src_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_entropy_src_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_entropy_src_i.d_user.data_intg[6:0] Yes Yes T158,T159,T160 Yes T158,T159,T160 INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_data[31:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_entropy_src_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_entropy_src_i.d_source[5:0] Yes Yes *T30,*T101,*T99 Yes T30,T101,T98 INPUT
tl_entropy_src_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_entropy_src_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_opcode[0] Yes Yes *T158,*T159,*T160 Yes T158,T159,T160 INPUT
tl_entropy_src_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_entropy_src_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_data[31:0] Yes Yes T298,T83,T158 Yes T298,T83,T158 OUTPUT
tl_csrng_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_csrng_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_csrng_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_csrng_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_csrng_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_csrng_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_csrng_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_csrng_i.d_user.data_intg[6:0] Yes Yes T298,T158,T416 Yes T298,T158,T416 INPUT
tl_csrng_i.d_user.rsp_intg[6:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_csrng_i.d_data[31:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_csrng_i.d_sink Yes Yes T98,T100,T161 Yes T98,T99,T100 INPUT
tl_csrng_i.d_source[5:0] Yes Yes *T30,*T101,*T100 Yes T30,T101,T98 INPUT
tl_csrng_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_csrng_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_opcode[0] Yes Yes *T298,*T158,*T416 Yes T298,T158,T416 INPUT
tl_csrng_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_csrng_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.data_intg[6:0] Yes Yes T298,T83,T158 Yes T298,T83,T158 OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_data[31:0] Yes Yes T298,T83,T158 Yes T298,T83,T158 OUTPUT
tl_edn0_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_edn0_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_edn0_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn0_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_edn0_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_edn0_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn0_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_edn0_i.d_user.data_intg[6:0] Yes Yes T298,T158,T160 Yes T298,T158,T160 INPUT
tl_edn0_i.d_user.rsp_intg[6:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_edn0_i.d_data[31:0] Yes Yes T46,T53,T47 Yes T1,T2,T3 INPUT
tl_edn0_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_edn0_i.d_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 INPUT
tl_edn0_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_edn0_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_opcode[0] Yes Yes *T298,*T158,*T160 Yes T298,T158,T160 INPUT
tl_edn0_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn0_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_edn1_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_edn1_o.a_user.data_intg[6:0] Yes Yes T83,T158,T160 Yes T83,T158,T160 OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0] Yes Yes T83,T158,T160 Yes T83,T158,T160 OUTPUT
tl_edn1_o.a_user.instr_type[3:0] Yes Yes T83,T158,T160 Yes T83,T158,T160 OUTPUT
tl_edn1_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_data[31:0] Yes Yes T83,T158,T160 Yes T83,T158,T160 OUTPUT
tl_edn1_o.a_mask[3:0] Yes Yes T83,T158,T160 Yes T83,T158,T160 OUTPUT
tl_edn1_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_edn1_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_size[1:0] Yes Yes T99,T100,T161 Yes T99,T100,T161 OUTPUT
tl_edn1_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_edn1_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_edn1_o.a_valid Yes Yes T83,T158,T160 Yes T83,T158,T160 OUTPUT
tl_edn1_i.a_ready Yes Yes T83,T158,T160 Yes T83,T158,T160 INPUT
tl_edn1_i.d_error Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_edn1_i.d_user.data_intg[6:0] Yes Yes T158,T160,T155 Yes T158,T160,T155 INPUT
tl_edn1_i.d_user.rsp_intg[6:0] Yes Yes T160,T155,T156 Yes T83,T158,T160 INPUT
tl_edn1_i.d_data[31:0] Yes Yes T160,T155,T156 Yes T83,T158,T160 INPUT
tl_edn1_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_edn1_i.d_source[5:0] Yes Yes *T30,*T101,*T99 Yes T30,T101,T98 INPUT
tl_edn1_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_size[1:0] Yes Yes T99,T100,T185 Yes T99,T100,T185 INPUT
tl_edn1_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_opcode[0] Yes Yes *T158,*T160,*T155 Yes T158,T160,T155 INPUT
tl_edn1_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_edn1_i.d_valid Yes Yes T83,T158,T160 Yes T83,T158,T160 INPUT
tl_rv_plic_o.d_ready Yes Yes T2,T5,T6 Yes T1,T2,T3 OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_data[31:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
tl_rv_plic_o.a_mask[3:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
tl_rv_plic_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_source[5:0] Yes Yes *T98,*T100,*T161 Yes T98,T100,T161 OUTPUT
tl_rv_plic_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_size[1:0] Yes Yes T98,T100,T161 Yes T98,T100,T161 OUTPUT
tl_rv_plic_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_plic_o.a_opcode[2:0] Yes Yes T98,T100,T161 Yes T98,T100,T161 OUTPUT
tl_rv_plic_o.a_valid Yes Yes T2,T5,T6 Yes T2,T5,T6 OUTPUT
tl_rv_plic_i.a_ready Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_rv_plic_i.d_error Yes Yes T98,T100,T185 Yes T98,T100,T185 INPUT
tl_rv_plic_i.d_user.data_intg[6:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_rv_plic_i.d_data[31:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_rv_plic_i.d_sink Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_rv_plic_i.d_source[5:0] Yes Yes *T98,*T100,*T185 Yes T98,T100,T161 INPUT
tl_rv_plic_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_size[1:0] Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_rv_plic_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_opcode[0] Yes Yes *T2,*T5,*T6 Yes T2,T5,T6 INPUT
tl_rv_plic_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_plic_i.d_valid Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_otbn_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_otbn_o.a_user.data_intg[6:0] Yes Yes T209,T83,T160 Yes T209,T83,T160 OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0] Yes Yes T209,T83,T160 Yes T209,T83,T160 OUTPUT
tl_otbn_o.a_user.instr_type[3:0] Yes Yes T209,T83,T160 Yes T209,T83,T160 OUTPUT
tl_otbn_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_data[31:0] Yes Yes T209,T83,T160 Yes T209,T83,T160 OUTPUT
tl_otbn_o.a_mask[3:0] Yes Yes T209,T83,T160 Yes T209,T83,T160 OUTPUT
tl_otbn_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_source[5:0] Yes Yes *T45,*T230,*T74 Yes T45,T230,T74 OUTPUT
tl_otbn_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_size[1:0] Yes Yes T98,T100,T185 Yes T98,T100,T185 OUTPUT
tl_otbn_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_otbn_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_otbn_o.a_valid Yes Yes T209,T83,T160 Yes T209,T83,T160 OUTPUT
tl_otbn_i.a_ready Yes Yes T209,T83,T160 Yes T209,T83,T160 INPUT
tl_otbn_i.d_error Yes Yes T98,T100,T185 Yes T98,T100,T185 INPUT
tl_otbn_i.d_user.data_intg[6:0] Yes Yes T209,T160,T155 Yes T209,T160,T155 INPUT
tl_otbn_i.d_user.rsp_intg[6:0] Yes Yes T209,T160,T155 Yes T209,T160,T155 INPUT
tl_otbn_i.d_data[31:0] Yes Yes T209,T83,T160 Yes T209,T160,T155 INPUT
tl_otbn_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_otbn_i.d_source[5:0] Yes Yes *T45,*T230,*T74 Yes T45,T230,T74 INPUT
tl_otbn_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_size[1:0] Yes Yes T98,T100,T185 Yes T98,T100,T185 INPUT
tl_otbn_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_opcode[0] Yes Yes *T209,*T83,*T160 Yes T209,T160,T155 INPUT
tl_otbn_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_otbn_i.d_valid Yes Yes T209,T83,T160 Yes T209,T83,T160 INPUT
tl_keymgr_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_keymgr_o.a_user.data_intg[6:0] Yes Yes T46,T196,T197 Yes T46,T196,T197 OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_keymgr_o.a_user.instr_type[3:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_keymgr_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_data[31:0] Yes Yes T46,T196,T197 Yes T46,T196,T197 OUTPUT
tl_keymgr_o.a_mask[3:0] Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_keymgr_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 OUTPUT
tl_keymgr_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_size[1:0] Yes Yes T98,T100,T161 Yes T98,T100,T161 OUTPUT
tl_keymgr_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_keymgr_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_keymgr_o.a_valid Yes Yes T46,T242,T196 Yes T46,T242,T196 OUTPUT
tl_keymgr_i.a_ready Yes Yes T46,T242,T196 Yes T46,T242,T196 INPUT
tl_keymgr_i.d_error Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_keymgr_i.d_user.data_intg[6:0] Yes Yes T46,T196,T197 Yes T46,T196,T197 INPUT
tl_keymgr_i.d_user.rsp_intg[6:0] Yes Yes T46,T196,T197 Yes T46,T196,T197 INPUT
tl_keymgr_i.d_data[31:0] Yes Yes T46,T196,T197 Yes T46,T196,T197 INPUT
tl_keymgr_i.d_sink Yes Yes T98,T99,T100 Yes T98,T100,T161 INPUT
tl_keymgr_i.d_source[5:0] Yes Yes *T30,*T101,*T98 Yes T30,T101,T98 INPUT
tl_keymgr_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_size[1:0] Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_keymgr_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_opcode[0] Yes Yes *T46,*T196,*T197 Yes T46,T242,T196 INPUT
tl_keymgr_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_keymgr_i.d_valid Yes Yes T46,T242,T196 Yes T46,T242,T196 INPUT
tl_rv_core_ibex__cfg_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0] Yes Yes *T286,*T98,*T99 Yes T286,T98,T99 OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_rv_core_ibex__cfg_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_rv_core_ibex__cfg_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_error Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0] Yes Yes T2,T5,T6 Yes T2,T5,T6 INPUT
tl_rv_core_ibex__cfg_i.d_sink Yes Yes T98,T100,T161 Yes T98,T100,T161 INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0] Yes Yes *T100,*T185,*T281 Yes T286,T98,T99 INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0] Yes Yes T99,T100,T161 Yes T100,T161,T185 INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T2,T3,T4 INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_rv_core_ibex__cfg_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__regs_o.d_ready Yes Yes T46,T53,T47 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0] Yes Yes T83,T203,T148 Yes T83,T203,T148 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0] Yes Yes T83,T203,T148 Yes T83,T203,T148 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0] Yes Yes T83,T203,T148 Yes T83,T203,T148 OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0] Yes Yes T83,T203,T148 Yes T83,T203,T148 OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0] Yes Yes T83,T203,T148 Yes T83,T203,T148 OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0] Yes Yes *T463,*T464,*T98 Yes T463,T464,T98 OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_sram_ctrl_main__regs_o.a_valid Yes Yes T83,T203,T148 Yes T83,T203,T148 OUTPUT
tl_sram_ctrl_main__regs_i.a_ready Yes Yes T83,T203,T148 Yes T83,T203,T148 INPUT
tl_sram_ctrl_main__regs_i.d_error Yes Yes T99,T100,T161 Yes T99,T100,T161 INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0] Yes Yes T205,T339,T340 Yes T205,T339,T340 INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0] Yes Yes T203,T148,T205 Yes T83,T203,T148 INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0] Yes Yes T203,T148,T205 Yes T83,T203,T148 INPUT
tl_sram_ctrl_main__regs_i.d_sink Yes Yes T99,T100,T161 Yes T98,T99,T100 INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0] Yes Yes *T100,*T161,*T185 Yes T463,T464,T98 INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0] Yes Yes T99,T100,T161 Yes T99,T100,T161 INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0] Yes Yes *T203,*T148,*T205 Yes T203,T148,T205 INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__regs_i.d_valid Yes Yes T83,T203,T148 Yes T83,T203,T148 INPUT
tl_sram_ctrl_main__ram_o.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_o.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_sram_ctrl_main__ram_i.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_error Yes Yes T1,T2,T3 Yes T46,T53,T47 INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_sink Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0] Yes Yes T98,T99,T100 Yes T98,T99,T100 INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1] Unreachable Unreachable Unreachable INPUT
tl_sram_ctrl_main__ram_i.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT

*Tests covering at least one bit in the range