Module Definition
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Module : prim_reg_cdc_arb
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.91 96.00 93.02 82.61 100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc_arb.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb 41.67 50.00 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb 90.16 92.00 86.05 82.61 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb 100.00 100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb 100.00 100.00 100.00

Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 )
Line Coverage for Module self-instances :
SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb

SCORELINE
41.67 50.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb

SCORELINE
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN10000
CONT_ASSIGN28311100.00
CONT_ASSIGN28411100.00
CONT_ASSIGN29900


99                        logic dst_update;
100        unreachable    assign dst_update = dst_update_i & (dst_qs_o != dst_ds_i);
101                     
102                       if (DstWrReq) begin : gen_wr_req
103                         logic dst_lat_q;
104                         logic dst_lat_d;
105                         logic dst_update_req;
106                         logic dst_update_ack;
107                         req_sel_e id_q;
108                     
109                         state_e state_q, state_d;
110                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
111                           if (!rst_dst_ni) begin
112                             state_q <= StIdle;
113                           end else begin
114                             state_q <= state_d;
115                           end
116                         end
117                     
118                         logic busy;
119                         logic dst_req_q, dst_req;
120                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
121                           if (!rst_dst_ni) begin
122                             dst_req_q <= '0;
123                           end else if (dst_req_q && dst_lat_d) begin
124                             // if request is held, when the transaction starts,
125                             // automatically clear.
126                             // dst_lat_d is safe to used here because dst_req_q, if set,
127                             // always has priority over other hardware based events.
128                             dst_req_q <= '0;
129                           end else if (dst_req_i && !dst_req_q && busy) begin
130                             // if destination request arrives when a handshake event
131                             // is already ongoing, hold on to request and send later
132                             dst_req_q <= 1'b1;
133                           end
134                         end
135                         assign dst_req = dst_req_q | dst_req_i;
136                     
137                         // Hold data at the beginning of a transaction
138                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
139                           if (!rst_dst_ni) begin
140                             dst_qs_o <= ResetVal;
141                           end else if (dst_lat_d) begin
142                             dst_qs_o <= dst_ds_i;
143                           end else if (dst_lat_q) begin
144                             dst_qs_o <= dst_qs_i;
145                           end
146                         end
147                     
148                         // Which type of transaction is being ack'd back?
149                         // 0 - software initiated request
150                         // 1 - hardware initiated request
151                         // The id information is used by prim_reg_cdc to disambiguate
152                         // simultaneous updates from software and hardware.
153                         // See scenario 2 case 3 for an example of how this is handled.
154                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
155                           if (!rst_dst_ni) begin
156                             id_q <= SelSwReq;
157                           end else if (dst_update_req && dst_update_ack) begin
158                             id_q <= SelSwReq;
159                           end else if (dst_req && dst_lat_d) begin
160                             id_q <= SelSwReq;
161                           end else if (!dst_req && dst_lat_d) begin
162                             id_q <= SelHwReq;
163                           end else if (dst_lat_q) begin
164                             id_q <= SelHwReq;
165                           end
166                         end
167                     
168                         // if a destination update is received when the system is idle and there is no
169                         // software side request, hw update must be selected.
170                         `ASSERT(DstUpdateReqCheck_A, ##1 dst_update & !dst_req & !busy |=> id_q == SelHwReq,
171                           clk_dst_i, !rst_dst_ni)
172                     
173                         // if hw select was chosen, then it must be the case there was a destination update
174                         // indication or there was a difference between the transit register and the
175                         // latest incoming value.
176                         `ASSERT(HwIdSelCheck_A, $rose(id_q == SelHwReq) |-> $past(dst_update_i, 1) ||
177                           $past(dst_lat_q, 1),
178                           clk_dst_i, !rst_dst_ni)
179                     
180                     
181                         // send out prim_subreg request only when proceeding
182                         // with software request
183                         assign dst_req_o = ~busy & dst_req;
184                     
185                         logic dst_hold_req;
186                         always_comb begin
187                           state_d = state_q;
188                           dst_hold_req = '0;
189                     
190                           // depending on when the request is received, we
191                           // may latch d or q.
192                           dst_lat_q = '0;
193                           dst_lat_d = '0;
194                     
195                           busy = 1'b1;
196                     
197                           unique case (state_q)
198                             StIdle: begin
199                               busy = '0;
200                               if (dst_req) begin
201                                 // there's a software issued request for change
202                                 state_d = StWait;
203                                 dst_lat_d = 1'b1;
204                               end else if (dst_update) begin
205                                 state_d = StWait;
206                                 dst_lat_d = 1'b1;
207                               end else if (dst_qs_o != dst_qs_i) begin
208                                 // there's a direct destination update
209                                 // that was blocked by an ongoing transaction
210                                 state_d = StWait;
211                                 dst_lat_q = 1'b1;
212                               end
213                             end
214                     
215                             StWait: begin
216                               dst_hold_req = 1'b1;
217                               if (dst_update_ack) begin
218                                 state_d = StIdle;
219                               end
220                             end
221                     
222                             default: begin
223                               state_d = StIdle;
224                             end
225                           endcase // unique case (state_q)
226                         end // always_comb
227                     
228                         assign dst_update_req = dst_hold_req | dst_lat_d | dst_lat_q;
229                         logic src_req;
230                         prim_sync_reqack u_dst_update_sync (
231                           .clk_src_i(clk_dst_i),
232                           .rst_src_ni(rst_dst_ni),
233                           .clk_dst_i(clk_src_i),
234                           .rst_dst_ni(rst_src_ni),
235                           .req_chk_i(1'b1),
236                           .src_req_i(dst_update_req),
237                           .src_ack_o(dst_update_ack),
238                           .dst_req_o(src_req),
239                           // immediate ack
240                           .dst_ack_i(src_req)
241                         );
242                     
243                         assign src_ack_o = src_req & (id_q == SelSwReq);
244                         assign src_update_o = src_req & (id_q == SelHwReq);
245                     
246                         // once hardware makes an update request, we must eventually see an update pulse
247                         `ifdef FPV_ON
248                           `ASSERT(ReqTimeout_A, $rose(id_q == SelHwReq) |-> s_eventually(src_update_o),
249                                   clk_src_i, !rst_src_ni)
250                           // TODO: #14913 check if we can add additional sim assertions.
251                         `endif
252                     
253                         `ifdef FPV_ON
254                           //VCS coverage off
255                           // pragma coverage off
256                     
257                           logic async_flag;
258                           always_ff @(posedge clk_dst_i or negedge rst_dst_ni or posedge src_update_o) begin
259                             if (!rst_dst_ni) begin
260                               async_flag <= '0;
261                             end else if (src_update_o) begin
262                               async_flag <= '0;
263                             end else if (dst_update && !dst_req_o && !busy) begin
264                               async_flag <= 1'b1;
265                             end
266                           end
267                     
268                           //VCS coverage on
269                           // pragma coverage on
270                     
271                           // once hardware makes an update request, we must eventually see an update pulse
272                           // TODO: #14913 check if we can add additional sim assertions.
273                           `ASSERT(UpdateTimeout_A, $rose(async_flag) |-> s_eventually(src_update_o),
274                                   clk_src_i, !rst_src_ni)
275                         `endif
276                     
277                       end else begin : gen_passthru
278                         // when there is no possibility of conflicting HW transactions,
279                         // we can assume that dst_qs_i will only ever take on the value
280                         // that is directly related to the transaction. As a result,
281                         // there is no need to latch further, and the end destination
282                         // can in fact be used as the holding register.
283        1/1              assign dst_qs_o = dst_qs_i;
           Tests:       T5 T23 T26 
284        1/1              assign dst_req_o = dst_req_i;
           Tests:       T5 T23 T26 
285                     
286                         // since there are no hw transactions, src_update_o is always '0
287                         assign src_update_o = '0;
288                     
289                         prim_pulse_sync u_dst_to_src_ack (
290                           .clk_src_i(clk_dst_i),
291                           .rst_src_ni(rst_dst_ni),
292                           .clk_dst_i(clk_src_i),
293                           .rst_dst_ni(rst_src_ni),
294                           .src_pulse_i(dst_req_i),
295                           .dst_pulse_o(src_ack_o)
296                         );
297                     
298                         logic unused_sigs;
299        unreachable      assign unused_sigs = |{dst_ds_i, dst_update};
Line Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=11,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=9,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 )
Line Coverage for Module self-instances :
SCORELINE
90.16 92.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb

Line No.TotalCoveredPercent
TOTAL504692.00
CONT_ASSIGN10011100.00
ALWAYS11133100.00
ALWAYS12166100.00
CONT_ASSIGN13511100.00
ALWAYS1396583.33
ALWAYS15510990.00
CONT_ASSIGN18311100.00
ALWAYS187191789.47
CONT_ASSIGN22811100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24411100.00


99                        logic dst_update;
100        1/1            assign dst_update = dst_update_i & (dst_qs_o != dst_ds_i);
           Tests:       T5 T23 T26 
101                     
102                       if (DstWrReq) begin : gen_wr_req
103                         logic dst_lat_q;
104                         logic dst_lat_d;
105                         logic dst_update_req;
106                         logic dst_update_ack;
107                         req_sel_e id_q;
108                     
109                         state_e state_q, state_d;
110                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
111        1/1                if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
112        1/1                  state_q <= StIdle;
           Tests:       T1 T2 T3 
113                           end else begin
114        1/1                  state_q <= state_d;
           Tests:       T1 T2 T3 
115                           end
116                         end
117                     
118                         logic busy;
119                         logic dst_req_q, dst_req;
120                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
121        1/1                if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
122        1/1                  dst_req_q <= '0;
           Tests:       T1 T2 T3 
123        1/1                end else if (dst_req_q && dst_lat_d) begin
           Tests:       T1 T2 T3 
124                             // if request is held, when the transaction starts,
125                             // automatically clear.
126                             // dst_lat_d is safe to used here because dst_req_q, if set,
127                             // always has priority over other hardware based events.
128        1/1                  dst_req_q <= '0;
           Tests:       T392 T393 T394 
129        1/1                end else if (dst_req_i && !dst_req_q && busy) begin
           Tests:       T1 T2 T3 
130                             // if destination request arrives when a handshake event
131                             // is already ongoing, hold on to request and send later
132        1/1                  dst_req_q <= 1'b1;
           Tests:       T392 T393 T394 
133                           end
                        MISSING_ELSE
134                         end
135        1/1              assign dst_req = dst_req_q | dst_req_i;
           Tests:       T5 T26 T72 
136                     
137                         // Hold data at the beginning of a transaction
138                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
139        1/1                if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
140        1/1                  dst_qs_o <= ResetVal;
           Tests:       T1 T2 T3 
141        1/1                end else if (dst_lat_d) begin
           Tests:       T1 T2 T3 
142        1/1                  dst_qs_o <= dst_ds_i;
           Tests:       T5 T23 T26 
143        1/1                end else if (dst_lat_q) begin
           Tests:       T1 T2 T3 
144        0/1     ==>          dst_qs_o <= dst_qs_i;
145                           end
                        MISSING_ELSE
146                         end
147                     
148                         // Which type of transaction is being ack'd back?
149                         // 0 - software initiated request
150                         // 1 - hardware initiated request
151                         // The id information is used by prim_reg_cdc to disambiguate
152                         // simultaneous updates from software and hardware.
153                         // See scenario 2 case 3 for an example of how this is handled.
154                         always_ff @(posedge clk_dst_i or negedge rst_dst_ni) begin
155        1/1                if (!rst_dst_ni) begin
           Tests:       T1 T2 T3 
156        1/1                  id_q <= SelSwReq;
           Tests:       T1 T2 T3 
157        1/1                end else if (dst_update_req && dst_update_ack) begin
           Tests:       T1 T2 T3 
158        1/1                  id_q <= SelSwReq;
           Tests:       T5 T23 T26 
159        1/1                end else if (dst_req && dst_lat_d) begin
           Tests:       T1 T2 T3 
160        1/1                  id_q <= SelSwReq;
           Tests:       T5 T72 T73 
161        1/1                end else if (!dst_req && dst_lat_d) begin
           Tests:       T1 T2 T3 
162        1/1                  id_q <= SelHwReq;
           Tests:       T5 T23 T26 
163        1/1                end else if (dst_lat_q) begin
           Tests:       T1 T2 T3 
164        0/1     ==>          id_q <= SelHwReq;
165                           end
                        MISSING_ELSE
166                         end
167                     
168                         // if a destination update is received when the system is idle and there is no
169                         // software side request, hw update must be selected.
170                         `ASSERT(DstUpdateReqCheck_A, ##1 dst_update & !dst_req & !busy |=> id_q == SelHwReq,
171                           clk_dst_i, !rst_dst_ni)
172                     
173                         // if hw select was chosen, then it must be the case there was a destination update
174                         // indication or there was a difference between the transit register and the
175                         // latest incoming value.
176                         `ASSERT(HwIdSelCheck_A, $rose(id_q == SelHwReq) |-> $past(dst_update_i, 1) ||
177                           $past(dst_lat_q, 1),
178                           clk_dst_i, !rst_dst_ni)
179                     
180                     
181                         // send out prim_subreg request only when proceeding
182                         // with software request
183        1/1              assign dst_req_o = ~busy & dst_req;
           Tests:       T5 T23 T26 
184                     
185                         logic dst_hold_req;
186                         always_comb begin
187        1/1                state_d = state_q;
           Tests:       T5 T23 T26 
188        1/1                dst_hold_req = '0;
           Tests:       T5 T23 T26 
189                     
190                           // depending on when the request is received, we
191                           // may latch d or q.
192        1/1                dst_lat_q = '0;
           Tests:       T5 T23 T26 
193        1/1                dst_lat_d = '0;
           Tests:       T5 T23 T26 
194                     
195        1/1                busy = 1'b1;
           Tests:       T5 T23 T26 
196                     
197        1/1                unique case (state_q)
           Tests:       T5 T23 T26 
198                             StIdle: begin
199        1/1                    busy = '0;
           Tests:       T5 T23 T26 
200        1/1                    if (dst_req) begin
           Tests:       T5 T23 T26 
201                                 // there's a software issued request for change
202        1/1                      state_d = StWait;
           Tests:       T5 T26 T72 
203        1/1                      dst_lat_d = 1'b1;
           Tests:       T5 T26 T72 
204        1/1                    end else if (dst_update) begin
           Tests:       T5 T23 T26 
205        1/1                      state_d = StWait;
           Tests:       T5 T23 T26 
206        1/1                      dst_lat_d = 1'b1;
           Tests:       T5 T23 T26 
207        1/1                    end else if (dst_qs_o != dst_qs_i) begin
           Tests:       T5 T23 T26 
208                                 // there's a direct destination update
209                                 // that was blocked by an ongoing transaction
210        0/1     ==>              state_d = StWait;
211        0/1     ==>              dst_lat_q = 1'b1;
212                               end
                        MISSING_ELSE
213                             end
214                     
215                             StWait: begin
216        1/1                    dst_hold_req = 1'b1;
           Tests:       T5 T23 T26 
217        1/1                    if (dst_update_ack) begin
           Tests:       T5 T23 T26 
218        1/1                      state_d = StIdle;
           Tests:       T5 T23 T26 
219                               end
                        MISSING_ELSE
220                             end
221                     
222                             default: begin
223                               state_d = StIdle;
224                             end
225                           endcase // unique case (state_q)
226                         end // always_comb
227                     
228        1/1              assign dst_update_req = dst_hold_req | dst_lat_d | dst_lat_q;
           Tests:       T5 T23 T26 
229                         logic src_req;
230                         prim_sync_reqack u_dst_update_sync (
231                           .clk_src_i(clk_dst_i),
232                           .rst_src_ni(rst_dst_ni),
233                           .clk_dst_i(clk_src_i),
234                           .rst_dst_ni(rst_src_ni),
235                           .req_chk_i(1'b1),
236                           .src_req_i(dst_update_req),
237                           .src_ack_o(dst_update_ack),
238                           .dst_req_o(src_req),
239                           // immediate ack
240                           .dst_ack_i(src_req)
241                         );
242                     
243        1/1              assign src_ack_o = src_req & (id_q == SelSwReq);
           Tests:       T5 T23 T26 
244        1/1              assign src_update_o = src_req & (id_q == SelHwReq);
           Tests:       T5 T23 T26 
Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 )
Cond Coverage for Module self-instances :
SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb

SCORECOND
41.67 33.33
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb

SCORECOND
100.00 100.00
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb

TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01CoveredT5,T23,T26
10Unreachable
11Unreachable 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T23,T26
Cond Coverage for Module : prim_reg_cdc_arb ( parameter DataWidth=11,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal=9,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 )
Cond Coverage for Module self-instances :
SCORECOND
90.16 86.05
tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc.u_arb

TotalCoveredPercent
Conditions433786.05
Logical433786.05
Non-Logical00
Event00

 LINE       100
 EXPRESSION (dst_update_i & (dst_qs_o != dst_ds_i))
             ------1-----   -----------2----------
-1--2-StatusTests
01Not Covered
10CoveredT5,T72,T73
11CoveredT5,T23,T26 

 LINE       100
 SUB-EXPRESSION (dst_qs_o != dst_ds_i)
                -----------1----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T23,T26 

 LINE       123
 EXPRESSION (gen_wr_req.dst_req_q && gen_wr_req.dst_lat_d)
             ----------1---------    ----------2---------
-1--2-StatusTests
01CoveredT5,T23,T26
10CoveredT392,T393,T395
11CoveredT392,T393,T394 

 LINE       129
 EXPRESSION (dst_req_i && ((!gen_wr_req.dst_req_q)) && gen_wr_req.busy)
             ----1----    ------------2------------    -------3-------
-1--2--3-StatusTests
011CoveredT5,T23,T26
101Not Covered
110CoveredT5,T72,T73
111CoveredT392,T393,T394 

 LINE       135
 EXPRESSION (gen_wr_req.dst_req_q | dst_req_i)
             ----------1---------   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT5,T26,T72
10CoveredT392,T393,T394 

 LINE       157
 EXPRESSION (gen_wr_req.dst_update_req && gen_wr_req.dst_update_ack)
             ------------1------------    ------------2------------
-1--2-StatusTests
01Not Covered
10CoveredT5,T23,T26
11CoveredT5,T23,T26 

 LINE       159
 EXPRESSION (gen_wr_req.dst_req && gen_wr_req.dst_lat_d)
             ---------1--------    ----------2---------
-1--2-StatusTests
01CoveredT5,T23,T26
10CoveredT392,T393,T395
11CoveredT5,T72,T73 

 LINE       161
 EXPRESSION (((!gen_wr_req.dst_req)) && gen_wr_req.dst_lat_d)
             -----------1-----------    ----------2---------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT5,T23,T26 

 LINE       183
 EXPRESSION (((~gen_wr_req.busy)) & gen_wr_req.dst_req)
             ----------1---------   ---------2--------
-1--2-StatusTests
01CoveredT392,T393,T394
10CoveredT1,T2,T3
11CoveredT5,T26,T72 

 LINE       207
 EXPRESSION (dst_qs_o != dst_qs_i)
            -----------1----------
-1-StatusTests
0CoveredT5,T23,T26
1Not Covered 

 LINE       228
 EXPRESSION (gen_wr_req.dst_hold_req | gen_wr_req.dst_lat_d | gen_wr_req.dst_lat_q)
             -----------1-----------   ----------2---------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010CoveredT5,T23,T26
100CoveredT5,T23,T26 

 LINE       243
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelSwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT5,T23,T26
11CoveredT5,T72,T73 

 LINE       243
 SUB-EXPRESSION (gen_wr_req.id_q == SelSwReq)
                --------------1--------------
-1-StatusTests
0CoveredT5,T23,T26
1CoveredT1,T2,T3 

 LINE       244
 EXPRESSION (gen_wr_req.src_req & (gen_wr_req.id_q == SelHwReq))
             ---------1--------   --------------2--------------
-1--2-StatusTests
01CoveredT5,T23,T26
10CoveredT5,T72,T73
11CoveredT5,T23,T26 

 LINE       244
 SUB-EXPRESSION (gen_wr_req.id_q == SelHwReq)
                --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT5,T23,T26
Branch Coverage for Module : prim_reg_cdc_arb
Line No.TotalCoveredPercent
Branches 23 19 82.61
IF 111 2 2 100.00
IF 121 4 4 100.00
IF 139 4 3 75.00
IF 155 6 5 83.33
CASE 197 7 5 71.43 



111              if (!rst_dst_ni) begin
                 -1-  
112                state_q <= StIdle;
                   ==>
113              end else begin
114                state_q <= state_d;
                   ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



121              if (!rst_dst_ni) begin
                 -1-  
122                dst_req_q <= '0;
                   ==>
123              end else if (dst_req_q && dst_lat_d) begin
                          -2-  
124                // if request is held, when the transaction starts,
125                // automatically clear.
126                // dst_lat_d is safe to used here because dst_req_q, if set,
127                // always has priority over other hardware based events.
128                dst_req_q <= '0;
                   ==>
129              end else if (dst_req_i && !dst_req_q && busy) begin
                          -3-  
130                // if destination request arrives when a handshake event
131                // is already ongoing, hold on to request and send later
132                dst_req_q <= 1'b1;
                   ==>
133              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T392,T393,T394
0 0 1 Covered T392,T393,T394
0 0 0 Covered T1,T2,T3 



139              if (!rst_dst_ni) begin
                 -1-  
140                dst_qs_o <= ResetVal;
                   ==>
141              end else if (dst_lat_d) begin
                          -2-  
142                dst_qs_o <= dst_ds_i;
                   ==>
143              end else if (dst_lat_q) begin
                          -3-  
144                dst_qs_o <= dst_qs_i;
                   ==>
145              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T5,T23,T26
0 0 1 Not Covered
0 0 0 Covered T1,T2,T3 



155              if (!rst_dst_ni) begin
                 -1-  
156                id_q <= SelSwReq;
                   ==>
157              end else if (dst_update_req && dst_update_ack) begin
                          -2-  
158                id_q <= SelSwReq;
                   ==>
159              end else if (dst_req && dst_lat_d) begin
                          -3-  
160                id_q <= SelSwReq;
                   ==>
161              end else if (!dst_req && dst_lat_d) begin
                          -4-  
162                id_q <= SelHwReq;
                   ==>
163              end else if (dst_lat_q) begin
                          -5-  
164                id_q <= SelHwReq;
                   ==>
165              end
                 MISSING_ELSE
                 ==>

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T5,T23,T26
0 0 1 - - Covered T5,T72,T73
0 0 0 1 - Covered T5,T23,T26
0 0 0 0 1 Not Covered
0 0 0 0 0 Covered T1,T2,T3 



197              unique case (state_q)
                        -1-  
198                StIdle: begin
199                  busy = '0;
200                  if (dst_req) begin
                     -2-  
201                    // there's a software issued request for change
202                    state_d = StWait;
                       ==>
203                    dst_lat_d = 1'b1;
204                  end else if (dst_update) begin
                              -3-  
205                    state_d = StWait;
                       ==>
206                    dst_lat_d = 1'b1;
207                  end else if (dst_qs_o != dst_qs_i) begin
                              -4-  
208                    // there's a direct destination update
209                    // that was blocked by an ongoing transaction
210                    state_d = StWait;
                       ==>
211                    dst_lat_q = 1'b1;
212                  end
                     MISSING_ELSE
                     ==>
213                end
214        
215                StWait: begin
216                  dst_hold_req = 1'b1;
217                  if (dst_update_ack) begin
                     -5-  
218                    state_d = StIdle;
                       ==>
219                  end
                     MISSING_ELSE
                     ==>
220                end
221        
222                default: begin
223                  state_d = StIdle;
                     ==>

Branches:
-1--2--3--4--5-StatusTests
StIdle 1 - - - Covered T5,T26,T72
StIdle 0 1 - - Covered T5,T23,T26
StIdle 0 0 1 - Not Covered
StIdle 0 0 0 - Covered T5,T23,T26
StWait - - - 1 Covered T5,T23,T26
StWait - - - 0 Covered T5,T23,T26
default - - - - Not Covered

Assert Coverage for Module : prim_reg_cdc_arb
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
gen_wr_req.DstUpdateReqCheck_A 1668691 32 0 972
gen_wr_req.HwIdSelCheck_A 1668691 32 0 0


gen_wr_req.DstUpdateReqCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1668691 32 0 972
T5 559 3 0 1
T6 509 0 0 1
T11 438 0 0 1
T23 475 1 0 1
T24 0 1 0 0
T25 408 0 0 1
T26 0 1 0 0
T30 389 0 0 1
T68 713 0 0 1
T71 0 1 0 0
T72 0 1 0 0
T73 0 2 0 0
T74 0 1 0 0
T78 0 3 0 0
T104 382 0 0 1
T105 405 0 0 1
T120 0 1 0 0
T121 458 0 0 1

gen_wr_req.HwIdSelCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1668691 32 0 0
T5 559 3 0 0
T6 509 0 0 0
T11 438 0 0 0
T23 475 1 0 0
T24 0 1 0 0
T25 408 0 0 0
T26 0 1 0 0
T30 389 0 0 0
T68 713 0 0 0
T71 0 1 0 0
T72 0 1 0 0
T73 0 2 0 0
T74 0 1 0 0
T78 0 3 0 0
T104 382 0 0 0
T105 405 0 0 0
T120 0 1 0 0
T121 458 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%