Unified Coverage Report :: Module :: xbar_peri

Module : xbar_peri

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_peri_0.1/rtl/autogen/xbar_peri.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_peri	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_peri

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.94	92.47		89.34			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_peri

	Total	Covered	Percent
Totals	562	562	100.00
Total Bits	7060	7060	100.00
Total Bits 0->1	3530	3530	100.00
Total Bits 1->0	3530	3530	100.00

Ports	562	562	100.00
Port Bits	7060	7060	100.00
Port Bits 0->1	3530	3530	100.00
Port Bits 1->0	3530	3530	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_peri_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_peri_ni	Yes	Yes	T46,T53,T47	Yes	T1,T2,T3	INPUT
tl_main_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	INPUT
tl_main_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_main_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_main_i.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	INPUT
tl_main_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_main_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_error	Yes	Yes	T357,T388,T108	Yes	T357,T388,T108	OUTPUT
tl_main_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_main_o.d_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_main_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_main_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_main_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_main_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.data_intg[6:0]	Yes	Yes	T131,T223,T346	Yes	T131,T223,T346	OUTPUT
tl_uart0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_data[31:0]	Yes	Yes	T131,T223,T346	Yes	T131,T223,T346	OUTPUT
tl_uart0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_uart0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_uart0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart0_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_uart0_o.a_valid	Yes	Yes	T131,T83,T223	Yes	T131,T83,T223	OUTPUT
tl_uart0_i.a_ready	Yes	Yes	T131,T83,T346	Yes	T131,T83,T346	INPUT
tl_uart0_i.d_error	Yes	Yes	T99,T100,T161	Yes	T99,T100,T161	INPUT
tl_uart0_i.d_user.data_intg[6:0]	Yes	Yes	T131,T346,T349	Yes	T131,T346,T349	INPUT
tl_uart0_i.d_user.rsp_intg[6:0]	Yes	Yes	T131,T346,T189	Yes	T131,T83,T346	INPUT
tl_uart0_i.d_data[31:0]	Yes	Yes	T131,T346,T189	Yes	T131,T83,T346	INPUT
tl_uart0_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart0_i.d_source[5:0]	Yes	Yes	*T285,*T286,*T101	Yes	T285,T286,T101	INPUT
tl_uart0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_opcode[0]	Yes	Yes	*T131,*T346,*T349	Yes	T131,T346,T349	INPUT
tl_uart0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart0_i.d_valid	Yes	Yes	T131,T83,T346	Yes	T131,T83,T346	INPUT
tl_uart1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.data_intg[6:0]	Yes	Yes	T32,T346,T13	Yes	T32,T346,T13	OUTPUT
tl_uart1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_data[31:0]	Yes	Yes	T32,T346,T13	Yes	T32,T346,T13	OUTPUT
tl_uart1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_uart1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_uart1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart1_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_uart1_o.a_valid	Yes	Yes	T32,T83,T346	Yes	T32,T83,T346	OUTPUT
tl_uart1_i.a_ready	Yes	Yes	T32,T83,T346	Yes	T32,T83,T346	INPUT
tl_uart1_i.d_error	Yes	Yes	T99,T100,T161	Yes	T99,T100,T161	INPUT
tl_uart1_i.d_user.data_intg[6:0]	Yes	Yes	T32,T346,T13	Yes	T32,T346,T13	INPUT
tl_uart1_i.d_user.rsp_intg[6:0]	Yes	Yes	T32,T346,T189	Yes	T32,T83,T346	INPUT
tl_uart1_i.d_data[31:0]	Yes	Yes	T32,T346,T189	Yes	T32,T83,T346	INPUT
tl_uart1_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart1_i.d_source[5:0]	Yes	Yes	*T101,*T99,*T100	Yes	T101,T98,T99	INPUT
tl_uart1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_opcode[0]	Yes	Yes	*T32,*T346,*T13	Yes	T32,T346,T13	INPUT
tl_uart1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart1_i.d_valid	Yes	Yes	T32,T83,T346	Yes	T32,T83,T346	INPUT
tl_uart2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.data_intg[6:0]	Yes	Yes	T31,T37,T346	Yes	T31,T37,T346	OUTPUT
tl_uart2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_data[31:0]	Yes	Yes	T31,T37,T346	Yes	T31,T37,T346	OUTPUT
tl_uart2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_uart2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_uart2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart2_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_uart2_o.a_valid	Yes	Yes	T31,T37,T83	Yes	T31,T37,T83	OUTPUT
tl_uart2_i.a_ready	Yes	Yes	T31,T37,T83	Yes	T31,T37,T83	INPUT
tl_uart2_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart2_i.d_user.data_intg[6:0]	Yes	Yes	T31,T37,T346	Yes	T31,T37,T346	INPUT
tl_uart2_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T37,T346	Yes	T31,T37,T83	INPUT
tl_uart2_i.d_data[31:0]	Yes	Yes	T31,T37,T346	Yes	T31,T37,T83	INPUT
tl_uart2_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart2_i.d_source[5:0]	Yes	Yes	*T101,*T100,*T161	Yes	T101,T98,T99	INPUT
tl_uart2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_opcode[0]	Yes	Yes	*T31,*T37,*T346	Yes	T31,T37,T346	INPUT
tl_uart2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart2_i.d_valid	Yes	Yes	T31,T37,T83	Yes	T31,T37,T83	INPUT
tl_uart3_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.data_intg[6:0]	Yes	Yes	T29,T72,T73	Yes	T29,T72,T73	OUTPUT
tl_uart3_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_data[31:0]	Yes	Yes	T29,T72,T73	Yes	T29,T72,T73	OUTPUT
tl_uart3_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_uart3_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_uart3_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_uart3_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_uart3_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_uart3_o.a_valid	Yes	Yes	T29,T83,T72	Yes	T29,T83,T72	OUTPUT
tl_uart3_i.a_ready	Yes	Yes	T29,T83,T72	Yes	T29,T83,T72	INPUT
tl_uart3_i.d_error	Yes	Yes	T98,T100,T185	Yes	T98,T100,T161	INPUT
tl_uart3_i.d_user.data_intg[6:0]	Yes	Yes	T29,T72,T73	Yes	T29,T72,T73	INPUT
tl_uart3_i.d_user.rsp_intg[6:0]	Yes	Yes	T29,T72,T73	Yes	T29,T83,T72	INPUT
tl_uart3_i.d_data[31:0]	Yes	Yes	T29,T72,T73	Yes	T29,T83,T72	INPUT
tl_uart3_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_uart3_i.d_source[5:0]	Yes	Yes	*T101,*T98,*T100	Yes	T101,T98,T99	INPUT
tl_uart3_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T100,T185	INPUT
tl_uart3_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_opcode[0]	Yes	Yes	*T29,*T72,*T73	Yes	T29,T72,T73	INPUT
tl_uart3_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_uart3_i.d_valid	Yes	Yes	T29,T83,T72	Yes	T29,T83,T72	INPUT
tl_i2c0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.data_intg[6:0]	Yes	Yes	T68,T315,T344	Yes	T68,T315,T344	OUTPUT
tl_i2c0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_data[31:0]	Yes	Yes	T68,T315,T344	Yes	T68,T315,T344	OUTPUT
tl_i2c0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_i2c0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_i2c0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c0_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_i2c0_o.a_valid	Yes	Yes	T68,T315,T83	Yes	T68,T315,T83	OUTPUT
tl_i2c0_i.a_ready	Yes	Yes	T68,T315,T83	Yes	T68,T315,T83	INPUT
tl_i2c0_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_i2c0_i.d_user.data_intg[6:0]	Yes	Yes	T68,T344,T30	Yes	T68,T344,T30	INPUT
tl_i2c0_i.d_user.rsp_intg[6:0]	Yes	Yes	T68,T315,T189	Yes	T68,T315,T83	INPUT
tl_i2c0_i.d_data[31:0]	Yes	Yes	T68,T315,T189	Yes	T68,T315,T83	INPUT
tl_i2c0_i.d_sink	Yes	Yes	T98,T100,T161	Yes	T98,T100,T161	INPUT
tl_i2c0_i.d_source[5:0]	Yes	Yes	*T30,*T101,*T98	Yes	T30,T101,T98	INPUT
tl_i2c0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_i2c0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_opcode[0]	Yes	Yes	*T68,*T315,*T344	Yes	T68,T315,T344	INPUT
tl_i2c0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c0_i.d_valid	Yes	Yes	T68,T315,T83	Yes	T68,T315,T83	INPUT
tl_i2c1_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.data_intg[6:0]	Yes	Yes	T34,T315,T344	Yes	T34,T315,T344	OUTPUT
tl_i2c1_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_data[31:0]	Yes	Yes	T34,T315,T344	Yes	T34,T315,T344	OUTPUT
tl_i2c1_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_i2c1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_i2c1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c1_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_i2c1_o.a_valid	Yes	Yes	T34,T315,T83	Yes	T34,T315,T83	OUTPUT
tl_i2c1_i.a_ready	Yes	Yes	T34,T315,T83	Yes	T34,T315,T83	INPUT
tl_i2c1_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_i2c1_i.d_user.data_intg[6:0]	Yes	Yes	T34,T344,T30	Yes	T34,T344,T30	INPUT
tl_i2c1_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T315,T189	Yes	T34,T315,T83	INPUT
tl_i2c1_i.d_data[31:0]	Yes	Yes	T34,T315,T189	Yes	T34,T315,T83	INPUT
tl_i2c1_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T99,T100,T185	INPUT
tl_i2c1_i.d_source[5:0]	Yes	Yes	*T30,*T101,*T100	Yes	T30,T101,T98	INPUT
tl_i2c1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_i2c1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_opcode[0]	Yes	Yes	*T34,*T315,*T344	Yes	T34,T315,T344	INPUT
tl_i2c1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c1_i.d_valid	Yes	Yes	T34,T315,T83	Yes	T34,T315,T83	INPUT
tl_i2c2_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.data_intg[6:0]	Yes	Yes	T35,T315,T71	Yes	T35,T315,T71	OUTPUT
tl_i2c2_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_data[31:0]	Yes	Yes	T35,T315,T71	Yes	T35,T315,T71	OUTPUT
tl_i2c2_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_i2c2_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_i2c2_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_i2c2_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_i2c2_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_i2c2_o.a_valid	Yes	Yes	T35,T315,T71	Yes	T35,T315,T71	OUTPUT
tl_i2c2_i.a_ready	Yes	Yes	T35,T315,T71	Yes	T35,T315,T71	INPUT
tl_i2c2_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_i2c2_i.d_user.data_intg[6:0]	Yes	Yes	T35,T71,T344	Yes	T35,T71,T344	INPUT
tl_i2c2_i.d_user.rsp_intg[6:0]	Yes	Yes	T35,T315,T71	Yes	T35,T315,T71	INPUT
tl_i2c2_i.d_data[31:0]	Yes	Yes	T35,T315,T71	Yes	T35,T315,T71	INPUT
tl_i2c2_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_i2c2_i.d_source[5:0]	Yes	Yes	*T30,*T101,*T98	Yes	T30,T101,T98	INPUT
tl_i2c2_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_i2c2_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_opcode[0]	Yes	Yes	*T35,*T315,*T71	Yes	T35,T315,T71	INPUT
tl_i2c2_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_i2c2_i.d_valid	Yes	Yes	T35,T315,T71	Yes	T35,T315,T71	INPUT
tl_pattgen_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.data_intg[6:0]	Yes	Yes	T2,T128,T13	Yes	T2,T128,T13	OUTPUT
tl_pattgen_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_data[31:0]	Yes	Yes	T2,T128,T13	Yes	T2,T128,T13	OUTPUT
tl_pattgen_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pattgen_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_pattgen_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_pattgen_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pattgen_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_pattgen_o.a_valid	Yes	Yes	T2,T83,T128	Yes	T2,T83,T128	OUTPUT
tl_pattgen_i.a_ready	Yes	Yes	T2,T83,T128	Yes	T2,T83,T128	INPUT
tl_pattgen_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_pattgen_i.d_user.data_intg[6:0]	Yes	Yes	T2,T128,T13	Yes	T2,T128,T13	INPUT
tl_pattgen_i.d_user.rsp_intg[6:0]	Yes	Yes	T2,T128,T13	Yes	T2,T83,T128	INPUT
tl_pattgen_i.d_data[31:0]	Yes	Yes	T2,T128,T13	Yes	T2,T83,T128	INPUT
tl_pattgen_i.d_sink	Yes	Yes	T98,T100,T185	Yes	T98,T100,T161	INPUT
tl_pattgen_i.d_source[5:0]	Yes	Yes	*T74,*T98,*T99	Yes	T74,T98,T100	INPUT
tl_pattgen_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T99,T100	INPUT
tl_pattgen_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_opcode[0]	Yes	Yes	*T2,*T128,*T13	Yes	T2,T128,T13	INPUT
tl_pattgen_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pattgen_i.d_valid	Yes	Yes	T2,T83,T128	Yes	T2,T83,T128	INPUT
tl_pwm_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.data_intg[6:0]	Yes	Yes	T43,T77,T136	Yes	T43,T77,T136	OUTPUT
tl_pwm_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_data[31:0]	Yes	Yes	T43,T77,T136	Yes	T43,T77,T136	OUTPUT
tl_pwm_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwm_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_pwm_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_pwm_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwm_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_pwm_aon_o.a_valid	Yes	Yes	T43,T83,T77	Yes	T43,T83,T77	OUTPUT
tl_pwm_aon_i.a_ready	Yes	Yes	T43,T83,T77	Yes	T43,T83,T77	INPUT
tl_pwm_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pwm_aon_i.d_user.data_intg[6:0]	Yes	Yes	T43,T77,T136	Yes	T43,T77,T136	INPUT
tl_pwm_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T43,T77,T136	Yes	T43,T83,T77	INPUT
tl_pwm_aon_i.d_data[31:0]	Yes	Yes	T43,T77,T136	Yes	T43,T83,T77	INPUT
tl_pwm_aon_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pwm_aon_i.d_source[5:0]	Yes	Yes	*T99,*T100,*T161	Yes	T98,T99,T100	INPUT
tl_pwm_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pwm_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_opcode[0]	Yes	Yes	*T43,*T77,*T136	Yes	T43,T77,T136	INPUT
tl_pwm_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwm_aon_i.d_valid	Yes	Yes	T43,T83,T77	Yes	T43,T83,T77	INPUT
tl_gpio_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_gpio_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_gpio_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_gpio_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_gpio_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_gpio_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_gpio_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_gpio_i.d_user.data_intg[6:0]	Yes	Yes	T6,T28,T344	Yes	T6,T28,T344	INPUT
tl_gpio_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T28,T344	Yes	T6,T27,T28	INPUT
tl_gpio_i.d_data[31:0]	Yes	Yes	T6,T28,T344	Yes	T6,T27,T28	INPUT
tl_gpio_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_gpio_i.d_source[5:0]	Yes	Yes	*T30,*T101,*T99	Yes	T30,T101,T98	INPUT
tl_gpio_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_gpio_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_opcode[0]	Yes	Yes	*T6,*T27,*T28	Yes	T2,T3,T4	INPUT
tl_gpio_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_gpio_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_spi_device_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.data_intg[6:0]	Yes	Yes	T6,T14,T11	Yes	T6,T14,T11	OUTPUT
tl_spi_device_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_data[31:0]	Yes	Yes	T6,T14,T11	Yes	T6,T14,T11	OUTPUT
tl_spi_device_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_spi_device_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_spi_device_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_spi_device_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_device_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_spi_device_o.a_valid	Yes	Yes	T6,T14,T11	Yes	T6,T14,T11	OUTPUT
tl_spi_device_i.a_ready	Yes	Yes	T6,T14,T11	Yes	T6,T14,T11	INPUT
tl_spi_device_i.d_error	Yes	Yes	T98,T99,T100	Yes	T99,T100,T161	INPUT
tl_spi_device_i.d_user.data_intg[6:0]	Yes	Yes	T14,T11,T12	Yes	T14,T11,T12	INPUT
tl_spi_device_i.d_user.rsp_intg[6:0]	Yes	Yes	T6,T14,T11	Yes	T6,T14,T11	INPUT
tl_spi_device_i.d_data[31:0]	Yes	Yes	T6,T14,T11	Yes	T14,T11,T12	INPUT
tl_spi_device_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_spi_device_i.d_source[5:0]	Yes	Yes	*T100,*T161,*T185	Yes	T98,T99,T100	INPUT
tl_spi_device_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_size[1:0]	Yes	Yes	T100,T161,T185	Yes	T100,T185,T236	INPUT
tl_spi_device_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_opcode[0]	Yes	Yes	*T6,*T14,*T11	Yes	T6,T14,T11	INPUT
tl_spi_device_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_device_i.d_valid	Yes	Yes	T6,T14,T11	Yes	T6,T14,T11	INPUT
tl_rv_timer_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.data_intg[6:0]	Yes	Yes	T127,T268,T265	Yes	T127,T268,T265	OUTPUT
tl_rv_timer_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_data[31:0]	Yes	Yes	T127,T268,T265	Yes	T127,T268,T265	OUTPUT
tl_rv_timer_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_timer_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_rv_timer_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_rv_timer_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_timer_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_rv_timer_o.a_valid	Yes	Yes	T127,T268,T83	Yes	T127,T268,T83	OUTPUT
tl_rv_timer_i.a_ready	Yes	Yes	T127,T268,T83	Yes	T127,T268,T83	INPUT
tl_rv_timer_i.d_error	Yes	Yes	T98,T100,T185	Yes	T98,T100,T185	INPUT
tl_rv_timer_i.d_user.data_intg[6:0]	Yes	Yes	T127,T268,T265	Yes	T127,T268,T265	INPUT
tl_rv_timer_i.d_user.rsp_intg[6:0]	Yes	Yes	T127,T268,T265	Yes	T127,T268,T83	INPUT
tl_rv_timer_i.d_data[31:0]	Yes	Yes	T127,T268,T265	Yes	T127,T268,T83	INPUT
tl_rv_timer_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_rv_timer_i.d_source[5:0]	Yes	Yes	*T100,*T185,*T236	Yes	T98,T100,T161	INPUT
tl_rv_timer_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_rv_timer_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_opcode[0]	Yes	Yes	*T127,*T268,*T265	Yes	T127,T268,T265	INPUT
tl_rv_timer_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_timer_i.d_valid	Yes	Yes	T127,T268,T83	Yes	T127,T268,T83	INPUT
tl_pwrmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	OUTPUT
tl_pwrmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_data[31:0]	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	OUTPUT
tl_pwrmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pwrmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_pwrmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_pwrmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pwrmgr_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_pwrmgr_aon_o.a_valid	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	OUTPUT
tl_pwrmgr_aon_i.a_ready	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	INPUT
tl_pwrmgr_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pwrmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	INPUT
tl_pwrmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	INPUT
tl_pwrmgr_aon_i.d_data[31:0]	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	INPUT
tl_pwrmgr_aon_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pwrmgr_aon_i.d_source[5:0]	Yes	Yes	*T100,*T185,*T236	Yes	T98,T100,T161	INPUT
tl_pwrmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T100,T161	INPUT
tl_pwrmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_opcode[0]	Yes	Yes	*T5,*T6,*T27	Yes	T5,T6,T27	INPUT
tl_pwrmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pwrmgr_aon_i.d_valid	Yes	Yes	T5,T6,T27	Yes	T5,T6,T27	INPUT
tl_rstmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rstmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_rstmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_rstmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rstmgr_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_rstmgr_aon_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_rstmgr_aon_i.a_ready	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_rstmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T53,T47	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_data[31:0]	Yes	Yes	T46,T53,T47	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_rstmgr_aon_i.d_source[5:0]	Yes	Yes	*T99,*T100,*T185	Yes	T98,T99,T100	INPUT
tl_rstmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T99,T100,T185	INPUT
tl_rstmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_rstmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rstmgr_aon_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_clkmgr_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.data_intg[6:0]	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	OUTPUT
tl_clkmgr_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_data[31:0]	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	OUTPUT
tl_clkmgr_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_clkmgr_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_clkmgr_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_clkmgr_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_clkmgr_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_clkmgr_aon_o.a_valid	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	OUTPUT
tl_clkmgr_aon_i.a_ready	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	INPUT
tl_clkmgr_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_clkmgr_aon_i.d_user.data_intg[6:0]	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	INPUT
tl_clkmgr_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	INPUT
tl_clkmgr_aon_i.d_data[31:0]	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	INPUT
tl_clkmgr_aon_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_clkmgr_aon_i.d_source[5:0]	Yes	Yes	*T98,*T99,*T100	Yes	T182,T183,T670	INPUT
tl_clkmgr_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_clkmgr_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_opcode[0]	Yes	Yes	*T31,*T29,*T131	Yes	T31,T29,T131	INPUT
tl_clkmgr_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_clkmgr_aon_i.d_valid	Yes	Yes	T31,T29,T131	Yes	T31,T29,T131	INPUT
tl_pinmux_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_pinmux_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_pinmux_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_pinmux_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_pinmux_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_pinmux_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pinmux_aon_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pinmux_aon_i.d_source[5:0]	Yes	Yes	*T74,*T98,*T99	Yes	T74,T98,T99	INPUT
tl_pinmux_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_pinmux_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_pinmux_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_pinmux_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_otp_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_otp_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_otp_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_otp_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__core_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_otp_ctrl__core_i.d_source[5:0]	Yes	Yes	*T182,*T183,*T74	Yes	T182,T183,T74	INPUT
tl_otp_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_otp_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_opcode[0]	Yes	Yes	*T122,*T44,*T184	Yes	T122,T184,T46	INPUT
tl_otp_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T74,T98,T99	Yes	T74,T98,T99	OUTPUT
tl_otp_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_data[31:0]	Yes	Yes	T74,T98,T99	Yes	T74,T98,T99	OUTPUT
tl_otp_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_otp_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_otp_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_otp_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otp_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_otp_ctrl__prim_o.a_valid	Yes	Yes	T74,T98,T99	Yes	T74,T98,T99	OUTPUT
tl_otp_ctrl__prim_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_otp_ctrl__prim_i.d_error	Yes	Yes	T1,T2,T3	Yes	T53,T47,T88	INPUT
tl_otp_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T74,T98,T99	Yes	T74,T98,T99	INPUT
tl_otp_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T74,T98,T99	Yes	T74,T98,T99	INPUT
tl_otp_ctrl__prim_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T53,T47,T88	INPUT
tl_otp_ctrl__prim_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_otp_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T74,T100,T185	Yes	T74,T98,T99	INPUT
tl_otp_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_otp_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T53,T47,T88	INPUT
tl_otp_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otp_ctrl__prim_i.d_valid	Yes	Yes	T74,T98,T99	Yes	T74,T98,T99	INPUT
tl_lc_ctrl_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.data_intg[6:0]	Yes	Yes	T121,T122,T46	Yes	T121,T122,T46	OUTPUT
tl_lc_ctrl_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_data[31:0]	Yes	Yes	T121,T122,T46	Yes	T121,T122,T46	OUTPUT
tl_lc_ctrl_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_lc_ctrl_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_lc_ctrl_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_lc_ctrl_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_lc_ctrl_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_lc_ctrl_o.a_valid	Yes	Yes	T121,T122,T46	Yes	T121,T122,T46	OUTPUT
tl_lc_ctrl_i.a_ready	Yes	Yes	T121,T122,T46	Yes	T121,T122,T46	INPUT
tl_lc_ctrl_i.d_error	Yes	Yes	T98,T100,T185	Yes	T98,T99,T100	INPUT
tl_lc_ctrl_i.d_user.data_intg[6:0]	Yes	Yes	T122,T46,T47	Yes	T121,T122,T46	INPUT
tl_lc_ctrl_i.d_user.rsp_intg[6:0]	Yes	Yes	T47,T193,T214	Yes	T47,T83,T193	INPUT
tl_lc_ctrl_i.d_data[31:0]	Yes	Yes	T122,T46,T47	Yes	T121,T122,T46	INPUT
tl_lc_ctrl_i.d_sink	Yes	Yes	T98,T100,T185	Yes	T98,T100,T185	INPUT
tl_lc_ctrl_i.d_source[5:0]	Yes	Yes	*T94,*T263,*T264	Yes	T94,T263,T264	INPUT
tl_lc_ctrl_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_size[1:0]	Yes	Yes	T98,T100,T185	Yes	T98,T100,T185	INPUT
tl_lc_ctrl_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_opcode[0]	Yes	Yes	*T46,*T47,*T196	Yes	T121,T122,T46	INPUT
tl_lc_ctrl_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_lc_ctrl_i.d_valid	Yes	Yes	T121,T122,T46	Yes	T121,T122,T46	INPUT
tl_sensor_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_sensor_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_sensor_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sensor_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_sensor_ctrl_aon_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sensor_ctrl_aon_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_sensor_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T177,T163,T164	Yes	T177,T163,T164	INPUT
tl_sensor_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T177,T163,T164	Yes	T83,T177,T163	INPUT
tl_sensor_ctrl_aon_i.d_data[31:0]	Yes	Yes	T46,T53,T47	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_sensor_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T100,*T161,*T185	Yes	T98,T99,T100	INPUT
tl_sensor_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_sensor_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T46,*T53,*T47	Yes	T1,T2,T3	INPUT
tl_sensor_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sensor_ctrl_aon_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_alert_handler_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.data_intg[6:0]	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	OUTPUT
tl_alert_handler_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_data[31:0]	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	OUTPUT
tl_alert_handler_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_alert_handler_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_alert_handler_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_alert_handler_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_alert_handler_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_alert_handler_o.a_valid	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	OUTPUT
tl_alert_handler_i.a_ready	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	INPUT
tl_alert_handler_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_alert_handler_i.d_user.data_intg[6:0]	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	INPUT
tl_alert_handler_i.d_user.rsp_intg[6:0]	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	INPUT
tl_alert_handler_i.d_data[31:0]	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	INPUT
tl_alert_handler_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_alert_handler_i.d_source[5:0]	Yes	Yes	*T100,*T161,*T185	Yes	T98,T99,T100	INPUT
tl_alert_handler_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_alert_handler_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_opcode[0]	Yes	Yes	*T53,*T88,*T89	Yes	T53,T88,T89	INPUT
tl_alert_handler_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_alert_handler_i.d_valid	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	INPUT
tl_sram_ctrl_ret_aon__regs_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.data_intg[6:0]	Yes	Yes	T203,T148,T204	Yes	T203,T148,T204	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_data[31:0]	Yes	Yes	T203,T148,T204	Yes	T203,T148,T204	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_sram_ctrl_ret_aon__regs_o.a_valid	Yes	Yes	T83,T203,T148	Yes	T83,T203,T148	OUTPUT
tl_sram_ctrl_ret_aon__regs_i.a_ready	Yes	Yes	T83,T203,T148	Yes	T83,T203,T148	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.data_intg[6:0]	Yes	Yes	T203,T148,T204	Yes	T203,T148,T204	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T203,T148,T204	Yes	T83,T203,T148	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_data[31:0]	Yes	Yes	T203,T148,T204	Yes	T83,T203,T148	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[5:0]	Yes	Yes	*T100,*T161,*T185	Yes	T98,T99,T100	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T99,T100	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[0]	Yes	Yes	*T203,*T148,*T204	Yes	T203,T148,T204	INPUT
tl_sram_ctrl_ret_aon__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__regs_i.d_valid	Yes	Yes	T83,T203,T148	Yes	T83,T203,T148	INPUT
tl_sram_ctrl_ret_aon__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.data_intg[6:0]	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_data[31:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_sram_ctrl_ret_aon__ram_o.a_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
tl_sram_ctrl_ret_aon__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T46,T53,T47	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.data_intg[6:0]	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T267,T46,T53	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_data[31:0]	Yes	Yes	T53,T88,T89	Yes	T53,T88,T89	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_sink	Yes	Yes	T98,T100,T161	Yes	T98,T100,T185	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[5:0]	Yes	Yes	*T45,*T230,*T231	Yes	T45,T230,T231	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T100,T185	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[0]	Yes	Yes	*T2,*T3,*T4	Yes	T2,T3,T4	INPUT
tl_sram_ctrl_ret_aon__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_ret_aon__ram_i.d_valid	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
tl_aon_timer_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.data_intg[6:0]	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	OUTPUT
tl_aon_timer_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_data[31:0]	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	OUTPUT
tl_aon_timer_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_aon_timer_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_aon_timer_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_aon_timer_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aon_timer_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_aon_timer_aon_o.a_valid	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	OUTPUT
tl_aon_timer_aon_i.a_ready	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	INPUT
tl_aon_timer_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_aon_timer_aon_i.d_user.data_intg[6:0]	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	INPUT
tl_aon_timer_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	INPUT
tl_aon_timer_aon_i.d_data[31:0]	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	INPUT
tl_aon_timer_aon_i.d_sink	Yes	Yes	T98,T100,T185	Yes	T98,T99,T100	INPUT
tl_aon_timer_aon_i.d_source[5:0]	Yes	Yes	*T98,*T100,*T185	Yes	T63,T285,T464	INPUT
tl_aon_timer_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_aon_timer_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_opcode[0]	Yes	Yes	*T267,*T53,*T88	Yes	T267,T53,T88	INPUT
tl_aon_timer_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aon_timer_aon_i.d_valid	Yes	Yes	T267,T53,T88	Yes	T267,T53,T88	INPUT
tl_sysrst_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T33,T15,T18	Yes	T33,T15,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_data[31:0]	Yes	Yes	T33,T15,T18	Yes	T33,T15,T18	OUTPUT
tl_sysrst_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sysrst_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_sysrst_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_sysrst_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sysrst_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_sysrst_ctrl_aon_o.a_valid	Yes	Yes	T33,T15,T18	Yes	T33,T15,T18	OUTPUT
tl_sysrst_ctrl_aon_i.a_ready	Yes	Yes	T33,T15,T18	Yes	T33,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T100,T161	INPUT
tl_sysrst_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T33,T15,T18	Yes	T33,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T15,T18,T76	Yes	T15,T18,T83	INPUT
tl_sysrst_ctrl_aon_i.d_data[31:0]	Yes	Yes	T33,T15,T18	Yes	T33,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_sink	Yes	Yes	T98,T100,T161	Yes	T98,T100,T161	INPUT
tl_sysrst_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T101,*T98,*T100	Yes	T101,T98,T99	INPUT
tl_sysrst_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T100,T161	INPUT
tl_sysrst_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T15,*T18,*T76	Yes	T33,T15,T18	INPUT
tl_sysrst_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sysrst_ctrl_aon_i.d_valid	Yes	Yes	T33,T15,T18	Yes	T33,T15,T18	INPUT
tl_adc_ctrl_aon_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.data_intg[6:0]	Yes	Yes	T138,T344,T80	Yes	T138,T344,T80	OUTPUT
tl_adc_ctrl_aon_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_data[31:0]	Yes	Yes	T138,T344,T80	Yes	T138,T344,T80	OUTPUT
tl_adc_ctrl_aon_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_adc_ctrl_aon_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_adc_ctrl_aon_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_adc_ctrl_aon_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_adc_ctrl_aon_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_adc_ctrl_aon_o.a_valid	Yes	Yes	T138,T83,T344	Yes	T138,T83,T344	OUTPUT
tl_adc_ctrl_aon_i.a_ready	Yes	Yes	T138,T83,T344	Yes	T138,T83,T344	INPUT
tl_adc_ctrl_aon_i.d_error	Yes	Yes	T98,T99,T100	Yes	T99,T100,T161	INPUT
tl_adc_ctrl_aon_i.d_user.data_intg[6:0]	Yes	Yes	T138,T344,T80	Yes	T138,T344,T80	INPUT
tl_adc_ctrl_aon_i.d_user.rsp_intg[6:0]	Yes	Yes	T138,T344,T80	Yes	T138,T83,T344	INPUT
tl_adc_ctrl_aon_i.d_data[31:0]	Yes	Yes	T138,T80,T93	Yes	T138,T83,T344	INPUT
tl_adc_ctrl_aon_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_adc_ctrl_aon_i.d_source[5:0]	Yes	Yes	*T100,*T161,*T185	Yes	T98,T99,T100	INPUT
tl_adc_ctrl_aon_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T100,T161	INPUT
tl_adc_ctrl_aon_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_opcode[0]	Yes	Yes	*T138,*T344,*T80	Yes	T138,T344,T80	INPUT
tl_adc_ctrl_aon_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_adc_ctrl_aon_i.d_valid	Yes	Yes	T138,T83,T344	Yes	T138,T83,T344	INPUT
tl_ast_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_source[5:0]	Yes	Yes	*T94,*T30,*T45	Yes	T94,T30,T45	OUTPUT
tl_ast_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_size[1:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	OUTPUT
tl_ast_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_ast_o.a_opcode[2:0]	Yes	Yes	T30,T45,T101	Yes	T30,T45,T101	OUTPUT
tl_ast_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_ast_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_ast_i.d_error	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_ast_i.d_user.data_intg[6:0]	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_ast_i.d_user.rsp_intg[6:0]	Yes	Yes	T46,T53,T47	Yes	T1,T2,T3	INPUT
tl_ast_i.d_data[31:0]	Yes	Yes	T46,T53,T47	Yes	T1,T2,T3	INPUT
tl_ast_i.d_sink	Yes	Yes	T98,T99,T100	Yes	T98,T99,T100	INPUT
tl_ast_i.d_source[5:0]	Yes	Yes	*T98,*T99,*T100	Yes	T98,T99,T100	INPUT
tl_ast_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_size[1:0]	Yes	Yes	T98,T100,T161	Yes	T98,T99,T100	INPUT
tl_ast_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_opcode[0]	Yes	Yes	*T98,*T100,*T161	Yes	T98,T99,T100	INPUT
tl_ast_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_ast_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range