Unified Coverage Report :: Module

Module : rv_plic_target

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/chip_earlgrey_asic-sim-vcs/default/sim-vcs/../src/lowrisc_ip_rv_plic_component_0.1/rtl/rv_plic_target.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target	100.00	100.00	100.00			100.00

Module Instance : tb.dut.top_earlgrey.u_rv_plic.gen_target[0].u_target

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	89.34	77.21			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.30	99.83	66.67	100.00		100.00	90.00	u_rv_plic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_max_tree	91.61	89.27	77.18			100.00	100.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rv_plic_target

	Line No.	Total	Covered	Percent
TOTAL		9	9	100.00
CONT_ASSIGN	58	1	1	100.00
CONT_ASSIGN	59	1	1	100.00
ALWAYS	62	5	5	100.00
CONT_ASSIGN	71	1	1	100.00
CONT_ASSIGN	72	1	1	100.00



57                      
58         1/1            assign irq_d    = (max_value > threshold_i) ? max_valid : 1'b0;
           Tests:       T2 T3 T5 
59         1/1            assign irq_id_d = (max_valid) ? max_idx : '0;
           Tests:       T2 T3 T5 
60                      
61                        always_ff @(posedge clk_i or negedge rst_ni) begin : gen_regs
62         1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
63         1/1                irq_q    <= 1'b0;
           Tests:       T1 T2 T3 
64         1/1                irq_id_q <= '0;
           Tests:       T1 T2 T3 
65                          end else begin
66         1/1                irq_q    <= irq_d;
           Tests:       T1 T2 T3 
67         1/1                irq_id_q <= irq_id_d;
           Tests:       T1 T2 T3 
68                          end
69                        end
70                      
71         1/1            assign irq_o    = irq_q;
           Tests:       T2 T3 T5 
72         1/1            assign irq_id_o = irq_id_q;
           Tests:       T2 T3 T5

Cond Coverage for Module : rv_plic_target

	Total	Covered	Percent
Conditions	4	4	100.00
Logical	4	4	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION ((max_value > threshold_i) ? max_valid : 1'b0)
             ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

 LINE       59
 EXPRESSION (max_valid ? max_idx : '0)
             ----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T5

Branch Coverage for Module : rv_plic_target

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	58	2	2	100.00
TERNARY	59	2	2	100.00
IF	62	2	2	100.00



58           assign irq_d    = (max_value > threshold_i) ? max_valid : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3



59           assign irq_id_d = (max_valid) ? max_idx : '0;
                                           -1-  
                                           ==>  
                                           ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T5
0	Covered	T1,T2,T3



62             if (!rst_ni) begin
               -1-  
63               irq_q    <= 1'b0;
                 ==>
64               irq_id_q <= '0;
65             end else begin
66               irq_q    <= irq_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3