Line Coverage for Module :
chip_earlgrey_asic
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 25 | 20 | 80.00 |
| CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 857 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 870 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 899 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 907 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 914 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 917 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 925 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 929 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 932 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1097 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1098 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1099 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1107 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1124 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1127 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1134 | 1 | 1 | 100.00 |
281 logic unused_dio_in_raw;
282 1/1 assign unused_mio_in_raw = ^mio_in_raw;
Tests: T1 T2 T3
283 1/1 assign unused_dio_in_raw = ^dio_in_raw;
Tests: T1 T2 T3
284
285 // Manual pads
286 logic manual_in_por_n, manual_out_por_n, manual_oe_por_n;
287 logic manual_in_usb_p, manual_out_usb_p, manual_oe_usb_p;
288 logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n;
289 logic manual_in_cc1, manual_out_cc1, manual_oe_cc1;
290 logic manual_in_cc2, manual_out_cc2, manual_oe_cc2;
291 logic manual_in_flash_test_volt, manual_out_flash_test_volt, manual_oe_flash_test_volt;
292 logic manual_in_flash_test_mode0, manual_out_flash_test_mode0, manual_oe_flash_test_mode0;
293 logic manual_in_flash_test_mode1, manual_out_flash_test_mode1, manual_oe_flash_test_mode1;
294 logic manual_in_otp_ext_volt, manual_out_otp_ext_volt, manual_oe_otp_ext_volt;
295
296 pad_attr_t manual_attr_por_n;
297 pad_attr_t manual_attr_usb_p;
298 pad_attr_t manual_attr_usb_n;
299 pad_attr_t manual_attr_cc1;
300 pad_attr_t manual_attr_cc2;
301 pad_attr_t manual_attr_flash_test_volt;
302 pad_attr_t manual_attr_flash_test_mode0;
303 pad_attr_t manual_attr_flash_test_mode1;
304 pad_attr_t manual_attr_otp_ext_volt;
305
306
307 //////////////////////
308 // Padring Instance //
309 //////////////////////
310
311 ast_pkg::ast_clks_t ast_base_clks;
312
313 // AST signals needed in padring
314 logic scan_rst_n;
315 prim_mubi_pkg::mubi4_t scanmode;
316
317 padring #(
318 // Padring specific counts may differ from pinmux config due
319 // to custom, stubbed or added pads.
320 .NDioPads(23),
321 .NMioPads(47),
322 .PhysicalPads(1),
323 .NIoBanks(int'(IoBankCount)),
324 .DioScanRole ({
325 scan_role_pkg::DioPadIor9ScanRole,
326 scan_role_pkg::DioPadIor8ScanRole,
327 scan_role_pkg::DioPadSpiDevCsLScanRole,
328 scan_role_pkg::DioPadSpiDevClkScanRole,
329 scan_role_pkg::DioPadSpiDevD3ScanRole,
330 scan_role_pkg::DioPadSpiDevD2ScanRole,
331 scan_role_pkg::DioPadSpiDevD1ScanRole,
332 scan_role_pkg::DioPadSpiDevD0ScanRole,
333 scan_role_pkg::DioPadSpiHostCsLScanRole,
334 scan_role_pkg::DioPadSpiHostClkScanRole,
335 scan_role_pkg::DioPadSpiHostD3ScanRole,
336 scan_role_pkg::DioPadSpiHostD2ScanRole,
337 scan_role_pkg::DioPadSpiHostD1ScanRole,
338 scan_role_pkg::DioPadSpiHostD0ScanRole,
339 scan_role_pkg::DioPadOtpExtVoltScanRole,
340 scan_role_pkg::DioPadFlashTestMode1ScanRole,
341 scan_role_pkg::DioPadFlashTestMode0ScanRole,
342 scan_role_pkg::DioPadFlashTestVoltScanRole,
343 scan_role_pkg::DioPadCc2ScanRole,
344 scan_role_pkg::DioPadCc1ScanRole,
345 scan_role_pkg::DioPadUsbNScanRole,
346 scan_role_pkg::DioPadUsbPScanRole,
347 scan_role_pkg::DioPadPorNScanRole
348 }),
349 .MioScanRole ({
350 scan_role_pkg::MioPadIor13ScanRole,
351 scan_role_pkg::MioPadIor12ScanRole,
352 scan_role_pkg::MioPadIor11ScanRole,
353 scan_role_pkg::MioPadIor10ScanRole,
354 scan_role_pkg::MioPadIor7ScanRole,
355 scan_role_pkg::MioPadIor6ScanRole,
356 scan_role_pkg::MioPadIor5ScanRole,
357 scan_role_pkg::MioPadIor4ScanRole,
358 scan_role_pkg::MioPadIor3ScanRole,
359 scan_role_pkg::MioPadIor2ScanRole,
360 scan_role_pkg::MioPadIor1ScanRole,
361 scan_role_pkg::MioPadIor0ScanRole,
362 scan_role_pkg::MioPadIoc12ScanRole,
363 scan_role_pkg::MioPadIoc11ScanRole,
364 scan_role_pkg::MioPadIoc10ScanRole,
365 scan_role_pkg::MioPadIoc9ScanRole,
366 scan_role_pkg::MioPadIoc8ScanRole,
367 scan_role_pkg::MioPadIoc7ScanRole,
368 scan_role_pkg::MioPadIoc6ScanRole,
369 scan_role_pkg::MioPadIoc5ScanRole,
370 scan_role_pkg::MioPadIoc4ScanRole,
371 scan_role_pkg::MioPadIoc3ScanRole,
372 scan_role_pkg::MioPadIoc2ScanRole,
373 scan_role_pkg::MioPadIoc1ScanRole,
374 scan_role_pkg::MioPadIoc0ScanRole,
375 scan_role_pkg::MioPadIob12ScanRole,
376 scan_role_pkg::MioPadIob11ScanRole,
377 scan_role_pkg::MioPadIob10ScanRole,
378 scan_role_pkg::MioPadIob9ScanRole,
379 scan_role_pkg::MioPadIob8ScanRole,
380 scan_role_pkg::MioPadIob7ScanRole,
381 scan_role_pkg::MioPadIob6ScanRole,
382 scan_role_pkg::MioPadIob5ScanRole,
383 scan_role_pkg::MioPadIob4ScanRole,
384 scan_role_pkg::MioPadIob3ScanRole,
385 scan_role_pkg::MioPadIob2ScanRole,
386 scan_role_pkg::MioPadIob1ScanRole,
387 scan_role_pkg::MioPadIob0ScanRole,
388 scan_role_pkg::MioPadIoa8ScanRole,
389 scan_role_pkg::MioPadIoa7ScanRole,
390 scan_role_pkg::MioPadIoa6ScanRole,
391 scan_role_pkg::MioPadIoa5ScanRole,
392 scan_role_pkg::MioPadIoa4ScanRole,
393 scan_role_pkg::MioPadIoa3ScanRole,
394 scan_role_pkg::MioPadIoa2ScanRole,
395 scan_role_pkg::MioPadIoa1ScanRole,
396 scan_role_pkg::MioPadIoa0ScanRole
397 }),
398 .DioPadBank ({
399 IoBankVcc, // IOR9
400 IoBankVcc, // IOR8
401 IoBankVioa, // SPI_DEV_CS_L
402 IoBankVioa, // SPI_DEV_CLK
403 IoBankVioa, // SPI_DEV_D3
404 IoBankVioa, // SPI_DEV_D2
405 IoBankVioa, // SPI_DEV_D1
406 IoBankVioa, // SPI_DEV_D0
407 IoBankVioa, // SPI_HOST_CS_L
408 IoBankVioa, // SPI_HOST_CLK
409 IoBankVioa, // SPI_HOST_D3
410 IoBankVioa, // SPI_HOST_D2
411 IoBankVioa, // SPI_HOST_D1
412 IoBankVioa, // SPI_HOST_D0
413 IoBankVcc, // OTP_EXT_VOLT
414 IoBankVcc, // FLASH_TEST_MODE1
415 IoBankVcc, // FLASH_TEST_MODE0
416 IoBankVcc, // FLASH_TEST_VOLT
417 IoBankAvcc, // CC2
418 IoBankAvcc, // CC1
419 IoBankVcc, // USB_N
420 IoBankVcc, // USB_P
421 IoBankVcc // POR_N
422 }),
423 .MioPadBank ({
424 IoBankVcc, // IOR13
425 IoBankVcc, // IOR12
426 IoBankVcc, // IOR11
427 IoBankVcc, // IOR10
428 IoBankVcc, // IOR7
429 IoBankVcc, // IOR6
430 IoBankVcc, // IOR5
431 IoBankVcc, // IOR4
432 IoBankVcc, // IOR3
433 IoBankVcc, // IOR2
434 IoBankVcc, // IOR1
435 IoBankVcc, // IOR0
436 IoBankVcc, // IOC12
437 IoBankVcc, // IOC11
438 IoBankVcc, // IOC10
439 IoBankVcc, // IOC9
440 IoBankVcc, // IOC8
441 IoBankVcc, // IOC7
442 IoBankVcc, // IOC6
443 IoBankVcc, // IOC5
444 IoBankVcc, // IOC4
445 IoBankVcc, // IOC3
446 IoBankVcc, // IOC2
447 IoBankVcc, // IOC1
448 IoBankVcc, // IOC0
449 IoBankViob, // IOB12
450 IoBankViob, // IOB11
451 IoBankViob, // IOB10
452 IoBankViob, // IOB9
453 IoBankViob, // IOB8
454 IoBankViob, // IOB7
455 IoBankViob, // IOB6
456 IoBankViob, // IOB5
457 IoBankViob, // IOB4
458 IoBankViob, // IOB3
459 IoBankViob, // IOB2
460 IoBankViob, // IOB1
461 IoBankViob, // IOB0
462 IoBankVioa, // IOA8
463 IoBankVioa, // IOA7
464 IoBankVioa, // IOA6
465 IoBankVioa, // IOA5
466 IoBankVioa, // IOA4
467 IoBankVioa, // IOA3
468 IoBankVioa, // IOA2
469 IoBankVioa, // IOA1
470 IoBankVioa // IOA0
471 }),
472 .DioPadType ({
473 BidirOd, // IOR9
474 BidirOd, // IOR8
475 InputStd, // SPI_DEV_CS_L
476 InputStd, // SPI_DEV_CLK
477 BidirStd, // SPI_DEV_D3
478 BidirStd, // SPI_DEV_D2
479 BidirStd, // SPI_DEV_D1
480 BidirStd, // SPI_DEV_D0
481 BidirStd, // SPI_HOST_CS_L
482 BidirStd, // SPI_HOST_CLK
483 BidirStd, // SPI_HOST_D3
484 BidirStd, // SPI_HOST_D2
485 BidirStd, // SPI_HOST_D1
486 BidirStd, // SPI_HOST_D0
487 AnalogIn1, // OTP_EXT_VOLT
488 InputStd, // FLASH_TEST_MODE1
489 InputStd, // FLASH_TEST_MODE0
490 AnalogIn0, // FLASH_TEST_VOLT
491 BidirTol, // CC2
492 BidirTol, // CC1
493 DualBidirTol, // USB_N
494 DualBidirTol, // USB_P
495 InputStd // POR_N
496 }),
497 .MioPadType ({
498 BidirOd, // IOR13
499 BidirOd, // IOR12
500 BidirOd, // IOR11
501 BidirOd, // IOR10
502 BidirStd, // IOR7
503 BidirStd, // IOR6
504 BidirStd, // IOR5
505 BidirStd, // IOR4
506 BidirStd, // IOR3
507 BidirStd, // IOR2
508 BidirStd, // IOR1
509 BidirStd, // IOR0
510 BidirOd, // IOC12
511 BidirOd, // IOC11
512 BidirOd, // IOC10
513 BidirStd, // IOC9
514 BidirStd, // IOC8
515 BidirStd, // IOC7
516 BidirStd, // IOC6
517 BidirStd, // IOC5
518 BidirStd, // IOC4
519 BidirStd, // IOC3
520 BidirStd, // IOC2
521 BidirStd, // IOC1
522 BidirStd, // IOC0
523 BidirOd, // IOB12
524 BidirOd, // IOB11
525 BidirOd, // IOB10
526 BidirOd, // IOB9
527 BidirStd, // IOB8
528 BidirStd, // IOB7
529 BidirStd, // IOB6
530 BidirStd, // IOB5
531 BidirStd, // IOB4
532 BidirStd, // IOB3
533 BidirStd, // IOB2
534 BidirStd, // IOB1
535 BidirStd, // IOB0
536 BidirOd, // IOA8
537 BidirOd, // IOA7
538 BidirOd, // IOA6
539 BidirStd, // IOA5
540 BidirStd, // IOA4
541 BidirStd, // IOA3
542 BidirStd, // IOA2
543 BidirStd, // IOA1
544 BidirStd // IOA0
545 })
546 ) u_padring (
547 // This is only used for scan and DFT purposes
548 .clk_scan_i ( ast_base_clks.clk_sys ),
549 .scanmode_i ( scanmode ),
550 .mux_iob_sel_i ( mux_iob_sel ),
551 .dio_in_raw_o ( dio_in_raw ),
552 // Chip IOs
553 .dio_pad_io ({
554 IOR9,
555 IOR8,
556 SPI_DEV_CS_L,
557 SPI_DEV_CLK,
558 SPI_DEV_D3,
559 SPI_DEV_D2,
560 SPI_DEV_D1,
561 SPI_DEV_D0,
562 SPI_HOST_CS_L,
563 SPI_HOST_CLK,
564 SPI_HOST_D3,
565 SPI_HOST_D2,
566 SPI_HOST_D1,
567 SPI_HOST_D0,
568 OTP_EXT_VOLT,
569 FLASH_TEST_MODE1,
570 FLASH_TEST_MODE0,
571 FLASH_TEST_VOLT,
572 `ifdef ANALOGSIM
573 '0,
574 `else
575 CC2,
576 `endif
577 `ifdef ANALOGSIM
578 '0,
579 `else
580 CC1,
581 `endif
582 USB_N,
583 USB_P,
584 POR_N
585 }),
586
587 .mio_pad_io ({
588 IOR13,
589 IOR12,
590 IOR11,
591 IOR10,
592 IOR7,
593 IOR6,
594 IOR5,
595 IOR4,
596 IOR3,
597 IOR2,
598 IOR1,
599 IOR0,
600 IOC12,
601 IOC11,
602 IOC10,
603 IOC9,
604 IOC8,
605 IOC7,
606 IOC6,
607 IOC5,
608 IOC4,
609 IOC3,
610 IOC2,
611 IOC1,
612 IOC0,
613 IOB12,
614 IOB11,
615 IOB10,
616 IOB9,
617 IOB8,
618 IOB7,
619 IOB6,
620 IOB5,
621 IOB4,
622 IOB3,
623 IOB2,
624 IOB1,
625 IOB0,
626 IOA8,
627 IOA7,
628 IOA6,
629 IOA5,
630 IOA4,
631 `ifdef ANALOGSIM
632 '0,
633 `else
634 IOA3,
635 `endif
636 `ifdef ANALOGSIM
637 '0,
638 `else
639 IOA2,
640 `endif
641 IOA1,
642 IOA0
643 }),
644
645 // Core-facing
646 .dio_in_o ({
647 dio_in[DioSysrstCtrlAonFlashWpL],
648 dio_in[DioSysrstCtrlAonEcRstL],
649 dio_in[DioSpiDeviceCsb],
650 dio_in[DioSpiDeviceSck],
651 dio_in[DioSpiDeviceSd3],
652 dio_in[DioSpiDeviceSd2],
653 dio_in[DioSpiDeviceSd1],
654 dio_in[DioSpiDeviceSd0],
655 dio_in[DioSpiHost0Csb],
656 dio_in[DioSpiHost0Sck],
657 dio_in[DioSpiHost0Sd3],
658 dio_in[DioSpiHost0Sd2],
659 dio_in[DioSpiHost0Sd1],
660 dio_in[DioSpiHost0Sd0],
661 manual_in_otp_ext_volt,
662 manual_in_flash_test_mode1,
663 manual_in_flash_test_mode0,
664 manual_in_flash_test_volt,
665 manual_in_cc2,
666 manual_in_cc1,
667 manual_in_usb_n,
668 manual_in_usb_p,
669 manual_in_por_n
670 }),
671 .dio_out_i ({
672 dio_out[DioSysrstCtrlAonFlashWpL],
673 dio_out[DioSysrstCtrlAonEcRstL],
674 dio_out[DioSpiDeviceCsb],
675 dio_out[DioSpiDeviceSck],
676 dio_out[DioSpiDeviceSd3],
677 dio_out[DioSpiDeviceSd2],
678 dio_out[DioSpiDeviceSd1],
679 dio_out[DioSpiDeviceSd0],
680 dio_out[DioSpiHost0Csb],
681 dio_out[DioSpiHost0Sck],
682 dio_out[DioSpiHost0Sd3],
683 dio_out[DioSpiHost0Sd2],
684 dio_out[DioSpiHost0Sd1],
685 dio_out[DioSpiHost0Sd0],
686 manual_out_otp_ext_volt,
687 manual_out_flash_test_mode1,
688 manual_out_flash_test_mode0,
689 manual_out_flash_test_volt,
690 manual_out_cc2,
691 manual_out_cc1,
692 manual_out_usb_n,
693 manual_out_usb_p,
694 manual_out_por_n
695 }),
696 .dio_oe_i ({
697 dio_oe[DioSysrstCtrlAonFlashWpL],
698 dio_oe[DioSysrstCtrlAonEcRstL],
699 dio_oe[DioSpiDeviceCsb],
700 dio_oe[DioSpiDeviceSck],
701 dio_oe[DioSpiDeviceSd3],
702 dio_oe[DioSpiDeviceSd2],
703 dio_oe[DioSpiDeviceSd1],
704 dio_oe[DioSpiDeviceSd0],
705 dio_oe[DioSpiHost0Csb],
706 dio_oe[DioSpiHost0Sck],
707 dio_oe[DioSpiHost0Sd3],
708 dio_oe[DioSpiHost0Sd2],
709 dio_oe[DioSpiHost0Sd1],
710 dio_oe[DioSpiHost0Sd0],
711 manual_oe_otp_ext_volt,
712 manual_oe_flash_test_mode1,
713 manual_oe_flash_test_mode0,
714 manual_oe_flash_test_volt,
715 manual_oe_cc2,
716 manual_oe_cc1,
717 manual_oe_usb_n,
718 manual_oe_usb_p,
719 manual_oe_por_n
720 }),
721 .dio_attr_i ({
722 dio_attr[DioSysrstCtrlAonFlashWpL],
723 dio_attr[DioSysrstCtrlAonEcRstL],
724 dio_attr[DioSpiDeviceCsb],
725 dio_attr[DioSpiDeviceSck],
726 dio_attr[DioSpiDeviceSd3],
727 dio_attr[DioSpiDeviceSd2],
728 dio_attr[DioSpiDeviceSd1],
729 dio_attr[DioSpiDeviceSd0],
730 dio_attr[DioSpiHost0Csb],
731 dio_attr[DioSpiHost0Sck],
732 dio_attr[DioSpiHost0Sd3],
733 dio_attr[DioSpiHost0Sd2],
734 dio_attr[DioSpiHost0Sd1],
735 dio_attr[DioSpiHost0Sd0],
736 manual_attr_otp_ext_volt,
737 manual_attr_flash_test_mode1,
738 manual_attr_flash_test_mode0,
739 manual_attr_flash_test_volt,
740 manual_attr_cc2,
741 manual_attr_cc1,
742 manual_attr_usb_n,
743 manual_attr_usb_p,
744 manual_attr_por_n
745 }),
746
747 .mio_in_o (mio_in[46:0]),
748 .mio_out_i (mio_out[46:0]),
749 .mio_oe_i (mio_oe[46:0]),
750 .mio_attr_i (mio_attr[46:0]),
751 .mio_in_raw_o (mio_in_raw[46:0])
752 );
753
754
755
756
757
758 //////////////////////////////////
759 // AST - Common for all targets //
760 //////////////////////////////////
761
762 // pwrmgr interface
763 pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
764 pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
765
766 // assorted ast status
767 ast_pkg::ast_pwst_t ast_pwst;
768 ast_pkg::ast_pwst_t ast_pwst_h;
769
770 // TLUL interface
771 tlul_pkg::tl_h2d_t base_ast_bus;
772 tlul_pkg::tl_d2h_t ast_base_bus;
773
774 // synchronization clocks / rests
775 clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
776 rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
777
778 // external clock
779 logic ext_clk;
780
781 // monitored clock
782 logic sck_monitor;
783
784 // observe interface
785 logic [7:0] fla_obs;
786 logic [7:0] otp_obs;
787 ast_pkg::ast_obs_ctrl_t obs_ctrl;
788
789 // otp power sequence
790 otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
791 otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
792
793 logic usb_ref_pulse;
794 logic usb_ref_val;
795
796 // adc
797 ast_pkg::adc_ast_req_t adc_req;
798 ast_pkg::adc_ast_rsp_t adc_rsp;
799
800 // entropy source interface
801 // The entropy source pacakge definition should eventually be moved to es
802 entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
803 entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
804 logic es_rng_fips;
805
806 // entropy distribution network
807 edn_pkg::edn_req_t ast_edn_edn_req;
808 edn_pkg::edn_rsp_t ast_edn_edn_rsp;
809
810 // alerts interface
811 ast_pkg::ast_alert_rsp_t ast_alert_rsp;
812 ast_pkg::ast_alert_req_t ast_alert_req;
813
814 // Flash connections
815 prim_mubi_pkg::mubi4_t flash_bist_enable;
816 logic flash_power_down_h;
817 logic flash_power_ready_h;
818
819 // clock bypass req/ack
820 prim_mubi_pkg::mubi4_t io_clk_byp_req;
821 prim_mubi_pkg::mubi4_t io_clk_byp_ack;
822 prim_mubi_pkg::mubi4_t all_clk_byp_req;
823 prim_mubi_pkg::mubi4_t all_clk_byp_ack;
824 prim_mubi_pkg::mubi4_t hi_speed_sel;
825 prim_mubi_pkg::mubi4_t div_step_down_req;
826
827 // DFT connections
828 logic scan_en;
829 lc_ctrl_pkg::lc_tx_t dft_en;
830 pinmux_pkg::dft_strap_test_req_t dft_strap_test;
831
832 // Debug connections
833 logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
834 logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast;
835
836 // Jitter enable
837 prim_mubi_pkg::mubi4_t jen;
838
839 // reset domain connections
840 import rstmgr_pkg::PowerDomains;
841 import rstmgr_pkg::DomainAonSel;
842 import rstmgr_pkg::Domain0Sel;
843
844 // Memory configuration connections
845 ast_pkg::spm_rm_t ast_ram_1p_cfg;
846 ast_pkg::spm_rm_t ast_rf_cfg;
847 ast_pkg::spm_rm_t ast_rom_cfg;
848 ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
849 ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
850
851 prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
852 prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg;
853 prim_ram_1p_pkg::ram_1p_cfg_t usb_ram_1p_cfg;
854 prim_rom_pkg::rom_cfg_t rom_cfg;
855
856 // conversion from ast structure to memory centric structures
857 0/1 ==> assign ram_1p_cfg = '{
858 ram_cfg: '{
859 test: ast_ram_1p_cfg.test,
860 cfg_en: ast_ram_1p_cfg.marg_en,
861 cfg: ast_ram_1p_cfg.marg
862 },
863 rf_cfg: '{
864 test: ast_rf_cfg.test,
865 cfg_en: ast_rf_cfg.marg_en,
866 cfg: ast_rf_cfg.marg
867 }
868 };
869
870 0/1 ==> assign usb_ram_1p_cfg = '{
871 ram_cfg: '{
872 test: ast_ram_1p_cfg.test,
873 cfg_en: ast_ram_1p_cfg.marg_en,
874 cfg: ast_ram_1p_cfg.marg
875 },
876 rf_cfg: '{
877 test: ast_rf_cfg.test,
878 cfg_en: ast_rf_cfg.marg_en,
879 cfg: ast_rf_cfg.marg
880 }
881 };
882
883 // this maps as follows:
884 // assign spi_ram_2p_cfg = {10'h000, ram_2p_cfg_i.a_ram_lcfg, ram_2p_cfg_i.b_ram_lcfg};
885 assign spi_ram_2p_cfg = '{
886 a_ram_lcfg: '{
887 test: ast_ram_2p_lcfg.test_a,
888 cfg_en: ast_ram_2p_lcfg.marg_en_a,
889 cfg: ast_ram_2p_lcfg.marg_a
890 },
891 b_ram_lcfg: '{
892 test: ast_ram_2p_lcfg.test_b,
893 cfg_en: ast_ram_2p_lcfg.marg_en_b,
894 cfg: ast_ram_2p_lcfg.marg_b
895 },
896 default: '0
897 };
898
899 0/1 ==> assign rom_cfg = '{
900 test: ast_rom_cfg.test,
901 cfg_en: ast_rom_cfg.marg_en,
902 cfg: ast_rom_cfg.marg
903 };
904
905 // unused cfg bits
906 logic unused_ram_cfg;
907 0/1 ==> assign unused_ram_cfg = ^ast_ram_2p_fcfg;
908
909 //////////////////////////////////
910 // AST - Custom for targets //
911 //////////////////////////////////
912
913
914 1/1 assign ast_base_pwr.main_pok = ast_pwst.main_pok;
Tests: T1 T2 T3
915
916 logic [rstmgr_pkg::PowerDomains-1:0] por_n;
917 1/1 assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
Tests: T1 T2 T3
918
919
920 logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
921
922 // external clock comes in at a fixed position
923 1/1 assign ext_clk = mio_in_raw[MioPadIoc6];
Tests: T6 T28 T29
924
925 1/1 assign pad2ast = `PAD2AST_WIRES ;
Tests: T1 T2 T3
926
927 // AST does not use all clocks / resets forwarded to it
928 logic unused_slow_clk_en;
929 0/1 ==> assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
930
931 logic unused_pwr_clamp;
932 1/1 assign unused_pwr_clamp = base_ast_pwr.pwr_clamp;
Tests: T1 T2 T3
933
934 logic usb_diff_rx_obs;
935
936
937 prim_mubi_pkg::mubi4_t ast_init_done;
938
939 ast #(
940 .EntropyStreams(ast_pkg::EntropyStreams),
941 .AdcChannels(ast_pkg::AdcChannels),
942 .AdcDataWidth(ast_pkg::AdcDataWidth),
943 .UsbCalibWidth(ast_pkg::UsbCalibWidth),
944 .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
945 .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
946 ) u_ast (
947 // external POR
948 .por_ni ( manual_in_por_n ),
949
950 // USB IO Pull-up Calibration Setting
951 .usb_io_pu_cal_o ( usb_io_pu_cal ),
952
953 // adc
954 .adc_a0_ai ( CC1 ),
955 .adc_a1_ai ( CC2 ),
956
957 // Direct short to PAD
958 .ast2pad_t0_ao ( IOA2 ),
959 .ast2pad_t1_ao ( IOA3 ),
960 // clocks and resets supplied for detection
961 .sns_clks_i ( clkmgr_aon_clocks ),
962 .sns_rsts_i ( rstmgr_aon_resets ),
963 .sns_spi_ext_clk_i ( sck_monitor ),
964 // tlul
965 .tl_i ( base_ast_bus ),
966 .tl_o ( ast_base_bus ),
967 // init done indication
968 .ast_init_done_o ( ast_init_done ),
969 // buffered clocks & resets
970 .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra),
971 .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri),
972 .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure),
973 .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure),
974 .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure),
975 .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_peri),
976 .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
977 .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
978 .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
979 .rst_ast_es_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
980 .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
981 .rst_ast_usb_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
982 .clk_ast_ext_i ( ext_clk ),
983
984 // pok test for FPGA
985 .vcc_supp_i ( 1'b1 ),
986 .vcaon_supp_i ( 1'b1 ),
987 .vcmain_supp_i ( 1'b1 ),
988 .vioa_supp_i ( 1'b1 ),
989 .viob_supp_i ( 1'b1 ),
990 // pok
991 .ast_pwst_o ( ast_pwst ),
992 .ast_pwst_h_o ( ast_pwst_h ),
993 // main regulator
994 .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
995 .main_pd_ni ( base_ast_pwr.main_pd_n ),
996 // pdm control (flash)/otp
997 .flash_power_down_h_o ( flash_power_down_h ),
998 .flash_power_ready_h_o ( flash_power_ready_h ),
999 .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
1000 .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
1001 // system source clock
1002 .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
1003 // need to add function in clkmgr
1004 .clk_src_sys_jen_i ( jen ),
1005 .clk_src_sys_o ( ast_base_clks.clk_sys ),
1006 .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
1007 // aon source clock
1008 .clk_src_aon_o ( ast_base_clks.clk_aon ),
1009 .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
1010 // io source clock
1011 .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
1012 .clk_src_io_o ( ast_base_clks.clk_io ),
1013 .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
1014 .clk_src_io_48m_o ( div_step_down_req ),
1015 // usb source clock
1016 .usb_ref_pulse_i ( usb_ref_pulse ),
1017 .usb_ref_val_i ( usb_ref_val ),
1018 .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
1019 .clk_src_usb_o ( ast_base_clks.clk_usb ),
1020 .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
1021 // adc
1022 .adc_pd_i ( adc_req.pd ),
1023 .adc_chnsel_i ( adc_req.channel_sel ),
1024 .adc_d_o ( adc_rsp.data ),
1025 .adc_d_val_o ( adc_rsp.data_valid ),
1026 // rng
1027 .rng_en_i ( es_rng_req.rng_enable ),
1028 .rng_fips_i ( es_rng_fips ),
1029 .rng_val_o ( es_rng_rsp.rng_valid ),
1030 .rng_b_o ( es_rng_rsp.rng_b ),
1031 // entropy
1032 .entropy_rsp_i ( ast_edn_edn_rsp ),
1033 .entropy_req_o ( ast_edn_edn_req ),
1034 // alerts
1035 .alert_rsp_i ( ast_alert_rsp ),
1036 .alert_req_o ( ast_alert_req ),
1037 // dft
1038 .dft_strap_test_i ( dft_strap_test ),
1039 .lc_dft_en_i ( dft_en ),
1040 .fla_obs_i ( fla_obs ),
1041 .otp_obs_i ( otp_obs ),
1042 .otm_obs_i ( '0 ),
1043 .usb_obs_i ( usb_diff_rx_obs ),
1044 .obs_ctrl_o ( obs_ctrl ),
1045 // pinmux related
1046 .padmux2ast_i ( pad2ast ),
1047 .ast2padmux_o ( ast2pinmux ),
1048 .mux_iob_sel_o ( mux_iob_sel ),
1049 .ext_freq_is_96m_i ( hi_speed_sel ),
1050 .all_clk_byp_req_i ( all_clk_byp_req ),
1051 .all_clk_byp_ack_o ( all_clk_byp_ack ),
1052 .io_clk_byp_req_i ( io_clk_byp_req ),
1053 .io_clk_byp_ack_o ( io_clk_byp_ack ),
1054 .flash_bist_en_o ( flash_bist_enable ),
1055 // Memory configuration connections
1056 .dpram_rmf_o ( ast_ram_2p_fcfg ),
1057 .dpram_rml_o ( ast_ram_2p_lcfg ),
1058 .spram_rm_o ( ast_ram_1p_cfg ),
1059 .sprgf_rm_o ( ast_rf_cfg ),
1060 .sprom_rm_o ( ast_rom_cfg ),
1061 // scan
1062 .dft_scan_md_o ( scanmode ),
1063 .scan_shift_en_o ( scan_en ),
1064 .scan_reset_no ( scan_rst_n )
1065 );
1066
1067
1068
1069
1070 //////////////////////////////////
1071 // Manual Pad / Signal Tie-offs //
1072 //////////////////////////////////
1073
1074 assign manual_out_por_n = 1'b0;
1075 assign manual_oe_por_n = 1'b0;
1076
1077 assign manual_out_cc1 = 1'b0;
1078 assign manual_oe_cc1 = 1'b0;
1079 assign manual_out_cc2 = 1'b0;
1080 assign manual_oe_cc2 = 1'b0;
1081
1082 assign manual_out_flash_test_mode0 = 1'b0;
1083 assign manual_oe_flash_test_mode0 = 1'b0;
1084 assign manual_out_flash_test_mode1 = 1'b0;
1085 assign manual_oe_flash_test_mode1 = 1'b0;
1086 assign manual_out_flash_test_volt = 1'b0;
1087 assign manual_oe_flash_test_volt = 1'b0;
1088 assign manual_out_otp_ext_volt = 1'b0;
1089 assign manual_oe_otp_ext_volt = 1'b0;
1090
1091 // Enable schmitt trigger on POR for better signal integrity.
1092 assign manual_attr_por_n = '{schmitt_en: 1'b1, pull_en: 1'b1, pull_select: 1'b1, default: '0};
1093
1094 // These pad attributes are controlled through sensor_ctrl. Update the description of
1095 // `MANUAL_PAD_ATTR` in `sensor_ctrl.hjson` when you change or extend the mapping below.
1096 prim_pad_wrapper_pkg::pad_attr_t [3:0] sensor_ctrl_manual_pad_attr;
1097 1/1 assign manual_attr_cc1 = sensor_ctrl_manual_pad_attr[0];
Tests: T20 T21 T22
1098 1/1 assign manual_attr_cc2 = sensor_ctrl_manual_pad_attr[1];
Tests: T20 T21 T22
1099 1/1 assign manual_attr_flash_test_mode0 = sensor_ctrl_manual_pad_attr[2];
Tests: T20 T21 T22
1100 1/1 assign manual_attr_flash_test_mode1 = sensor_ctrl_manual_pad_attr[3];
Tests: T20 T21 T22
1101
1102 // These pad attributes are currently tied off permanently (these are supply pads).
1103 assign manual_attr_flash_test_volt = '0;
1104 assign manual_attr_otp_ext_volt = '0;
1105
1106 logic unused_manual_sigs;
1107 1/1 assign unused_manual_sigs = ^{
Tests: T4 T30 T6
1108 manual_in_cc2,
1109 manual_in_cc1,
1110 manual_in_flash_test_volt,
1111 manual_in_flash_test_mode0,
1112 manual_in_flash_test_mode1,
1113 manual_in_otp_ext_volt
1114 };
1115
1116 ///////////////////////////////
1117 // Differential USB Receiver //
1118 ///////////////////////////////
1119
1120 // TODO: generalize this USB mux code and align with other tops.
1121
1122 // Connect the D+ pad
1123 // Note that we use two pads in parallel for the D+ channel to meet electrical specifications.
1124 1/1 assign dio_in[DioUsbdevUsbDp] = manual_in_usb_p;
Tests: T4 T30 T6
1125 1/1 assign manual_out_usb_p = dio_out[DioUsbdevUsbDp];
Tests: T4 T6 T7
1126 1/1 assign manual_oe_usb_p = dio_oe[DioUsbdevUsbDp];
Tests: T16 T17 T18
1127 1/1 assign manual_attr_usb_p = dio_attr[DioUsbdevUsbDp];
Tests: T1 T2 T3
1128
1129 // Connect the D- pads
1130 // Note that we use two pads in parallel for the D- channel to meet electrical specifications.
1131 1/1 assign dio_in[DioUsbdevUsbDn] = manual_in_usb_n;
Tests: T4 T6 T7
1132 1/1 assign manual_out_usb_n = dio_out[DioUsbdevUsbDn];
Tests: T4 T6 T7
1133 1/1 assign manual_oe_usb_n = dio_oe[DioUsbdevUsbDn];
Tests: T6 T16 T17
1134 1/1 assign manual_attr_usb_n = dio_attr[DioUsbdevUsbDn];
Tests: T1 T2 T3
Cond Coverage for Module :
chip_earlgrey_asic
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 79
EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T23 |
Toggle Coverage for Module :
chip_earlgrey_asic
| Total | Covered | Percent |
| Totals |
70 |
64 |
91.43 |
| Total Bits |
140 |
134 |
95.71 |
| Total Bits 0->1 |
70 |
70 |
100.00 |
| Total Bits 1->0 |
70 |
64 |
91.43 |
| | | |
| Ports |
70 |
64 |
91.43 |
| Port Bits |
140 |
134 |
95.71 |
| Port Bits 0->1 |
70 |
70 |
100.00 |
| Port Bits 1->0 |
70 |
64 |
91.43 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction |
| POR_N |
Yes |
Yes |
T29,T36,T37 |
Yes |
T1,T2,T3 |
INOUT |
| USB_P |
Yes |
Yes |
T4,T30,T6 |
Yes |
T4,T6,T7 |
INOUT |
| USB_N |
Yes |
Yes |
T4,T7,T16 |
Yes |
T4,T6,T7 |
INOUT |
| CC1 |
No |
No |
|
Yes |
T6,T19,T20 |
INOUT |
| CC2 |
No |
No |
|
Yes |
T6,T19,T20 |
INOUT |
| FLASH_TEST_VOLT |
No |
No |
|
Yes |
T6,T19 |
INOUT |
| FLASH_TEST_MODE0 |
No |
No |
|
Yes |
T6,T19,T20 |
INOUT |
| FLASH_TEST_MODE1 |
No |
No |
|
Yes |
T6,T19,T20 |
INOUT |
| OTP_EXT_VOLT |
No |
No |
|
Yes |
T6,T19 |
INOUT |
| SPI_HOST_D0 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T23,T8,T9 |
INOUT |
| SPI_HOST_D1 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T8,T9,T10 |
INOUT |
| SPI_HOST_D2 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T6,T8,T9 |
INOUT |
| SPI_HOST_D3 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T6,T8,T9 |
INOUT |
| SPI_HOST_CLK |
Yes |
Yes |
T8,T9,T10 |
Yes |
T8,T9,T10 |
INOUT |
| SPI_HOST_CS_L |
Yes |
Yes |
T8,T9,T10 |
Yes |
T6,T8,T9 |
INOUT |
| SPI_DEV_D0 |
Yes |
Yes |
T5,T11,T8 |
Yes |
T5,T11,T8 |
INOUT |
| SPI_DEV_D1 |
Yes |
Yes |
T5,T11,T8 |
Yes |
T5,T11,T8 |
INOUT |
| SPI_DEV_D2 |
Yes |
Yes |
T5,T8,T9 |
Yes |
T5,T8,T9 |
INOUT |
| SPI_DEV_D3 |
Yes |
Yes |
T5,T8,T9 |
Yes |
T5,T8,T9 |
INOUT |
| SPI_DEV_CLK |
Yes |
Yes |
T5,T11,T8 |
Yes |
T5,T6,T11 |
INOUT |
| SPI_DEV_CS_L |
Yes |
Yes |
T5,T6,T23 |
Yes |
T6,T8,T9 |
INOUT |
| IOR8 |
Yes |
Yes |
T6,T12,T66 |
Yes |
T6,T23,T12 |
INOUT |
| IOR9 |
Yes |
Yes |
T6,T12,T67 |
Yes |
T6,T23,T12 |
INOUT |
| IOA0 |
Yes |
Yes |
T26,T27,T38 |
Yes |
T26,T27,T38 |
INOUT |
| IOA1 |
Yes |
Yes |
T26,T27,T38 |
Yes |
T26,T27,T38 |
INOUT |
| IOA2 |
Yes |
Yes |
T26,T27,T70 |
Yes |
T26,T27,T70 |
INOUT |
| IOA3 |
Yes |
Yes |
T26,T27,T39 |
Yes |
T26,T27,T39 |
INOUT |
| IOA4 |
Yes |
Yes |
T26,T27,T63 |
Yes |
T6,T26,T27 |
INOUT |
| IOA5 |
Yes |
Yes |
T26,T27,T63 |
Yes |
T26,T27,T63 |
INOUT |
| IOA6 |
Yes |
Yes |
T26,T27,T39 |
Yes |
T26,T27,T39 |
INOUT |
| IOA7 |
Yes |
Yes |
T11,T26,T27 |
Yes |
T6,T11,T26 |
INOUT |
| IOA8 |
Yes |
Yes |
T5,T26,T27 |
Yes |
T5,T26,T27 |
INOUT |
| IOB0 |
Yes |
Yes |
T25,T10,T69 |
Yes |
T25,T10,T19 |
INOUT |
| IOB1 |
Yes |
Yes |
T25,T10,T69 |
Yes |
T25,T10,T69 |
INOUT |
| IOB2 |
Yes |
Yes |
T10,T69,T131 |
Yes |
T6,T10,T69 |
INOUT |
| IOB3 |
Yes |
Yes |
T25,T12,T66 |
Yes |
T25,T12,T66 |
INOUT |
| IOB4 |
Yes |
Yes |
T25,T28,T132 |
Yes |
T25,T28,T132 |
INOUT |
| IOB5 |
Yes |
Yes |
T28,T132,T10 |
Yes |
T28,T132,T10 |
INOUT |
| IOB6 |
Yes |
Yes |
T27,T12,T66 |
Yes |
T27,T12,T66 |
INOUT |
| IOB7 |
Yes |
Yes |
T27,T12,T72 |
Yes |
T27,T12,T15 |
INOUT |
| IOB8 |
Yes |
Yes |
T27,T12,T66 |
Yes |
T27,T12,T66 |
INOUT |
| IOB9 |
Yes |
Yes |
T2,T27,T59 |
Yes |
T2,T27,T59 |
INOUT |
| IOB10 |
Yes |
Yes |
T2,T27,T59 |
Yes |
T2,T27,T59 |
INOUT |
| IOB11 |
Yes |
Yes |
T2,T27,T61 |
Yes |
T2,T27,T61 |
INOUT |
| IOB12 |
Yes |
Yes |
T2,T27,T61 |
Yes |
T2,T6,T27 |
INOUT |
| IOC0 |
Yes |
Yes |
T54,T55,T56 |
Yes |
T6,T19,T376 |
INOUT |
| IOC1 |
Yes |
Yes |
T244,T377,T378 |
Yes |
T6,T19,T244 |
INOUT |
| IOC2 |
Yes |
Yes |
T244,T377,T378 |
Yes |
T6,T19,T244 |
INOUT |
| IOC3 |
Yes |
Yes |
T68,T19,T296 |
Yes |
T68,T296,T362 |
INOUT |
| IOC4 |
Yes |
Yes |
T68,T6,T54 |
Yes |
T68,T54,T55 |
INOUT |
| IOC5 |
Yes |
Yes |
T32,T84,T85 |
Yes |
T6,T31,T32 |
INOUT |
| IOC6 |
Yes |
Yes |
T28,T29,T57 |
Yes |
T28,T29,T57 |
INOUT |
| IOC7 |
Yes |
Yes |
T12,T66,T67 |
Yes |
T4,T30,T6 |
INOUT |
| IOC8 |
Yes |
Yes |
T31,T32,T84 |
Yes |
T6,T31,T32 |
INOUT |
| IOC9 |
Yes |
Yes |
T27,T12,T66 |
Yes |
T6,T27,T12 |
INOUT |
| IOC10 |
Yes |
Yes |
T27,T33,T70 |
Yes |
T27,T33,T70 |
INOUT |
| IOC11 |
Yes |
Yes |
T27,T33,T70 |
Yes |
T6,T27,T33 |
INOUT |
| IOC12 |
Yes |
Yes |
T27,T33,T70 |
Yes |
T27,T33,T70 |
INOUT |
| IOR0 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
| IOR1 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
| IOR2 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
| IOR3 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
| IOR4 |
Yes |
Yes |
T27,T29,T36 |
Yes |
T34,T27,T29 |
INOUT |
| IOR5 |
Yes |
Yes |
T27,T12,T14 |
Yes |
T27,T12,T14 |
INOUT |
| IOR6 |
Yes |
Yes |
T27,T12,T10 |
Yes |
T6,T27,T12 |
INOUT |
| IOR7 |
Yes |
Yes |
T27,T10,T39 |
Yes |
T27,T10,T39 |
INOUT |
| IOR10 |
Yes |
Yes |
T27,T10,T39 |
Yes |
T6,T27,T10 |
INOUT |
| IOR11 |
Yes |
Yes |
T27,T10,T39 |
Yes |
T6,T27,T10 |
INOUT |
| IOR12 |
Yes |
Yes |
T27,T39,T40 |
Yes |
T6,T27,T39 |
INOUT |
| IOR13 |
Yes |
Yes |
T27,T66,T67 |
Yes |
T27,T12,T66 |
INOUT |
Line Coverage for Instance : tb.dut
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 25 | 20 | 80.00 |
| CONT_ASSIGN | 282 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 283 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 857 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 870 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 899 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 907 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 914 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 917 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 923 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 925 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 929 | 1 | 0 | 0.00 |
| CONT_ASSIGN | 932 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1097 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1098 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1099 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1100 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1107 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1124 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1125 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1126 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1127 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1131 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1132 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1133 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 1134 | 1 | 1 | 100.00 |
281 logic unused_dio_in_raw;
282 1/1 assign unused_mio_in_raw = ^mio_in_raw;
Tests: T1 T2 T3
283 1/1 assign unused_dio_in_raw = ^dio_in_raw;
Tests: T1 T2 T3
284
285 // Manual pads
286 logic manual_in_por_n, manual_out_por_n, manual_oe_por_n;
287 logic manual_in_usb_p, manual_out_usb_p, manual_oe_usb_p;
288 logic manual_in_usb_n, manual_out_usb_n, manual_oe_usb_n;
289 logic manual_in_cc1, manual_out_cc1, manual_oe_cc1;
290 logic manual_in_cc2, manual_out_cc2, manual_oe_cc2;
291 logic manual_in_flash_test_volt, manual_out_flash_test_volt, manual_oe_flash_test_volt;
292 logic manual_in_flash_test_mode0, manual_out_flash_test_mode0, manual_oe_flash_test_mode0;
293 logic manual_in_flash_test_mode1, manual_out_flash_test_mode1, manual_oe_flash_test_mode1;
294 logic manual_in_otp_ext_volt, manual_out_otp_ext_volt, manual_oe_otp_ext_volt;
295
296 pad_attr_t manual_attr_por_n;
297 pad_attr_t manual_attr_usb_p;
298 pad_attr_t manual_attr_usb_n;
299 pad_attr_t manual_attr_cc1;
300 pad_attr_t manual_attr_cc2;
301 pad_attr_t manual_attr_flash_test_volt;
302 pad_attr_t manual_attr_flash_test_mode0;
303 pad_attr_t manual_attr_flash_test_mode1;
304 pad_attr_t manual_attr_otp_ext_volt;
305
306
307 //////////////////////
308 // Padring Instance //
309 //////////////////////
310
311 ast_pkg::ast_clks_t ast_base_clks;
312
313 // AST signals needed in padring
314 logic scan_rst_n;
315 prim_mubi_pkg::mubi4_t scanmode;
316
317 padring #(
318 // Padring specific counts may differ from pinmux config due
319 // to custom, stubbed or added pads.
320 .NDioPads(23),
321 .NMioPads(47),
322 .PhysicalPads(1),
323 .NIoBanks(int'(IoBankCount)),
324 .DioScanRole ({
325 scan_role_pkg::DioPadIor9ScanRole,
326 scan_role_pkg::DioPadIor8ScanRole,
327 scan_role_pkg::DioPadSpiDevCsLScanRole,
328 scan_role_pkg::DioPadSpiDevClkScanRole,
329 scan_role_pkg::DioPadSpiDevD3ScanRole,
330 scan_role_pkg::DioPadSpiDevD2ScanRole,
331 scan_role_pkg::DioPadSpiDevD1ScanRole,
332 scan_role_pkg::DioPadSpiDevD0ScanRole,
333 scan_role_pkg::DioPadSpiHostCsLScanRole,
334 scan_role_pkg::DioPadSpiHostClkScanRole,
335 scan_role_pkg::DioPadSpiHostD3ScanRole,
336 scan_role_pkg::DioPadSpiHostD2ScanRole,
337 scan_role_pkg::DioPadSpiHostD1ScanRole,
338 scan_role_pkg::DioPadSpiHostD0ScanRole,
339 scan_role_pkg::DioPadOtpExtVoltScanRole,
340 scan_role_pkg::DioPadFlashTestMode1ScanRole,
341 scan_role_pkg::DioPadFlashTestMode0ScanRole,
342 scan_role_pkg::DioPadFlashTestVoltScanRole,
343 scan_role_pkg::DioPadCc2ScanRole,
344 scan_role_pkg::DioPadCc1ScanRole,
345 scan_role_pkg::DioPadUsbNScanRole,
346 scan_role_pkg::DioPadUsbPScanRole,
347 scan_role_pkg::DioPadPorNScanRole
348 }),
349 .MioScanRole ({
350 scan_role_pkg::MioPadIor13ScanRole,
351 scan_role_pkg::MioPadIor12ScanRole,
352 scan_role_pkg::MioPadIor11ScanRole,
353 scan_role_pkg::MioPadIor10ScanRole,
354 scan_role_pkg::MioPadIor7ScanRole,
355 scan_role_pkg::MioPadIor6ScanRole,
356 scan_role_pkg::MioPadIor5ScanRole,
357 scan_role_pkg::MioPadIor4ScanRole,
358 scan_role_pkg::MioPadIor3ScanRole,
359 scan_role_pkg::MioPadIor2ScanRole,
360 scan_role_pkg::MioPadIor1ScanRole,
361 scan_role_pkg::MioPadIor0ScanRole,
362 scan_role_pkg::MioPadIoc12ScanRole,
363 scan_role_pkg::MioPadIoc11ScanRole,
364 scan_role_pkg::MioPadIoc10ScanRole,
365 scan_role_pkg::MioPadIoc9ScanRole,
366 scan_role_pkg::MioPadIoc8ScanRole,
367 scan_role_pkg::MioPadIoc7ScanRole,
368 scan_role_pkg::MioPadIoc6ScanRole,
369 scan_role_pkg::MioPadIoc5ScanRole,
370 scan_role_pkg::MioPadIoc4ScanRole,
371 scan_role_pkg::MioPadIoc3ScanRole,
372 scan_role_pkg::MioPadIoc2ScanRole,
373 scan_role_pkg::MioPadIoc1ScanRole,
374 scan_role_pkg::MioPadIoc0ScanRole,
375 scan_role_pkg::MioPadIob12ScanRole,
376 scan_role_pkg::MioPadIob11ScanRole,
377 scan_role_pkg::MioPadIob10ScanRole,
378 scan_role_pkg::MioPadIob9ScanRole,
379 scan_role_pkg::MioPadIob8ScanRole,
380 scan_role_pkg::MioPadIob7ScanRole,
381 scan_role_pkg::MioPadIob6ScanRole,
382 scan_role_pkg::MioPadIob5ScanRole,
383 scan_role_pkg::MioPadIob4ScanRole,
384 scan_role_pkg::MioPadIob3ScanRole,
385 scan_role_pkg::MioPadIob2ScanRole,
386 scan_role_pkg::MioPadIob1ScanRole,
387 scan_role_pkg::MioPadIob0ScanRole,
388 scan_role_pkg::MioPadIoa8ScanRole,
389 scan_role_pkg::MioPadIoa7ScanRole,
390 scan_role_pkg::MioPadIoa6ScanRole,
391 scan_role_pkg::MioPadIoa5ScanRole,
392 scan_role_pkg::MioPadIoa4ScanRole,
393 scan_role_pkg::MioPadIoa3ScanRole,
394 scan_role_pkg::MioPadIoa2ScanRole,
395 scan_role_pkg::MioPadIoa1ScanRole,
396 scan_role_pkg::MioPadIoa0ScanRole
397 }),
398 .DioPadBank ({
399 IoBankVcc, // IOR9
400 IoBankVcc, // IOR8
401 IoBankVioa, // SPI_DEV_CS_L
402 IoBankVioa, // SPI_DEV_CLK
403 IoBankVioa, // SPI_DEV_D3
404 IoBankVioa, // SPI_DEV_D2
405 IoBankVioa, // SPI_DEV_D1
406 IoBankVioa, // SPI_DEV_D0
407 IoBankVioa, // SPI_HOST_CS_L
408 IoBankVioa, // SPI_HOST_CLK
409 IoBankVioa, // SPI_HOST_D3
410 IoBankVioa, // SPI_HOST_D2
411 IoBankVioa, // SPI_HOST_D1
412 IoBankVioa, // SPI_HOST_D0
413 IoBankVcc, // OTP_EXT_VOLT
414 IoBankVcc, // FLASH_TEST_MODE1
415 IoBankVcc, // FLASH_TEST_MODE0
416 IoBankVcc, // FLASH_TEST_VOLT
417 IoBankAvcc, // CC2
418 IoBankAvcc, // CC1
419 IoBankVcc, // USB_N
420 IoBankVcc, // USB_P
421 IoBankVcc // POR_N
422 }),
423 .MioPadBank ({
424 IoBankVcc, // IOR13
425 IoBankVcc, // IOR12
426 IoBankVcc, // IOR11
427 IoBankVcc, // IOR10
428 IoBankVcc, // IOR7
429 IoBankVcc, // IOR6
430 IoBankVcc, // IOR5
431 IoBankVcc, // IOR4
432 IoBankVcc, // IOR3
433 IoBankVcc, // IOR2
434 IoBankVcc, // IOR1
435 IoBankVcc, // IOR0
436 IoBankVcc, // IOC12
437 IoBankVcc, // IOC11
438 IoBankVcc, // IOC10
439 IoBankVcc, // IOC9
440 IoBankVcc, // IOC8
441 IoBankVcc, // IOC7
442 IoBankVcc, // IOC6
443 IoBankVcc, // IOC5
444 IoBankVcc, // IOC4
445 IoBankVcc, // IOC3
446 IoBankVcc, // IOC2
447 IoBankVcc, // IOC1
448 IoBankVcc, // IOC0
449 IoBankViob, // IOB12
450 IoBankViob, // IOB11
451 IoBankViob, // IOB10
452 IoBankViob, // IOB9
453 IoBankViob, // IOB8
454 IoBankViob, // IOB7
455 IoBankViob, // IOB6
456 IoBankViob, // IOB5
457 IoBankViob, // IOB4
458 IoBankViob, // IOB3
459 IoBankViob, // IOB2
460 IoBankViob, // IOB1
461 IoBankViob, // IOB0
462 IoBankVioa, // IOA8
463 IoBankVioa, // IOA7
464 IoBankVioa, // IOA6
465 IoBankVioa, // IOA5
466 IoBankVioa, // IOA4
467 IoBankVioa, // IOA3
468 IoBankVioa, // IOA2
469 IoBankVioa, // IOA1
470 IoBankVioa // IOA0
471 }),
472 .DioPadType ({
473 BidirOd, // IOR9
474 BidirOd, // IOR8
475 InputStd, // SPI_DEV_CS_L
476 InputStd, // SPI_DEV_CLK
477 BidirStd, // SPI_DEV_D3
478 BidirStd, // SPI_DEV_D2
479 BidirStd, // SPI_DEV_D1
480 BidirStd, // SPI_DEV_D0
481 BidirStd, // SPI_HOST_CS_L
482 BidirStd, // SPI_HOST_CLK
483 BidirStd, // SPI_HOST_D3
484 BidirStd, // SPI_HOST_D2
485 BidirStd, // SPI_HOST_D1
486 BidirStd, // SPI_HOST_D0
487 AnalogIn1, // OTP_EXT_VOLT
488 InputStd, // FLASH_TEST_MODE1
489 InputStd, // FLASH_TEST_MODE0
490 AnalogIn0, // FLASH_TEST_VOLT
491 BidirTol, // CC2
492 BidirTol, // CC1
493 DualBidirTol, // USB_N
494 DualBidirTol, // USB_P
495 InputStd // POR_N
496 }),
497 .MioPadType ({
498 BidirOd, // IOR13
499 BidirOd, // IOR12
500 BidirOd, // IOR11
501 BidirOd, // IOR10
502 BidirStd, // IOR7
503 BidirStd, // IOR6
504 BidirStd, // IOR5
505 BidirStd, // IOR4
506 BidirStd, // IOR3
507 BidirStd, // IOR2
508 BidirStd, // IOR1
509 BidirStd, // IOR0
510 BidirOd, // IOC12
511 BidirOd, // IOC11
512 BidirOd, // IOC10
513 BidirStd, // IOC9
514 BidirStd, // IOC8
515 BidirStd, // IOC7
516 BidirStd, // IOC6
517 BidirStd, // IOC5
518 BidirStd, // IOC4
519 BidirStd, // IOC3
520 BidirStd, // IOC2
521 BidirStd, // IOC1
522 BidirStd, // IOC0
523 BidirOd, // IOB12
524 BidirOd, // IOB11
525 BidirOd, // IOB10
526 BidirOd, // IOB9
527 BidirStd, // IOB8
528 BidirStd, // IOB7
529 BidirStd, // IOB6
530 BidirStd, // IOB5
531 BidirStd, // IOB4
532 BidirStd, // IOB3
533 BidirStd, // IOB2
534 BidirStd, // IOB1
535 BidirStd, // IOB0
536 BidirOd, // IOA8
537 BidirOd, // IOA7
538 BidirOd, // IOA6
539 BidirStd, // IOA5
540 BidirStd, // IOA4
541 BidirStd, // IOA3
542 BidirStd, // IOA2
543 BidirStd, // IOA1
544 BidirStd // IOA0
545 })
546 ) u_padring (
547 // This is only used for scan and DFT purposes
548 .clk_scan_i ( ast_base_clks.clk_sys ),
549 .scanmode_i ( scanmode ),
550 .mux_iob_sel_i ( mux_iob_sel ),
551 .dio_in_raw_o ( dio_in_raw ),
552 // Chip IOs
553 .dio_pad_io ({
554 IOR9,
555 IOR8,
556 SPI_DEV_CS_L,
557 SPI_DEV_CLK,
558 SPI_DEV_D3,
559 SPI_DEV_D2,
560 SPI_DEV_D1,
561 SPI_DEV_D0,
562 SPI_HOST_CS_L,
563 SPI_HOST_CLK,
564 SPI_HOST_D3,
565 SPI_HOST_D2,
566 SPI_HOST_D1,
567 SPI_HOST_D0,
568 OTP_EXT_VOLT,
569 FLASH_TEST_MODE1,
570 FLASH_TEST_MODE0,
571 FLASH_TEST_VOLT,
572 `ifdef ANALOGSIM
573 '0,
574 `else
575 CC2,
576 `endif
577 `ifdef ANALOGSIM
578 '0,
579 `else
580 CC1,
581 `endif
582 USB_N,
583 USB_P,
584 POR_N
585 }),
586
587 .mio_pad_io ({
588 IOR13,
589 IOR12,
590 IOR11,
591 IOR10,
592 IOR7,
593 IOR6,
594 IOR5,
595 IOR4,
596 IOR3,
597 IOR2,
598 IOR1,
599 IOR0,
600 IOC12,
601 IOC11,
602 IOC10,
603 IOC9,
604 IOC8,
605 IOC7,
606 IOC6,
607 IOC5,
608 IOC4,
609 IOC3,
610 IOC2,
611 IOC1,
612 IOC0,
613 IOB12,
614 IOB11,
615 IOB10,
616 IOB9,
617 IOB8,
618 IOB7,
619 IOB6,
620 IOB5,
621 IOB4,
622 IOB3,
623 IOB2,
624 IOB1,
625 IOB0,
626 IOA8,
627 IOA7,
628 IOA6,
629 IOA5,
630 IOA4,
631 `ifdef ANALOGSIM
632 '0,
633 `else
634 IOA3,
635 `endif
636 `ifdef ANALOGSIM
637 '0,
638 `else
639 IOA2,
640 `endif
641 IOA1,
642 IOA0
643 }),
644
645 // Core-facing
646 .dio_in_o ({
647 dio_in[DioSysrstCtrlAonFlashWpL],
648 dio_in[DioSysrstCtrlAonEcRstL],
649 dio_in[DioSpiDeviceCsb],
650 dio_in[DioSpiDeviceSck],
651 dio_in[DioSpiDeviceSd3],
652 dio_in[DioSpiDeviceSd2],
653 dio_in[DioSpiDeviceSd1],
654 dio_in[DioSpiDeviceSd0],
655 dio_in[DioSpiHost0Csb],
656 dio_in[DioSpiHost0Sck],
657 dio_in[DioSpiHost0Sd3],
658 dio_in[DioSpiHost0Sd2],
659 dio_in[DioSpiHost0Sd1],
660 dio_in[DioSpiHost0Sd0],
661 manual_in_otp_ext_volt,
662 manual_in_flash_test_mode1,
663 manual_in_flash_test_mode0,
664 manual_in_flash_test_volt,
665 manual_in_cc2,
666 manual_in_cc1,
667 manual_in_usb_n,
668 manual_in_usb_p,
669 manual_in_por_n
670 }),
671 .dio_out_i ({
672 dio_out[DioSysrstCtrlAonFlashWpL],
673 dio_out[DioSysrstCtrlAonEcRstL],
674 dio_out[DioSpiDeviceCsb],
675 dio_out[DioSpiDeviceSck],
676 dio_out[DioSpiDeviceSd3],
677 dio_out[DioSpiDeviceSd2],
678 dio_out[DioSpiDeviceSd1],
679 dio_out[DioSpiDeviceSd0],
680 dio_out[DioSpiHost0Csb],
681 dio_out[DioSpiHost0Sck],
682 dio_out[DioSpiHost0Sd3],
683 dio_out[DioSpiHost0Sd2],
684 dio_out[DioSpiHost0Sd1],
685 dio_out[DioSpiHost0Sd0],
686 manual_out_otp_ext_volt,
687 manual_out_flash_test_mode1,
688 manual_out_flash_test_mode0,
689 manual_out_flash_test_volt,
690 manual_out_cc2,
691 manual_out_cc1,
692 manual_out_usb_n,
693 manual_out_usb_p,
694 manual_out_por_n
695 }),
696 .dio_oe_i ({
697 dio_oe[DioSysrstCtrlAonFlashWpL],
698 dio_oe[DioSysrstCtrlAonEcRstL],
699 dio_oe[DioSpiDeviceCsb],
700 dio_oe[DioSpiDeviceSck],
701 dio_oe[DioSpiDeviceSd3],
702 dio_oe[DioSpiDeviceSd2],
703 dio_oe[DioSpiDeviceSd1],
704 dio_oe[DioSpiDeviceSd0],
705 dio_oe[DioSpiHost0Csb],
706 dio_oe[DioSpiHost0Sck],
707 dio_oe[DioSpiHost0Sd3],
708 dio_oe[DioSpiHost0Sd2],
709 dio_oe[DioSpiHost0Sd1],
710 dio_oe[DioSpiHost0Sd0],
711 manual_oe_otp_ext_volt,
712 manual_oe_flash_test_mode1,
713 manual_oe_flash_test_mode0,
714 manual_oe_flash_test_volt,
715 manual_oe_cc2,
716 manual_oe_cc1,
717 manual_oe_usb_n,
718 manual_oe_usb_p,
719 manual_oe_por_n
720 }),
721 .dio_attr_i ({
722 dio_attr[DioSysrstCtrlAonFlashWpL],
723 dio_attr[DioSysrstCtrlAonEcRstL],
724 dio_attr[DioSpiDeviceCsb],
725 dio_attr[DioSpiDeviceSck],
726 dio_attr[DioSpiDeviceSd3],
727 dio_attr[DioSpiDeviceSd2],
728 dio_attr[DioSpiDeviceSd1],
729 dio_attr[DioSpiDeviceSd0],
730 dio_attr[DioSpiHost0Csb],
731 dio_attr[DioSpiHost0Sck],
732 dio_attr[DioSpiHost0Sd3],
733 dio_attr[DioSpiHost0Sd2],
734 dio_attr[DioSpiHost0Sd1],
735 dio_attr[DioSpiHost0Sd0],
736 manual_attr_otp_ext_volt,
737 manual_attr_flash_test_mode1,
738 manual_attr_flash_test_mode0,
739 manual_attr_flash_test_volt,
740 manual_attr_cc2,
741 manual_attr_cc1,
742 manual_attr_usb_n,
743 manual_attr_usb_p,
744 manual_attr_por_n
745 }),
746
747 .mio_in_o (mio_in[46:0]),
748 .mio_out_i (mio_out[46:0]),
749 .mio_oe_i (mio_oe[46:0]),
750 .mio_attr_i (mio_attr[46:0]),
751 .mio_in_raw_o (mio_in_raw[46:0])
752 );
753
754
755
756
757
758 //////////////////////////////////
759 // AST - Common for all targets //
760 //////////////////////////////////
761
762 // pwrmgr interface
763 pwrmgr_pkg::pwr_ast_req_t base_ast_pwr;
764 pwrmgr_pkg::pwr_ast_rsp_t ast_base_pwr;
765
766 // assorted ast status
767 ast_pkg::ast_pwst_t ast_pwst;
768 ast_pkg::ast_pwst_t ast_pwst_h;
769
770 // TLUL interface
771 tlul_pkg::tl_h2d_t base_ast_bus;
772 tlul_pkg::tl_d2h_t ast_base_bus;
773
774 // synchronization clocks / rests
775 clkmgr_pkg::clkmgr_out_t clkmgr_aon_clocks;
776 rstmgr_pkg::rstmgr_out_t rstmgr_aon_resets;
777
778 // external clock
779 logic ext_clk;
780
781 // monitored clock
782 logic sck_monitor;
783
784 // observe interface
785 logic [7:0] fla_obs;
786 logic [7:0] otp_obs;
787 ast_pkg::ast_obs_ctrl_t obs_ctrl;
788
789 // otp power sequence
790 otp_ctrl_pkg::otp_ast_req_t otp_ctrl_otp_ast_pwr_seq;
791 otp_ctrl_pkg::otp_ast_rsp_t otp_ctrl_otp_ast_pwr_seq_h;
792
793 logic usb_ref_pulse;
794 logic usb_ref_val;
795
796 // adc
797 ast_pkg::adc_ast_req_t adc_req;
798 ast_pkg::adc_ast_rsp_t adc_rsp;
799
800 // entropy source interface
801 // The entropy source pacakge definition should eventually be moved to es
802 entropy_src_pkg::entropy_src_rng_req_t es_rng_req;
803 entropy_src_pkg::entropy_src_rng_rsp_t es_rng_rsp;
804 logic es_rng_fips;
805
806 // entropy distribution network
807 edn_pkg::edn_req_t ast_edn_edn_req;
808 edn_pkg::edn_rsp_t ast_edn_edn_rsp;
809
810 // alerts interface
811 ast_pkg::ast_alert_rsp_t ast_alert_rsp;
812 ast_pkg::ast_alert_req_t ast_alert_req;
813
814 // Flash connections
815 prim_mubi_pkg::mubi4_t flash_bist_enable;
816 logic flash_power_down_h;
817 logic flash_power_ready_h;
818
819 // clock bypass req/ack
820 prim_mubi_pkg::mubi4_t io_clk_byp_req;
821 prim_mubi_pkg::mubi4_t io_clk_byp_ack;
822 prim_mubi_pkg::mubi4_t all_clk_byp_req;
823 prim_mubi_pkg::mubi4_t all_clk_byp_ack;
824 prim_mubi_pkg::mubi4_t hi_speed_sel;
825 prim_mubi_pkg::mubi4_t div_step_down_req;
826
827 // DFT connections
828 logic scan_en;
829 lc_ctrl_pkg::lc_tx_t dft_en;
830 pinmux_pkg::dft_strap_test_req_t dft_strap_test;
831
832 // Debug connections
833 logic [ast_pkg::Ast2PadOutWidth-1:0] ast2pinmux;
834 logic [ast_pkg::Pad2AstInWidth-1:0] pad2ast;
835
836 // Jitter enable
837 prim_mubi_pkg::mubi4_t jen;
838
839 // reset domain connections
840 import rstmgr_pkg::PowerDomains;
841 import rstmgr_pkg::DomainAonSel;
842 import rstmgr_pkg::Domain0Sel;
843
844 // Memory configuration connections
845 ast_pkg::spm_rm_t ast_ram_1p_cfg;
846 ast_pkg::spm_rm_t ast_rf_cfg;
847 ast_pkg::spm_rm_t ast_rom_cfg;
848 ast_pkg::dpm_rm_t ast_ram_2p_fcfg;
849 ast_pkg::dpm_rm_t ast_ram_2p_lcfg;
850
851 prim_ram_1p_pkg::ram_1p_cfg_t ram_1p_cfg;
852 prim_ram_2p_pkg::ram_2p_cfg_t spi_ram_2p_cfg;
853 prim_ram_1p_pkg::ram_1p_cfg_t usb_ram_1p_cfg;
854 prim_rom_pkg::rom_cfg_t rom_cfg;
855
856 // conversion from ast structure to memory centric structures
857 0/1 ==> assign ram_1p_cfg = '{
858 ram_cfg: '{
859 test: ast_ram_1p_cfg.test,
860 cfg_en: ast_ram_1p_cfg.marg_en,
861 cfg: ast_ram_1p_cfg.marg
862 },
863 rf_cfg: '{
864 test: ast_rf_cfg.test,
865 cfg_en: ast_rf_cfg.marg_en,
866 cfg: ast_rf_cfg.marg
867 }
868 };
869
870 0/1 ==> assign usb_ram_1p_cfg = '{
871 ram_cfg: '{
872 test: ast_ram_1p_cfg.test,
873 cfg_en: ast_ram_1p_cfg.marg_en,
874 cfg: ast_ram_1p_cfg.marg
875 },
876 rf_cfg: '{
877 test: ast_rf_cfg.test,
878 cfg_en: ast_rf_cfg.marg_en,
879 cfg: ast_rf_cfg.marg
880 }
881 };
882
883 // this maps as follows:
884 // assign spi_ram_2p_cfg = {10'h000, ram_2p_cfg_i.a_ram_lcfg, ram_2p_cfg_i.b_ram_lcfg};
885 assign spi_ram_2p_cfg = '{
886 a_ram_lcfg: '{
887 test: ast_ram_2p_lcfg.test_a,
888 cfg_en: ast_ram_2p_lcfg.marg_en_a,
889 cfg: ast_ram_2p_lcfg.marg_a
890 },
891 b_ram_lcfg: '{
892 test: ast_ram_2p_lcfg.test_b,
893 cfg_en: ast_ram_2p_lcfg.marg_en_b,
894 cfg: ast_ram_2p_lcfg.marg_b
895 },
896 default: '0
897 };
898
899 0/1 ==> assign rom_cfg = '{
900 test: ast_rom_cfg.test,
901 cfg_en: ast_rom_cfg.marg_en,
902 cfg: ast_rom_cfg.marg
903 };
904
905 // unused cfg bits
906 logic unused_ram_cfg;
907 0/1 ==> assign unused_ram_cfg = ^ast_ram_2p_fcfg;
908
909 //////////////////////////////////
910 // AST - Custom for targets //
911 //////////////////////////////////
912
913
914 1/1 assign ast_base_pwr.main_pok = ast_pwst.main_pok;
Tests: T1 T2 T3
915
916 logic [rstmgr_pkg::PowerDomains-1:0] por_n;
917 1/1 assign por_n = {ast_pwst.main_pok, ast_pwst.aon_pok};
Tests: T1 T2 T3
918
919
920 logic [ast_pkg::UsbCalibWidth-1:0] usb_io_pu_cal;
921
922 // external clock comes in at a fixed position
923 1/1 assign ext_clk = mio_in_raw[MioPadIoc6];
Tests: T6 T28 T29
924
925 1/1 assign pad2ast = `PAD2AST_WIRES ;
Tests: T1 T2 T3
926
927 // AST does not use all clocks / resets forwarded to it
928 logic unused_slow_clk_en;
929 0/1 ==> assign unused_slow_clk_en = base_ast_pwr.slow_clk_en;
930
931 logic unused_pwr_clamp;
932 1/1 assign unused_pwr_clamp = base_ast_pwr.pwr_clamp;
Tests: T1 T2 T3
933
934 logic usb_diff_rx_obs;
935
936
937 prim_mubi_pkg::mubi4_t ast_init_done;
938
939 ast #(
940 .EntropyStreams(ast_pkg::EntropyStreams),
941 .AdcChannels(ast_pkg::AdcChannels),
942 .AdcDataWidth(ast_pkg::AdcDataWidth),
943 .UsbCalibWidth(ast_pkg::UsbCalibWidth),
944 .Ast2PadOutWidth(ast_pkg::Ast2PadOutWidth),
945 .Pad2AstInWidth(ast_pkg::Pad2AstInWidth)
946 ) u_ast (
947 // external POR
948 .por_ni ( manual_in_por_n ),
949
950 // USB IO Pull-up Calibration Setting
951 .usb_io_pu_cal_o ( usb_io_pu_cal ),
952
953 // adc
954 .adc_a0_ai ( CC1 ),
955 .adc_a1_ai ( CC2 ),
956
957 // Direct short to PAD
958 .ast2pad_t0_ao ( IOA2 ),
959 .ast2pad_t1_ao ( IOA3 ),
960 // clocks and resets supplied for detection
961 .sns_clks_i ( clkmgr_aon_clocks ),
962 .sns_rsts_i ( rstmgr_aon_resets ),
963 .sns_spi_ext_clk_i ( sck_monitor ),
964 // tlul
965 .tl_i ( base_ast_bus ),
966 .tl_o ( ast_base_bus ),
967 // init done indication
968 .ast_init_done_o ( ast_init_done ),
969 // buffered clocks & resets
970 .clk_ast_tlul_i (clkmgr_aon_clocks.clk_io_div4_infra),
971 .clk_ast_adc_i (clkmgr_aon_clocks.clk_aon_peri),
972 .clk_ast_alert_i (clkmgr_aon_clocks.clk_io_div4_secure),
973 .clk_ast_es_i (clkmgr_aon_clocks.clk_main_secure),
974 .clk_ast_rng_i (clkmgr_aon_clocks.clk_main_secure),
975 .clk_ast_usb_i (clkmgr_aon_clocks.clk_usb_peri),
976 .rst_ast_tlul_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
977 .rst_ast_adc_ni (rstmgr_aon_resets.rst_lc_aon_n[rstmgr_pkg::DomainAonSel]),
978 .rst_ast_alert_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]),
979 .rst_ast_es_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
980 .rst_ast_rng_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]),
981 .rst_ast_usb_ni (rstmgr_aon_resets.rst_usb_n[rstmgr_pkg::Domain0Sel]),
982 .clk_ast_ext_i ( ext_clk ),
983
984 // pok test for FPGA
985 .vcc_supp_i ( 1'b1 ),
986 .vcaon_supp_i ( 1'b1 ),
987 .vcmain_supp_i ( 1'b1 ),
988 .vioa_supp_i ( 1'b1 ),
989 .viob_supp_i ( 1'b1 ),
990 // pok
991 .ast_pwst_o ( ast_pwst ),
992 .ast_pwst_h_o ( ast_pwst_h ),
993 // main regulator
994 .main_env_iso_en_i ( base_ast_pwr.pwr_clamp_env ),
995 .main_pd_ni ( base_ast_pwr.main_pd_n ),
996 // pdm control (flash)/otp
997 .flash_power_down_h_o ( flash_power_down_h ),
998 .flash_power_ready_h_o ( flash_power_ready_h ),
999 .otp_power_seq_i ( otp_ctrl_otp_ast_pwr_seq ),
1000 .otp_power_seq_h_o ( otp_ctrl_otp_ast_pwr_seq_h ),
1001 // system source clock
1002 .clk_src_sys_en_i ( base_ast_pwr.core_clk_en ),
1003 // need to add function in clkmgr
1004 .clk_src_sys_jen_i ( jen ),
1005 .clk_src_sys_o ( ast_base_clks.clk_sys ),
1006 .clk_src_sys_val_o ( ast_base_pwr.core_clk_val ),
1007 // aon source clock
1008 .clk_src_aon_o ( ast_base_clks.clk_aon ),
1009 .clk_src_aon_val_o ( ast_base_pwr.slow_clk_val ),
1010 // io source clock
1011 .clk_src_io_en_i ( base_ast_pwr.io_clk_en ),
1012 .clk_src_io_o ( ast_base_clks.clk_io ),
1013 .clk_src_io_val_o ( ast_base_pwr.io_clk_val ),
1014 .clk_src_io_48m_o ( div_step_down_req ),
1015 // usb source clock
1016 .usb_ref_pulse_i ( usb_ref_pulse ),
1017 .usb_ref_val_i ( usb_ref_val ),
1018 .clk_src_usb_en_i ( base_ast_pwr.usb_clk_en ),
1019 .clk_src_usb_o ( ast_base_clks.clk_usb ),
1020 .clk_src_usb_val_o ( ast_base_pwr.usb_clk_val ),
1021 // adc
1022 .adc_pd_i ( adc_req.pd ),
1023 .adc_chnsel_i ( adc_req.channel_sel ),
1024 .adc_d_o ( adc_rsp.data ),
1025 .adc_d_val_o ( adc_rsp.data_valid ),
1026 // rng
1027 .rng_en_i ( es_rng_req.rng_enable ),
1028 .rng_fips_i ( es_rng_fips ),
1029 .rng_val_o ( es_rng_rsp.rng_valid ),
1030 .rng_b_o ( es_rng_rsp.rng_b ),
1031 // entropy
1032 .entropy_rsp_i ( ast_edn_edn_rsp ),
1033 .entropy_req_o ( ast_edn_edn_req ),
1034 // alerts
1035 .alert_rsp_i ( ast_alert_rsp ),
1036 .alert_req_o ( ast_alert_req ),
1037 // dft
1038 .dft_strap_test_i ( dft_strap_test ),
1039 .lc_dft_en_i ( dft_en ),
1040 .fla_obs_i ( fla_obs ),
1041 .otp_obs_i ( otp_obs ),
1042 .otm_obs_i ( '0 ),
1043 .usb_obs_i ( usb_diff_rx_obs ),
1044 .obs_ctrl_o ( obs_ctrl ),
1045 // pinmux related
1046 .padmux2ast_i ( pad2ast ),
1047 .ast2padmux_o ( ast2pinmux ),
1048 .mux_iob_sel_o ( mux_iob_sel ),
1049 .ext_freq_is_96m_i ( hi_speed_sel ),
1050 .all_clk_byp_req_i ( all_clk_byp_req ),
1051 .all_clk_byp_ack_o ( all_clk_byp_ack ),
1052 .io_clk_byp_req_i ( io_clk_byp_req ),
1053 .io_clk_byp_ack_o ( io_clk_byp_ack ),
1054 .flash_bist_en_o ( flash_bist_enable ),
1055 // Memory configuration connections
1056 .dpram_rmf_o ( ast_ram_2p_fcfg ),
1057 .dpram_rml_o ( ast_ram_2p_lcfg ),
1058 .spram_rm_o ( ast_ram_1p_cfg ),
1059 .sprgf_rm_o ( ast_rf_cfg ),
1060 .sprom_rm_o ( ast_rom_cfg ),
1061 // scan
1062 .dft_scan_md_o ( scanmode ),
1063 .scan_shift_en_o ( scan_en ),
1064 .scan_reset_no ( scan_rst_n )
1065 );
1066
1067
1068
1069
1070 //////////////////////////////////
1071 // Manual Pad / Signal Tie-offs //
1072 //////////////////////////////////
1073
1074 assign manual_out_por_n = 1'b0;
1075 assign manual_oe_por_n = 1'b0;
1076
1077 assign manual_out_cc1 = 1'b0;
1078 assign manual_oe_cc1 = 1'b0;
1079 assign manual_out_cc2 = 1'b0;
1080 assign manual_oe_cc2 = 1'b0;
1081
1082 assign manual_out_flash_test_mode0 = 1'b0;
1083 assign manual_oe_flash_test_mode0 = 1'b0;
1084 assign manual_out_flash_test_mode1 = 1'b0;
1085 assign manual_oe_flash_test_mode1 = 1'b0;
1086 assign manual_out_flash_test_volt = 1'b0;
1087 assign manual_oe_flash_test_volt = 1'b0;
1088 assign manual_out_otp_ext_volt = 1'b0;
1089 assign manual_oe_otp_ext_volt = 1'b0;
1090
1091 // Enable schmitt trigger on POR for better signal integrity.
1092 assign manual_attr_por_n = '{schmitt_en: 1'b1, pull_en: 1'b1, pull_select: 1'b1, default: '0};
1093
1094 // These pad attributes are controlled through sensor_ctrl. Update the description of
1095 // `MANUAL_PAD_ATTR` in `sensor_ctrl.hjson` when you change or extend the mapping below.
1096 prim_pad_wrapper_pkg::pad_attr_t [3:0] sensor_ctrl_manual_pad_attr;
1097 1/1 assign manual_attr_cc1 = sensor_ctrl_manual_pad_attr[0];
Tests: T20 T21 T22
1098 1/1 assign manual_attr_cc2 = sensor_ctrl_manual_pad_attr[1];
Tests: T20 T21 T22
1099 1/1 assign manual_attr_flash_test_mode0 = sensor_ctrl_manual_pad_attr[2];
Tests: T20 T21 T22
1100 1/1 assign manual_attr_flash_test_mode1 = sensor_ctrl_manual_pad_attr[3];
Tests: T20 T21 T22
1101
1102 // These pad attributes are currently tied off permanently (these are supply pads).
1103 assign manual_attr_flash_test_volt = '0;
1104 assign manual_attr_otp_ext_volt = '0;
1105
1106 logic unused_manual_sigs;
1107 1/1 assign unused_manual_sigs = ^{
Tests: T4 T30 T6
1108 manual_in_cc2,
1109 manual_in_cc1,
1110 manual_in_flash_test_volt,
1111 manual_in_flash_test_mode0,
1112 manual_in_flash_test_mode1,
1113 manual_in_otp_ext_volt
1114 };
1115
1116 ///////////////////////////////
1117 // Differential USB Receiver //
1118 ///////////////////////////////
1119
1120 // TODO: generalize this USB mux code and align with other tops.
1121
1122 // Connect the D+ pad
1123 // Note that we use two pads in parallel for the D+ channel to meet electrical specifications.
1124 1/1 assign dio_in[DioUsbdevUsbDp] = manual_in_usb_p;
Tests: T4 T30 T6
1125 1/1 assign manual_out_usb_p = dio_out[DioUsbdevUsbDp];
Tests: T4 T6 T7
1126 1/1 assign manual_oe_usb_p = dio_oe[DioUsbdevUsbDp];
Tests: T16 T17 T18
1127 1/1 assign manual_attr_usb_p = dio_attr[DioUsbdevUsbDp];
Tests: T1 T2 T3
1128
1129 // Connect the D- pads
1130 // Note that we use two pads in parallel for the D- channel to meet electrical specifications.
1131 1/1 assign dio_in[DioUsbdevUsbDn] = manual_in_usb_n;
Tests: T4 T6 T7
1132 1/1 assign manual_out_usb_n = dio_out[DioUsbdevUsbDn];
Tests: T4 T6 T7
1133 1/1 assign manual_oe_usb_n = dio_oe[DioUsbdevUsbDn];
Tests: T6 T16 T17
1134 1/1 assign manual_attr_usb_n = dio_attr[DioUsbdevUsbDn];
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut
| Total | Covered | Percent |
|---|
| Conditions | 2 | 2 | 100.00 |
| Logical | 2 | 2 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 79
EXPRESSION (tb.dut.top_earlgrey.u_pwrmgr_aon.pwr_rst_o.reset_cause == LowPwrEntry)
-----------------------------------1-----------------------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T5,T6,T23 |
Toggle Coverage for Instance : tb.dut
| Total | Covered | Percent |
| Totals |
66 |
64 |
96.97 |
| Total Bits |
132 |
130 |
98.48 |
| Total Bits 0->1 |
66 |
66 |
100.00 |
| Total Bits 1->0 |
66 |
64 |
96.97 |
| | | |
| Ports |
66 |
64 |
96.97 |
| Port Bits |
132 |
130 |
98.48 |
| Port Bits 0->1 |
66 |
66 |
100.00 |
| Port Bits 1->0 |
66 |
64 |
96.97 |
Port Details
| Name | Toggle | Toggle 1->0 | Tests | Toggle 0->1 | Tests | Direction | Exclude Annotation |
| POR_N |
Yes |
Yes |
T29,T36,T37 |
Yes |
T1,T2,T3 |
INOUT |
|
| USB_P |
Yes |
Yes |
T4,T30,T6 |
Yes |
T4,T6,T7 |
INOUT |
|
| USB_N |
Yes |
Yes |
T4,T7,T16 |
Yes |
T4,T6,T7 |
INOUT |
|
| CC1 |
No |
No |
|
Yes |
T6,T19,T20 |
INOUT |
|
| CC2 |
No |
No |
|
Yes |
T6,T19,T20 |
INOUT |
|
| FLASH_TEST_VOLT[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INOUT |
[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV. |
| FLASH_TEST_MODE0[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INOUT |
[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV. |
| FLASH_TEST_MODE1[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INOUT |
[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV. |
| OTP_EXT_VOLT[0:0] |
Excluded |
Excluded |
|
Excluded |
|
INOUT |
[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV. |
| SPI_HOST_D0 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T23,T8,T9 |
INOUT |
|
| SPI_HOST_D1 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T8,T9,T10 |
INOUT |
|
| SPI_HOST_D2 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T6,T8,T9 |
INOUT |
|
| SPI_HOST_D3 |
Yes |
Yes |
T8,T9,T10 |
Yes |
T6,T8,T9 |
INOUT |
|
| SPI_HOST_CLK |
Yes |
Yes |
T8,T9,T10 |
Yes |
T8,T9,T10 |
INOUT |
|
| SPI_HOST_CS_L |
Yes |
Yes |
T8,T9,T10 |
Yes |
T6,T8,T9 |
INOUT |
|
| SPI_DEV_D0 |
Yes |
Yes |
T5,T11,T8 |
Yes |
T5,T11,T8 |
INOUT |
|
| SPI_DEV_D1 |
Yes |
Yes |
T5,T11,T8 |
Yes |
T5,T11,T8 |
INOUT |
|
| SPI_DEV_D2 |
Yes |
Yes |
T5,T8,T9 |
Yes |
T5,T8,T9 |
INOUT |
|
| SPI_DEV_D3 |
Yes |
Yes |
T5,T8,T9 |
Yes |
T5,T8,T9 |
INOUT |
|
| SPI_DEV_CLK |
Yes |
Yes |
T5,T11,T8 |
Yes |
T5,T6,T11 |
INOUT |
|
| SPI_DEV_CS_L |
Yes |
Yes |
T5,T6,T23 |
Yes |
T6,T8,T9 |
INOUT |
|
| IOR8 |
Yes |
Yes |
T6,T12,T66 |
Yes |
T6,T23,T12 |
INOUT |
|
| IOR9 |
Yes |
Yes |
T6,T12,T67 |
Yes |
T6,T23,T12 |
INOUT |
|
| IOA0 |
Yes |
Yes |
T26,T27,T38 |
Yes |
T26,T27,T38 |
INOUT |
|
| IOA1 |
Yes |
Yes |
T26,T27,T38 |
Yes |
T26,T27,T38 |
INOUT |
|
| IOA2 |
Yes |
Yes |
T26,T27,T70 |
Yes |
T26,T27,T70 |
INOUT |
|
| IOA3 |
Yes |
Yes |
T26,T27,T39 |
Yes |
T26,T27,T39 |
INOUT |
|
| IOA4 |
Yes |
Yes |
T26,T27,T63 |
Yes |
T6,T26,T27 |
INOUT |
|
| IOA5 |
Yes |
Yes |
T26,T27,T63 |
Yes |
T26,T27,T63 |
INOUT |
|
| IOA6 |
Yes |
Yes |
T26,T27,T39 |
Yes |
T26,T27,T39 |
INOUT |
|
| IOA7 |
Yes |
Yes |
T11,T26,T27 |
Yes |
T6,T11,T26 |
INOUT |
|
| IOA8 |
Yes |
Yes |
T5,T26,T27 |
Yes |
T5,T26,T27 |
INOUT |
|
| IOB0 |
Yes |
Yes |
T25,T10,T69 |
Yes |
T25,T10,T19 |
INOUT |
|
| IOB1 |
Yes |
Yes |
T25,T10,T69 |
Yes |
T25,T10,T69 |
INOUT |
|
| IOB2 |
Yes |
Yes |
T10,T69,T131 |
Yes |
T6,T10,T69 |
INOUT |
|
| IOB3 |
Yes |
Yes |
T25,T12,T66 |
Yes |
T25,T12,T66 |
INOUT |
|
| IOB4 |
Yes |
Yes |
T25,T28,T132 |
Yes |
T25,T28,T132 |
INOUT |
|
| IOB5 |
Yes |
Yes |
T28,T132,T10 |
Yes |
T28,T132,T10 |
INOUT |
|
| IOB6 |
Yes |
Yes |
T27,T12,T66 |
Yes |
T27,T12,T66 |
INOUT |
|
| IOB7 |
Yes |
Yes |
T27,T12,T72 |
Yes |
T27,T12,T15 |
INOUT |
|
| IOB8 |
Yes |
Yes |
T27,T12,T66 |
Yes |
T27,T12,T66 |
INOUT |
|
| IOB9 |
Yes |
Yes |
T2,T27,T59 |
Yes |
T2,T27,T59 |
INOUT |
|
| IOB10 |
Yes |
Yes |
T2,T27,T59 |
Yes |
T2,T27,T59 |
INOUT |
|
| IOB11 |
Yes |
Yes |
T2,T27,T61 |
Yes |
T2,T27,T61 |
INOUT |
|
| IOB12 |
Yes |
Yes |
T2,T27,T61 |
Yes |
T2,T6,T27 |
INOUT |
|
| IOC0 |
Yes |
Yes |
T54,T55,T56 |
Yes |
T6,T19,T376 |
INOUT |
|
| IOC1 |
Yes |
Yes |
T244,T377,T378 |
Yes |
T6,T19,T244 |
INOUT |
|
| IOC2 |
Yes |
Yes |
T244,T377,T378 |
Yes |
T6,T19,T244 |
INOUT |
|
| IOC3 |
Yes |
Yes |
T68,T19,T296 |
Yes |
T68,T296,T362 |
INOUT |
|
| IOC4 |
Yes |
Yes |
T68,T6,T54 |
Yes |
T68,T54,T55 |
INOUT |
|
| IOC5 |
Yes |
Yes |
T32,T84,T85 |
Yes |
T6,T31,T32 |
INOUT |
|
| IOC6 |
Yes |
Yes |
T28,T29,T57 |
Yes |
T28,T29,T57 |
INOUT |
|
| IOC7 |
Yes |
Yes |
T12,T66,T67 |
Yes |
T4,T30,T6 |
INOUT |
|
| IOC8 |
Yes |
Yes |
T31,T32,T84 |
Yes |
T6,T31,T32 |
INOUT |
|
| IOC9 |
Yes |
Yes |
T27,T12,T66 |
Yes |
T6,T27,T12 |
INOUT |
|
| IOC10 |
Yes |
Yes |
T27,T33,T70 |
Yes |
T27,T33,T70 |
INOUT |
|
| IOC11 |
Yes |
Yes |
T27,T33,T70 |
Yes |
T6,T27,T33 |
INOUT |
|
| IOC12 |
Yes |
Yes |
T27,T33,T70 |
Yes |
T27,T33,T70 |
INOUT |
|
| IOR0 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
|
| IOR1 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
|
| IOR2 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
|
| IOR3 |
Yes |
Yes |
T34,T27,T29 |
Yes |
T6,T34,T27 |
INOUT |
|
| IOR4 |
Yes |
Yes |
T27,T29,T36 |
Yes |
T34,T27,T29 |
INOUT |
|
| IOR5 |
Yes |
Yes |
T27,T12,T14 |
Yes |
T27,T12,T14 |
INOUT |
|
| IOR6 |
Yes |
Yes |
T27,T12,T10 |
Yes |
T6,T27,T12 |
INOUT |
|
| IOR7 |
Yes |
Yes |
T27,T10,T39 |
Yes |
T27,T10,T39 |
INOUT |
|
| IOR10 |
Yes |
Yes |
T27,T10,T39 |
Yes |
T6,T27,T10 |
INOUT |
|
| IOR11 |
Yes |
Yes |
T27,T10,T39 |
Yes |
T6,T27,T10 |
INOUT |
|
| IOR12 |
Yes |
Yes |
T27,T39,T40 |
Yes |
T6,T27,T39 |
INOUT |
|
| IOR13 |
Yes |
Yes |
T27,T66,T67 |
Yes |
T27,T12,T66 |
INOUT |
|
