ALERT_HANDLER Simulation Results

Sunday December 31 2023 20:02:18 UTC

GitHub Revision: `a9c19f09f3`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 36521940887861431083267591129785326983863798057293121812910170439117479843669

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	alert_handler_smoke	1.052m	3.704ms	50	50	100.00
V1	csr_hw_reset	alert_handler_csr_hw_reset	6.310s	76.193us	5	5	100.00
V1	csr_rw	alert_handler_csr_rw	9.190s	512.386us	20	20	100.00
V1	csr_bit_bash	alert_handler_csr_bit_bash	5.820m	22.834ms	5	5	100.00
V1	csr_aliasing	alert_handler_csr_aliasing	5.537m	18.538ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	alert_handler_csr_mem_rw_with_rand_reset	7.100s	70.465us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	alert_handler_csr_rw	9.190s	512.386us	20	20	100.00
		alert_handler_csr_aliasing	5.537m	18.538ms	5	5	100.00
V1		TOTAL			105	105	100.00
V2	esc_accum	alert_handler_esc_alert_accum	4.635m	20.555ms	50	50	100.00
V2	esc_timeout	alert_handler_esc_intr_timeout	1.227m	3.026ms	50	50	100.00
V2	entropy	alert_handler_entropy	47.079m	173.971ms	50	50	100.00
V2	sig_int_fail	alert_handler_sig_int_fail	1.326m	4.413ms	48	50	96.00
V2	clk_skew	alert_handler_smoke	1.052m	3.704ms	50	50	100.00
V2	random_alerts	alert_handler_random_alerts	1.189m	2.579ms	50	50	100.00
V2	random_classes	alert_handler_random_classes	1.212m	1.297ms	50	50	100.00
V2	ping_timeout	alert_handler_ping_timeout	10.458m	62.432ms	50	50	100.00
V2	lpg	alert_handler_lpg	50.991m	222.035ms	50	50	100.00
		alert_handler_lpg_stub_clk	49.583m	846.338ms	50	50	100.00
V2	stress_all	alert_handler_stress_all	1.094h	78.581ms	49	50	98.00
V2	alert_handler_entropy_stress_test	alert_handler_entropy_stress	51.830s	4.404ms	20	20	100.00
V2	alert_handler_alert_accum_saturation	alert_handler_alert_accum_saturation	4.360s	194.243us	20	20	100.00
V2	intr_test	alert_handler_intr_test	2.370s	33.009us	50	50	100.00
V2	tl_d_oob_addr_access	alert_handler_tl_errors	31.000s	5.126ms	20	20	100.00
V2	tl_d_illegal_access	alert_handler_tl_errors	31.000s	5.126ms	20	20	100.00
V2	tl_d_outstanding_access	alert_handler_csr_hw_reset	6.310s	76.193us	5	5	100.00
		alert_handler_csr_rw	9.190s	512.386us	20	20	100.00
		alert_handler_csr_aliasing	5.537m	18.538ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.420s	1.442ms	20	20	100.00
V2	tl_d_partial_access	alert_handler_csr_hw_reset	6.310s	76.193us	5	5	100.00
		alert_handler_csr_rw	9.190s	512.386us	20	20	100.00
		alert_handler_csr_aliasing	5.537m	18.538ms	5	5	100.00
		alert_handler_same_csr_outstanding	48.420s	1.442ms	20	20	100.00
V2		TOTAL			627	630	99.52
V2S	shadow_reg_update_error	alert_handler_shadow_reg_errors	5.453m	5.688ms	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	alert_handler_shadow_reg_errors	5.453m	5.688ms	20	20	100.00
V2S	shadow_reg_storage_error	alert_handler_shadow_reg_errors	5.453m	5.688ms	20	20	100.00
V2S	shadowed_reset_glitch	alert_handler_shadow_reg_errors	5.453m	5.688ms	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	alert_handler_shadow_reg_errors_with_csr_rw	19.133m	32.836ms	20	20	100.00
V2S	tl_intg_err	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
		alert_handler_tl_intg_err	1.379m	1.302ms	20	20	100.00
V2S	sec_cm_bus_integrity	alert_handler_tl_intg_err	1.379m	1.302ms	20	20	100.00
V2S	sec_cm_config_shadow	alert_handler_shadow_reg_errors	5.453m	5.688ms	20	20	100.00
V2S	sec_cm_ping_timer_config_regwen	alert_handler_smoke	1.052m	3.704ms	50	50	100.00
V2S	sec_cm_alert_config_regwen	alert_handler_smoke	1.052m	3.704ms	50	50	100.00
V2S	sec_cm_alert_loc_config_regwen	alert_handler_smoke	1.052m	3.704ms	50	50	100.00
V2S	sec_cm_class_config_regwen	alert_handler_smoke	1.052m	3.704ms	50	50	100.00
V2S	sec_cm_alert_intersig_diff	alert_handler_sig_int_fail	1.326m	4.413ms	48	50	96.00
V2S	sec_cm_lpg_intersig_mubi	alert_handler_lpg	50.991m	222.035ms	50	50	100.00
V2S	sec_cm_esc_intersig_diff	alert_handler_sig_int_fail	1.326m	4.413ms	48	50	96.00
V2S	sec_cm_alert_rx_intersig_bkgn_chk	alert_handler_entropy	47.079m	173.971ms	50	50	100.00
V2S	sec_cm_esc_tx_intersig_bkgn_chk	alert_handler_entropy	47.079m	173.971ms	50	50	100.00
V2S	sec_cm_esc_timer_fsm_sparse	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_sparse	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_local_esc	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_ping_timer_fsm_local_esc	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_esc_timer_fsm_global_esc	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_accu_ctr_redun	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_esc_timer_ctr_redun	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_ping_timer_ctr_redun	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S	sec_cm_ping_timer_lfsr_redun	alert_handler_sec_cm	55.760s	1.392ms	5	5	100.00
V2S		TOTAL			65	65	100.00
V3	stress_all_with_rand_reset	alert_handler_stress_all_with_rand_reset	2.241h	585.294ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			847	850	99.65

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	15	15	13	86.67
V2S	4	4	4	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.49	99.99	98.68	91.69	100.00	100.00	99.38	99.72

Failure Buckets

UVM_ERROR (alert_handler_scoreboard.sv:250) [scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (* [*] vs * [*]) Interrupt class_c, is_local_err *, local_alert_type LocalEscIntFail

has 3 failures:

Test alert_handler_sig_int_fail has 2 failures.

2.alert_handler_sig_int_fail.80007408603237346628830293126832162557611455376892444183920349186226119111987
Line 259, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/2.alert_handler_sig_int_fail/latest/run.log

  UVM_ERROR @ 348905124 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 348905124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.alert_handler_sig_int_fail.84372347024102545795008138315737943226028887370971536738804779879497973744417
Line 256, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/35.alert_handler_sig_int_fail/latest/run.log

  UVM_ERROR @ 394061818 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 394061818 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test alert_handler_stress_all has 1 failures.

27.alert_handler_stress_all.39120460767955807308551665628613991726979362399972026479197854290774423566320
Line 259, in log /container/opentitan-public/scratch/os_regression/alert_handler-sim-vcs/27.alert_handler_stress_all/latest/run.log

  UVM_ERROR @ 1839605026 ps: (alert_handler_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed cfg.intr_vif.pins[class_i] === intr_en[class_i] (0x0 [0] vs 0x1 [1]) Interrupt class_c, is_local_err 1, local_alert_type LocalEscIntFail
  UVM_INFO @ 1839605026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---