Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.72	100.00	93.62		70.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.56	100.00	97.78		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.56	100.00	97.78		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.39	100.00	97.78	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T11 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T11 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T11 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T14 T13 T24 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T14 T13 T24 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T14 T13 T24 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T14 T13 T24 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T14 T9 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T14 T9 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T3 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T3 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T3 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T3 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
194        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T35 T36 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T3 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T3 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T3 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T3 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T3 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
211        1/1                    state_d = IdleSt;
           Tests:       T37 T38 T39 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T38 T39 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T38 T39 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T3 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T3 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T3 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T3 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T3 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T3 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
229        1/1                    state_d = IdleSt;
           Tests:       T24 T40 T41 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T40 T41 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T24 T40 T41 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T3 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T3 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T3 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T3 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T3 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T3 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
245        1/1                    state_d = IdleSt;
           Tests:       T42 T38 T43 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T42 T38 T43 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T42 T38 T43 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T3 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T3 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T3 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T3 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T3 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T11 T13 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	44	93.62
Logical	47	44	93.62
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Covered	T44
1	1	1	Covered	T2,T3,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T32,T14
1	0	1	Covered	T3,T13,T33
1	1	0	Covered	T12,T14,T13
1	1	1	Covered	T12,T14,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T13
0	1	Covered	T14,T13,T24
1	0	Covered	T29,T45,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T13
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T29,T45,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T13
1	0	Covered	T46
1	1	Covered	T14,T13,T24

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T32
1	Covered	T3,T33,T47

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T11
1	Covered	T14,T13,T26

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T32,T33

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T32
1	Covered	T2,T11,T13

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T11

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T11

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T12,T14,T13

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T4,T6,T10
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T12,T14,T13
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T34,T36,T48
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T37,T38,T39
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T24,T40,T41
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T42,T38,T43
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T2,T11,T13
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T12,T14,T9
TimeoutSt->Phase0St	172	Covered	T14,T13,T24

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T13,T24
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T9
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T35,T36
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T11,T32
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T37,T38,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T11,T32
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T40,T41
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T11,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T42,T38,T43
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T11,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T11,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	976	0	0
CheckAccumTrig0_A	2147483647	2213	0	0
CheckAccumTrig1_A	2147483647	118	0	0
CheckClr_A	2147483647	1065	0	0
CheckEn_A	2147483647	1179781972	0	0
CheckPhase0_A	2147483647	2549	0	0
CheckPhase1_A	2147483647	2507	0	0
CheckPhase2_A	2147483647	2456	0	0
CheckPhase3_A	2147483647	2418	0	0
CheckTimeout0_A	2147483647	3542	0	0
CheckTimeoutSt1_A	2147483647	427169	0	0
CheckTimeoutSt2_A	2147483647	3158	0	0
CheckTimeoutStTrig_A	2147483647	263	0	0
ErrorStAllEscAsserted_A	2147483647	5908	0	0
ErrorStIsTerminal_A	2147483647	4828	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	976	0	0
T4	77740	105	0	0
T5	187140	0	0	0
T6	0	186	0	0
T9	254440	0	0	0
T10	0	228	0	0
T11	56892	0	0	0
T12	124864	0	0	0
T13	108428	0	0	0
T14	88860	0	0	0
T32	125464	0	0	0
T33	98104	0	0	0
T47	83980	0	0	0
T49	0	233	0	0
T50	0	224	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2213	0	0
T1	905	1	0	0
T2	24696	5	0	0
T3	3868	1	0	0
T4	77740	0	0	0
T11	56892	3	0	0
T12	124864	0	0	0
T13	108428	4	0	0
T14	88860	0	0	0
T24	0	3	0	0
T25	0	1	0	0
T27	0	5	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	125464	1	0	0
T33	98104	2	0	0
T42	0	15	0	0
T47	62985	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	4	0	0
T54	0	3	0	0
T55	0	1	0	0
T56	0	5	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	118	0	0
T7	105181	0	0	0
T10	41637	0	0	0
T15	47695	0	0	0
T29	64024	2	0	0
T30	70800	0	0	0
T31	0	2	0	0
T35	30246	1	0	0
T42	77912	0	0	0
T45	0	1	0	0
T51	66533	0	0	0
T52	30014	0	0	0
T53	37255	0	0	0
T58	0	1	0	0
T59	39681	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	1155	0	0	0
T76	16015	0	0	0
T77	4451	0	0	0
T78	893275	0	0	0
T79	612486	0	0	0
T80	149939	0	0	0
T81	14719	0	0	0
T82	941000	0	0	0
T83	28621	0	0	0
T84	121958	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1065	0	0
T2	24696	4	0	0
T3	3868	0	0	0
T4	77740	0	0	0
T11	56892	2	0	0
T12	124864	0	0	0
T13	108428	1	0	0
T14	88860	0	0	0
T24	0	2	0	0
T27	0	2	0	0
T29	0	3	0	0
T32	125464	0	0	0
T33	98104	0	0	0
T40	0	4	0	0
T42	0	7	0	0
T45	0	2	0	0
T47	83980	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0
T85	0	1	0	0
T86	0	3	0	0
T87	0	1	0	0
T88	0	3	0	0
T89	0	1	0	0
T90	0	1	0	0
T91	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1179781972	0	0
T1	3620	2416	0	0
T2	24696	10649	0	0
T3	3868	2464	0	0
T4	804	508	0	0
T11	56892	43023	0	0
T12	124864	56060	0	0
T13	108428	17411	0	0
T14	88860	63492	0	0
T32	125464	95845	0	0
T33	98104	30801	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2549	0	0
T1	905	1	0	0
T2	24696	5	0	0
T3	3868	1	0	0
T4	77740	0	0	0
T11	56892	3	0	0
T12	124864	0	0	0
T13	108428	5	0	0
T14	88860	1	0	0
T15	0	2	0	0
T24	0	4	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	5	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	125464	1	0	0
T33	98104	2	0	0
T42	0	15	0	0
T47	62985	3	0	0
T51	0	1	0	0
T53	0	4	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2507	0	0
T1	905	1	0	0
T2	24696	5	0	0
T3	3868	1	0	0
T4	77740	0	0	0
T11	56892	3	0	0
T12	124864	0	0	0
T13	108428	5	0	0
T14	88860	1	0	0
T15	0	2	0	0
T24	0	4	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	5	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	125464	1	0	0
T33	98104	2	0	0
T42	0	15	0	0
T47	62985	3	0	0
T51	0	1	0	0
T53	0	4	0	0
T54	0	2	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2456	0	0
T1	905	1	0	0
T2	24696	5	0	0
T3	3868	1	0	0
T4	77740	0	0	0
T11	56892	3	0	0
T12	124864	0	0	0
T13	108428	5	0	0
T14	88860	1	0	0
T15	0	2	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	5	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	125464	1	0	0
T33	98104	2	0	0
T42	0	15	0	0
T47	62985	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	4	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2418	0	0
T1	905	1	0	0
T2	24696	5	0	0
T3	3868	1	0	0
T4	77740	0	0	0
T11	56892	3	0	0
T12	124864	0	0	0
T13	108428	5	0	0
T14	88860	1	0	0
T15	0	2	0	0
T24	0	3	0	0
T25	0	1	0	0
T26	0	1	0	0
T27	0	5	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	125464	1	0	0
T33	98104	2	0	0
T42	0	14	0	0
T47	62985	3	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	4	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3542	0	0
T5	187140	0	0	0
T9	254440	1	0	0
T12	124864	6	0	0
T13	108428	1	0	0
T14	88860	4	0	0
T15	0	5	0	0
T24	42404	4	0	0
T25	12792	0	0	0
T26	0	4	0	0
T29	0	3	0	0
T32	125464	0	0	0
T33	98104	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	83980	0	0	0
T56	0	4	0	0
T57	0	2	0	0
T85	0	1	0	0
T86	0	22	0	0
T88	0	4	0	0
T89	0	1	0	0
T90	0	2	0	0
T92	0	1	0	0
T93	0	2	0	0
T94	0	3	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	427169	0	0
T5	187140	0	0	0
T9	254440	161	0	0
T12	124864	883	0	0
T13	108428	39	0	0
T14	88860	141	0	0
T15	0	651	0	0
T24	42404	287	0	0
T25	12792	0	0	0
T26	0	444	0	0
T29	0	171	0	0
T32	125464	0	0	0
T33	98104	0	0	0
T42	0	44	0	0
T45	0	1	0	0
T47	83980	0	0	0
T56	0	149	0	0
T57	0	156	0	0
T85	0	71	0	0
T86	0	3432	0	0
T88	0	886	0	0
T89	0	439	0	0
T90	0	272	0	0
T92	0	48	0	0
T93	0	192	0	0
T94	0	258	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3158	0	0
T5	187140	0	0	0
T9	254440	1	0	0
T12	124864	5	0	0
T13	108428	0	0	0
T14	88860	2	0	0
T15	0	3	0	0
T24	42404	2	0	0
T25	12792	0	0	0
T26	0	3	0	0
T29	0	1	0	0
T32	125464	0	0	0
T33	98104	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T47	83980	0	0	0
T56	0	3	0	0
T57	0	1	0	0
T85	0	1	0	0
T86	0	13	0	0
T88	0	2	0	0
T90	0	2	0	0
T93	0	8	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	2	0	0
T97	0	1	0	0
T98	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	263	0	0
T5	46785	0	0	0
T6	62876	0	0	0
T7	105181	0	0	0
T9	63610	0	0	0
T10	83274	0	0	0
T13	27107	1	0	0
T14	22215	1	0	0
T15	143085	1	0	0
T24	21202	1	0	0
T25	6396	0	0	0
T26	95040	1	0	0
T27	80112	0	0	0
T28	15570	0	0	0
T29	128048	0	0	0
T30	212400	0	0	0
T33	24526	0	0	0
T38	0	3	0	0
T42	155824	0	0	0
T43	0	1	0	0
T47	20995	0	0	0
T51	199599	0	0	0
T52	60028	0	0	0
T59	0	1	0	0
T64	0	6	0	0
T75	1155	0	0	0
T86	0	4	0	0
T88	0	2	0	0
T89	0	1	0	0
T93	0	2	0	0
T98	0	1	0	0
T99	0	1	0	0
T100	0	2	0	0
T101	0	1	0	0
T102	0	11	0	0
T103	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	5908	0	0
T4	77740	654	0	0
T5	187140	0	0	0
T6	0	1258	0	0
T9	254440	0	0	0
T10	0	1357	0	0
T11	56892	0	0	0
T12	124864	0	0	0
T13	108428	0	0	0
T14	88860	0	0	0
T32	125464	0	0	0
T33	98104	0	0	0
T47	83980	0	0	0
T49	0	1322	0	0
T50	0	1317	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4828	0	0
T4	77740	534	0	0
T5	187140	0	0	0
T6	0	1018	0	0
T9	254440	0	0	0
T10	0	1117	0	0
T11	56892	0	0	0
T12	124864	0	0	0
T13	108428	0	0	0
T14	88860	0	0	0
T32	125464	0	0	0
T33	98104	0	0	0
T47	83980	0	0	0
T49	0	1082	0	0
T50	0	1077	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3620	3328	0	0
T2	24696	24452	0	0
T3	3868	3584	0	0
T4	292	0	0	0
T11	56892	56592	0	0
T12	124864	124596	0	0
T13	108428	108072	0	0
T14	88860	88512	0	0
T32	125464	125148	0	0
T33	98104	97748	0	0
T47	0	83768	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	3620	3328	0	0
T2	24696	24452	0	0
T3	3868	3584	0	0
T4	77740	25316	0	0
T11	56892	56592	0	0
T12	124864	124596	0	0
T13	108428	108072	0	0
T14	88860	88512	0	0
T32	125464	125148	0	0
T33	98104	97748	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T3 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T3 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T3 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T24 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T24 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T24 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T24 
172        1/1                    state_d    = Phase0St;
           Tests:       T26 T15 T86 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T26 T15 T86 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T26 T15 T86 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T26 T15 T86 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T24 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T24 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T14 T24 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T14 T24 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T3 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T3 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T3 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T3 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T3 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T106 T107 T108 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T106 T107 T108 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T106 T107 T108 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T3 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T3 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T3 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T3 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T3 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T3 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T109 T70 T110 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T109 T70 T110 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T109 T70 T110 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T3 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T3 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T3 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T3 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T3 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T3 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T3 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T39 T111 T109 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T39 T111 T109 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T39 T111 T109 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T3 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T3 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T3 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T3 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T3 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T3 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T3 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T43 T102 T112 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T43 T102 T112 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T43 T102 T112 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T3 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T3 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T3 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T3 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T3 T13 
260        1/1                  if (clr_i) begin
           Tests:       T2 T3 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T13 T24 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T3,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T3,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T24
1	0	1	Covered	T3,T33,T24
1	1	0	Covered	T14,T26,T27
1	1	1	Covered	T12,T14,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T24
0	1	Covered	T26,T15,T86
1	0	Covered	T59,T64,T67

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T59,T64,T67

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T24
1	0	Not Covered
1	1	Covered	T26,T15,T86

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T24
1	Covered	T3,T47,T55

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T47
1	Covered	T13,T26,T15

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T2,T24,T53

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T3,T13
1	Covered	T2,T53,T91

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T3,T13
Phase1St	198	Covered	T2,T3,T13
Phase2St	215	Covered	T2,T3,T13
Phase3St	233	Covered	T2,T3,T13
TerminalSt	249	Covered	T2,T3,T13
TimeoutSt	159	Covered	T12,T14,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T10
IdleSt->Phase0St	152	Covered	T2,T3,T13
IdleSt->TimeoutSt	159	Covered	T12,T14,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T106,T107,T108
Phase0St->Phase1St	198	Covered	T2,T3,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T109,T70,T110
Phase1St->Phase2St	215	Covered	T2,T3,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T39,T111,T109
Phase2St->Phase3St	233	Covered	T2,T3,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T43,T102,T112
Phase3St->TerminalSt	249	Covered	T2,T3,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T13,T24
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T14,T24
TimeoutSt->Phase0St	172	Covered	T26,T15,T86

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T3,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T26,T15,T86
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T106,T107,T108
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T3,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T13,T47
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T109,T70,T110
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T3,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T13,T47
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T39,T111,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T3,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T13,T47
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T43,T102,T112
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T3,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T13,T47
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T13,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T3,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653253201	227	0	0
CheckAccumTrig0_A	653253201	470	0	0
CheckAccumTrig1_A	653253201	16	0	0
CheckClr_A	653253201	230	0	0
CheckEn_A	653083950	317175423	0	0
CheckPhase0_A	653253201	552	0	0
CheckPhase1_A	653253201	547	0	0
CheckPhase2_A	653253201	538	0	0
CheckPhase3_A	653253201	527	0	0
CheckTimeout0_A	653253201	746	0	0
CheckTimeoutSt1_A	653253201	94930	0	0
CheckTimeoutSt2_A	653253201	655	0	0
CheckTimeoutStTrig_A	653253201	75	0	0
ErrorStAllEscAsserted_A	653253201	1447	0	0
ErrorStIsTerminal_A	653253201	1177	0	0
EscStateOut_A	653083129	653015626	0	0
u_state_regs_A	653253201	653070951	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	227	0	0
T4	19435	22	0	0
T5	46785	0	0	0
T6	0	44	0	0
T9	63610	0	0	0
T10	0	47	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	55	0	0
T50	0	59	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	470	0	0
T2	6174	2	0	0
T3	967	1	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	2	0	0
T14	22215	0	0	0
T24	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T47	20995	1	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	16	0	0
T59	39681	1	0	0
T64	0	1	0	0
T67	0	1	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	0	2	0	0
T72	0	1	0	0
T73	0	1	0	0
T74	0	1	0	0
T76	16015	0	0	0
T77	4451	0	0	0
T78	893275	0	0	0
T79	612486	0	0	0
T80	149939	0	0	0
T81	14719	0	0	0
T82	941000	0	0	0
T83	28621	0	0	0
T84	121958	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	230	0	0
T2	6174	2	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T24	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	2	0	0
T47	20995	0	0	0
T53	0	1	0	0
T56	0	1	0	0
T86	0	3	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083950	317175423	0	0
T1	905	602	0	0
T2	6174	851	0	0
T3	967	614	0	0
T4	201	127	0	0
T11	14223	14147	0	0
T12	31216	3053	0	0
T13	27107	2044	0	0
T14	22215	14646	0	0
T32	31366	31286	0	0
T33	24526	5193	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	552	0	0
T2	6174	2	0	0
T3	967	1	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	2	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T47	20995	1	0	0
T53	0	2	0	0
T55	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	547	0	0
T2	6174	2	0	0
T3	967	1	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	2	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T47	20995	1	0	0
T53	0	2	0	0
T55	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	538	0	0
T2	6174	2	0	0
T3	967	1	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	2	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T47	20995	1	0	0
T53	0	2	0	0
T55	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	527	0	0
T2	6174	2	0	0
T3	967	1	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	2	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	1	0	0
T26	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T47	20995	1	0	0
T53	0	2	0	0
T55	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	746	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	3	0	0
T13	27107	0	0	0
T14	22215	2	0	0
T15	0	1	0	0
T24	10601	1	0	0
T25	3198	0	0	0
T26	0	4	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T56	0	2	0	0
T86	0	4	0	0
T88	0	1	0	0
T90	0	2	0	0
T93	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	94930	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	450	0	0
T13	27107	0	0	0
T14	22215	94	0	0
T15	0	121	0	0
T24	10601	94	0	0
T25	3198	0	0	0
T26	0	444	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T56	0	79	0	0
T86	0	396	0	0
T88	0	45	0	0
T90	0	272	0	0
T93	0	146	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	655	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	3	0	0
T13	27107	0	0	0
T14	22215	2	0	0
T24	10601	1	0	0
T25	3198	0	0	0
T26	0	3	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T35	0	1	0	0
T47	20995	0	0	0
T56	0	2	0	0
T88	0	1	0	0
T90	0	2	0	0
T96	0	1	0	0
T97	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	75	0	0
T10	41637	0	0	0
T15	47695	1	0	0
T26	31680	1	0	0
T27	40056	0	0	0
T28	7785	0	0	0
T29	64024	0	0	0
T30	70800	0	0	0
T38	0	2	0	0
T42	77912	0	0	0
T43	0	1	0	0
T51	66533	0	0	0
T52	30014	0	0	0
T64	0	2	0	0
T86	0	4	0	0
T93	0	1	0	0
T98	0	1	0	0
T100	0	1	0	0
T102	0	3	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1447	0	0
T4	19435	174	0	0
T5	46785	0	0	0
T6	0	310	0	0
T9	63610	0	0	0
T10	0	342	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	307	0	0
T50	0	314	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1177	0	0
T4	19435	144	0	0
T5	46785	0	0	0
T6	0	250	0	0
T9	63610	0	0	0
T10	0	282	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	247	0	0
T50	0	254	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083129	653015626	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	73	0	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0
T47	0	20942	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	653070951	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	19435	6329	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T33 T47 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T33 T47 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T33 T47 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T13 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T13 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T13 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T13 
172        1/1                    state_d    = Phase0St;
           Tests:       T14 T13 T93 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T14 T13 T93 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T14 T13 T93 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T14 T13 T93 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T13 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T13 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T15 T86 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T15 T86 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T14 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T14 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T14 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T14 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T14 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T14 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T36 T113 T114 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T36 T113 T114 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T36 T113 T114 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T14 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T14 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T14 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T14 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T14 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T14 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T14 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T14 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T14 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T14 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T115 T116 T117 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T115 T116 T117 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T115 T116 T117 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T14 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T14 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T14 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T14 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T14 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T14 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T14 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T14 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T14 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T14 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T118 T119 T120 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T118 T119 T120 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T118 T119 T120 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T14 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T14 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T14 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T14 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T14 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T14 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T14 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T14 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T14 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T64 T120 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T64 T120 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T64 T120 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T14 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T14 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T14 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T14 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T14 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T14 T13 
260        1/1                  if (clr_i) begin
           Tests:       T2 T14 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T47 T27 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T12,T14
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T14

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T33,T47

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T13
1	0	1	Covered	T33,T47,T25
1	1	0	Covered	T13,T26,T27
1	1	1	Covered	T12,T14,T13

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T13
0	1	Covered	T14,T13,T93
1	0	Covered	T35,T61,T121

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T13
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T35,T61,T121

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T13
1	0	Not Covered
1	1	Covered	T14,T13,T93

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T14,T13
1	Covered	T47,T25,T27

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T13,T33
1	Covered	T14,T51,T42

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T14,T13,T47
1	Covered	T2,T33,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T14,T33
1	Covered	T13,T47,T27

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T14,T13

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T13,T47

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T14,T13,T33

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T47,T25,T27

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T14,T13
Phase1St	198	Covered	T2,T14,T13
Phase2St	215	Covered	T2,T14,T13
Phase3St	233	Covered	T2,T14,T13
TerminalSt	249	Covered	T2,T14,T13
TimeoutSt	159	Covered	T12,T14,T13

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T10
IdleSt->Phase0St	152	Covered	T2,T33,T47
IdleSt->TimeoutSt	159	Covered	T12,T14,T13
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T36,T113,T114
Phase0St->Phase1St	198	Covered	T2,T14,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T115,T116,T117
Phase1St->Phase2St	215	Covered	T2,T14,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T118,T119,T120
Phase2St->Phase3St	233	Covered	T2,T14,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T64,T120
Phase3St->TerminalSt	249	Covered	T2,T14,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T47,T27
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T15,T86
TimeoutSt->Phase0St	172	Covered	T14,T13,T93

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T33,T47
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T13
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T14,T13,T93
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T13
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T15,T86
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T36,T113,T114
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T14,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T14,T13
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T115,T116,T117
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T14,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T14,T13
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T118,T119,T120
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T14,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T14,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T64,T120
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T14,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T14,T13
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T47,T27
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T14,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653253201	243	0	0
CheckAccumTrig0_A	653253201	454	0	0
CheckAccumTrig1_A	653253201	23	0	0
CheckClr_A	653253201	195	0	0
CheckEn_A	653083950	307473113	0	0
CheckPhase0_A	653253201	527	0	0
CheckPhase1_A	653253201	519	0	0
CheckPhase2_A	653253201	514	0	0
CheckPhase3_A	653253201	511	0	0
CheckTimeout0_A	653253201	764	0	0
CheckTimeoutSt1_A	653253201	85739	0	0
CheckTimeoutSt2_A	653253201	673	0	0
CheckTimeoutStTrig_A	653253201	67	0	0
ErrorStAllEscAsserted_A	653253201	1490	0	0
ErrorStIsTerminal_A	653253201	1220	0	0
EscStateOut_A	653083129	653015626	0	0
u_state_regs_A	653253201	653070951	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	243	0	0
T4	19435	18	0	0
T5	46785	0	0	0
T6	0	53	0	0
T9	63610	0	0	0
T10	0	47	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	64	0	0
T50	0	61	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	454	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T25	0	1	0	0
T27	0	3	0	0
T32	31366	0	0	0
T33	24526	1	0	0
T42	0	4	0	0
T47	20995	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T56	0	2	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	23	0	0
T35	30246	1	0	0
T61	0	1	0	0
T98	27120	0	0	0
T99	27434	0	0	0
T121	0	1	0	0
T122	0	2	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	54446	0	0	0
T130	898278	0	0	0
T131	905075	0	0	0
T132	189764	0	0	0
T133	2930	0	0	0
T134	19095	0	0	0
T135	136177	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	195	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T27	0	2	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T36	0	1	0	0
T42	0	2	0	0
T47	20995	1	0	0
T54	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T88	0	1	0	0
T91	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083950	307473113	0	0
T1	905	606	0	0
T2	6174	4136	0	0
T3	967	618	0	0
T4	201	127	0	0
T11	14223	14147	0	0
T12	31216	9573	0	0
T13	27107	11267	0	0
T14	22215	7487	0	0
T32	31366	31286	0	0
T33	24526	1628	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	527	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	1	0	0
T25	0	1	0	0
T27	0	3	0	0
T32	31366	0	0	0
T33	24526	1	0	0
T42	0	4	0	0
T47	20995	2	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	519	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	1	0	0
T25	0	1	0	0
T27	0	3	0	0
T32	31366	0	0	0
T33	24526	1	0	0
T42	0	4	0	0
T47	20995	2	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	514	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	1	0	0
T25	0	1	0	0
T27	0	3	0	0
T32	31366	0	0	0
T33	24526	1	0	0
T42	0	4	0	0
T47	20995	2	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	511	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	1	0	0
T25	0	1	0	0
T27	0	3	0	0
T32	31366	0	0	0
T33	24526	1	0	0
T42	0	4	0	0
T47	20995	2	0	0
T51	0	1	0	0
T53	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	764	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	1	0	0
T13	27107	1	0	0
T14	22215	1	0	0
T15	0	2	0	0
T24	10601	0	0	0
T25	3198	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T57	0	1	0	0
T86	0	6	0	0
T88	0	1	0	0
T89	0	1	0	0
T93	0	1	0	0
T94	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	85739	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	148	0	0
T13	27107	39	0	0
T14	22215	1	0	0
T15	0	356	0	0
T24	10601	0	0	0
T25	3198	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T57	0	30	0	0
T86	0	977	0	0
T88	0	38	0	0
T89	0	439	0	0
T93	0	46	0	0
T94	0	49	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	673	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	1	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T15	0	2	0	0
T24	10601	0	0	0
T25	3198	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T35	0	1	0	0
T47	20995	0	0	0
T57	0	1	0	0
T86	0	6	0	0
T88	0	1	0	0
T94	0	1	0	0
T95	0	1	0	0
T96	0	1	0	0
T98	0	5	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	67	0	0
T5	46785	0	0	0
T6	31438	0	0	0
T9	63610	0	0	0
T13	27107	1	0	0
T14	22215	1	0	0
T24	10601	0	0	0
T25	3198	0	0	0
T26	31680	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T64	0	2	0	0
T89	0	1	0	0
T93	0	1	0	0
T102	0	2	0	0
T103	0	1	0	0
T105	0	1	0	0
T136	0	1	0	0
T137	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1490	0	0
T4	19435	147	0	0
T5	46785	0	0	0
T6	0	325	0	0
T9	63610	0	0	0
T10	0	330	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	346	0	0
T50	0	342	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1220	0	0
T4	19435	117	0	0
T5	46785	0	0	0
T6	0	265	0	0
T9	63610	0	0	0
T10	0	270	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	286	0	0
T50	0	282	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083129	653015626	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	73	0	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0
T47	0	20942	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	653070951	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	19435	6329	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T1 T2 T13 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T1 T2 T13 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T1 T2 T13 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T24 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T14 T24 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T14 T24 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T14 T24 
172        1/1                    state_d    = Phase0St;
           Tests:       T15 T56 T57 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T15 T56 T57 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T15 T56 T57 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T15 T56 T57 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T14 T24 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T14 T24 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T14 T24 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T14 T24 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T13 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T1 T2 T13 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T1 T2 T13 
190        1/1                  esc_state_o = Phase0;
           Tests:       T1 T2 T13 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T1 T2 T13 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T1 T2 T13 
194        1/1                    state_d = IdleSt;
           Tests:       T35 T138 T120 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T138 T120 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T138 T120 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T13 
198        1/1                    state_d = Phase1St;
           Tests:       T1 T2 T13 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T13 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T13 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T13 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T1 T2 T13 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T1 T2 T13 
207        1/1                  esc_state_o = Phase1;
           Tests:       T1 T2 T13 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T1 T2 T13 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T1 T2 T13 
211        1/1                    state_d = IdleSt;
           Tests:       T139 T109 T140 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T139 T109 T140 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T139 T109 T140 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T13 
215        1/1                    state_d = Phase2St;
           Tests:       T1 T2 T13 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T13 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T1 T2 T13 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T13 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T1 T2 T13 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T1 T2 T13 
224        1/1                  esc_state_o = Phase2;
           Tests:       T1 T2 T13 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T1 T2 T13 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T1 T2 T13 
229        1/1                    state_d = IdleSt;
           Tests:       T35 T141 T138 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T141 T138 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T35 T141 T138 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T13 
233        1/1                    state_d = Phase3St;
           Tests:       T1 T2 T13 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T13 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T1 T2 T13 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T1 T2 T13 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T1 T2 T13 
241        1/1                  esc_state_o = Phase3;
           Tests:       T1 T2 T13 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T1 T2 T13 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T1 T2 T13 
245        1/1                    state_d = IdleSt;
           Tests:       T109 T142 T143 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T109 T142 T143 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T109 T142 T143 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T1 T2 T13 
249        1/1                    state_d = TerminalSt;
           Tests:       T1 T2 T13 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T2 T13 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T1 T2 T13 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T13 
259        1/1                  esc_state_o = Terminal;
           Tests:       T1 T2 T13 
260        1/1                  if (clr_i) begin
           Tests:       T1 T2 T13 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T24 T42 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T2,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T12,T14
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T13

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T14,T24
1	0	1	Covered	T1,T2,T33
1	1	0	Covered	T12,T14,T26
1	1	1	Covered	T12,T14,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T14,T24
0	1	Covered	T15,T56,T57
1	0	Covered	T88,T90,T61

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T14,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T88,T90,T61

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T14,T24
1	0	Not Covered
1	1	Covered	T15,T56,T57

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T24,T27
1	Covered	T1,T13,T24

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T54,T56,T57

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T13
1	Covered	T24,T15,T42

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T13,T24
1	Covered	T2,T27,T42

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T42,T53

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T2,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T13,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T1,T2,T24

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T13
Phase1St	198	Covered	T1,T2,T13
Phase2St	215	Covered	T1,T2,T13
Phase3St	233	Covered	T1,T2,T13
TerminalSt	249	Covered	T1,T2,T13
TimeoutSt	159	Covered	T12,T14,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T10
IdleSt->Phase0St	152	Covered	T1,T2,T13
IdleSt->TimeoutSt	159	Covered	T12,T14,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T35,T138,T120
Phase0St->Phase1St	198	Covered	T1,T2,T13
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T139,T38,T109
Phase1St->Phase2St	215	Covered	T1,T2,T13
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T35,T141,T138
Phase2St->Phase3St	233	Covered	T1,T2,T13
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T109,T142,T143
Phase3St->TerminalSt	249	Covered	T1,T2,T13
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T24,T42
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T14,T24
TimeoutSt->Phase0St	172	Covered	T15,T56,T57

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T13
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T15,T56,T57
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T14,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T35,T138,T120
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T13
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T13,T24
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T139,T109,T140
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T13
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T13,T24
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T35,T141,T138
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T13
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T13,T24
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T109,T142,T143
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T13
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T13,T24
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T24,T42
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T13
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653253201	273	0	0
CheckAccumTrig0_A	653253201	479	0	0
CheckAccumTrig1_A	653253201	23	0	0
CheckClr_A	653253201	230	0	0
CheckEn_A	653083950	311706560	0	0
CheckPhase0_A	653253201	555	0	0
CheckPhase1_A	653253201	544	0	0
CheckPhase2_A	653253201	528	0	0
CheckPhase3_A	653253201	523	0	0
CheckTimeout0_A	653253201	718	0	0
CheckTimeoutSt1_A	653253201	103641	0	0
CheckTimeoutSt2_A	653253201	633	0	0
CheckTimeoutStTrig_A	653253201	62	0	0
ErrorStAllEscAsserted_A	653253201	1502	0	0
ErrorStIsTerminal_A	653253201	1232	0	0
EscStateOut_A	653083129	653015626	0	0
u_state_regs_A	653253201	653070951	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	273	0	0
T4	19435	41	0	0
T5	46785	0	0	0
T6	0	43	0	0
T9	63610	0	0	0
T10	0	63	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	65	0	0
T50	0	61	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	479	0	0
T1	905	1	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T24	0	2	0	0
T27	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	1	0	0
T144	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	23	0	0
T16	761834	0	0	0
T41	8057	0	0	0
T61	0	1	0	0
T64	0	1	0	0
T69	0	1	0	0
T71	0	1	0	0
T88	74180	1	0	0
T89	27945	0	0	0
T90	54333	1	0	0
T95	9913	0	0	0
T121	0	1	0	0
T124	0	1	0	0
T145	0	1	0	0
T146	0	2	0	0
T147	192280	0	0	0
T148	1236	0	0	0
T149	17031	0	0	0
T150	44911	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	230	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T24	0	2	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T35	0	2	0	0
T42	0	1	0	0
T47	20995	0	0	0
T54	0	1	0	0
T56	0	1	0	0
T88	0	1	0	0
T89	0	1	0	0
T90	0	3	0	0
T97	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083950	311706560	0	0
T1	905	610	0	0
T2	6174	2831	0	0
T3	967	622	0	0
T4	201	127	0	0
T11	14223	14147	0	0
T12	31216	18785	0	0
T13	27107	2064	0	0
T14	22215	19232	0	0
T32	31366	31286	0	0
T33	24526	23398	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	555	0	0
T1	905	1	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	2	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	544	0	0
T1	905	1	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	2	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	528	0	0
T1	905	1	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	2	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	523	0	0
T1	905	1	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	0	2	0	0
T27	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	3	0	0
T53	0	1	0	0
T54	0	2	0	0
T56	0	2	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	718	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	1	0	0
T13	27107	0	0	0
T14	22215	1	0	0
T15	0	1	0	0
T24	10601	1	0	0
T25	3198	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T86	0	5	0	0
T88	0	2	0	0
T92	0	1	0	0
T94	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	103641	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	142	0	0
T13	27107	0	0	0
T14	22215	46	0	0
T15	0	1	0	0
T24	10601	94	0	0
T25	3198	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T56	0	29	0	0
T57	0	126	0	0
T86	0	877	0	0
T88	0	803	0	0
T92	0	48	0	0
T94	0	209	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	633	0	0
T5	46785	0	0	0
T9	63610	0	0	0
T12	31216	1	0	0
T13	27107	0	0	0
T14	22215	1	0	0
T24	10601	1	0	0
T25	3198	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T35	0	1	0	0
T47	20995	0	0	0
T86	0	5	0	0
T88	0	1	0	0
T92	0	1	0	0
T94	0	2	0	0
T95	0	3	0	0
T96	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	62	0	0
T7	105181	0	0	0
T10	41637	0	0	0
T15	47695	1	0	0
T30	70800	0	0	0
T42	77912	0	0	0
T43	0	1	0	0
T51	66533	0	0	0
T52	30014	0	0	0
T53	37255	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	1	0	0
T64	0	5	0	0
T75	1155	0	0	0
T89	0	1	0	0
T98	0	1	0	0
T100	0	1	0	0
T103	0	1	0	0
T151	3976	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1502	0	0
T4	19435	156	0	0
T5	46785	0	0	0
T6	0	314	0	0
T9	63610	0	0	0
T10	0	352	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	351	0	0
T50	0	329	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1232	0	0
T4	19435	126	0	0
T5	46785	0	0	0
T6	0	254	0	0
T9	63610	0	0	0
T10	0	292	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	291	0	0
T50	0	269	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083129	653015626	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	73	0	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0
T47	0	20942	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	653070951	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	19435	6329	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

84                        logic [EscCntDw-1:0] thresh;
85         1/1            assign cnt_ge = (esc_cnt_o >= thresh);
           Tests:       T1 T2 T3 
86                      
87                        //////////////
88                        // Main FSM //
89                        //////////////
90                      
91                        logic [N_PHASES-1:0] phase_oh;
92                      
93                        // SEC_CM: ESC_TIMER.FSM.SPARSE
94                        // Encoding generated with:
95                        // $ ./util/design/sparse-fsm-encode.py -d 5 -m 8 -n 10 \
96                        //      -s 784905746 --language=sv
97                        //
98                        // Hamming distance histogram:
99                        //
100                       //  0: --
101                       //  1: --
102                       //  2: --
103                       //  3: --
104                       //  4: --
105                       //  5: |||||||||||||||||||| (46.43%)
106                       //  6: |||||||||||||||||||| (46.43%)
107                       //  7: ||| (7.14%)
108                       //  8: --
109                       //  9: --
110                       // 10: --
111                       //
112                       // Minimum Hamming distance: 5
113                       // Maximum Hamming distance: 7
114                       // Minimum Hamming weight: 3
115                       // Maximum Hamming weight: 9
116                       //
117                       localparam int StateWidth = 10;
118                       typedef enum logic [StateWidth-1:0] {
119                         IdleSt     = 10'b1011011010,
120                         TimeoutSt  = 10'b0000100110,
121                         Phase0St   = 10'b1110000101,
122                         Phase1St   = 10'b0101010100,
123                         Phase2St   = 10'b0000011001,
124                         Phase3St   = 10'b1001100001,
125                         TerminalSt = 10'b1101111111,
126                         FsmErrorSt = 10'b0111101000
127                       } state_e;
128                     
129                       logic fsm_error;
130                       state_e state_d, state_q;
131                     
132                       always_comb begin : p_fsm
133                         // default
134        1/1              state_d     = state_q;
           Tests:       T1 T2 T3 
135        1/1              esc_state_o = Idle;
           Tests:       T1 T2 T3 
136        1/1              cnt_en      = 1'b0;
           Tests:       T1 T2 T3 
137        1/1              cnt_clr     = 1'b0;
           Tests:       T1 T2 T3 
138        1/1              esc_trig_o  = 1'b0;
           Tests:       T1 T2 T3 
139        1/1              phase_oh    = '0;
           Tests:       T1 T2 T3 
140        1/1              thresh      = timeout_cyc_i;
           Tests:       T1 T2 T3 
141        1/1              fsm_error   = 1'b0;
           Tests:       T1 T2 T3 
142        1/1              latch_crashdump_o = 1'b0;
           Tests:       T1 T2 T3 
143                     
144        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
145                           // wait for an escalation trigger or an alert trigger
146                           // the latter will trigger an interrupt timeout
147                           IdleSt: begin
148        1/1                  cnt_clr = 1'b1;
           Tests:       T1 T2 T3 
149        1/1                  esc_state_o = Idle;
           Tests:       T1 T2 T3 
150                     
151        1/1                  if (accu_trig_i && en_i && !clr_i) begin
           Tests:       T1 T2 T3 
152        1/1                    state_d    = Phase0St;
           Tests:       T2 T11 T32 
153        1/1                    cnt_en     = 1'b1;
           Tests:       T2 T11 T32 
154        1/1                    esc_trig_o = 1'b1;
           Tests:       T2 T11 T32 
155                             // the counter is zero in this state. so if the
156                             // timeout count is zero (==disabled), cnt_ge will be true.
157        1/1                  end else if (timeout_en_i && !cnt_ge && en_i) begin
           Tests:       T1 T2 T3 
158        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T9 T24 
159        1/1                    state_d = TimeoutSt;
           Tests:       T12 T9 T24 
160                             end
                        MISSING_ELSE
161                           end
162                           // we are in interrupt timeout state
163                           // in case an escalation comes in, we immediately have to
164                           // switch over to the first escalation phase.
165                           // in case the interrupt timeout hits it's cycle count, we
166                           // also enter escalation phase0.
167                           // ongoing timeouts can always be cleared.
168                           TimeoutSt: begin
169        1/1                  esc_state_o = Timeout;
           Tests:       T12 T9 T24 
170                     
171        1/1                  if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
           Tests:       T12 T9 T24 
172        1/1                    state_d    = Phase0St;
           Tests:       T24 T29 T45 
173        1/1                    cnt_en     = 1'b1;
           Tests:       T24 T29 T45 
174        1/1                    cnt_clr    = 1'b1;
           Tests:       T24 T29 T45 
175        1/1                    esc_trig_o = 1'b1;
           Tests:       T24 T29 T45 
176                             // the timeout enable is connected to the irq state
177                             // if that is cleared, stop the timeout counter
178        1/1                  end else if (timeout_en_i) begin
           Tests:       T12 T9 T24 
179        1/1                    cnt_en  = 1'b1;
           Tests:       T12 T9 T24 
180                             end else begin
181        1/1                    state_d = IdleSt;
           Tests:       T12 T9 T24 
182        1/1                    cnt_clr = 1'b1;
           Tests:       T12 T9 T24 
183                             end
184                           end
185                           // note: autolocking the clear signal is done in the regfile
186                           Phase0St: begin
187        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T11 T32 
188        1/1                  phase_oh[0] = 1'b1;
           Tests:       T2 T11 T32 
189        1/1                  thresh      = phase_cyc_i[0];
           Tests:       T2 T11 T32 
190        1/1                  esc_state_o = Phase0;
           Tests:       T2 T11 T32 
191        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b00);
           Tests:       T2 T11 T32 
192                     
193        1/1                  if (clr_i) begin
           Tests:       T2 T11 T32 
194        1/1                    state_d = IdleSt;
           Tests:       T34 T48 T152 
195        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T48 T152 
196        1/1                    cnt_en  = 1'b0;
           Tests:       T34 T48 T152 
197        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T11 T32 
198        1/1                    state_d = Phase1St;
           Tests:       T2 T11 T32 
199        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T11 T32 
200        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T11 T32 
201                             end
                        MISSING_ELSE
202                           end
203                           Phase1St: begin
204        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T11 T32 
205        1/1                  phase_oh[1] = 1'b1;
           Tests:       T2 T11 T32 
206        1/1                  thresh      = phase_cyc_i[1];
           Tests:       T2 T11 T32 
207        1/1                  esc_state_o = Phase1;
           Tests:       T2 T11 T32 
208        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b01);
           Tests:       T2 T11 T32 
209                     
210        1/1                  if (clr_i) begin
           Tests:       T2 T11 T32 
211        1/1                    state_d = IdleSt;
           Tests:       T37 T38 T39 
212        1/1                    cnt_clr = 1'b1;
           Tests:       T37 T38 T39 
213        1/1                    cnt_en  = 1'b0;
           Tests:       T37 T38 T39 
214        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T11 T32 
215        1/1                    state_d = Phase2St;
           Tests:       T2 T11 T32 
216        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T11 T32 
217        1/1                    cnt_en  = 1'b1;
           Tests:       T2 T11 T32 
218                             end
                        MISSING_ELSE
219                           end
220                           Phase2St: begin
221        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T11 T32 
222        1/1                  phase_oh[2] = 1'b1;
           Tests:       T2 T11 T32 
223        1/1                  thresh      = phase_cyc_i[2];
           Tests:       T2 T11 T32 
224        1/1                  esc_state_o = Phase2;
           Tests:       T2 T11 T32 
225        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b10);
           Tests:       T2 T11 T32 
226                     
227                     
228        1/1                  if (clr_i) begin
           Tests:       T2 T11 T32 
229        1/1                    state_d = IdleSt;
           Tests:       T24 T40 T41 
230        1/1                    cnt_clr = 1'b1;
           Tests:       T24 T40 T41 
231        1/1                    cnt_en  = 1'b0;
           Tests:       T24 T40 T41 
232        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T11 T32 
233        1/1                    state_d = Phase3St;
           Tests:       T2 T11 T32 
234        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T11 T32 
235                             end
                        MISSING_ELSE
236                           end
237                           Phase3St: begin
238        1/1                  cnt_en      = 1'b1;
           Tests:       T2 T11 T32 
239        1/1                  phase_oh[3] = 1'b1;
           Tests:       T2 T11 T32 
240        1/1                  thresh      = phase_cyc_i[3];
           Tests:       T2 T11 T32 
241        1/1                  esc_state_o = Phase3;
           Tests:       T2 T11 T32 
242        1/1                  latch_crashdump_o = (crashdump_phase_i == 2'b11);
           Tests:       T2 T11 T32 
243                     
244        1/1                  if (clr_i) begin
           Tests:       T2 T11 T32 
245        1/1                    state_d = IdleSt;
           Tests:       T42 T38 T153 
246        1/1                    cnt_clr = 1'b1;
           Tests:       T42 T38 T153 
247        1/1                    cnt_en  = 1'b0;
           Tests:       T42 T38 T153 
248        1/1                  end else if (cnt_ge) begin
           Tests:       T2 T11 T32 
249        1/1                    state_d = TerminalSt;
           Tests:       T2 T11 T32 
250        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T11 T32 
251        1/1                    cnt_en  = 1'b0;
           Tests:       T2 T11 T32 
252                             end
                        MISSING_ELSE
253                           end
254                           // final, terminal state after escalation.
255                           // if clr is locked down, only a system reset
256                           // will get us out of this state
257                           TerminalSt: begin
258        1/1                  cnt_clr = 1'b1;
           Tests:       T2 T11 T32 
259        1/1                  esc_state_o = Terminal;
           Tests:       T2 T11 T32 
260        1/1                  if (clr_i) begin
           Tests:       T2 T11 T32 
261        1/1                    state_d = IdleSt;
           Tests:       T2 T11 T29 
262                             end
                        MISSING_ELSE
263                           end
264                           // error state, only reached if the FSM has been
265                           // glitched. in this state, we trigger all escalation
266                           // actions at once.
267                           FsmErrorSt: begin
268        1/1                  esc_state_o = FsmError;
           Tests:       T4 T6 T10 
269        1/1                  fsm_error = 1'b1;
           Tests:       T4 T6 T10 
270                           end
271                           // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272                           // catch glitches.
273                           default: begin
274                             state_d = FsmErrorSt;
275                             esc_state_o = FsmError;
276                             fsm_error = 1'b1;
277                           end
278                         endcase
279                     
280                         // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
281                         // if any of the duplicate counter pairs has an inconsistent state
282                         // we move into the terminal FSM error state.
283        1/1              if (accu_fail_i || cnt_error) begin
           Tests:       T1 T2 T3 
284        1/1                state_d = FsmErrorSt;
           Tests:       T4 T6 T10 
285        1/1                fsm_error = 1'b1;
           Tests:       T4 T6 T10 
286                         end
                        MISSING_ELSE
287                       end
288                     
289                       logic [N_ESC_SEV-1:0][N_PHASES-1:0] esc_map_oh;
290                       for (genvar k = 0; k < N_ESC_SEV; k++) begin : gen_phase_map
291                         // generate configuration mask for escalation enable signals
292        4/4              assign esc_map_oh[k] = N_ESC_SEV'(esc_en_i[k]) << esc_map_i[k];
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
293                         // mask reduce current phase state vector
294                         // SEC_CM: ESC_TIMER.FSM.GLOBAL_ESC
295        4/4              assign esc_sig_req_o[k] = |(esc_map_oh[k] & phase_oh) | fsm_error;
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
296                       end
297                     
298                       ///////////////////
299                       // FSM Registers //
300                       ///////////////////
301                     
302                       // The alert handler behaves differently than other comportable IP. I.e., instead of sending out
303                       // an alert signal, this condition is handled internally in the alert handler. The
304                       // EnableAlertTriggerSVA parameter is therefore set to 0.
305        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0):
305.1                   `ifdef SIMULATION                                   
305.2                       prim_sparse_fsm_flop #(                           
305.3                         .StateEnumT(state_e),                            
305.4                         .Width($bits(state_e)),                          
305.5                         .ResetValue($bits(state_e)'(IdleSt)),          
305.6                         .EnableAlertTriggerSVA(0), 
305.7                         .CustomForceName("state_q")          
305.8                       ) u_state_regs (                                        
305.9                         .clk_i   ( clk_i   ),                           
305.10                        .rst_ni  ( rst_ni ),                           
305.11                        .state_i ( state_d     ),                           
305.12                        .state_o (         )                            
305.13                      );                                                
305.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
305.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
305.16     1/1                state_q <= IdleSt;                                
           Tests:       T1 T2 T3 
305.17                      end else begin                                    
305.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
305.19                      end                                               
305.20                    end  
305.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
305.22                      else begin                                                                           
305.23                        `ifdef UVM                                                                               
305.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
305.25                                              "../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv", 305, "", 1);                                
305.26                  `else                                                                                    
305.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
305.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
305.29                  `endif                                                              
305.30                      end 
305.31                    `else                                               
305.32                      prim_sparse_fsm_flop #(                           
305.33                        .StateEnumT(state_e),                            
305.34                        .Width($bits(state_e)),                          
305.35                        .ResetValue($bits(state_e)'(IdleSt)),          
305.36                        .EnableAlertTriggerSVA(0)  
305.37                      ) u_state_regs (                                        
305.38                        .clk_i   ( clk_i   ),                           
305.39                        .rst_ni  ( rst_ni ),                           
305.40                        .state_i ( state_d     ),                           
305.41                        .state_o ( state_q     )                            
305.42                      );                                                
305.43                    `endif

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	44	97.78
Logical	45	44	97.78
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T11,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T11,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T11,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Covered	T44
1	1	1	Covered	T2,T11,T32

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T12,T32,T9
1	0	1	Covered	T13,T33,T30
1	1	0	Covered	T12,T14,T9
1	1	1	Covered	T12,T9,T24

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T12,T9,T24
0	1	Covered	T24,T88,T99
1	0	Covered	T29,T45,T31

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T12,T9,T24
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T29,T45,T31

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T12,T9,T24
1	0	Covered	T46
1	1	Covered	T24,T88,T99

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T32
1	Covered	T33,T29,T42

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T32
1	Covered	T13,T27,T29

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T11,T13
1	Covered	T32,T24,T30

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T32,T13,T33
1	Covered	T2,T11,T29

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T4,T6,T10

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T11,T32

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T11,T13,T24

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T11,T32

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T6,T10
1	0	Covered	T2,T11,T32

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T4,T6,T10
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T11,T32
Phase1St	198	Covered	T2,T11,T32
Phase2St	215	Covered	T2,T11,T32
Phase3St	233	Covered	T2,T11,T32
TerminalSt	249	Covered	T2,T11,T32
TimeoutSt	159	Covered	T12,T9,T24

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T4,T6,T10
IdleSt->Phase0St	152	Covered	T2,T11,T32
IdleSt->TimeoutSt	159	Covered	T12,T9,T24
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T34,T48,T152
Phase0St->Phase1St	198	Covered	T2,T11,T32
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T37,T38,T39
Phase1St->Phase2St	215	Covered	T2,T11,T32
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T24,T40,T41
Phase2St->Phase3St	233	Covered	T2,T11,T32
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T42,T38,T153
Phase3St->TerminalSt	249	Covered	T2,T11,T32
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T2,T11,T29
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T12,T9,T24
TimeoutSt->Phase0St	172	Covered	T24,T29,T45

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

144            unique case (state_q)
                      -1-  
145              // wait for an escalation trigger or an alert trigger
146              // the latter will trigger an interrupt timeout
147              IdleSt: begin
148                cnt_clr = 1'b1;
149                esc_state_o = Idle;
150        
151                if (accu_trig_i && en_i && !clr_i) begin
                   -2-  
152                  state_d    = Phase0St;
                     ==>
153                  cnt_en     = 1'b1;
154                  esc_trig_o = 1'b1;
155                // the counter is zero in this state. so if the
156                // timeout count is zero (==disabled), cnt_ge will be true.
157                end else if (timeout_en_i && !cnt_ge && en_i) begin
                            -3-  
158                  cnt_en  = 1'b1;
                     ==>
159                  state_d = TimeoutSt;
160                end
                   MISSING_ELSE
                   ==>
161              end
162              // we are in interrupt timeout state
163              // in case an escalation comes in, we immediately have to
164              // switch over to the first escalation phase.
165              // in case the interrupt timeout hits it's cycle count, we
166              // also enter escalation phase0.
167              // ongoing timeouts can always be cleared.
168              TimeoutSt: begin
169                esc_state_o = Timeout;
170        
171                if ((accu_trig_i && en_i && !clr_i) || (cnt_ge && timeout_en_i)) begin
                   -4-  
172                  state_d    = Phase0St;
                     ==>
173                  cnt_en     = 1'b1;
174                  cnt_clr    = 1'b1;
175                  esc_trig_o = 1'b1;
176                // the timeout enable is connected to the irq state
177                // if that is cleared, stop the timeout counter
178                end else if (timeout_en_i) begin
                            -5-  
179                  cnt_en  = 1'b1;
                     ==>
180                end else begin
181                  state_d = IdleSt;
                     ==>
182                  cnt_clr = 1'b1;
183                end
184              end
185              // note: autolocking the clear signal is done in the regfile
186              Phase0St: begin
187                cnt_en      = 1'b1;
188                phase_oh[0] = 1'b1;
189                thresh      = phase_cyc_i[0];
190                esc_state_o = Phase0;
191                latch_crashdump_o = (crashdump_phase_i == 2'b00);
192        
193                if (clr_i) begin
                   -6-  
194                  state_d = IdleSt;
                     ==>
195                  cnt_clr = 1'b1;
196                  cnt_en  = 1'b0;
197                end else if (cnt_ge) begin
                            -7-  
198                  state_d = Phase1St;
                     ==>
199                  cnt_clr = 1'b1;
200                  cnt_en  = 1'b1;
201                end
                   MISSING_ELSE
                   ==>
202              end
203              Phase1St: begin
204                cnt_en      = 1'b1;
205                phase_oh[1] = 1'b1;
206                thresh      = phase_cyc_i[1];
207                esc_state_o = Phase1;
208                latch_crashdump_o = (crashdump_phase_i == 2'b01);
209        
210                if (clr_i) begin
                   -8-  
211                  state_d = IdleSt;
                     ==>
212                  cnt_clr = 1'b1;
213                  cnt_en  = 1'b0;
214                end else if (cnt_ge) begin
                            -9-  
215                  state_d = Phase2St;
                     ==>
216                  cnt_clr = 1'b1;
217                  cnt_en  = 1'b1;
218                end
                   MISSING_ELSE
                   ==>
219              end
220              Phase2St: begin
221                cnt_en      = 1'b1;
222                phase_oh[2] = 1'b1;
223                thresh      = phase_cyc_i[2];
224                esc_state_o = Phase2;
225                latch_crashdump_o = (crashdump_phase_i == 2'b10);
226        
227        
228                if (clr_i) begin
                   -10-  
229                  state_d = IdleSt;
                     ==>
230                  cnt_clr = 1'b1;
231                  cnt_en  = 1'b0;
232                end else if (cnt_ge) begin
                            -11-  
233                  state_d = Phase3St;
                     ==>
234                  cnt_clr = 1'b1;
235                end
                   MISSING_ELSE
                   ==>
236              end
237              Phase3St: begin
238                cnt_en      = 1'b1;
239                phase_oh[3] = 1'b1;
240                thresh      = phase_cyc_i[3];
241                esc_state_o = Phase3;
242                latch_crashdump_o = (crashdump_phase_i == 2'b11);
243        
244                if (clr_i) begin
                   -12-  
245                  state_d = IdleSt;
                     ==>
246                  cnt_clr = 1'b1;
247                  cnt_en  = 1'b0;
248                end else if (cnt_ge) begin
                            -13-  
249                  state_d = TerminalSt;
                     ==>
250                  cnt_clr = 1'b1;
251                  cnt_en  = 1'b0;
252                end
                   MISSING_ELSE
                   ==>
253              end
254              // final, terminal state after escalation.
255              // if clr is locked down, only a system reset
256              // will get us out of this state
257              TerminalSt: begin
258                cnt_clr = 1'b1;
259                esc_state_o = Terminal;
260                if (clr_i) begin
                   -14-  
261                  state_d = IdleSt;
                     ==>
262                end
                   MISSING_ELSE
                   ==>
263              end
264              // error state, only reached if the FSM has been
265              // glitched. in this state, we trigger all escalation
266              // actions at once.
267              FsmErrorSt: begin
268                esc_state_o = FsmError;
                   ==>
269                fsm_error = 1'b1;
270              end
271              // SEC_CM: ESC_TIMER.FSM.LOCAL_ESC
272              // catch glitches.
273              default: begin
274                state_d = FsmErrorSt;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T11,T32
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T9,T24
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T24,T29,T45
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T12,T9,T24
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T12,T9,T24
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T34,T48,T152
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T11,T32
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T11,T32
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T37,T38,T39
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T11,T32
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T11,T32
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T24,T40,T41
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T11,T32
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T11,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T42,T38,T153
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T11,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T11,T32
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T2,T11,T29
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T11,T32
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T4,T6,T10

283            if (accu_fail_i || cnt_error) begin
               -1-  
284              state_d = FsmErrorSt;
                 ==>
285              fsm_error = 1'b1;
286            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T6,T10
0	Covered	T1,T2,T3

305          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, IdleSt, clk_i, rst_ni, 0)
             -1-                                                                                        
             ==>                                                                                        
             ==>                                                                                        

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	653253201	233	0	0
CheckAccumTrig0_A	653253201	810	0	0
CheckAccumTrig1_A	653253201	56	0	0
CheckClr_A	653253201	410	0	0
CheckEn_A	653083950	243426876	0	0
CheckPhase0_A	653253201	915	0	0
CheckPhase1_A	653253201	897	0	0
CheckPhase2_A	653253201	876	0	0
CheckPhase3_A	653253201	857	0	0
CheckTimeout0_A	653253201	1314	0	0
CheckTimeoutSt1_A	653253201	142859	0	0
CheckTimeoutSt2_A	653253201	1197	0	0
CheckTimeoutStTrig_A	653253201	59	0	0
ErrorStAllEscAsserted_A	653253201	1469	0	0
ErrorStIsTerminal_A	653253201	1199	0	0
EscStateOut_A	653083129	653015626	0	0
u_state_regs_A	653253201	653070951	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	233	0	0
T4	19435	24	0	0
T5	46785	0	0	0
T6	0	46	0	0
T9	63610	0	0	0
T10	0	71	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	49	0	0
T50	0	43	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	810	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	3	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T27	0	1	0	0
T29	0	2	0	0
T30	0	1	0	0
T32	31366	1	0	0
T33	24526	1	0	0
T42	0	5	0	0
T47	20995	0	0	0
T52	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	56	0	0
T7	105181	0	0	0
T10	41637	0	0	0
T15	47695	0	0	0
T29	64024	2	0	0
T30	70800	0	0	0
T31	0	2	0	0
T42	77912	0	0	0
T45	0	1	0	0
T51	66533	0	0	0
T52	30014	0	0	0
T53	37255	0	0	0
T58	0	1	0	0
T60	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T75	1155	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	410	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	2	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T24	0	1	0	0
T29	0	3	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T40	0	4	0	0
T42	0	3	0	0
T45	0	2	0	0
T47	20995	0	0	0
T85	0	1	0	0
T87	0	1	0	0
T88	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083950	243426876	0	0
T1	905	598	0	0
T2	6174	2831	0	0
T3	967	610	0	0
T4	201	127	0	0
T11	14223	582	0	0
T12	31216	24649	0	0
T13	27107	2036	0	0
T14	22215	22127	0	0
T32	31366	1987	0	0
T33	24526	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	915	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	3	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	31366	1	0	0
T33	24526	1	0	0
T42	0	5	0	0
T47	20995	0	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	897	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	3	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T24	0	1	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	31366	1	0	0
T33	24526	1	0	0
T42	0	5	0	0
T47	20995	0	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	876	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	3	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	31366	1	0	0
T33	24526	1	0	0
T42	0	5	0	0
T47	20995	0	0	0
T52	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	857	0	0
T2	6174	1	0	0
T3	967	0	0	0
T4	19435	0	0	0
T11	14223	3	0	0
T12	31216	0	0	0
T13	27107	1	0	0
T14	22215	0	0	0
T27	0	1	0	0
T29	0	4	0	0
T30	0	1	0	0
T32	31366	1	0	0
T33	24526	1	0	0
T42	0	4	0	0
T47	20995	0	0	0
T52	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1314	0	0
T5	46785	0	0	0
T9	63610	1	0	0
T12	31216	1	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	10601	2	0	0
T25	3198	0	0	0
T29	0	3	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	1	0	0
T45	0	1	0	0
T47	20995	0	0	0
T56	0	1	0	0
T85	0	1	0	0
T86	0	7	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	142859	0	0
T5	46785	0	0	0
T9	63610	161	0	0
T12	31216	143	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T15	0	173	0	0
T24	10601	99	0	0
T25	3198	0	0	0
T29	0	171	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	44	0	0
T45	0	1	0	0
T47	20995	0	0	0
T56	0	41	0	0
T85	0	71	0	0
T86	0	1182	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1197	0	0
T5	46785	0	0	0
T9	63610	1	0	0
T12	31216	1	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T15	0	1	0	0
T24	10601	1	0	0
T25	3198	0	0	0
T29	0	1	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T42	0	1	0	0
T47	20995	0	0	0
T56	0	1	0	0
T85	0	1	0	0
T86	0	7	0	0
T93	0	8	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	59	0	0
T6	31438	0	0	0
T15	47695	0	0	0
T24	10601	1	0	0
T25	3198	0	0	0
T26	31680	0	0	0
T27	40056	0	0	0
T28	7785	0	0	0
T29	64024	0	0	0
T30	70800	0	0	0
T38	0	1	0	0
T51	66533	0	0	0
T59	0	1	0	0
T64	0	2	0	0
T88	0	2	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T102	0	6	0	0
T104	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1469	0	0
T4	19435	177	0	0
T5	46785	0	0	0
T6	0	309	0	0
T9	63610	0	0	0
T10	0	333	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	318	0	0
T50	0	332	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	1199	0	0
T4	19435	147	0	0
T5	46785	0	0	0
T6	0	249	0	0
T9	63610	0	0	0
T10	0	273	0	0
T11	14223	0	0	0
T12	31216	0	0	0
T13	27107	0	0	0
T14	22215	0	0	0
T32	31366	0	0	0
T33	24526	0	0	0
T47	20995	0	0	0
T49	0	258	0	0
T50	0	272	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653083129	653015626	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	73	0	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0
T47	0	20942	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	653253201	653070951	0	0
T1	905	832	0	0
T2	6174	6113	0	0
T3	967	896	0	0
T4	19435	6329	0	0
T11	14223	14148	0	0
T12	31216	31149	0	0
T13	27107	27018	0	0
T14	22215	22128	0	0
T32	31366	31287	0	0
T33	24526	24437	0	0