Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.52			89.52

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_10_14/alert_handler-sim-vcs/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_esc_timer.u_prim_count	68.57			68.57
tb.dut.gen_classes[1].u_esc_timer.u_prim_count	68.57			68.57
tb.dut.gen_classes[2].u_esc_timer.u_prim_count	68.57			68.57
tb.dut.gen_classes[3].u_esc_timer.u_prim_count	68.57			68.57
tb.dut.u_ping_timer.u_prim_count_esc_cnt	100.00			100.00
tb.dut.u_ping_timer.u_prim_count_cnt	100.00			100.00
tb.dut.gen_classes[0].u_accu.u_prim_count	100.00			100.00
tb.dut.gen_classes[1].u_accu.u_prim_count	100.00			100.00
tb.dut.gen_classes[2].u_accu.u_prim_count	100.00			100.00
tb.dut.gen_classes[3].u_accu.u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.11	100.00	95.56		100.00	100.00	100.00	gen_classes[0].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.67	100.00	93.33		100.00	100.00	100.00	gen_classes[1].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.67	100.00	93.33		100.00	100.00	100.00	gen_classes[2].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
68.57			68.57

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.67	100.00	93.33		100.00	100.00	100.00	gen_classes[3].u_esc_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.30		100.00	100.00	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.u_ping_timer.u_prim_count_cnt

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.46	100.00	97.30		100.00	100.00	100.00	u_ping_timer

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[0].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[1].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[2].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00				100.00	gen_classes[3].u_accu

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : prim_count ( parameter Width=2,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=5,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_ping_timer.u_prim_count_esc_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	7	7	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=10,NumCnt=2 + Width=16,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=15,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
100.00	100.00

tb.dut.u_ping_timer.u_prim_count_cnt

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_classes[0].u_accu.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_classes[1].u_accu.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_classes[2].u_accu.u_prim_count

SCORE	TOGGLE
100.00	100.00

tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	9	9	100.00
Total Bits	108	108	100.00
Total Bits 0->1	54	54	100.00
Total Bits 1->0	54	54	100.00

Ports	9	9	100.00
Port Bits	108	108	100.00
Port Bits 0->1	54	54	100.00
Port Bits 1->0	54	54	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
set_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
set_cnt_i[15:0]	Yes	Yes	T3,T4,T11	Yes	T3,T4,T12	INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

---

Toggle Coverage for Module : prim_count ( parameter Width=32,ResetValue=0,EnableAlertTriggerSVA=0,PossibleActions=7,NumCnt=2 )
Toggle Coverage for Module self-instances :

SCORE	TOGGLE
68.57	68.57

tb.dut.gen_classes[0].u_esc_timer.u_prim_count

SCORE	TOGGLE
68.57	68.57

tb.dut.gen_classes[1].u_esc_timer.u_prim_count

SCORE	TOGGLE
68.57	68.57

tb.dut.gen_classes[2].u_esc_timer.u_prim_count

SCORE	TOGGLE
68.57	68.57

tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	140	96	68.57
Total Bits 0->1	70	48	68.57
Total Bits 1->0	70	48	68.57

Ports	8	7	87.50
Port Bits	140	96	68.57
Port Bits 0->1	70	48	68.57
Port Bits 1->0	70	48	68.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	140	96	68.57
Total Bits 0->1	70	48	68.57
Total Bits 1->0	70	48	68.57

Ports	8	7	87.50
Port Bits	140	96	68.57
Port Bits 0->1	70	48	68.57
Port Bits 1->0	70	48	68.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	INPUT
set_i	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	*T3,*T10,*T12	Yes	T3,T10,T12	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	140	96	68.57
Total Bits 0->1	70	48	68.57
Total Bits 1->0	70	48	68.57

Ports	8	7	87.50
Port Bits	140	96	68.57
Port Bits 0->1	70	48	68.57
Port Bits 1->0	70	48	68.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T2,T13,T5	Yes	T2,T13,T5	INPUT
set_i	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T2,T13,*T14	Yes	T2,T13,T14	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	140	96	68.57
Total Bits 0->1	70	48	68.57
Total Bits 1->0	70	48	68.57

Ports	8	7	87.50
Port Bits	140	96	68.57
Port Bits 0->1	70	48	68.57
Port Bits 1->0	70	48	68.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer.u_prim_count

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	140	96	68.57
Total Bits 0->1	70	48	68.57
Total Bits 1->0	70	48	68.57

Ports	8	7	87.50
Port Bits	140	96	68.57
Port Bits 0->1	70	48	68.57
Port Bits 1->0	70	48	68.57

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T2,T5,T15	Yes	T2,T5,T15	INPUT
set_i	Yes	Yes	T2,T15,T16	Yes	T2,T15,T16	INPUT
set_cnt_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T2,T15,T16	Yes	T2,T15,T16	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T2,T15,T6	Yes	T2,T15,T6	OUTPUT
cnt_after_commit_o[9:0]	Yes	Yes	T2,*T15,*T16	Yes	T2,T15,T16	OUTPUT
cnt_after_commit_o[31:10]	No	No		No		OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_esc_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	18	18	100.00
Total Bits 0->1	9	9	100.00
Total Bits 1->0	9	9	100.00

Ports	7	7	100.00
Port Bits	18	18	100.00
Port Bits 0->1	9	9	100.00
Port Bits 1->0	9	9	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T4,T7,T8	Yes	T4,T7,T8	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[1:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[1:0]	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
cnt_after_commit_o[1:0]	Yes	Yes	T4,T6,T7	Yes	T4,T6,T7	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

Toggle Coverage for Instance : tb.dut.u_ping_timer.u_prim_count_cnt

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	104	104	100.00
Total Bits 0->1	52	52	100.00
Total Bits 1->0	52	52	100.00

Ports	7	7	100.00
Port Bits	104	104	100.00
Port Bits 0->1	52	52	100.00
Port Bits 1->0	52	52	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
set_cnt_i[15:0]	Yes	Yes	T3,T4,T11	Yes	T3,T4,T12	INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[0].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	74	74	100.00
Total Bits 0->1	37	37	100.00
Total Bits 1->0	37	37	100.00

Ports	7	7	100.00
Port Bits	74	74	100.00
Port Bits 0->1	37	37	100.00
Port Bits 1->0	37	37	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T17,T11	Yes	T3,T17,T11	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[1].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	74	74	100.00
Total Bits 0->1	37	37	100.00
Total Bits 1->0	37	37	100.00

Ports	7	7	100.00
Port Bits	74	74	100.00
Port Bits 0->1	37	37	100.00
Port Bits 1->0	37	37	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T3,T10,T12	Yes	T3,T10,T12	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T2,T13,T14	Yes	T2,T13,T14	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[2].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	74	74	100.00
Total Bits 0->1	37	37	100.00
Total Bits 1->0	37	37	100.00

Ports	7	7	100.00
Port Bits	74	74	100.00
Port Bits 0->1	37	37	100.00
Port Bits 1->0	37	37	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T2,T3,T12	Yes	T2,T3,T12	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT

Toggle Coverage for Instance : tb.dut.gen_classes[3].u_accu.u_prim_count

	Total	Covered	Percent
Totals	7	7	100.00
Total Bits	74	74	100.00
Total Bits 0->1	37	37	100.00
Total Bits 1->0	37	37	100.00

Ports	7	7	100.00
Port Bits	74	74	100.00
Port Bits 0->1	37	37	100.00
Port Bits 1->0	37	37	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
set_i	Unreachable	Unreachable		Unreachable		INPUT
set_cnt_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
incr_en_i	Yes	Yes	T2,T13,T15	Yes	T2,T13,T15	INPUT
decr_en_i	Unreachable	Unreachable		Unreachable		INPUT
step_i[15:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[15:0]	Yes	Yes	T2,T13,T15	Yes	T2,T13,T15	OUTPUT
cnt_after_commit_o[15:0]	Yes	Yes	T2,T13,T15	Yes	T2,T13,T15	OUTPUT
err_o	Yes	Yes	T5,T6,T9	Yes	T5,T6,T9	OUTPUT