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Module Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_40

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_41

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_42

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00


Module Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_43

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.18 100.00 96.71 100.00 100.00 u_reg


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed
tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_40
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_41
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_42
tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_43
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T11 T12 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T11 T12 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T11 T12 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT161,T162,T163
11CoveredT2,T11,T12 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT164,T165,T161
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT2,T11,T12
110CoveredT161,T162,T163
111CoveredT2,T11,T12 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT2,T11,T12
1011CoveredT2,T11,T12
1101CoveredT164,T165,T161
1110Excluded VC_COV_UNR
1111CoveredT2,T11,T12 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT2,T11,T12
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT2,T11,T12
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT2,T11,T12
10CoveredT2,T11,T12
11CoveredT164,T165,T161 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT164,T165,T161
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T2,T11,T12 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T11,T12
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timeout_cyc_shadowed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T4 T11 T12 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T4 T11 T12 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T4 T11 T12 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T159,T160
11CoveredT4,T11,T12 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T159,T160
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT4,T11,T12
110CoveredT156,T159,T160
111CoveredT4,T11,T12 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT4,T11,T12
1011CoveredT4,T11,T12
1101CoveredT156,T158,T160
1110Excluded VC_COV_UNR
1111CoveredT4,T11,T12 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT4,T11,T12
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T9,T5 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT4,T9,T5 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT4,T9,T5
10CoveredT4,T9,T5
11CoveredT156,T158,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T159,T160
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T4,T9,T5
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T4,T11,T12
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_ping_timer_en_shadowed
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T158,T160
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T158,T160
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT156,T158,T160
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T160,T166
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT158,T160,T166 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T158,T160
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_0
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T167,T159
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T158,T167
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T167,T159
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT157,T158,T167
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT157,T158,T167 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T158,T167
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT160,T164,T168
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT160,T164,T168
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT160,T164,T168
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT159,T160,T164
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT159,T160,T164 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT160,T164,T168
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_2
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T160,T161
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T160,T161
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T160,T161
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T160,T165
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT158,T160,T165 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T160,T161
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_3
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT157,T159,T160
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T169,T159
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT157,T159,T160
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT159,T170,T171
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT159,T170,T171 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T169,T159
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_4
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT160,T164,T172
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT160,T164,T172
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT160,T164,T172
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT157,T160,T164
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT157,T160,T164 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT160,T164,T172
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_5
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT171,T173,T166
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T167,T171
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT171,T173,T166
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT157,T167,T171
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT157,T167,T171 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T167,T171
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_6
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT174,T173,T161
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT174,T173,T166
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT174,T173,T161
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT174,T171,T173
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT174,T171,T173 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT174,T173,T166
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_7
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT173,T165,T175
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T173,T164
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT173,T165,T175
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT157,T173,T164
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT157,T173,T164 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T173,T164
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_8
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT174,T166,T165
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT169,T174,T166
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT174,T166,T165
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T174,T166
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT158,T174,T166 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT169,T174,T166
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_9
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT173,T168,T165
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T173,T168
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT173,T168,T165
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT173,T168,T176
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT173,T168,T176 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T173,T168
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_10
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T167,T172
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T167,T177
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT156,T167,T172
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT156,T167,T160
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT156,T167,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T167,T177
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_11
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T164,T166
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T164,T166
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T164,T166
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT167,T164,T168
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT167,T164,T168 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T164,T166
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_12
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T174,T164
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T174,T164
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T174,T164
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT167,T174,T177
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT167,T174,T177 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T174,T164
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_13
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT160,T164,T161
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT160,T177,T164
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT160,T164,T161
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT160,T177,T164
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT160,T177,T164 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT160,T177,T164
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_14
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT169,T174,T168
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT169,T174,T164
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT169,T174,T168
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT174,T173,T164
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT174,T173,T164 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT169,T174,T164
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_15
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T159,T160
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T157,T159
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT156,T159,T160
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT156,T159,T160
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT156,T159,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T157,T159
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_16
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T160,T171
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T160,T171
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T160,T171
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T160,T166
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT158,T160,T166 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T160,T171
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_17
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT157,T167,T171
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T167,T171
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT157,T167,T171
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT167,T171,T173
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT167,T171,T173 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T167,T171
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_18
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT171,T166,T161
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT169,T171,T166
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT171,T166,T161
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT159,T171,T177
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT159,T171,T177 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT169,T171,T166
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_19
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T169,T159
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T169,T159
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT156,T169,T159
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT156,T158,T160
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT156,T158,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T169,T159
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_20
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT171,T176,T178
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT170,T171,T176
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT171,T176,T178
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT171,T164,T165
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT171,T164,T165 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT170,T171,T176
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_21
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T159,T160
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T159,T160
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T159,T160
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T159,T160
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT158,T159,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T159,T160
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_22
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T169,T159
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T169,T159
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T169,T159
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT169,T159,T178
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT169,T159,T178 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T169,T159
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_23
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T170,T171
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T167,T170
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T170,T171
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T167,T170
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT158,T167,T170 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T167,T170
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_24
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T174,T173
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T167,T174
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T174,T173
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T167,T174
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT158,T167,T174 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T167,T174
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_25
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T174,T173
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T174,T173
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T174,T173
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T167,T174
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT158,T167,T174 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T174,T173
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_26
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT166,T168,T165
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT169,T160,T177
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT166,T168,T165
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT160,T173,T168
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT160,T173,T168 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT169,T160,T177
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_27
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T159,T160
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T169,T159
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T159,T160
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T167,T159
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT158,T167,T159 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T169,T159
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_28
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T166,T168
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T169,T166
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T166,T168
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT169,T160,T166
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT169,T160,T166 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T169,T166
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_29
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T167,T160
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T158,T167
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T167,T160
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T167,T171
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT158,T167,T171 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T158,T167
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_30
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T159,T166
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T159,T166
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T159,T166
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT167,T159,T166
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT167,T159,T166 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T159,T166
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_31
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT174,T172,T179
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT174,T170,T172
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT174,T172,T179
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT174,T172,T161
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT174,T172,T161 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT174,T170,T172
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_32
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT157,T169,T160
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T169,T160
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT157,T169,T160
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT157,T167,T160
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT157,T167,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T169,T160
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_33
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T160,T164
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T160,T164
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T160,T164
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT167,T177,T164
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT167,T177,T164 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T160,T164
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_34
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT167,T171,T166
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT167,T171,T166
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT167,T171,T166
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT167,T171,T173
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT167,T171,T173 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT167,T171,T166
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_35
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T167,T159
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT158,T167,T169
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T167,T159
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT158,T167,T169
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT158,T167,T169 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT158,T167,T169
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_36
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT160,T174,T170
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT160,T174,T170
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT160,T174,T170
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT171,T173,T164
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT171,T173,T164 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT160,T174,T170
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_37
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT160,T174,T173
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT160,T174,T177
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT160,T174,T173
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT156,T157,T160
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT156,T157,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT160,T174,T177
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_38
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T160,T171
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T167,T169
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT156,T160,T171
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT156,T167,T160
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T3,T11 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T3,T11
10CoveredT1,T3,T11
11CoveredT156,T167,T160 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T167,T169
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T3,T11
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_39
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_40
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_40
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT156,T159,T163
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T159,T161
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT156,T159,T163
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT178,T163,T180
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT178,T163,T180 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T159,T161
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_40
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_40
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_41
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_41
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT171,T173,T164
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT169,T171,T177
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT171,T173,T164
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT171,T177,T173
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT171,T177,T173 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT169,T171,T177
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_41
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_41
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_42
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_42
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T174,T161
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT157,T158,T160
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T174,T161
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT157,T160,T174
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT157,T160,T174 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT157,T158,T160
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_42
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_42
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_43
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00


93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T38 T103 T155 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T38 T103 T155 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_43
TotalCoveredPercent
Conditions2525100.00
Logical2525100.00
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT158,T167,T170
11CoveredT1,T2,T3 

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT156,T158,T167
10CoveredT38,T103,T155 

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT158,T167,T170
111CoveredT1,T2,T3 

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable 

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTestsExclude Annotation
0111CoveredT1,T2,T3
1011CoveredT1,T2,T3
1101CoveredT156,T158,T167
1110Excluded VC_COV_UNR
1111CoveredT1,T2,T3 

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT1,T2,T3
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable 

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3 

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT156,T158,T167 

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT156,T158,T167
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_43
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00 



183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3 



100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T38,T103,T155
0 0 0 Covered T1,T2,T3

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_alert_en_shadowed_43
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00



Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 827 827 0 0
MubiIsNotYetSupported_A 678394440 677700103 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 827 827 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T4 1 1 0 0
T11 1 1 0 0
T12 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T32 1 1 0 0
T33 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 678394440 677700103 0 0
T1 905 832 0 0
T2 6174 6113 0 0
T3 967 896 0 0
T4 19435 6329 0 0
T11 14223 14148 0 0
T12 31216 31149 0 0
T13 27107 27018 0 0
T14 22215 22128 0 0
T32 31366 31287 0 0
T33 24526 24437 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%