Line Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T44 T45 T94
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T44 T45 T94
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Module :
prim_subreg_shadow
| Total | Covered | Percent |
|---|
| Conditions | 26 | 25 | 96.15 |
| Logical | 26 | 25 | 96.15 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T184,T186,T187 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T184,T186,T188 |
| 1 | 0 | Covered | T44,T45,T94 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T184,T186,T187 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T184,T186,T187 |
| 1 | 1 | 1 | 0 | Not Covered | |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T184,T186,T187 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T184,T186,T188 |
Branch Coverage for Module :
prim_subreg_shadow
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T44,T45,T94 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
prim_subreg_shadow
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
180286 |
180286 |
0 |
0 |
| T1 |
218 |
218 |
0 |
0 |
| T2 |
218 |
218 |
0 |
0 |
| T3 |
218 |
218 |
0 |
0 |
| T4 |
218 |
218 |
0 |
0 |
| T5 |
218 |
218 |
0 |
0 |
| T10 |
218 |
218 |
0 |
0 |
| T12 |
218 |
218 |
0 |
0 |
| T13 |
218 |
218 |
0 |
0 |
| T14 |
218 |
218 |
0 |
0 |
| T17 |
218 |
218 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
2147483647 |
2147483647 |
0 |
0 |
| T1 |
755588 |
735750 |
0 |
0 |
| T2 |
5962954 |
5943334 |
0 |
0 |
| T3 |
9038280 |
9024764 |
0 |
0 |
| T4 |
6087650 |
6058002 |
0 |
0 |
| T5 |
7475874 |
1832726 |
0 |
0 |
| T10 |
8781694 |
8764690 |
0 |
0 |
| T12 |
12913666 |
12897752 |
0 |
0 |
| T13 |
16615306 |
16594596 |
0 |
0 |
| T14 |
1002582 |
986232 |
0 |
0 |
| T17 |
10417784 |
10401652 |
0 |
0 |
