Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_6
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T173,T164 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T160,T173 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T158,T173,T164 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T160,T173 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T11 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T4,T11 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T4,T11 |
| 1 | 0 | Covered | T2,T4,T11 |
| 1 | 1 | Covered | T167,T160,T173 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T160,T173 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_6
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T4,T11 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_en_shadowed_6
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_0
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T157,T158 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T158,T167 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T14 |
| 1 | 0 | Covered | T2,T12,T14 |
| 1 | 1 | Covered | T156,T158,T167 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T157,T158 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_0
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T12,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_0
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_1
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T158,T167 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T158,T167 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T158,T167 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T160 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T14 |
| 1 | 0 | Covered | T2,T12,T14 |
| 1 | 1 | Covered | T156,T167,T160 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T158,T167 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_1
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T12,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_1
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_2
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T167,T166,T161 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T166 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T167,T166,T161 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T158,T167,T166 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T14,T13 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T14,T13 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T14,T13 |
| 1 | 0 | Covered | T2,T14,T13 |
| 1 | 1 | Covered | T158,T167,T166 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T166 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_2
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T14,T13 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_2
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_3
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T167,T171,T164 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T171 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T167,T171,T164 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T158,T167,T171 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T14 |
| 1 | 0 | Covered | T2,T12,T14 |
| 1 | 1 | Covered | T158,T167,T171 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T171 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_3
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T12,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_3
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_4
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_4
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T169,T168 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T169,T171 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T158,T169,T168 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T171,T173,T168 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T14 |
| 1 | 0 | Covered | T2,T12,T14 |
| 1 | 1 | Covered | T171,T173,T168 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T169,T171 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_4
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T12,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_4
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_5
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_5
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T158,T167 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T158,T167 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T158,T167 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T158,T167 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T14 |
| 1 | 0 | Covered | T2,T12,T14 |
| 1 | 1 | Covered | T156,T158,T167 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T158,T167 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_5
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T12,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_5
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_6
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_6
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T160,T171 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T169,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T158,T160,T171 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T169,T160 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T12,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T14 |
| 1 | 0 | Covered | T2,T12,T14 |
| 1 | 1 | Covered | T156,T169,T160 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T169,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_6
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T12,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_loc_alert_class_shadowed_6
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T172,T175,T182 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T172,T175,T182 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T172,T182 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T167,T172,T182 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_lock
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_lock
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T172,T182 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T172,T182 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T182 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T32,T14,T33 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T32,T14,T33 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T32,T14,T33 |
| 1 | 0 | Covered | T32,T14,T33 |
| 1 | 1 | Covered | T156,T167,T182 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_lock
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T32,T14,T33 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_lock
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T167,T172 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T167,T172 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T14,T13,T33 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T156,T167,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e0
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e1
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T175 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T175 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T32,T14 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T156,T167,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e1
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e1
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e2
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T172,T182 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T172,T182 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T156,T167,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e2
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e2
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e3
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T175 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T175 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T175 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T182 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T14 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T156,T167,T182 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T175 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e3
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_en_e3
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T172,T163 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T177 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T172,T163 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T182 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T32,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T32,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T32,T14 |
| 1 | 0 | Covered | T12,T32,T14 |
| 1 | 1 | Covered | T156,T167,T182 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T177 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T32,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e0
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e1
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T167,T172,T175 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T167,T172,T175 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T175 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T12,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T156,T167,T175 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e1
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e1
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e2
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T172,T182 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T172,T182 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T156,T167,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e2
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e2
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e3
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T167,T182 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T167,T172 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T156,T167,T182 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T156,T167,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T12,T32 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T156,T167,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T167,T172 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e3
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_ctrl_shadowed_map_e3
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T169 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T156,T158,T169 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T156,T158,T169 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T169 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_clr_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_accum_thresh_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_accum_thresh_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T168,T181 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T160,T171,T168 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T160,T168,T181 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T160,T171,T168 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T160,T171,T168 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T160,T171,T168 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_accum_thresh_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_accum_thresh_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_timeout_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T12 T32 T14
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T12 T32 T14
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T12 T32 T14
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_timeout_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T166,T168 |
| 1 | 1 | Covered | T12,T32,T14 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T12,T32,T14 |
| 1 | 1 | 0 | Covered | T160,T166,T168 |
| 1 | 1 | 1 | Covered | T12,T32,T14 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T12,T32,T14 |
| 1 | 0 | 1 | 1 | Covered | T12,T32,T14 |
| 1 | 1 | 0 | 1 | Covered | T167,T171,T166 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T12,T32,T14 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T12,T32,T14 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T32,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T32,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T32,T14 |
| 1 | 0 | Covered | T12,T32,T14 |
| 1 | 1 | Covered | T167,T171,T166 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_timeout_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T12,T32,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T12,T32,T14 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_timeout_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_crashdump_trigger_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_crashdump_trigger_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T169,T173,T166 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T169,T170 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T169,T173,T166 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T156,T169,T171 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T32 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T32 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T32 |
| 1 | 0 | Covered | T2,T11,T32 |
| 1 | 1 | Covered | T156,T169,T171 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T169,T170 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_crashdump_trigger_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T32 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_crashdump_trigger_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase0_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase0_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T158,T167 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T158,T167 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T156,T158,T167 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T156,T158,T167 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T156,T158,T167 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T158,T167 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase0_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase0_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase1_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase1_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T171,T166 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T171,T166 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T158,T171,T166 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T158,T166,T172 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T158,T166,T172 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T171,T166 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase1_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase1_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase2_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase2_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T169 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T158,T160,T171 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T158,T160,T171 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T169 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase2_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase2_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase3_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase3_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T171,T173 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T159,T171 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T158,T171,T173 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T158,T171,T173 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T158,T171,T173 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T159,T171 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase3_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classa_phase3_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T173,T164,T184 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T160,T173,T164 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T173,T164,T184 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T176,T184,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T176,T184,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T160,T173,T164 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_lock
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_lock
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T164,T168,T162 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T160,T164 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T164,T168,T162 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T173,T164 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T11,T32,T14 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T11,T32,T14 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T32,T14 |
| 1 | 0 | Covered | T11,T32,T14 |
| 1 | 1 | Covered | T167,T173,T164 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T160,T164 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_lock
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T11,T32,T14 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_lock
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T173,T184 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T160,T173,T184 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T160,T164 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T12,T14 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T167,T160,T164 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e0
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e1
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T184,T163,T179 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T184,T163,T179 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T164,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T167,T164,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e1
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e1
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e2
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T164,T168 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T167,T160,T173 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T160,T164,T168 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T173,T164,T181 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T173,T164,T181 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T167,T160,T173 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e2
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e2
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e3
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T173,T164,T168 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T173,T164,T168 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T173,T164,T163 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T14,T13 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T173,T164,T163 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e3
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_en_e3
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T167,T160,T173 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T167,T160,T173 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T158,T167,T173 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T158,T167,T173 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e0
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e1
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e1
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T164,T168 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T160,T164,T168 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T164,T180,T186 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T164,T180,T186 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e1
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e1
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e2
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e2
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T160,T173 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T158,T160,T173 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T164,T184 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T1,T3,T11 |
| 1 | 1 | Covered | T167,T164,T184 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e2
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e2
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e3
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e3
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T173,T164 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T160,T173,T164 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T173,T179 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T1,T3,T11 |
| 1 | 1 | Covered | T167,T173,T179 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e3
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_ctrl_shadowed_map_e3
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T167,T173 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T157,T158,T167 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T158,T167,T173 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T157,T158,T167 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T157,T158,T167 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T157,T158,T167 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_clr_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_accum_thresh_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_accum_thresh_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T157,T158,T167 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T158,T167,T160 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T157,T158,T160 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T157,T158,T160 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T157,T158,T167 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_accum_thresh_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_accum_thresh_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_timeout_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T11 T12 T32
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T11 T12 T32
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T11 T12 T32
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_timeout_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T167,T164,T184 |
| 1 | 1 | Covered | T11,T12,T32 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T167,T160,T164 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T11,T12,T32 |
| 1 | 1 | 0 | Covered | T167,T164,T184 |
| 1 | 1 | 1 | Covered | T11,T12,T32 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T11,T12,T32 |
| 1 | 0 | 1 | 1 | Covered | T11,T12,T32 |
| 1 | 1 | 0 | 1 | Covered | T167,T159,T160 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T11,T12,T32 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T11,T12,T32 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T11,T12,T32 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T11,T12,T32 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T12,T32 |
| 1 | 0 | Covered | T11,T12,T32 |
| 1 | 1 | Covered | T167,T159,T160 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T167,T160,T164 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_timeout_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T11,T12,T32 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T11,T12,T32 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_timeout_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_crashdump_trigger_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_crashdump_trigger_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T178,T180 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T167,T160,T170 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T160,T178,T180 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T160,T170,T178 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T160,T170,T178 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T167,T160,T170 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_crashdump_trigger_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_crashdump_trigger_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase0_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase0_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T156,T174,T171 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T156,T157,T159 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T156,T174,T171 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T156,T159,T174 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T156,T159,T174 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T156,T157,T159 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase0_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase0_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase1_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase1_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T167,T166 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T167,T166 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T158,T167,T166 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T158,T167,T164 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T158,T167,T164 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T167,T166 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase1_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase1_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase2_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase2_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T158,T174,T171 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T158,T174,T171 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T158,T174,T171 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T171,T177,T164 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T171,T177,T164 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T158,T174,T171 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase2_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase2_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase3_cyc_shadowed
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T2 T11 T12
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T2 T11 T12
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T2 T11 T12
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase3_cyc_shadowed
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T157,T158,T171 |
| 1 | 1 | Covered | T2,T11,T12 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T157,T158,T171 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | Covered | T157,T158,T171 |
| 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 1 | 0 | 1 | Covered | T171,T164,T180 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T2,T11,T12 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T2,T11,T12 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T11,T12 |
| 1 | 0 | Covered | T2,T11,T12 |
| 1 | 1 | Covered | T171,T164,T180 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T157,T158,T171 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase3_cyc_shadowed
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T11,T12 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T2,T11,T12 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classb_phase3_cyc_shadowed
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T160,T171,T163 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T157,T167,T160 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T160,T171,T163 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T173,T165,T181 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T173,T165,T181 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T157,T167,T160 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |
Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_lock
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 16 | 16 | 100.00 |
| CONT_ASSIGN | 94 | 1 | 1 | 100.00 |
| ALWAYS | 100 | 6 | 6 | 100.00 |
| CONT_ASSIGN | 113 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 114 | 0 | 0 | |
| CONT_ASSIGN | 138 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 139 | 0 | 0 | |
| CONT_ASSIGN | 160 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 161 | 0 | 0 | |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 183 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 184 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 187 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 188 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 189 | 1 | 1 | 100.00 |
93 // - In case of RO, SW should not interfere with update process.
94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
Tests: T38 T103 T155
95
96 // Phase tracker:
97 // - Reads from SW clear the phase back to 0.
98 // - Writes have priority (can come from SW or HW).
99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
101 1/1 phase_q <= 1'b0;
Tests: T1 T2 T3
102 1/1 end else if (wr_en && !err_storage) begin
Tests: T1 T2 T3
103 1/1 phase_q <= ~phase_q;
Tests: T1 T2 T3
104 1/1 end else if (phase_clear || err_storage) begin
Tests: T1 T2 T3
105 1/1 phase_q <= 1'b0;
Tests: T38 T103 T155
106 end
MISSING_ELSE
107 end
108
109 // The staged register:
110 // - Holds the 1's complement value.
111 // - Written in Phase 0.
112 // - Once storage error occurs, do not allow any further update until reset
113 1/1 assign staged_we = we & ~phase_q & ~err_storage;
Tests: T1 T2 T3
114 unreachable assign staged_de = de & ~phase_q & ~err_storage;
115 prim_subreg #(
116 .DW ( DW ),
117 .SwAccess ( StagedSwAccess ),
118 .RESVAL ( ~RESVAL )
119 ) staged_reg (
120 .clk_i ( clk_i ),
121 .rst_ni ( rst_ni ),
122 .we ( staged_we ),
123 .wd ( ~wr_data ),
124 .de ( staged_de ),
125 .d ( ~d ),
126 .qe ( ),
127 .q ( staged_q ),
128 .ds ( ),
129 .qs ( )
130 );
131
132 // The shadow register:
133 // - Holds the 1's complement value.
134 // - Written in Phase 1.
135 // - Writes are ignored in case of update errors.
136 // - Gets the value from the staged register.
137 // - Once storage error occurs, do not allow any further update until reset
138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage;
Tests: T1 T2 T3
139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140 prim_subreg #(
141 .DW ( DW ),
142 .SwAccess ( InvertedSwAccess ),
143 .RESVAL ( ~RESVAL )
144 ) shadow_reg (
145 .clk_i ( clk_i ),
146 .rst_ni ( rst_shadowed_ni ),
147 .we ( shadow_we ),
148 .wd ( staged_q ),
149 .de ( shadow_de ),
150 .d ( staged_q ),
151 .qe ( ),
152 .q ( shadow_q ),
153 .ds ( ),
154 .qs ( )
155 );
156
157 // The committed register:
158 // - Written in Phase 1.
159 // - Writes are ignored in case of update errors.
160 1/1 assign committed_we = shadow_we;
Tests: T1 T2 T3
161 unreachable assign committed_de = shadow_de;
162 prim_subreg #(
163 .DW ( DW ),
164 .SwAccess ( SwAccess ),
165 .RESVAL ( RESVAL )
166 ) committed_reg (
167 .clk_i ( clk_i ),
168 .rst_ni ( rst_ni ),
169 .we ( committed_we ),
170 .wd ( wr_data ),
171 .de ( committed_de ),
172 .d ( d ),
173 .qe ( committed_qe ),
174 .q ( committed_q ),
175 .ds ( ds ),
176 .qs ( committed_qs )
177 );
178
179 // Output phase for hwext.
180 1/1 assign phase = phase_q;
Tests: T1 T2 T3
181
182 // Error detection - all bits must match.
183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
Tests: T1 T2 T3
184 1/1 assign err_storage = (~shadow_q != committed_q);
Tests: T1 T2 T3
185
186 // Remaining output assignments
187 1/1 assign qe = committed_qe;
Tests: T1 T2 T3
188 1/1 assign q = committed_q;
Tests: T1 T2 T3
189 1/1 assign qs = committed_qs;
Tests: T1 T2 T3
Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_lock
| Total | Covered | Percent |
|---|
| Conditions | 25 | 25 | 100.00 |
| Logical | 25 | 25 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 102
EXPRESSION (wr_en && ((!err_storage)))
--1-- --------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | Covered | T167,T170,T171 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 104
EXPRESSION (phase_clear || err_storage)
-----1----- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T2,T3 |
| 0 | 1 | Covered | T157,T167,T170 |
| 1 | 0 | Covered | T38,T103,T155 |
LINE 113
EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | Covered | T167,T170,T171 |
| 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 114
EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
-1 ------2----- --------3-------
| -1- | -2- | -3- | Status | Tests |
|---|
| 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | Unreachable | |
LINE 138
EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests | Exclude Annotation |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 1 | 0 | 1 | Covered | T167,T159,T186 |
| 1 | 1 | 1 | 0 | Excluded | |
VC_COV_UNR |
| 1 | 1 | 1 | 1 | Covered | T1,T2,T3 |
LINE 139
EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
-1 ---2--- -------3------- --------4-------
| -1- | -2- | -3- | -4- | Status | Tests |
|---|
| 0 | 1 | 1 | 1 | Covered | T1,T2,T3 |
| 1 | 0 | 1 | 1 | Unreachable | |
| 1 | 1 | 0 | 1 | Unreachable | |
| 1 | 1 | 1 | 0 | Unreachable | |
| 1 | 1 | 1 | 1 | Unreachable | |
LINE 183
EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T14,T13,T33 |
LINE 183
SUB-EXPRESSION ((~staged_q) != wr_data)
------------1-----------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T14,T13,T33 |
LINE 183
SUB-EXPRESSION (phase_q & wr_en)
---1--- --2--
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T14,T13,T33 |
| 1 | 0 | Covered | T14,T13,T33 |
| 1 | 1 | Covered | T167,T159,T186 |
LINE 184
EXPRESSION ((~shadow_q) != committed_q)
--------------1-------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T157,T167,T170 |
Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_lock
| Line No. | Total | Covered | Percent |
| Branches |
|
6 |
6 |
100.00 |
| TERNARY |
183 |
2 |
2 |
100.00 |
| IF |
100 |
4 |
4 |
100.00 |
183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T14,T13,T33 |
| 0 |
Covered |
T1,T2,T3 |
100 if (!rst_ni) begin
-1-
101 phase_q <= 1'b0;
==>
102 end else if (wr_en && !err_storage) begin
-2-
103 phase_q <= ~phase_q;
==>
104 end else if (phase_clear || err_storage) begin
-3-
105 phase_q <= 1'b0;
==>
106 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | -3- | Status | Tests |
| 1 |
- |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
- |
Covered |
T1,T2,T3 |
| 0 |
0 |
1 |
Covered |
T38,T103,T155 |
| 0 |
0 |
0 |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_lock
Assertion Details
CheckSwAccessIsLegal_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
827 |
827 |
0 |
0 |
| T1 |
1 |
1 |
0 |
0 |
| T2 |
1 |
1 |
0 |
0 |
| T3 |
1 |
1 |
0 |
0 |
| T4 |
1 |
1 |
0 |
0 |
| T11 |
1 |
1 |
0 |
0 |
| T12 |
1 |
1 |
0 |
0 |
| T13 |
1 |
1 |
0 |
0 |
| T14 |
1 |
1 |
0 |
0 |
| T32 |
1 |
1 |
0 |
0 |
| T33 |
1 |
1 |
0 |
0 |
MubiIsNotYetSupported_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
678394440 |
677700103 |
0 |
0 |
| T1 |
905 |
832 |
0 |
0 |
| T2 |
6174 |
6113 |
0 |
0 |
| T3 |
967 |
896 |
0 |
0 |
| T4 |
19435 |
6329 |
0 |
0 |
| T11 |
14223 |
14148 |
0 |
0 |
| T12 |
31216 |
31149 |
0 |
0 |
| T13 |
27107 |
27018 |
0 |
0 |
| T14 |
22215 |
22128 |
0 |
0 |
| T32 |
31366 |
31287 |
0 |
0 |
| T33 |
24526 |
24437 |
0 |
0 |