Unified Coverage Report :: Module Instance :: tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.00	100.00	92.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	96.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.00	100.00	92.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	96.36			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Module Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.16	100.00	96.65			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
committed_reg	100.00	100.00	100.00			100.00
shadow_reg	100.00	100.00	100.00			100.00
staged_reg	100.00	100.00	100.00			100.00
wr_en_data_arb	100.00	100.00	100.00			100.00

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T200
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T194,T190
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T183,T200
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T188,T200,T209
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T188,T200,T209

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T194,T190

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e0

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T200,T192
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T194,T190
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T183,T200,T192
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T188,T194,T209
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T4
1	1	Covered	T188,T194,T209

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T194,T190

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T192
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T188,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T200,T192
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T200,T192,T215
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T200,T192,T215

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T188,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T200,T192,T216
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T188,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T200,T192,T216
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T200,T192,T214
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T200,T192,T214

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T188,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_en_e3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T197,T200,T192
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T188,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T197,T200,T192
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T197,T200,T209
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Covered	T197,T200,T209

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T188,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e0

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T200,T192
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T188,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T183,T200,T192
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T188,T200,T209
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T188,T200,T209

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T188,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T200,T192
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T188,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T183,T200,T192
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T188,T192,T214
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T188,T192,T214

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T188,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T200,T192
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T188,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T183,T200,T192
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T188,T200,T209
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T188,T200,T209

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T188,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_ctrl_shadowed_map_e3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T12 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T12 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T12 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T194,T190
1	1	Covered	T2,T3,T12

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T187,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T12
1	1	0	Covered	T184,T194,T190
1	1	1	Covered	T2,T3,T12

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T12
1	0	1	1	Covered	T2,T3,T12
1	1	0	1	Covered	T184,T188,T194
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T12

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T12
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T12

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T12

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T12
1	0	Covered	T2,T3,T12
1	1	Covered	T184,T188,T194

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T187,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T12
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T12
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_clr_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T185,T187
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T185,T187
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T185,T187
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T184,T187,T191
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T184,T187,T191

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T185,T187

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_accum_thresh_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T188,T194
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T187,T188,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T187,T188,T194
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T188,T194,T191
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T188,T194,T191

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T187,T188,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_timeout_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T189,T194
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T187,T188,T189
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T188,T189,T194
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T187,T188,T189
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T187,T188,T189

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T187,T188,T189

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_crashdump_trigger_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T184,T189
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T184,T189
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T183,T184,T189
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T183,T189,T195
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T183,T189,T195

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T184,T189

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase0_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T194,T197
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T187,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T184,T194,T197
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T184,T187,T194
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T184,T187,T194

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T187,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase1_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T201,T191
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T201
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T184,T201,T191
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T184,T194,T201
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T184,T194,T201

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T201

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase2_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T189,T194
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T188,T189,T194
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T188,T189,T194
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T188,T189,T194
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T188,T189,T194

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T188,T189,T194

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classc_phase3_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en

	Total	Covered	Percent
Conditions	25	23	92.00
Logical	25	23	92.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T194,T209,T195
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T194,T209,T195
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T194,T209,T195
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T194,T209,T195

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock

	Total	Covered	Percent
Conditions	25	23	92.00
Logical	25	23	92.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T209,T195
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T209
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T209,T195
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Not Covered
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T4

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T2,T3,T4
1	1	Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T209

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T4
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_lock

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T194,T209
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T209
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T194,T209
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T196
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T196

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T209

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e0

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T209,T215
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T209,T195
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T209,T215
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T195
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T195

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T209,T195

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T209,T195,T206
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T209,T195
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T209,T195,T206
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T205,T215
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T205,T215

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T209,T195

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T194,T195
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T209
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T194,T195
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T213
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T213

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T209

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_en_e3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T194,T209
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T209
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T194,T209
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T215
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T4,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T4,T10
1	0	Covered	T2,T4,T10
1	1	Covered	T215

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T209

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T4,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e0

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T194,T209
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T209
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T194,T209
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T184,T215
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T184,T215

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T209

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e1

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T209,T206
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T209
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T209,T206
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T215
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T215

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T209

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e2

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T194,T209
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T194,T209
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T184,T194,T209
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T194,T210,T215
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T194,T210,T215

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T194,T209

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_ctrl_shadowed_map_e3

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T186,T190
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T186,T190
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T183,T186,T190
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T190,T197,T195
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T190,T197,T195

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T186,T190

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_clr_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T1 T2 T3 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T1 T2 T3 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T1 T2 T3 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T201,T197
1	1	Covered	T1,T2,T3

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T187,T201,T191
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T187,T201,T197
1	1	1	Covered	T1,T2,T3

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Covered	T1,T2,T3
1	1	0	1	Covered	T184,T185,T187
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T1,T2,T3

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T1,T2,T3
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T184,T185,T187

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T187,T201,T191

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_accum_thresh_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T189,T194
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T187,T189
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T187,T189,T194
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T184,T186,T187
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T184,T186,T187

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T187,T189

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_timeout_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T187,T194,T197
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T187,T194,T190
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T187,T194,T197
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T194,T190,T195
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T194,T190,T195

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T187,T194,T190

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_crashdump_trigger_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T185,T193,T200
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T185,T190
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T185,T193,T200
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T184,T185,T190
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T184,T185,T190

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T185,T190

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase0_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T183,T184,T190
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T184,T190
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T183,T184,T190
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T190,T201,T197
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T190,T201,T197

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T184,T190

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase1_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T184,T193,T196
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T184,T193,T196
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T184,T193,T196
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T184,T193,T191
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T184,T193,T191

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T184,T193,T196

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase2_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0

Line Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	94	1	1	100.00
ALWAYS	100	6	6	100.00
CONT_ASSIGN	113	1	1	100.00
CONT_ASSIGN	114	0	0
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	139	0	0
CONT_ASSIGN	160	1	1	100.00
CONT_ASSIGN	161	0	0
CONT_ASSIGN	180	1	1	100.00
CONT_ASSIGN	183	1	1	100.00
CONT_ASSIGN	184	1	1	100.00
CONT_ASSIGN	187	1	1	100.00
CONT_ASSIGN	188	1	1	100.00
CONT_ASSIGN	189	1	1	100.00

93                        // - In case of RO, SW should not interfere with update process.
94         1/1            assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re;
           Tests:       T44 T45 T94 
95                      
96                        // Phase tracker:
97                        // - Reads from SW clear the phase back to 0.
98                        // - Writes have priority (can come from SW or HW).
99                        always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg
100        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
101        1/1                phase_q <= 1'b0;
           Tests:       T1 T2 T3 
102        1/1              end else if (wr_en && !err_storage) begin
           Tests:       T1 T2 T3 
103        1/1                phase_q <= ~phase_q;
           Tests:       T2 T3 T10 
104        1/1              end else if (phase_clear || err_storage) begin
           Tests:       T1 T2 T3 
105        1/1                phase_q <= 1'b0;
           Tests:       T44 T45 T94 
106                         end
                        MISSING_ELSE
107                       end
108                     
109                       // The staged register:
110                       // - Holds the 1's complement value.
111                       // - Written in Phase 0.
112                       // - Once storage error occurs, do not allow any further update until reset
113        1/1            assign staged_we = we & ~phase_q & ~err_storage;
           Tests:       T1 T2 T3 
114        unreachable    assign staged_de = de & ~phase_q & ~err_storage;
115                       prim_subreg #(
116                         .DW       ( DW             ),
117                         .SwAccess ( StagedSwAccess ),
118                         .RESVAL   ( ~RESVAL        )
119                       ) staged_reg (
120                         .clk_i    ( clk_i     ),
121                         .rst_ni   ( rst_ni    ),
122                         .we       ( staged_we ),
123                         .wd       ( ~wr_data  ),
124                         .de       ( staged_de ),
125                         .d        ( ~d        ),
126                         .qe       (           ),
127                         .q        ( staged_q  ),
128                         .ds       (           ),
129                         .qs       (           )
130                       );
131                     
132                       // The shadow register:
133                       // - Holds the 1's complement value.
134                       // - Written in Phase 1.
135                       // - Writes are ignored in case of update errors.
136                       // - Gets the value from the staged register.
137                       // - Once storage error occurs, do not allow any further update until reset
138        1/1            assign shadow_we = we & phase_q & ~err_update & ~err_storage;
           Tests:       T1 T2 T3 
139        unreachable    assign shadow_de = de & phase_q & ~err_update & ~err_storage;
140                       prim_subreg #(
141                         .DW       ( DW               ),
142                         .SwAccess ( InvertedSwAccess ),
143                         .RESVAL   ( ~RESVAL          )
144                       ) shadow_reg (
145                         .clk_i    ( clk_i           ),
146                         .rst_ni   ( rst_shadowed_ni ),
147                         .we       ( shadow_we       ),
148                         .wd       ( staged_q        ),
149                         .de       ( shadow_de       ),
150                         .d        ( staged_q        ),
151                         .qe       (                 ),
152                         .q        ( shadow_q        ),
153                         .ds       (                 ),
154                         .qs       (                 )
155                       );
156                     
157                       // The committed register:
158                       // - Written in Phase 1.
159                       // - Writes are ignored in case of update errors.
160        1/1            assign committed_we = shadow_we;
           Tests:       T2 T3 T10 
161        unreachable    assign committed_de = shadow_de;
162                       prim_subreg #(
163                         .DW       ( DW       ),
164                         .SwAccess ( SwAccess ),
165                         .RESVAL   ( RESVAL   )
166                       ) committed_reg (
167                         .clk_i    ( clk_i        ),
168                         .rst_ni   ( rst_ni       ),
169                         .we       ( committed_we ),
170                         .wd       ( wr_data      ),
171                         .de       ( committed_de ),
172                         .d        ( d            ),
173                         .qe       ( committed_qe ),
174                         .q        ( committed_q  ),
175                         .ds       ( ds           ),
176                         .qs       ( committed_qs )
177                       );
178                     
179                       // Output phase for hwext.
180        1/1            assign phase = phase_q;
           Tests:       T1 T2 T3 
181                     
182                       // Error detection - all bits must match.
183        1/1            assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
           Tests:       T1 T2 T3 
184        1/1            assign err_storage = (~shadow_q != committed_q);
           Tests:       T1 T2 T3 
185                     
186                       // Remaining output assignments
187        1/1            assign qe = committed_qe;
           Tests:       T2 T3 T10 
188        1/1            assign q  = committed_q;
           Tests:       T1 T2 T3 
189        1/1            assign qs = committed_qs;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed

	Total	Covered	Percent
Conditions	25	25	100.00
Logical	25	25	100.00
Non-Logical	0	0
Event	0	0

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T188,T193,T200
1	1	Covered	T2,T3,T10

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T183,T184,T188
1	0	Covered	T44,T45,T94

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T2,T3,T10
1	1	0	Covered	T188,T193,T200
1	1	1	Covered	T2,T3,T10

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Unreachable
1	1	0	Unreachable
1	1	1	Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests	Exclude Annotation
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Covered	T2,T3,T10
1	1	0	1	Covered	T183,T184,T188
1	1	1	0	Excluded		VC_COV_UNR
1	1	1	1	Covered	T2,T3,T10

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	1	1	1	Covered	T2,T3,T10
1	0	1	1	Unreachable
1	1	0	1	Unreachable
1	1	1	0	Unreachable
1	1	1	1	Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T10

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T2,T3,T10
1	1	Covered	T183,T184,T188

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T183,T184,T188

---

Branch Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	183	2	2	100.00
IF	100	4	4	100.00

183          assign err_update  = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0;
                                                         -1-  
                                                         ==>  
                                                         ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T10
0	Covered	T1,T2,T3

100            if (!rst_ni) begin
               -1-  
101              phase_q <= 1'b0;
                 ==>
102            end else if (wr_en && !err_storage) begin
                        -2-  
103              phase_q <= ~phase_q;
                 ==>
104            end else if (phase_clear || err_storage) begin
                        -3-  
105              phase_q <= 1'b0;
                 ==>
106            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T2,T3,T10
0	0	1	Covered	T44,T45,T94
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_reg_wrap.u_reg.u_classd_phase3_cyc_shadowed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckSwAccessIsLegal_A	827	827	0	0
MubiIsNotYetSupported_A	575319970	574651505	0	0

CheckSwAccessIsLegal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	827	827	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T10	1	1	0	0
T12	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T17	1	1	0	0

MubiIsNotYetSupported_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	575319970	574651505	0	0
T1	3466	3375	0	0
T2	27353	27263	0	0
T3	41460	41398	0	0
T4	27925	27789	0	0
T5	34293	8407	0	0
T10	40283	40205	0	0
T12	59237	59164	0	0
T13	76217	76122	0	0
T14	4599	4524	0	0
T17	47788	47714	0	0