CLKMGR Simulation Results

Tuesday April 23 2024 19:02:21 UTC

GitHub Revision: 41bc3e0c7f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 60193594966460162319774997373112005644450303415496697929754976735654535188776

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.310s	200.924us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.930s	53.566us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.090s	144.235us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.600s	1.011ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.010s	201.649us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.000s	39.704us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.090s	144.235us	20	20	100.00
		clkmgr_csr_aliasing	2.010s	201.649us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.200s	197.076us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.680s	329.380us	50	50	100.00
V2	extclk	clkmgr_extclk	1.710s	331.508us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.940s	105.788us	50	50	100.00
V2	jitter	clkmgr_smoke	1.310s	200.924us	50	50	100.00
V2	frequency	clkmgr_frequency	15.970s	2.235ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.810s	2.423ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	15.970s	2.235ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.458m	13.229ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.870s	103.257us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.420s	261.064us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	4.300s	361.732us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	4.300s	361.732us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.930s	53.566us	5	5	100.00
		clkmgr_csr_rw	1.090s	144.235us	20	20	100.00
		clkmgr_csr_aliasing	2.010s	201.649us	5	5	100.00
		clkmgr_same_csr_outstanding	2.260s	434.983us	19	20	95.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.930s	53.566us	5	5	100.00
		clkmgr_csr_rw	1.090s	144.235us	20	20	100.00
		clkmgr_csr_aliasing	2.010s	201.649us	5	5	100.00
		clkmgr_same_csr_outstanding	2.260s	434.983us	19	20	95.00
V2		TOTAL			489	490	99.80
V2S	tl_intg_err	clkmgr_sec_cm	3.420s	457.031us	5	5	100.00
		clkmgr_tl_intg_err	5.090s	740.040us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.580s	349.014us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.580s	349.014us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.580s	349.014us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.580s	349.014us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	7.420s	2.029ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	5.090s	740.040us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	15.970s	2.235ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.810s	2.423ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.580s	349.014us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.110s	477.498us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.620s	297.755us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.370s	213.083us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.570s	286.456us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.050s	137.939us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.090s	144.235us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	3.420s	457.031us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.090s	144.235us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.090s	144.235us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	3.420s	457.031us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.390s	2.606ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	1.104h	1.221s	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.01	98.80

Failure Buckets

• Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))' has 1 failures:
  • Test clkmgr_same_csr_outstanding has 1 failures.

    • 17.clkmgr_same_csr_outstanding.31882227246894790954846270663544676190068767148218956946243131276031004288866
      Line 250, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/17.clkmgr_same_csr_outstanding/latest/run.log

            Offending '((clk_enabled || $changed(clk_enabled)) || (!gated_clk))'
        UVM_ERROR @  11152538 ps: (clkmgr_gated_clock_sva_if.sv:23) [ASSERT FAILED] GateClose_A
        UVM_INFO @  11152538 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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