CLKMGR Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.600s	279.556us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.920s	69.535us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	1.060s	141.125us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	9.680s	1.358ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.530s	48.395us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.010s	42.367us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	1.060s	141.125us	20	20	100.00
		clkmgr_csr_aliasing	1.530s	48.395us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.110s	126.923us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.450s	257.039us	50	50	100.00
V2	extclk	clkmgr_extclk	1.510s	266.490us	50	50	100.00
V2	clk_status	clkmgr_clk_status	0.890s	101.513us	50	50	100.00
V2	jitter	clkmgr_smoke	1.600s	279.556us	50	50	100.00
V2	frequency	clkmgr_frequency	19.010s	2.480ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	16.630s	2.299ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.010s	2.480ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.610m	13.472ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.890s	130.730us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.330s	173.859us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	6.420s	1.361ms	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	6.420s	1.361ms	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.920s	69.535us	5	5	100.00
		clkmgr_csr_rw	1.060s	141.125us	20	20	100.00
		clkmgr_csr_aliasing	1.530s	48.395us	5	5	100.00
		clkmgr_same_csr_outstanding	3.090s	751.806us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.920s	69.535us	5	5	100.00
		clkmgr_csr_rw	1.060s	141.125us	20	20	100.00
		clkmgr_csr_aliasing	1.530s	48.395us	5	5	100.00
		clkmgr_same_csr_outstanding	3.090s	751.806us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.390s	872.115us	5	5	100.00
		clkmgr_tl_intg_err	3.470s	432.407us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.720s	244.515us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.720s	244.515us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.720s	244.515us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.720s	244.515us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	5.100s	1.104ms	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.470s	432.407us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.010s	2.480ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	16.630s	2.299ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.720s	244.515us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.120s	475.288us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.170s	125.911us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.400s	233.195us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.480s	261.090us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.440s	248.172us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	1.060s	141.125us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.390s	872.115us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	1.060s	141.125us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	1.060s	141.125us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.390s	872.115us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.240s	1.320ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	33.799m	518.191ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.50	99.15	95.75	100.00	100.00	98.81	97.01	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:753) [clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 43.clkmgr_stress_all_with_rand_reset.59356995675405374958440763011794970510641362206951971880428648239018852955729
      Line 1605, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/43.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 121883724701 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 121883724701 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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