CLKMGR Simulation Results

Thursday April 25 2024 19:02:55 UTC

GitHub Revision: b938dde05c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 108701404146925295560026896903905201131509842528412483454495187515568509489952

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.420s 262.771us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.070s 119.660us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.090s 97.923us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.910s 1.394ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.340s 519.997us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.080s 128.235us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.090s 97.923us 20 20 100.00
clkmgr_csr_aliasing 2.340s 519.997us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.170s 178.385us 50 50 100.00
V2 trans_enables clkmgr_trans 1.760s 340.866us 50 50 100.00
V2 extclk clkmgr_extclk 2.080s 478.438us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.020s 147.723us 50 50 100.00
V2 jitter clkmgr_smoke 1.420s 262.771us 50 50 100.00
V2 frequency clkmgr_frequency 17.990s 2.479ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.000s 2.299ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.990s 2.479ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.440m 13.091ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.830s 89.713us 50 50 100.00
V2 alert_test clkmgr_alert_test 0.990s 112.329us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.270s 848.519us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.270s 848.519us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.070s 119.660us 5 5 100.00
clkmgr_csr_rw 1.090s 97.923us 20 20 100.00
clkmgr_csr_aliasing 2.340s 519.997us 5 5 100.00
clkmgr_same_csr_outstanding 1.700s 192.679us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.070s 119.660us 5 5 100.00
clkmgr_csr_rw 1.090s 97.923us 20 20 100.00
clkmgr_csr_aliasing 2.340s 519.997us 5 5 100.00
clkmgr_same_csr_outstanding 1.700s 192.679us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.560s 1.164ms 5 5 100.00
clkmgr_tl_intg_err 3.640s 516.868us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.390s 298.975us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.390s 298.975us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.390s 298.975us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.390s 298.975us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.790s 563.329us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.640s 516.868us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.990s 2.479ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.000s 2.299ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.390s 298.975us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.000s 385.128us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.720s 327.138us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.290s 188.301us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.380s 231.042us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.770s 344.707us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.090s 97.923us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.560s 1.164ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.090s 97.923us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.090s 97.923us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.560s 1.164ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.430s 1.271ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 33.608m 530.904ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.50 99.15 95.75 100.00 100.00 98.81 97.01 98.80

Past Results