CLKMGR Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.690s 344.300us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.920s 37.650us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.060s 102.832us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.410s 1.020ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.750s 107.473us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.920s 204.401us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.060s 102.832us 20 20 100.00
clkmgr_csr_aliasing 1.750s 107.473us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.040s 128.173us 50 50 100.00
V2 trans_enables clkmgr_trans 1.580s 282.775us 50 50 100.00
V2 extclk clkmgr_extclk 1.350s 204.927us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.060s 172.255us 50 50 100.00
V2 jitter clkmgr_smoke 1.690s 344.300us 50 50 100.00
V2 frequency clkmgr_frequency 18.130s 2.483ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 15.570s 2.181ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.130s 2.483ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.512m 13.344ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.920s 126.156us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.120s 134.045us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.030s 794.403us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.030s 794.403us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.920s 37.650us 5 5 100.00
clkmgr_csr_rw 1.060s 102.832us 20 20 100.00
clkmgr_csr_aliasing 1.750s 107.473us 5 5 100.00
clkmgr_same_csr_outstanding 2.710s 558.040us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.920s 37.650us 5 5 100.00
clkmgr_csr_rw 1.060s 102.832us 20 20 100.00
clkmgr_csr_aliasing 1.750s 107.473us 5 5 100.00
clkmgr_same_csr_outstanding 2.710s 558.040us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.580s 832.472us 5 5 100.00
clkmgr_tl_intg_err 3.760s 574.464us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.260s 607.531us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.260s 607.531us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.260s 607.531us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.260s 607.531us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.850s 1.190ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.760s 574.464us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.130s 2.483ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 15.570s 2.181ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.260s 607.531us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.730s 322.049us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.670s 217.014us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.350s 196.004us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.480s 226.724us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.810s 372.154us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.060s 102.832us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.580s 832.472us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.060s 102.832us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.060s 102.832us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.580s 832.472us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.690s 1.152ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 21.316m 217.035ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.79 100.00 100.00 98.81 97.01 98.80

Past Results