CLKMGR Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.320s 210.006us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.920s 25.801us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.210s 179.677us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.500s 548.062us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.230s 480.624us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.000s 42.135us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.210s 179.677us 20 20 100.00
clkmgr_csr_aliasing 2.230s 480.624us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.940s 82.415us 50 50 100.00
V2 trans_enables clkmgr_trans 1.460s 194.826us 50 50 100.00
V2 extclk clkmgr_extclk 1.730s 337.268us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.820s 45.465us 50 50 100.00
V2 jitter clkmgr_smoke 1.320s 210.006us 50 50 100.00
V2 frequency clkmgr_frequency 18.780s 2.474ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.130s 2.414ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.780s 2.474ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.257m 10.421ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.800s 54.695us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.200s 190.555us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.460s 509.133us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.460s 509.133us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.920s 25.801us 5 5 100.00
clkmgr_csr_rw 1.210s 179.677us 20 20 100.00
clkmgr_csr_aliasing 2.230s 480.624us 5 5 100.00
clkmgr_same_csr_outstanding 2.200s 406.991us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.920s 25.801us 5 5 100.00
clkmgr_csr_rw 1.210s 179.677us 20 20 100.00
clkmgr_csr_aliasing 2.230s 480.624us 5 5 100.00
clkmgr_same_csr_outstanding 2.200s 406.991us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 11.570s 3.452ms 5 5 100.00
clkmgr_tl_intg_err 3.600s 387.975us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.010s 473.173us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.010s 473.173us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.010s 473.173us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.010s 473.173us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.990s 567.080us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.600s 387.975us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.780s 2.474ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.130s 2.414ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.010s 473.173us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.840s 351.262us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.500s 243.582us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.580s 316.968us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.260s 154.295us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.580s 246.143us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.210s 179.677us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 11.570s 3.452ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.210s 179.677us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.210s 179.677us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 11.570s 3.452ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.950s 1.273ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 46.002m 821.600ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results