CLKMGR Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.380s 245.210us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.860s 20.546us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.070s 130.889us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 6.580s 308.210us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.760s 65.361us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.940s 372.586us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.070s 130.889us 20 20 100.00
clkmgr_csr_aliasing 1.760s 65.361us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.080s 149.755us 50 50 100.00
V2 trans_enables clkmgr_trans 1.790s 373.284us 50 50 100.00
V2 extclk clkmgr_extclk 1.420s 248.654us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.010s 134.587us 50 50 100.00
V2 jitter clkmgr_smoke 1.380s 245.210us 50 50 100.00
V2 frequency clkmgr_frequency 18.590s 2.360ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.320s 2.298ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.590s 2.360ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.108m 17.717ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.920s 128.645us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.330s 200.340us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.610s 376.458us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.610s 376.458us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.860s 20.546us 5 5 100.00
clkmgr_csr_rw 1.070s 130.889us 20 20 100.00
clkmgr_csr_aliasing 1.760s 65.361us 5 5 100.00
clkmgr_same_csr_outstanding 1.830s 363.154us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.860s 20.546us 5 5 100.00
clkmgr_csr_rw 1.070s 130.889us 20 20 100.00
clkmgr_csr_aliasing 1.760s 65.361us 5 5 100.00
clkmgr_same_csr_outstanding 1.830s 363.154us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.160s 393.276us 5 5 100.00
clkmgr_tl_intg_err 4.750s 1.152ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.750s 453.140us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.750s 453.140us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.750s 453.140us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.750s 453.140us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.820s 466.878us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.750s 1.152ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.590s 2.360ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.320s 2.298ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.750s 453.140us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.030s 412.140us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.200s 156.733us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.310s 196.329us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.390s 222.985us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.580s 285.080us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.070s 130.889us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.160s 393.276us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.070s 130.889us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.070s 130.889us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.160s 393.276us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.150s 1.234ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 36.336m 647.473ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.79 100.00 100.00 98.81 97.01 98.80

Past Results