CLKMGR Simulation Results

Thursday May 09 2024 19:02:32 UTC

GitHub Revision: 9656691e03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 30170103562476460183108208532025718695603957360441815475011549460912256789439

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.190s 129.109us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.040s 86.191us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.320s 238.421us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.470s 1.686ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.790s 489.661us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.050s 342.414us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.320s 238.421us 20 20 100.00
clkmgr_csr_aliasing 2.790s 489.661us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.190s 184.123us 50 50 100.00
V2 trans_enables clkmgr_trans 1.380s 148.754us 50 50 100.00
V2 extclk clkmgr_extclk 1.420s 246.178us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.900s 97.692us 50 50 100.00
V2 jitter clkmgr_smoke 1.190s 129.109us 50 50 100.00
V2 frequency clkmgr_frequency 17.640s 2.362ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.830s 2.420ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.640s 2.362ms 50 50 100.00
V2 stress_all clkmgr_stress_all 58.810s 7.942ms 50 50 100.00
V2 intr_test clkmgr_intr_test 1.020s 167.078us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.420s 268.590us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 7.290s 1.946ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 7.290s 1.946ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.040s 86.191us 5 5 100.00
clkmgr_csr_rw 1.320s 238.421us 20 20 100.00
clkmgr_csr_aliasing 2.790s 489.661us 5 5 100.00
clkmgr_same_csr_outstanding 1.540s 242.521us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.040s 86.191us 5 5 100.00
clkmgr_csr_rw 1.320s 238.421us 20 20 100.00
clkmgr_csr_aliasing 2.790s 489.661us 5 5 100.00
clkmgr_same_csr_outstanding 1.540s 242.521us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.770s 648.571us 5 5 100.00
clkmgr_tl_intg_err 4.210s 866.899us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.960s 993.053us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.960s 993.053us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.960s 993.053us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.960s 993.053us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.640s 538.513us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.210s 866.899us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.640s 2.362ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.830s 2.420ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.960s 993.053us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.710s 337.559us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.440s 224.414us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.370s 182.477us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.810s 362.287us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.450s 198.050us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.320s 238.421us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.770s 648.571us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.320s 238.421us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.320s 238.421us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.770s 648.571us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.680s 1.301ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 41.519m 659.633ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results