CLKMGR Simulation Results

Sunday May 12 2024 19:02:35 UTC

GitHub Revision: 69c572b503

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 72674276607041733394622960695970595070180537542023880499199659375034056632550

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.330s 186.230us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.830s 49.489us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.100s 128.168us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.970s 1.009ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.780s 72.764us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.870s 79.797us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.100s 128.168us 20 20 100.00
clkmgr_csr_aliasing 1.780s 72.764us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.110s 160.826us 50 50 100.00
V2 trans_enables clkmgr_trans 1.710s 315.390us 50 50 100.00
V2 extclk clkmgr_extclk 1.890s 410.139us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.080s 183.687us 50 50 100.00
V2 jitter clkmgr_smoke 1.330s 186.230us 50 50 100.00
V2 frequency clkmgr_frequency 17.870s 2.359ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.210s 2.416ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.870s 2.359ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.477m 12.220ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.930s 133.872us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.060s 144.943us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 7.400s 1.556ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 7.400s 1.556ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.830s 49.489us 5 5 100.00
clkmgr_csr_rw 1.100s 128.168us 20 20 100.00
clkmgr_csr_aliasing 1.780s 72.764us 5 5 100.00
clkmgr_same_csr_outstanding 1.960s 269.814us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.830s 49.489us 5 5 100.00
clkmgr_csr_rw 1.100s 128.168us 20 20 100.00
clkmgr_csr_aliasing 1.780s 72.764us 5 5 100.00
clkmgr_same_csr_outstanding 1.960s 269.814us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 16.480s 5.351ms 5 5 100.00
clkmgr_tl_intg_err 7.140s 1.911ms 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 4.290s 1.103ms 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 4.290s 1.103ms 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 4.290s 1.103ms 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 4.290s 1.103ms 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.030s 180.667us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 7.140s 1.911ms 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.870s 2.359ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.210s 2.416ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 4.290s 1.103ms 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.430s 204.710us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.610s 288.635us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.490s 259.898us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.590s 270.239us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.560s 271.811us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.100s 128.168us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 16.480s 5.351ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.100s 128.168us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.100s 128.168us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 16.480s 5.351ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.090s 1.249ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 30.876m 552.908ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.01 98.80

Past Results