CLKMGR Simulation Results

Tuesday May 14 2024 19:02:33 UTC

GitHub Revision: 00fe426038

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56275124637035941820967954627144971699378360917446801543187025394370981034792

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.210s 98.253us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.080s 90.452us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.100s 126.720us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.910s 1.379ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.410s 316.009us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.000s 65.356us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.100s 126.720us 20 20 100.00
clkmgr_csr_aliasing 2.410s 316.009us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.330s 153.252us 50 50 100.00
V2 trans_enables clkmgr_trans 1.450s 143.302us 50 50 100.00
V2 extclk clkmgr_extclk 1.430s 94.941us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.010s 122.394us 50 50 100.00
V2 jitter clkmgr_smoke 1.210s 98.253us 50 50 100.00
V2 frequency clkmgr_frequency 13.470s 2.484ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 15.050s 1.816ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 13.470s 2.484ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.670m 12.800ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.840s 94.209us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.170s 131.844us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.930s 513.858us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.930s 513.858us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.080s 90.452us 5 5 100.00
clkmgr_csr_rw 1.100s 126.720us 20 20 100.00
clkmgr_csr_aliasing 2.410s 316.009us 5 5 100.00
clkmgr_same_csr_outstanding 1.650s 178.708us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.080s 90.452us 5 5 100.00
clkmgr_csr_rw 1.100s 126.720us 20 20 100.00
clkmgr_csr_aliasing 2.410s 316.009us 5 5 100.00
clkmgr_same_csr_outstanding 1.650s 178.708us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 4.610s 906.198us 5 5 100.00
clkmgr_tl_intg_err 3.540s 437.907us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.800s 360.676us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.800s 360.676us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.800s 360.676us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.800s 360.676us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 6.390s 1.634ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.540s 437.907us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 13.470s 2.484ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 15.050s 1.816ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.800s 360.676us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.130s 370.161us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.560s 242.619us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.850s 330.856us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.640s 237.855us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.770s 321.158us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.100s 126.720us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 4.610s 906.198us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.100s 126.720us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.100s 126.720us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 4.610s 906.198us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.240s 1.047ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 24.940m 279.851ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.50 99.15 95.75 100.00 100.00 98.81 97.01 98.80

Past Results