CLKMGR Simulation Results

Monday July 01 2024 23:02:26 UTC

GitHub Revision: e9ae10fb42

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81071883735317974084005537723499931298658500385730214730015283368929474034200

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.210s 121.937us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.930s 76.853us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.140s 176.757us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.690s 744.724us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.890s 179.805us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.560s 304.147us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.140s 176.757us 20 20 100.00
clkmgr_csr_aliasing 1.890s 179.805us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.120s 161.229us 50 50 100.00
V2 trans_enables clkmgr_trans 2.520s 489.870us 50 50 100.00
V2 extclk clkmgr_extclk 1.450s 183.699us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.960s 64.685us 50 50 100.00
V2 jitter clkmgr_smoke 1.210s 121.937us 50 50 100.00
V2 frequency clkmgr_frequency 18.740s 2.363ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.980s 2.422ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.740s 2.363ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.681m 12.962ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.980s 130.491us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.230s 150.790us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.340s 666.679us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.340s 666.679us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.930s 76.853us 5 5 100.00
clkmgr_csr_rw 1.140s 176.757us 20 20 100.00
clkmgr_csr_aliasing 1.890s 179.805us 5 5 100.00
clkmgr_same_csr_outstanding 1.640s 169.082us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.930s 76.853us 5 5 100.00
clkmgr_csr_rw 1.140s 176.757us 20 20 100.00
clkmgr_csr_aliasing 1.890s 179.805us 5 5 100.00
clkmgr_same_csr_outstanding 1.640s 169.082us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 5.620s 1.140ms 5 5 100.00
clkmgr_tl_intg_err 3.270s 252.843us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.040s 709.514us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.040s 709.514us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.040s 709.514us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.040s 709.514us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.530s 878.306us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.270s 252.843us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.740s 2.363ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.980s 2.422ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.040s 709.514us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 2.450s 503.022us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.490s 239.220us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.340s 166.985us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.570s 224.435us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.340s 181.771us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.140s 176.757us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 5.620s 1.140ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.140s 176.757us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.140s 176.757us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 5.620s 1.140ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 8.900s 2.861ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 28.145m 303.836ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.76 100.00 100.00 98.81 97.02 98.80

Past Results