CLKMGR Simulation Results

Saturday June 29 2024 23:02:35 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 9407974028806500767465982655187958599819354731549473124644158596869486113221

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.690s 313.726us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.070s 111.179us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.250s 190.807us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 7.490s 795.344us 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.340s 272.218us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 1.990s 112.768us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.250s 190.807us 20 20 100.00
clkmgr_csr_aliasing 2.340s 272.218us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.080s 120.441us 50 50 100.00
V2 trans_enables clkmgr_trans 2.150s 415.951us 50 50 100.00
V2 extclk clkmgr_extclk 1.170s 90.929us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.050s 91.231us 50 50 100.00
V2 jitter clkmgr_smoke 1.690s 313.726us 50 50 100.00
V2 frequency clkmgr_frequency 19.770s 2.478ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.640s 2.296ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.770s 2.478ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.868m 15.393ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.880s 69.116us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.370s 211.722us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.360s 695.274us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.360s 695.274us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.070s 111.179us 5 5 100.00
clkmgr_csr_rw 1.250s 190.807us 20 20 100.00
clkmgr_csr_aliasing 2.340s 272.218us 5 5 100.00
clkmgr_same_csr_outstanding 3.080s 784.480us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.070s 111.179us 5 5 100.00
clkmgr_csr_rw 1.250s 190.807us 20 20 100.00
clkmgr_csr_aliasing 2.340s 272.218us 5 5 100.00
clkmgr_same_csr_outstanding 3.080s 784.480us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 21.150s 4.853ms 5 5 100.00
clkmgr_tl_intg_err 4.670s 879.316us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.450s 896.623us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.450s 896.623us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.450s 896.623us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.450s 896.623us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.410s 876.427us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.670s 879.316us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.770s 2.478ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.640s 2.296ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.450s 896.623us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.590s 216.320us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.550s 267.990us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.530s 252.612us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.630s 269.321us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.490s 257.383us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.250s 190.807us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 21.150s 4.853ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.250s 190.807us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.250s 190.807us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 21.150s 4.853ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.350s 2.146ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 47.464m 779.567ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results