CLKMGR Simulation Results

Sunday June 30 2024 23:02:20 UTC

GitHub Revision: b33f0bcb4a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 105302396297609026156504164956156290718642058150905320202190590799028860124396

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.410s 235.446us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.940s 61.347us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.150s 187.463us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.480s 1.768ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.900s 139.536us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.360s 200.777us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.150s 187.463us 20 20 100.00
clkmgr_csr_aliasing 1.900s 139.536us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.100s 153.579us 50 50 100.00
V2 trans_enables clkmgr_trans 1.720s 265.415us 50 50 100.00
V2 extclk clkmgr_extclk 1.190s 114.768us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.040s 137.604us 50 50 100.00
V2 jitter clkmgr_smoke 1.410s 235.446us 50 50 100.00
V2 frequency clkmgr_frequency 20.180s 2.481ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.600s 2.301ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 20.180s 2.481ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.428m 10.878ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.850s 88.637us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.060s 137.847us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 4.250s 595.144us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 4.250s 595.144us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.940s 61.347us 5 5 100.00
clkmgr_csr_rw 1.150s 187.463us 20 20 100.00
clkmgr_csr_aliasing 1.900s 139.536us 5 5 100.00
clkmgr_same_csr_outstanding 3.410s 856.167us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.940s 61.347us 5 5 100.00
clkmgr_csr_rw 1.150s 187.463us 20 20 100.00
clkmgr_csr_aliasing 1.900s 139.536us 5 5 100.00
clkmgr_same_csr_outstanding 3.410s 856.167us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.610s 493.169us 5 5 100.00
clkmgr_tl_intg_err 3.980s 786.054us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.050s 542.742us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.050s 542.742us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.050s 542.742us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.050s 542.742us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 8.270s 2.439ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.980s 786.054us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 20.180s 2.481ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.600s 2.301ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.050s 542.742us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.980s 331.663us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.270s 196.664us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.150s 147.788us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.040s 396.284us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.230s 129.477us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.150s 187.463us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.610s 493.169us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.150s 187.463us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.150s 187.463us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.610s 493.169us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.160s 1.238ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 36.289m 543.989ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results