CLKMGR Simulation Results

Thursday June 27 2024 23:02:31 UTC

GitHub Revision: 8db2a18db1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 100513533386727882033709335126269317053614297947080434367729937568368619502352

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.450s	227.905us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	1.000s	123.558us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.970s	58.780us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	11.550s	2.003ms	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	1.600s	171.387us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	1.950s	111.908us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.970s	58.780us	20	20	100.00
		clkmgr_csr_aliasing	1.600s	171.387us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	1.130s	159.844us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.980s	362.361us	50	50	100.00
V2	extclk	clkmgr_extclk	1.790s	312.194us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.150s	201.542us	50	50	100.00
V2	jitter	clkmgr_smoke	1.450s	227.905us	50	50	100.00
V2	frequency	clkmgr_frequency	19.420s	2.477ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	17.350s	2.301ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	19.420s	2.477ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.707m	14.459ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.880s	110.132us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.250s	142.463us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.430s	369.642us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.430s	369.642us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	1.000s	123.558us	5	5	100.00
		clkmgr_csr_rw	0.970s	58.780us	20	20	100.00
		clkmgr_csr_aliasing	1.600s	171.387us	5	5	100.00
		clkmgr_same_csr_outstanding	2.420s	423.396us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	1.000s	123.558us	5	5	100.00
		clkmgr_csr_rw	0.970s	58.780us	20	20	100.00
		clkmgr_csr_aliasing	1.600s	171.387us	5	5	100.00
		clkmgr_same_csr_outstanding	2.420s	423.396us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.480s	877.671us	5	5	100.00
		clkmgr_tl_intg_err	4.340s	793.764us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.640s	412.536us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.640s	412.536us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.640s	412.536us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.640s	412.536us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	4.090s	603.067us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	4.340s	793.764us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	19.420s	2.477ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	17.350s	2.301ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.640s	412.536us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	1.810s	263.595us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.720s	328.462us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.610s	279.691us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.880s	364.523us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.380s	246.965us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.970s	58.780us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.480s	877.671us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.970s	58.780us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.970s	58.780us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.480s	877.671us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	7.960s	1.522ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	24.816m	324.984ms	50	50	100.00
V3		TOTAL			100	100	100.00
		TOTAL			1010	1010	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	2	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

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