CLKMGR Simulation Results

Friday June 28 2024 23:02:02 UTC

GitHub Revision: 3d5220a43f

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 73442097946972310753089853920865571566707682704390544987111276126114608747389

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.170s 117.317us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.900s 23.365us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.150s 140.443us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 11.730s 1.687ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.910s 74.524us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.010s 38.377us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.150s 140.443us 20 20 100.00
clkmgr_csr_aliasing 1.910s 74.524us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.210s 177.260us 50 50 100.00
V2 trans_enables clkmgr_trans 1.340s 187.728us 50 50 100.00
V2 extclk clkmgr_extclk 1.640s 282.793us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.150s 186.963us 50 50 100.00
V2 jitter clkmgr_smoke 1.170s 117.317us 50 50 100.00
V2 frequency clkmgr_frequency 19.120s 2.359ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 18.340s 2.417ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.120s 2.359ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.385m 11.176ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.950s 85.934us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.230s 178.378us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.550s 1.155ms 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.550s 1.155ms 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.900s 23.365us 5 5 100.00
clkmgr_csr_rw 1.150s 140.443us 20 20 100.00
clkmgr_csr_aliasing 1.910s 74.524us 5 5 100.00
clkmgr_same_csr_outstanding 2.260s 364.855us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.900s 23.365us 5 5 100.00
clkmgr_csr_rw 1.150s 140.443us 20 20 100.00
clkmgr_csr_aliasing 1.910s 74.524us 5 5 100.00
clkmgr_same_csr_outstanding 2.260s 364.855us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.300s 413.362us 5 5 100.00
clkmgr_tl_intg_err 3.590s 402.659us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.850s 669.161us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.850s 669.161us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.850s 669.161us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.850s 669.161us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.190s 524.890us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.590s 402.659us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.120s 2.359ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 18.340s 2.417ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.850s 669.161us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.400s 178.254us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.140s 86.785us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.340s 230.674us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.630s 296.829us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.370s 174.441us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.150s 140.443us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.300s 413.362us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.150s 140.443us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.150s 140.443us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.300s 413.362us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.480s 1.306ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 39.803m 544.187ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.52 99.15 95.84 100.00 100.00 98.81 97.02 98.80

Past Results