CLKMGR Simulation Results

Tuesday July 02 2024 14:17:13 UTC

GitHub Revision: abd7ce57f2

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 7120396591488306882161367642496372905152431708445539866860566607772054886363

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	clkmgr_smoke	1.200s	151.591us	50	50	100.00
V1	csr_hw_reset	clkmgr_csr_hw_reset	0.970s	96.445us	5	5	100.00
V1	csr_rw	clkmgr_csr_rw	0.900s	51.404us	20	20	100.00
V1	csr_bit_bash	clkmgr_csr_bit_bash	7.440s	433.201us	5	5	100.00
V1	csr_aliasing	clkmgr_csr_aliasing	2.520s	400.477us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	clkmgr_csr_mem_rw_with_rand_reset	2.720s	390.900us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	clkmgr_csr_rw	0.900s	51.404us	20	20	100.00
		clkmgr_csr_aliasing	2.520s	400.477us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	peri_enables	clkmgr_peri	0.920s	26.200us	50	50	100.00
V2	trans_enables	clkmgr_trans	1.830s	373.535us	50	50	100.00
V2	extclk	clkmgr_extclk	1.470s	257.797us	50	50	100.00
V2	clk_status	clkmgr_clk_status	1.140s	194.299us	50	50	100.00
V2	jitter	clkmgr_smoke	1.200s	151.591us	50	50	100.00
V2	frequency	clkmgr_frequency	17.850s	2.361ms	50	50	100.00
V2	frequency_timeout	clkmgr_frequency_timeout	15.980s	2.182ms	50	50	100.00
V2	frequency_overflow	clkmgr_frequency	17.850s	2.361ms	50	50	100.00
V2	stress_all	clkmgr_stress_all	1.268m	10.417ms	50	50	100.00
V2	intr_test	clkmgr_intr_test	0.780s	68.021us	50	50	100.00
V2	alert_test	clkmgr_alert_test	1.370s	222.754us	50	50	100.00
V2	tl_d_oob_addr_access	clkmgr_tl_errors	3.840s	354.577us	20	20	100.00
V2	tl_d_illegal_access	clkmgr_tl_errors	3.840s	354.577us	20	20	100.00
V2	tl_d_outstanding_access	clkmgr_csr_hw_reset	0.970s	96.445us	5	5	100.00
		clkmgr_csr_rw	0.900s	51.404us	20	20	100.00
		clkmgr_csr_aliasing	2.520s	400.477us	5	5	100.00
		clkmgr_same_csr_outstanding	1.890s	286.051us	20	20	100.00
V2	tl_d_partial_access	clkmgr_csr_hw_reset	0.970s	96.445us	5	5	100.00
		clkmgr_csr_rw	0.900s	51.404us	20	20	100.00
		clkmgr_csr_aliasing	2.520s	400.477us	5	5	100.00
		clkmgr_same_csr_outstanding	1.890s	286.051us	20	20	100.00
V2		TOTAL			490	490	100.00
V2S	tl_intg_err	clkmgr_sec_cm	4.350s	824.633us	5	5	100.00
		clkmgr_tl_intg_err	3.730s	465.749us	20	20	100.00
V2S	shadow_reg_update_error	clkmgr_shadow_reg_errors	2.420s	606.166us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	clkmgr_shadow_reg_errors	2.420s	606.166us	20	20	100.00
V2S	shadow_reg_storage_error	clkmgr_shadow_reg_errors	2.420s	606.166us	20	20	100.00
V2S	shadowed_reset_glitch	clkmgr_shadow_reg_errors	2.420s	606.166us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	clkmgr_shadow_reg_errors_with_csr_rw	3.770s	701.730us	20	20	100.00
V2S	sec_cm_bus_integrity	clkmgr_tl_intg_err	3.730s	465.749us	20	20	100.00
V2S	sec_cm_meas_clk_bkgn_chk	clkmgr_frequency	17.850s	2.361ms	50	50	100.00
V2S	sec_cm_timeout_clk_bkgn_chk	clkmgr_frequency_timeout	15.980s	2.182ms	50	50	100.00
V2S	sec_cm_meas_config_shadow	clkmgr_shadow_reg_errors	2.420s	606.166us	20	20	100.00
V2S	sec_cm_idle_intersig_mubi	clkmgr_idle_intersig_mubi	2.550s	519.739us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	clkmgr_lc_ctrl_intersig_mubi	1.530s	246.101us	50	50	100.00
V2S	sec_cm_lc_ctrl_clk_handshake_intersig_mubi	clkmgr_lc_clk_byp_req_intersig_mubi	1.520s	277.876us	50	50	100.00
V2S	sec_cm_clk_handshake_intersig_mubi	clkmgr_clk_handshake_intersig_mubi	1.810s	330.464us	50	50	100.00
V2S	sec_cm_div_intersig_mubi	clkmgr_div_intersig_mubi	1.210s	134.869us	50	50	100.00
V2S	sec_cm_jitter_config_mubi	clkmgr_csr_rw	0.900s	51.404us	20	20	100.00
V2S	sec_cm_idle_ctr_redun	clkmgr_sec_cm	4.350s	824.633us	5	5	100.00
V2S	sec_cm_meas_config_regwen	clkmgr_csr_rw	0.900s	51.404us	20	20	100.00
V2S	sec_cm_clk_ctrl_config_regwen	clkmgr_csr_rw	0.900s	51.404us	20	20	100.00
V2S	prim_count_check	clkmgr_sec_cm	4.350s	824.633us	5	5	100.00
V2S		TOTAL			315	315	100.00
V3	regwen	clkmgr_regwen	8.090s	1.387ms	50	50	100.00
V3	stress_all_with_rand_reset	clkmgr_stress_all_with_rand_reset	49.196m	841.252ms	49	50	98.00
V3		TOTAL			99	100	99.00
		TOTAL			1009	1010	99.90

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	9	9	9	100.00
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.52	99.15	95.84	100.00	100.00	98.81	97.02	98.80

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:749) [clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test clkmgr_stress_all_with_rand_reset has 1 failures.

    • 10.clkmgr_stress_all_with_rand_reset.51270328713031087086747167278710685755345832156820183432123136107619963056561
      Line 676, in log /container/opentitan-public/scratch/os_regression/clkmgr-sim-vcs/10.clkmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 7406971042 ps: (cip_base_vseq.sv:749) [uvm_test_top.env.virtual_sequencer.clkmgr_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 7406971042 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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