CLKMGR Simulation Results

Wednesday July 03 2024 23:02:32 UTC

GitHub Revision: e6706fcc7b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8083624550445280117614176890238357255195852125596561370221115831648066795492

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.630s 308.262us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.930s 41.924us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.030s 55.340us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 9.640s 1.271ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.670s 89.265us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.290s 181.807us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.030s 55.340us 20 20 100.00
clkmgr_csr_aliasing 1.670s 89.265us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.990s 104.131us 50 50 100.00
V2 trans_enables clkmgr_trans 1.360s 180.615us 50 50 100.00
V2 extclk clkmgr_extclk 1.220s 157.095us 50 50 100.00
V2 clk_status clkmgr_clk_status 1.100s 149.536us 50 50 100.00
V2 jitter clkmgr_smoke 1.630s 308.262us 50 50 100.00
V2 frequency clkmgr_frequency 18.830s 2.477ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.710s 2.418ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 18.830s 2.477ms 50 50 100.00
V2 stress_all clkmgr_stress_all 58.440s 8.203ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.910s 118.334us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.020s 81.792us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 5.610s 998.317us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 5.610s 998.317us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.930s 41.924us 5 5 100.00
clkmgr_csr_rw 1.030s 55.340us 20 20 100.00
clkmgr_csr_aliasing 1.670s 89.265us 5 5 100.00
clkmgr_same_csr_outstanding 1.680s 171.930us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.930s 41.924us 5 5 100.00
clkmgr_csr_rw 1.030s 55.340us 20 20 100.00
clkmgr_csr_aliasing 1.670s 89.265us 5 5 100.00
clkmgr_same_csr_outstanding 1.680s 171.930us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.340s 394.217us 5 5 100.00
clkmgr_tl_intg_err 4.650s 902.477us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.740s 388.013us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.740s 388.013us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.740s 388.013us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.740s 388.013us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 5.500s 1.114ms 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 4.650s 902.477us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 18.830s 2.477ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.710s 2.418ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.740s 388.013us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.470s 150.792us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.380s 202.936us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.830s 361.012us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.300s 188.956us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.630s 243.474us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.030s 55.340us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.340s 394.217us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.030s 55.340us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.030s 55.340us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.340s 394.217us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 6.790s 1.225ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 28.345m 417.480ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results