CLKMGR Simulation Results

Thursday July 04 2024 23:02:28 UTC

GitHub Revision: 3e678c112b

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 94940390549829454688103081328166376218078465228811124044523808815554354133843

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.460s 234.784us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 1.040s 98.854us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 1.380s 220.869us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 22.040s 6.609ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 1.710s 60.791us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.410s 138.140us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 1.380s 220.869us 20 20 100.00
clkmgr_csr_aliasing 1.710s 60.791us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 0.930s 92.149us 50 50 100.00
V2 trans_enables clkmgr_trans 1.490s 233.749us 50 50 100.00
V2 extclk clkmgr_extclk 1.650s 284.561us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.940s 102.476us 50 50 100.00
V2 jitter clkmgr_smoke 1.460s 234.784us 50 50 100.00
V2 frequency clkmgr_frequency 19.830s 2.484ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 17.000s 2.421ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 19.830s 2.484ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.443m 11.604ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.890s 110.954us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.220s 155.491us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.910s 267.131us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.910s 267.131us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 1.040s 98.854us 5 5 100.00
clkmgr_csr_rw 1.380s 220.869us 20 20 100.00
clkmgr_csr_aliasing 1.710s 60.791us 5 5 100.00
clkmgr_same_csr_outstanding 2.020s 361.917us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 1.040s 98.854us 5 5 100.00
clkmgr_csr_rw 1.380s 220.869us 20 20 100.00
clkmgr_csr_aliasing 1.710s 60.791us 5 5 100.00
clkmgr_same_csr_outstanding 2.020s 361.917us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 8.670s 1.480ms 5 5 100.00
clkmgr_tl_intg_err 2.980s 329.054us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 3.000s 544.716us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 3.000s 544.716us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 3.000s 544.716us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 3.000s 544.716us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 4.130s 519.519us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 2.980s 329.054us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 19.830s 2.484ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 17.000s 2.421ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 3.000s 544.716us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.680s 286.743us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.430s 151.834us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.440s 209.852us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 2.370s 463.796us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.850s 349.516us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 1.380s 220.869us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 8.670s 1.480ms 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 1.380s 220.869us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 1.380s 220.869us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 8.670s 1.480ms 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.450s 1.263ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 42.771m 581.534ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results