CLKMGR Simulation Results

Friday July 05 2024 23:02:55 UTC

GitHub Revision: 9edf84e236

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47623749544922802985321435118963335754001495105472137721881337469861493653463

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke clkmgr_smoke 1.330s 178.951us 50 50 100.00
V1 csr_hw_reset clkmgr_csr_hw_reset 0.940s 74.000us 5 5 100.00
V1 csr_rw clkmgr_csr_rw 0.980s 110.248us 20 20 100.00
V1 csr_bit_bash clkmgr_csr_bit_bash 10.510s 1.744ms 5 5 100.00
V1 csr_aliasing clkmgr_csr_aliasing 2.290s 265.910us 5 5 100.00
V1 csr_mem_rw_with_rand_reset clkmgr_csr_mem_rw_with_rand_reset 2.230s 69.029us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr clkmgr_csr_rw 0.980s 110.248us 20 20 100.00
clkmgr_csr_aliasing 2.290s 265.910us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 peri_enables clkmgr_peri 1.160s 163.416us 50 50 100.00
V2 trans_enables clkmgr_trans 2.470s 550.868us 50 50 100.00
V2 extclk clkmgr_extclk 1.720s 315.729us 50 50 100.00
V2 clk_status clkmgr_clk_status 0.970s 117.587us 50 50 100.00
V2 jitter clkmgr_smoke 1.330s 178.951us 50 50 100.00
V2 frequency clkmgr_frequency 17.880s 2.362ms 50 50 100.00
V2 frequency_timeout clkmgr_frequency_timeout 16.470s 2.297ms 50 50 100.00
V2 frequency_overflow clkmgr_frequency 17.880s 2.362ms 50 50 100.00
V2 stress_all clkmgr_stress_all 1.599m 13.059ms 50 50 100.00
V2 intr_test clkmgr_intr_test 0.800s 81.669us 50 50 100.00
V2 alert_test clkmgr_alert_test 1.000s 57.541us 50 50 100.00
V2 tl_d_oob_addr_access clkmgr_tl_errors 3.780s 263.966us 20 20 100.00
V2 tl_d_illegal_access clkmgr_tl_errors 3.780s 263.966us 20 20 100.00
V2 tl_d_outstanding_access clkmgr_csr_hw_reset 0.940s 74.000us 5 5 100.00
clkmgr_csr_rw 0.980s 110.248us 20 20 100.00
clkmgr_csr_aliasing 2.290s 265.910us 5 5 100.00
clkmgr_same_csr_outstanding 2.370s 510.575us 20 20 100.00
V2 tl_d_partial_access clkmgr_csr_hw_reset 0.940s 74.000us 5 5 100.00
clkmgr_csr_rw 0.980s 110.248us 20 20 100.00
clkmgr_csr_aliasing 2.290s 265.910us 5 5 100.00
clkmgr_same_csr_outstanding 2.370s 510.575us 20 20 100.00
V2 TOTAL 490 490 100.00
V2S tl_intg_err clkmgr_sec_cm 3.520s 730.271us 5 5 100.00
clkmgr_tl_intg_err 3.800s 615.255us 20 20 100.00
V2S shadow_reg_update_error clkmgr_shadow_reg_errors 2.510s 620.923us 20 20 100.00
V2S shadow_reg_read_clear_staged_value clkmgr_shadow_reg_errors 2.510s 620.923us 20 20 100.00
V2S shadow_reg_storage_error clkmgr_shadow_reg_errors 2.510s 620.923us 20 20 100.00
V2S shadowed_reset_glitch clkmgr_shadow_reg_errors 2.510s 620.923us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw clkmgr_shadow_reg_errors_with_csr_rw 3.900s 725.913us 20 20 100.00
V2S sec_cm_bus_integrity clkmgr_tl_intg_err 3.800s 615.255us 20 20 100.00
V2S sec_cm_meas_clk_bkgn_chk clkmgr_frequency 17.880s 2.362ms 50 50 100.00
V2S sec_cm_timeout_clk_bkgn_chk clkmgr_frequency_timeout 16.470s 2.297ms 50 50 100.00
V2S sec_cm_meas_config_shadow clkmgr_shadow_reg_errors 2.510s 620.923us 20 20 100.00
V2S sec_cm_idle_intersig_mubi clkmgr_idle_intersig_mubi 1.390s 140.115us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi clkmgr_lc_ctrl_intersig_mubi 1.120s 102.858us 50 50 100.00
V2S sec_cm_lc_ctrl_clk_handshake_intersig_mubi clkmgr_lc_clk_byp_req_intersig_mubi 1.590s 287.979us 50 50 100.00
V2S sec_cm_clk_handshake_intersig_mubi clkmgr_clk_handshake_intersig_mubi 1.670s 299.496us 50 50 100.00
V2S sec_cm_div_intersig_mubi clkmgr_div_intersig_mubi 1.390s 206.814us 50 50 100.00
V2S sec_cm_jitter_config_mubi clkmgr_csr_rw 0.980s 110.248us 20 20 100.00
V2S sec_cm_idle_ctr_redun clkmgr_sec_cm 3.520s 730.271us 5 5 100.00
V2S sec_cm_meas_config_regwen clkmgr_csr_rw 0.980s 110.248us 20 20 100.00
V2S sec_cm_clk_ctrl_config_regwen clkmgr_csr_rw 0.980s 110.248us 20 20 100.00
V2S prim_count_check clkmgr_sec_cm 3.520s 730.271us 5 5 100.00
V2S TOTAL 315 315 100.00
V3 regwen clkmgr_regwen 7.750s 1.272ms 50 50 100.00
V3 stress_all_with_rand_reset clkmgr_stress_all_with_rand_reset 39.200m 694.929ms 50 50 100.00
V3 TOTAL 100 100 100.00
TOTAL 1010 1010 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 9 9 9 100.00
V3 2 2 2 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
98.51 99.15 95.80 100.00 100.00 98.81 97.02 98.80

Past Results